128K x 8 Static RAM
CY7C 109
CY7C1009
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 7, 1999
Features
• High speed
—tAA = 10 ns
• Low active power
—1017 mW (max., 12 ns)
• Low CMOS standby power
—55 mW (max.) , 4 mW (Lo w -po w e r version)
• 2.0V Data Retention (Low-power version)
• A utomat ic power-down when desel ected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY7C109 / CY7C1009 is a hig h-perf ormance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1),
an act iv e HIGH Chi p Enabl e (CE2) , an act ive LO W Output En-
able (OE), and three- state driv ers . Writi ng to the device is ac -
complished by taking Chip Enable One (CE1) and Write En-
able (WE) inputs LOW and Chip Enable T wo (CE2) input HIGH.
Data on the eight I/O pins (I/O0 through I/O7) is then written
into the location specified on the address pins (A0 through
A16).
Reading from the device is accomplished by taking Chip En-
able One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (W E) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW , CE2 HIGH, and WE LOW).
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
14
15
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE2
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
A10
CE1
A
A16
A9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15 17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
109–1
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
109–2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I
Top View
(not to scal e)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
109–3
Selectio n Guide 7C109-10
7C1009-10 7C109-12
7C1009-12 7C109-15
7C1009-15 7C109-20
7C1009-20 7C109-25
7C1009-25 7C109-35
7C1009-35
Maximum Access Time (ns) 10 12 15 20 25 35
Maximum Operating Current (mA) 195 185 155 140 135 125
Maximum CMOS Standby Current (mA) 10 10 10 10 10 10
Maximum CMOS Standby Current (mA)
Low-Power Version 2 2 2 — — —
Shaded areas contain preliminary information.
CY7C109
CY7C1009
2
Maximum Ratings
(Above which the useful life may be impa ired. For user gui de-
li nes, not tested .)
Storage Temperature ... .. ....... ....... ..............–65°C to +1 5 0°C
Ambient Temperature with
Power Applied.............................................–55°C to +1 2 5°C
Supply Voltage on VCC to Relative GND[1] ....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Vol tage[1].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage ..... ......................................>2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +8 5 °C5V ± 10%
Electrical Characteristics Over the Ope rating Range[3]
Test Conditions
7C109-10
7C1009-10 7C109-12
7C1009-12 7C109-15
7C1009-15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Cur rent GND < VI < VCC –1+1 –1+1–1+1µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Di sabled –5+5 –5+5–5+5µA
IOS Output Short
Circuit Current[3] VCC = Max.,
VOUT = GN D –300 –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
195 185 155 mA
ISB1 Au to m a ti c C E
Power-Down Current
—TTL Inputs
Max. VCC, CE 1 > VIH
or CE2 < VIL,
VIN > VIH or
VIN < VIL, f = fMAX
45 45 40 mA
ISB2 Au to m a ti c C E
Power-Down Current
—CMOS Inputs
Max. VCC,
CE1 > VCC – 0.3V,
or CE2 < 0.3V,
VIN > VCC – 0.3V,
or VIN < 0. 3 V, f = 0
10 10 10 mA
L222
Shaded areas contain preliminary information.
Notes:
1. VIL (min.) = –2.0V for pulse durations of less t han 20 ns.
2. TA is the “instant on” case temperatu re.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C109
CY7C1009
3
Electrical Characteristics Over the Ope rating Range (cont inued)
7C109-20
7C1009-20 7C109-25
7C1009-25 7C109-35
7C1009-35
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltag e 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 V
VIL Input LO W Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Curren t GND < VI < VCC –1+1–1+1–1+1µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Disabled –5+5–5+5–5+5µA
IOS Output Short
Cir cuit Current[3] VCC = Ma x.,
VOUT = GND –300 –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = f MAX = 1/tRC
140 135 125 mA
ISB1 Automatic CE
Powe r-Down Curren t
—TTL Inputs
Max. VCC, CE 1 > VIH
or CE2 < VIL,
VIN > VIH or
VIN < VIL, f = fMAX
30 30 25 mA
ISB2 Automatic CE
Powe r-Down Curren t
—CMOS Inputs
Max. VCC,
CE1 > VCC – 0. 3 V,
or CE2 < 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10 10 10 mA
Capacitance[4]
P arameter De scri ption Test Conditi ons Max . Unit
CIN Input Capac it ance TA = 25°C, f = 1 MHz,
VCC = 5.0V 9pF
COUT Outpu t Capacitance 8 pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
109–4109–5
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 3ns ≤3ns
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2
255Ω
167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
CY7C109
CY7C1009
4
Switching Characteristics[3 , 5] Over t he Operating Range
7C109-10
7C1009-10 7C109-12
7C1009-12 7C109-15
7C1009-15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Ti me 10 12 15 ns
tAA Address to Data Valid 10 12 15 ns
tOHA Data Hold from Addr ess Change 333ns
tACE CE1 LOW to Data Valid, CE2 HIGH to Dat a
Valid 10 12 15 ns
tDOE OE LOW to D a ta Vali d 567ns
tLZOE OE LOW to Low Z 000ns
tHZOE OE HIGH to High Z[6, 7] 567ns
tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[7] 333ns
tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] 567ns
tPU CE1 LOW to Powe r- Up, CE2 HIG H to
Power-Up 000ns
tPD CE1 HIGH to Power-Down, CE2 LOW to
Power-Down 10 12 15 ns
WRITE CYCLE[8, 9]
tWC Write Cycle Time 10 12 15 ns
tSCE CE1 LOW to Write End, CE2 HIGH to Write End 810 12 ns
tAW Address Set-Up to Write End 810 12 ns
tHA Address Hold from Write End 000ns
tSA Address Set-Up to Write Start 000ns
tPWE WE Pulse Width 810 12 ns
tSD Da t a S e t- U p to W r it e E n d 678ns
tHD Data Hold from Write End 000ns
tLZWE WE HIGH to Low Z[7] 333ns
tHZWE WE LOW to High Z[6, 7] 567ns
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-p F load capac itance.
6. tHZOE, t HZCE, and tHZWE are specified w ith a l oa d capaci tance of 5 pF as in part (b) of A C Test Load s. Tr ansiti on is mea sured ±500 mV from s teady- state v ol tage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is l ess than t LZOE, and tHZWE is les s than tLZWE f or any given dev ice.
8. The internal write time of the memory is defined by the overlap of CE1 LO W, CE2 HIGH, and WE LOW . C E1 and WE m ust be LO W an d CE2 HIG H to in itia te a write ,
and the t r ansit ion of a ny of these s ignals can te rminate the write . The inpu t data s et-up and hol d timing s hould be ref er enced to the l eadin g edge of th e signal that terminates
the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C109
CY7C1009
5
Swit ching C haracter is ti cs[3, 5] Over the Operating Range (continued)
Parameter Description
7C109-20
7C1009-20 7C109-25
7C1009-25 7C109-35
7C1009-35
UnitMin. Max. Min. Max. Min. Min.
READ CYCLE
tRC Read Cycle Time 20 25 35 ns
tAA Address to Data Valid 20 25 35 ns
tOHA Data Hold from Address Change 3 5 5 ns
tACE CE1 LOW to Data Val id, CE2 HIGH to Data
Valid 20 25 35 ns
tDOE OE LOW to Data Valid 8 10 15 ns
tLZOE OE LOW to Lo w Z 0 0 0 ns
tHZOE OE HIGH to High Z[6 , 7 ] 81015ns
tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[7] 355ns
tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] 81015ns
tPU CE1 LOW to Power-Up, CE2 HIGH to
Power-Up 000ns
tPD CE1 HIGH to Power-Down, CE2 LOW to
Power-Down 20 25 35 ns
WRITE CYCLE[8]
tWC Write Cycl e Time 20 25 35 ns
tSCE CE1 LOW to Write End, CE 2 HIGH to Write End 15 20 25 ns
tAW Address Set- U p to Write End 15 20 25 n s
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE WE Pulse Width 12 15 20 ns
tSD Data Set-Up to Write End 10 15 20 ns
tHD Data Hold from Write End 0 0 0 ns
tLZWE WE HIGH to Low Z[7] 355ns
tHZWE WE LOW to High Z[6, 7] 81015ns
Data Reten ti o n C h ar acter i stic s Over the Operating Range (L Versi on Only)
Parameter Description Conditions Min. Max Unit
VDR VCC for Data Reten ti on No input may exce ed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0. 3V or VIN < 0.3V
2.0 V
ICCDR Data Retentio n Current 50 µA
tCDR Chi p Deselect to Data Retention Time 0 ns
tROper ati on Recove ry Time tRC ns
CY7C109
CY7C1009
6
Data Retention Waveform
Switching Wavef orms
Read Cycle No. 1[10, 11]
Read Cycle No. 2 (OE Contr oll ed)[11, 12]
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH f or read cycle.
12. Address v alid prior to or coincident with CE1 tr ansi tion LO W and C E2 tr ansiti on H IGH.
4.5V4.5V
CE
VCC
tCDR
VDR >2V
DATA RETENTION MODE
tR
109-6
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
109–7
ADDRESS
DATA OUT
109–8
50%
50%
DATA VALI D
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDA NCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
CY7C109
CY7C1009
7
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
Write Cycle No. 2 (WE Controlled, OE HIGH During Writ e)[13, 14]
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes L OW simul taneous ly wi th WE goi ng HIG H, the out put r emains in a high- impedance s tate .
Switching Wavef orms (continued)
109–9
tWC
DATA VA LI D
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
109–10
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE 15
CY7C109
CY7C1009
8
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
Note:
15. During this period the I/Os are in the output state and input signals should not be applied.
Switching Wavef orms (continued)
109–11
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZWE
CE1
ADDRESS
CE2
WE
DATA I/O NOTE 15
Truth Table
CE1CE2OE WE I/O0 – I/O7Mode Power
H X X X High Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L D a ta In Write Active (ICC)
L H H H High Z Se lected, Outputs Disabled Active (ICC)
CY7C109
CY7C1009
9
Document #: 38–00140–K
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C109-10VC V33 32-Lead (400-Mi l) Mo lded SOJ Commercial
CY7C1009-10VC V32 32-Lead (300-Mi l) Mo lded SOJ
CY7C1009L-10VC V32 32-Lead (300-Mi l) Molded SOJ
12 CY7C109-12VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009-12VC V32 32-Lead (300-Mil) Molded SOJ
CY7C1009L-12VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109-12ZC Z32 32-Lead TSOP Type I
15 CY7C109-15VC V33 32-Lead (400-Mil) Molded SOJ
CY7C1009-15VC V32 32-Lead (300-Mil) Molded SOJ
CY7C1009L-15VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109-15ZC Z32 32-Lead TSOP Type I
CY7C109-15VI V33 32-Lead (400-Mi l) Mo lded SOJ Industrial
CY7C109L-15VI V33 32-Lead (400-Mil) Molded SOJ
CY7C1009-15VI V32 32-Lead (300-Mil) Molded SOJ
CY7C109-15ZI Z32 32-Lead TSOP Type I
20 CY7C109-20VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009-20VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109-20VI V33 32-Lead (400-Mi l) Mo lded SOJ Industrial
CY7C109-20ZC Z32 32-Lead TSOP Type I Commercial
CY7C109-20ZI Z32 32-Lead TSOP Type I Industrial
25 CY7C109-25VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009-25VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109-25VI V33 32-Lead (400-Mi l) Mo lded SOJ Industrial
CY7C109-25ZC Z32 32-Lead TSOP Type I Commercial
CY7C109-25ZI Z32 32-Lead TSOP Type I Industrial
35 CY7C109-35VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009-35VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109-35VI V33 32-Lead (400-Mi l) Mo lded SOJ Industrial
Shaded areas contain preliminary information.
CY7C109
CY7C1009
10
Package D i ag ra ms
32-Lead (300-Mil) Molded SOJ V32
51-85041-A
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
CY7C109
CY7C1009
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag ra ms (continued)
51-85056-B
32-Lead Thin Small Outline Package Z32
