1. General description
The 74CBTLV16211 provides a dual 12-bit high-speed bus switch with separate output
enable inpu ts (1OE, 2OE). The low o n-state resist ance of the switch allows connections to
be made with minimal propagation delay. The switch is disabled (high-impedance
OFF-state) when the output enable (nOE) input is HIGH.
To ensure the high-im pedan ce OFF-st a te dur ing power-up or power-down, 1OE and 2OE
should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is
determined by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit toleran t to slower input rise and fall
times across the entire VCC range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the outpu t, pr eve n tin g the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Supply voltage range from 2.3 V to 3 .6 V
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5 switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
IOFF circuitry provides partial Power-down mode operation
TSSOP56 packages: SOT364-1 and SOT481-2
Specified from 40 Cto+85C and 40 Cto+125C
74CBTLV16211
24-bit bus switch
Rev. 7 — 9 November 2016 Product data sheet
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Product data sheet Rev. 7 — 9 November 2016 2 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74CBTLV16211DGG 40 C to +125 C TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm SOT364-1
74CBTLV16211DGV 40 C to +125 C TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 4.4 mm SOT481-2
Fig 1. Logic symbol
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Fig 2. Logic diagram (one switch)
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74CBTLV16211 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 7 — 9 November 2016 3 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 3. Pin configuration (SOT364-1 and SOT48 1-2)
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Table 2. Pin description
Symbol Pin Description
n.c. 1 not connected
1A0 to 1A11 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 independent input or output
2A0 to 2A11 15, 16, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28 independent input or output
GND 8, 19, 38, 49 ground (0 V)
VCC 17 supply voltage
2B0 to 2B11 41, 40, 39, 37, 36, 35, 34, 33, 32, 31, 30, 29 independent input or output
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Product data sheet Rev. 7 — 9 November 2016 4 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP56 packages: above 55 C the value of Ptot derates linearly with 8.0 mW/K.
8. Recommended operating conditions
[1] Applies to control signal levels.
1B0 to 1B11 54, 53, 52, 51, 50, 48, 47, 46, 45, 44, 43, 42 independent input or output
2OE 55 output enable input (activ e-LOW)
1OE 56 output enable input (activ e-LOW)
Table 2. Pin description …continued
Symbol Pin Description
Table 3. Function table[1]
Output enable input OE Function switch
L ON-state
HOFF-state
Table 4. L imiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
VIinput voltage [1] 0.5 +4.6 V
VSW switch voltage enable and disable mode [1] 0.5 VCC + 0.5 V
IIK input clamping current VI<0.5 V 50 - mA
ISK switch clamping current VI<0.5 V 50 - mA
ISW switch current VSW = 0 V to VCC -128 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 Cto+125C[2] - 600 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 2.3 3.6 V
VIinput voltage 03.6V
VSW switch voltage enable and disable mode 0 VCC V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 2.3 V to 3.6 V [1] 0200ns/V
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Product data sheet Rev. 7 — 9 November 2016 5 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
9. Static characteristics
[1] All typical values are measured at Tamb =25C.
[2] One input at 3 V, other inputs at VCC or GND.
9.1 Test circuits
Table 6. Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb =40 C to +85 C Tamb =40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level input
voltage VCC = 2.3 V to 2.7 V - - 0.7 - 0. 7 V
VCC = 3.0 V to 3.6 V - - 0.9 - 0.9 V
IIinput leakage
current pin nOE; VI = GND to VCC;
VCC =3.6V --1.0 - 20 A
IS(OFF) OFF-state
leakage current VCC = 3.6 V; see Figure 4 --1- 20 A
IS(ON) ON-state
leakage current VCC = 3.6 V; see Figure 5 --1- 20 A
IOFF power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0V --10 - 50 A
ICC supply current VI = GND or VCC; IO = 0 A;
VSW =GNDorV
CC;
VCC =3.6V
--10- 50A
ICC additional
supply current pin nOE; VI=V
CC 0.6 V;
VSW =GNDorV
CC;
VCC =3.6V
[2] - - 300 - 2000 A
CIinput
capacitance pin nOE; VCC = 3.3 V;
VI=0Vto3.3 V -0.9- - -pF
CS(OFF) OFF-state
capacitance VCC = 3.3 V; V I=0Vto3.3 V - 5.2 - - - pF
CS(ON) ON-state
capacitance VCC = 3.3 V; V I= 0 V to 3.3 V - 14.3 - - - pF
VI = VCC or GND and VO = GND or VCC.V
I = VCC or GND and VO = open circuit.
Fig 4. Test circuit for measuring OFF-state leakage
current (one channel) Fig 5. Test circuit for measuring ON-state leakage
current (one channel)
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74CBTLV16211 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 7 — 9 November 2016 6 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
9.2 ON resistance
[1] Typical values are measured at Tamb =25C and nominal VCC.
[2] Measured by the voltage drop between the A and B terminals at the indicated curre nt through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
9.3 ON resistance test circuit and graphs
Table 7. Re sistance RON
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter Conditions Tamb =40 C to +85 C Tamb =40 C to +125 CUnit
Min Typ[1] Max Min Max
RON ON resistance VCC = 2.3 V to 2.7 V;
see Figure 7 to Figure 9 [2]
ISW =64mA; V
I= 0 V - 4.2 8.0 - 15.0
ISW =24 mA; V
I= 0 V - 4.2 8.0 - 15.0
ISW = 15 mA; VI= 1.7 V - 8.4 40 - 60.0
VCC = 3.0 V to 3.6 V;
see Figure 10 to Figure 12
ISW =64mA; V
I=0V - 4.0 7.0 - 11.0
ISW =24 mA; V
I=0V - 4.0 7.0 - 11.0
ISW = 15 mA; VI= 2.4 V - 6.2 15 - 25.5
RON =V
SW / ISW.(1)T
amb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 6. Test circuit for measuring ON resistance
(one channel) Fig 7. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 15 mA
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Product data sheet Rev. 7 — 9 November 2016 7 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 8. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 24 mA Fig 9. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 64 mA
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(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 10. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 15 mA Fig 11. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 24 mA
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Product data sheet Rev. 7 — 9 November 2016 8 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
10. Dynamic characteristics
[1] All typical values are measured at Tamb =25C and at nominal VCC.
[2] The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the load capacitance, when
driven by an ideal voltage source (zero output impedance).
[3] tpd is the same as tPLH and tPHL.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 12. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA
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Table 8. Dynamic characteristics
GND = 0 V; for test circuit see Figure 15
Symbol Parameter Conditions Tamb =40 C to +85 C Tamb =40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay nAn to nBn or nBn to
nAn; see Figure 13 [2][3]
VCC = 2.3 V to 2.7 V - - 0.13 - 0.2 ns
VCC = 3.0 V to 3.6 V - - 0.2 - 0.31 ns
ten enable time nOE to nA n or nB n;
see Figure 14 [4]
VCC = 2.3 V to 2.7 V 1.0 2.0 7.0 1.0 7.8 ns
VCC = 3.0 V to 3.6 V 1.0 1.7 6.2 1.0 6.8 ns
tdis disable time nOE to nAn or nBn;
see Figure 14 [5]
VCC = 2.3 V to 2.7 V 1.0 2.6 7.2 1.0 8.1 ns
VCC = 3.0 V to 3.6 V 1.0 3.0 7.7 1.0 8.8 ns
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Product data sheet Rev. 7 — 9 November 2016 9 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
11. Waveforms
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The data input (nAn or nBn) to output (nBn or nAn) propagation delays
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Table 9. Mea surement points
Supply voltage Input Output
VCC VMVItr = tfVMVXVY
2.3 V to 2.7 V 0.5VCC VCC 2.0 ns 0.5VCC VOL +0.15V V
OH 0.15 V
3.0 V to 3.6 V 0.5VCC VCC 2.0 ns 0.5VCC VOL +0.3V V
OH 0.3 V
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. Enable and disable time s
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Product data sheet Rev. 7 — 9 November 2016 10 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 15. Test circuit for measuring switching times
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Supply voltage Load VEXT
VCC CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
2.3 V to 2.7 V 30 pF 500 open GND 2VCC
3.0 V to 3.6 V 50 pF 500 open GND 2VCC
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Product data sheet Rev. 7 — 9 November 2016 11 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
11.1 Additional dynamic characteristics
[1] fi is biased at 0.5VCC.
11.2 Test circuits
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specifie d ); tr = tf
2.5 ns.
Symbol Parameter Conditions Tamb = 25 CUnit
Min Typ Max
f(3dB) 3 dB frequency response VCC =3.3V; R
L=50; see Figure 16 [1] -458-MHz
nOE connected to GND; Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3dB.
Fig 16. Test circuit for measuring the frequency response when channel is in ON-state
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74CBTLV16211 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 7 — 9 November 2016 12 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
12. Package outline
Fig 17. Package outline SOT364-1 (TSSOP56)
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74CBTLV16211 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 7 — 9 November 2016 13 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
Fig 18. Package outline SOT481-2 (TSSOP56)
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Product data sheet Rev. 7 — 9 November 2016 14 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
13. Abbreviations
14. Revision history
Table 12 . Abbreviations
Acronym Description
CDM Charged Device Mo del
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74CBTLV16211 v.7 20161109 Product data sheet - 74CBTLV 16211 v.6
Modifications: •Section 11.1 and Section 11.2 added.
74CBTLV16211 v.6 20111215 Product data sheet - 74CBTLV16211 v.5
Modifications: •Legal pages updated.
74CBTLV16211 v.5 20101230 Product data sheet - 74CBTLV 16211 v.4
74CBTLV16211 v.4 20100816 Product data sheet - 74CBTLV 16211 v.3
74CBTLV16211 v.3 20100112 Product data sheet - 74CBTLV 16211 v.2
74CBTLV16211 v.2 20090826 Product data sheet - 74CBTLV 16211 v.1
74CBTLV16211 v.1 20080620 Product data sheet - -
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Product data sheet Rev. 7 — 9 November 2016 15 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
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Short data sheet — A short data sheet is an extract from a full dat a sheet
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for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
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full data sheet shall pre va il.
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Limited warr a nty and liability — Information in this document is believed to
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Applications — Applications that are described herein for any of these
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Customers are responsible for the design and ope ration of their applications
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customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings onl y and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document cont ains data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74CBTLV16211 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 7 — 9 November 2016 16 of 17
NXP Semiconductors 74CBTLV16211
24-bit bus switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74CBTLV16211
24-bit bus switch
© NXP Semiconductors N.V. 2016. All r ights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 November 2016
Document identifier: 74CBTLV16211
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
9.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
9.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9.3 ON resistance test circuit and graphs. . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
11.1 Additional dynamic characteristics . . . . . . . . 11
11.2 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16 Contact information. . . . . . . . . . . . . . . . . . . . . 16
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
