MR2A08AVYS35 - Everspin Technologies, Inc.

Freescale Semicondu ctor

Data Sheet Document Number: MR2A16A

Rev. 6, 11/2007

Introduction

The MR2A16A is a 4,194,304-bit magnetoresistive

rando m access memory (MRAM) device

organized as 262,144 words of 16 bits. The

MR2A16 A is eq uipped with c hip en able (E ), write

enable (W), and output enable (G) pins, allowing

for significant system design flexibility without bus

co ntenti on. Becau s e t he MR2 A16A has s epar ate

byte-enable controls (LB and UB) , ind i vi dual byt es

ca n be written an d read.

MRAM is a nonvolatile mem ory technology that

prot ec t s data in th e ev ent of pow er loss an d does

not require periodic refreshing. The MR2A16A is

the id eal mem ory so lution f or app lic at ions th at

must perm anen t ly store an d retriev e c ritica l data

quickly.

The MR2A16A is available in a 400-mil, 44-lead

plastic small-outline TSOP type-II package with an

industry-standard center power and ground SRAM

pinout.

The MR2A16A is available in Commercial (0°C to

70°C ), In dustr ial (-40 °C t o 85 °C) and E x t end ed

(-40°C t o 105°C) am bien t tem pera t ure ran ges.

Features

• Singl e 3.3- V power supp ly

• C ommerc ial temp erat ure ran ge (0°C to

70°C ), I ndus t ri al temperature range (-40°C

to 85°C) and Extended temperature range

(-40°C t o 105° C )

•

Symmetrical

hi gh -s peed r ead a nd w ri te wi th

fast access time (35 ns)

• F lexible data bus c ontrol — 8 bit or 16 bi t

access

• Equ al address and chip-en able a ccess

times

• Automatic data protection with low-voltage

inhibit ci rc uitry t o prevent wr ite s on power

loss

• All in put s and ou tp ut s are

tra ns is t or-transis to r logic (T T L) c ompatible

• Fully static operation

• F ull no nv olat ile oper at ion wit h 20 years

minimum data retention

256K x 16-Bit 3.3-V

Asynchr onous

Magnetoresistive RAM

MR2A16A

44-TSOP

Case 924A-02

MR2A16A Data Sheet, Rev. 6

2Freescale Semiconductor

Device Pin Assignment

Figure 1. Block Di agram

Device Pin Assignment

Figure 2. MR2A16A in 44-Pin TSOP Type II P ackage

UPPER BYTE OUTPUT ENABLE

LOWER BYTE OUTPUT ENABLE

COLUMN

DECODER

ROW

DECODER

256K x 16

BIT

MEMORY

ARRAY

FINAL

WRITE

DRIVERS

SENSE

AMPS

UPPER BYTE WRITE ENABLE

LOWER BYTE WRITE ENAB LE

OUTPUT

ENABLE

BUFFER

CHIP

ENABLE

BUFFER

WRITE

ENABLE

BUFFER

BYTE

ENABLE

BUFFER

ADDRESS

BUFFERS UPPER

BYTE

OUTPUT

BUFFER

LOWER

BYTE

OUTPUT

BUFFER

UPPER

BYTE

WRITE

DRIVER

LOWER

BYTE

WRITE

DRIVER DQL[7:0]

DQU[15:8]

10 8

A[17:0]

A17

A16

A15

DQU15

DQU14

DQU13

DQU12

VSS

VDD

DQU11

DQU10

DQU9

DQU8

A14

A13

A12

A11

A10

DQL0

DQL1

DQL2

DQL3

VDD

VSS

DQL4

DQL5

DQL6

DQL7

Table 1. Pin Functions

Signal Name Function

A Address input

EChip enable

WWrit e enable

GOutput enable

UB Upper byte select

LB Lower byte select

DQL Data I/O, lower byte

DQU Data I/O, upper byte

VDD Power supply

VSS Ground

NC Do not connect this pin

Electrical Spec if ications

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 3

Electrical Specifications

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or

el ect ri c f iel d s; ho wev er , i t is ad vi se d tha t no r mal prec au ti on s be ta ke n to avoi d app l ic at ion o f an y vo lt age

greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic fields. Precautions should be taken to

avoid application of any magnetic field more intense than the maximum field intensity specified in the

maximum ratings.

Table 2. Operating Modes

E1G1W1LB1UB1Mode VDD

Current DQL[7:0]2DQU[15:8]2

H XXXXNot selected I

SB1, ISB2 Hi-Z Hi-Z

L H H X X Output disabled IDDR Hi-Z Hi-Z

L X X H H Output disabled IDDR Hi-Z Hi-Z

L L H L H Lower byte read IDDR DOut Hi-Z

L L H H L Upper byte read IDDR Hi-Z DOut

L L H L L Word rea d IDDR DOut DOut

L X L L H Lower byte write IDDW DIn Hi-Z

L X L H L Upper byte write IDDW Hi-Z DIn

LXLLLWord write I

DDW DIn DIn

NOTES:

1H = high, L = low, X = don’t care

2Hi-Z = high impedance

MR2A16A Data Sheet, Rev. 6

4Freescale Semiconductor

Electrical Specifications

Table 3. Absolute Maximum Ratings1

Parameter Symbol Value Unit

Supply voltage2VDD –0.5 to 4.0 V

Voltage on any pin2VIn –0.5 to VDD + 0.5 V

Output current per pin IOut ±20 mA

Package power dissipation3PD0.600 W

Temperature under bias

MR2A 16ATS 35C (Com mercial - Legacy)

MR2A16AYS35 (Commercial - New)

MR2A16ACYS35 (Industrial)

MR2A 16A VYS35 (E xtende d)

TBias

–10 to 85

–45 to 95

–45 to 110

°C

Storage temperature Tstg –55 to 15 0 °C

Lead temperature during solder (3 minute max) TLead 260 °C

Maximum magnetic field during write

MR2A 16ATS 35C (Com mercial - Legacy)

MR2A16AYS35 (Commercial - New)

MR2A16ACYS35 (Industrial)

MR2A 16A VYS35 (E xtende d)

Hmax_write

Maximu m magnet ic field during read or standby Hmax_read 100 Oe

NOTES:

1Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation

shoul d be restr ic ted to reco mmended op erating condi tions. Exposur e to excessive vol tages or mag netic fi elds

could affect device reliability.

2All voltages are referenced to VSS.

3Power dissipat ion c apability depends on package characteristics and use environ me nt.

Electrical Spec if ications

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 5

Table 4. Operating Conditions

Parameter Symbol Min Typ Max Unit

Power supply voltage

MR2A16ATS35C (Commercial - Legacy )

MR2A16AYS35 (Commercial - New)

MR2A16ACYS35 (Industrial)

MR2A1 6 AVYS35 (Extended)

VDD

3.01

3.02

3.3

3.6

Write inh ibit voltage

MR2A16ATS35C (Commercial - Legacy )

MR2A16AYS35 (Commercial - New)

MR2A16ACYS35 (Industrial)

MR2A1 6 AVYS35 (Extended)

VWI

2.5

2.7

3.01

3.02

Input high voltage VIH 2.2 — VDD +

0.33V

Input low volt age VIL –0.54—0.8V

Operating temperature

MR2A16ATS35C (Commercial - Legacy )

MR2A16AYS35 (Commercial - New)

MR2A16ACYS35 (Industrial)

MR2A1 6 AVYS35 (Extended)

-40

105

°C

NOTES:

1After power up or if V DD falls below VWI, a waiting period of 2 μs must be observed, and E and W

must remain high for 2 μs. M emory is designed to prevent writing for all input pin conditions if VDD

falls below minimum VWI.

2After power up or if VDD falls below VWI, a waiting period of 2 ms must be observed, and E and W

must remain high for 2 ms. Memory is designed to prevent writing for all input pin conditions if VDD

falls below minimum VWI.

3VIH (max) = VDD + 0.3 Vdc; VIH (ma x ) = VDD + 2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20. 0 mA.

4VIL (min) = –0.5 Vdc; VIL (min) = –2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

MR2A16A Data Sheet, Rev. 6

6Freescale Semiconductor

Electrical Specifications

Direct Current (dc)

Table 5. dc Characteristics

Parameter Symbol Min Typ Max Unit

Input leakage c urrent Ilkg(I) ——±1μA

Output leakage c urrent Ilkg(O) ——±1μA

Output low voltage

(IOL = +4 mA)

(IOL = +100 μA) VOL — — 0.4

VSS + 0. 2 V

Output high voltage

(IOH = –4 m A)

(IOH = –100 mA) VOH 2.4

VDD – 0.2 ——V

Table 6. Power Supply Characteristics

Parameter Symbol Typ Max Unit

ac active supply current — read modes1

(IOut = 0 mA, VDD = m ax ) IDDR 55 80 mA

ac active supply current — write modes1

(VDD = max)

MR2A16ATS 35C (Commercial - Legacy)

MR2A16AYS35 (Com me rcial - New)

MR2A1 6ACYS35 (In dustrial)

MR2A1 6AVYS 35 (Extended )

IDDW 105

105

155

165

ac standby current

(VDD = max, E = VIH)

(no other restrict ions on other inputs) ISB1 18 28 mA

CMOS standby current

(E ≥ VDD – 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)

(VDD = max, f = 0 MH z ) ISB2 912mA

NOTES:

1All active current measurements are measured with one address transition per cycle.

Table 7. Capacitance1

Parameter Symbol Typ Max Unit

Address input capacit ance CIn —6pF

Control input capacita nce CIn —6pF

Input/ou tput capacitance C I/O —8pF

NOTES:

1f = 1.0 MHz, dV = 3.0 V, TA = 25 ° C , per iodical ly sa mp led r ather than 100% tes ted.

Electrical Spec if ications

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 7

Figure 3. Output Load for ac Test

Table 8. ac Measurement Conditions

Parameter Value

Logic input timing measurement reference level 1.5 V

Logic output timing measurement reference level 1.5 V

Logic input pulse levels 0 or 3.0 V

Input rise/fall time 2 ns

Output load for low and high im ped anc e parameters See Figure 3A

Output load for all other timing parameters See Figure 3B

OUTPUT

RL = 50 Ω

VL = 1 .5 V

ZD = 50 Ω

OUTPUT

600 Ω

725 Ω

5 pF

+3.3 V

MR2A16A Data Sheet, Rev. 6

8Freescale Semiconductor

Timing Specificati ons

Timin g Sp ecif icati ons

Read Mode

Table 9. Read Cycle T iming1, 2

Parameter Symbol Min Max Unit

Read cycle time tAVAV 35 — ns

Address access time tAVQV —35ns

Enable access time 3tELQV —35ns

Output enable access time tGLQV —15ns

Byte enab le access time tBLQV —15ns

Output hold fro m address change tAXQX 3—ns

Enabl e low to outp ut active4, 5 tELQX 3—ns

Output enable low to output active4, 5 tGLQX 0—ns

Byte enable low to output active4, 5 tBLQX 0—ns

Enabl e high to output Hi-Z4, 5 tEHQZ 015ns

Output enable high to output Hi-Z4, 5 tGHQZ 010ns

Byte high to output Hi-Z4, 5 tBHQZ 010ns

NOTES:

1W is high for read cycle.

2Due to product sensitivities to noise, power supplies must be properly grounded and

decoupled, and bus contentio n condition s mu st be mi nimized or el iminated dur ing read and

write cycles.

3Addresses valid before or at the same time E goes low.

4This parameter is sampled and not 100% tested.

5Transition is measured ±200 mV fro m steady-stat e voltage.

Timing Specificati ons

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 9

Figure 4. Read Cycle 1

Figure 5. Read Cycle 2

tAVAV

tAXQX

tAVQV

DATA VALIDPREVIOUS DATA VAL IDQ (DATA OUT)

A (ADDRESS)

NOTES:

Device is continuousl y selected (E ≤ VIL, G ≤ VIL).

tAVAV

tAVQV

A (ADDRESS)

tELQX

tGLQV

DATA VALID

E (CHIP ENABLE)

G (OUTPUT ENABLE)

LB, UB (BY TE ENABLE)

Q (DATA OUT)

tELQV

tGLQX

tBLQV

tBLQX

tBHQZ

tGHQZ

tEHQZ

MR2A16A Data Sheet, Rev. 6

10 Freescale Semiconductor

Timing Specificati ons

Write Mode

Tabl e 10. Writ e C ycle Timi n g 1 (W Controlled)1, 2, 3, 4, 5

Parameter Symbol Min Max Unit

Write cycl e time6tAVAV 35 — ns

Address set-up time tAVWL 0—ns

Address valid to end of write (G high) tAVWH 18 — ns

Address valid to end of write (G low) tAVWH 20 — ns

Write pulse width (G high) tWLWH

tWLEH 15 — ns

Write pulse width (G low) tWLWH

tWLEH 15 — ns

Data valid to end of write tDVWH 10 — ns

Data hold time tWHDX 0—ns

Write low to data Hi-Z7, 8, 9 tWLQZ 012ns

Write high to output active7, 8, 9 tWHQX 3—ns

Write reco very ti me tWHAX 12 — ns

NOTES:

1A writ e occurs during the overlap of E low and W low.

2Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and

bus contention co nditions must be mini m ized or eliminated durin g read and write cyc les.

3If G goes low at the sam e time or after W goes low, the out put will remai n in a hig h-i m pedance state.

4Afte r W, E, or UB/LB has been b rought high, th e signal mus t remai n in s teady- sta te hig h for a mi nimum

of 2 ns.

5The mini mum tim e between E bei ng as serte d low in one cycle t o E bei ng assert ed low i n a subsequen t

cycle is the same as the minimum cycle time allowed for the device.

6All writ e cycle timi ngs are r eferenced f rom the last val id ad dress to the first transition addre ss.

7This parameter is sam pled and not 100% test ed.

8Transition is measured ±200 mV from st eady-state v olt age.

9At any giv en voltage or te mp erat ure, tWLQZ max < tWHQX min.

Timing Specificati ons

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 11

Figur e 6. W r i te C ycle 1 (W Controlled)

tAVAV

tAVWH

A (ADDRESS)

tWLEH

DATA VA L ID

E (CHIP ENABLE)

W (WRITE ENABLE)

LB, UB (BYTE ENAB LE)

Q (DATA OUT)

tDVWH

tWLQZ

tWHDX

D (DATA IN)

tWHAX

Hi-ZHi-Z

tAVWL

tWLWH

tWHQX

MR2A16A Data Sheet, Rev. 6

12 Freescale Semiconductor

Timing Specificati ons

Tabl e 11. Writ e C ycle Timi n g 2 (E Controlled)1, 2, 3, 4, 5

Parameter Symbol Min Max Unit

Writ e cycle time6tAVAV 35 — ns

Address set-up time tAVEL 0—ns

Address valid to e nd of write (G high) tAVEH 18 — ns

Address valid to e nd of write (G low) tAVEH 20 — ns

Enable to end of write (G high) tELEH

tELWH 15 — ns

Enable to end of write (G low)7, 8 tELEH

tELWH 15 — ns

Da ta val id to e n d of wr ite t DVEH 10 — ns

Data hold time tEHDX 0—ns

Wri te recovery tim e t EHAX 12 — ns

NOTES:

1A writ e occurs durin g the overlap of E low and W low .

2Due to product sensitivities to noise, power supplies must be properly grounded and decoupled

and bus contention conditions must be minimized or eliminated duri ng read a nd write cycles.

3If G goes low at the same time or after W goes low, the output will remain in a high-impedance

state.

4After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a

minimum of 2 ns.

5The minimum time between E being asserted low in one cycle to E being asserted low in a

subsequent c ycle is the same as th e minimum cycle time allowed for the device.

6All write cycle timi ngs are referenced fro m the last valid address to the first transit ion address.

7If E goes low at the same time or after W goes low, the outp ut will remain in a high-imped ance state.

8If E goes high at the same tim e or before W goes high , t he outpu t will remain in a high-im pedance

state.

Timing Specificati ons

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 13

Figure 7. Write Cycle 2 (E Controlle d)

tAVAV

tAVEH

A (ADDRESS)

DATA VALID

E (CHIP ENABLE)

W (WRITE ENABLE)

LB, UB (BYTE ENAB LE)

Q (DATA OUT)

D (DATA IN)

tEHAX

Hi-Z

tELEH

tDVEH

tAVEL tELWH

tEHDX

MR2A16A Data Sheet, Rev. 6

14 Freescale Semiconductor

Timing Specificati ons

Table 12. Wri te C ycle Ti ming 3 (LB /UB Controlled)1, 2, 3, 4, 5, 6

Parameter Symbol Min Max Unit

Write cycle time7tAVAV 35 — ns

Address set-up time tAVBL 0—ns

Address valid to end of write (G high) tAVBH 18 — ns

Address valid to end of write (G low) tAVBH 20 — ns

Byte pulse width (G high) tBLEH

tBLWH 15 — ns

Byte pulse width (G low) tBLEH

tBLWH 15 — ns

Da ta val id to end of w rite tDVBH 10 — ns

Data hold time tBHDX 0—ns

Write recovery time tBHAX 12 — ns

NOTES:

1A write occurs during the overlap of E low and W low.

2Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and

bus contention conditions must be mi nimized or elim inated during read and write cycles.

3If G goe s low at the sam e ti m e or af ter W goes low, the output will rem ain in a high-im pedance state.

4After W, E , o r UB/LB has b een b rought high, the si gnal m ust remain in steady- st ate hi gh for a mi nimum

of 2 ns.

5If both byte control signals are asserted, the two signals must have no more than 2 ns skew between

them.

6The mini mum time between E bei ng asser ted low in one cycle t o E being as ser ted low i n a subsequ ent

cycle is the same as the minimum cycle time allowed for the device.

7All write c ycle timings are referenc ed from t he last valid address to the first t ransition address.

Timing Specificati ons

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 15

Figure 8. Write Cycle 3 (LB/UB Controlled)

tAVAV

tBHAX

A (ADDRESS)

DATA VALID

E (CHIP ENABLE)

W (W RITE ENABLE)

LB, UB (BYTE ENABLE)

Q (DATA OUT)

D (DATA IN)

Hi-Z

tAVBL tBLEH

tBLWH

tBHDX

tDVBH

tAVBH

MR2A16A Data Sheet, Rev. 6

16 Freescale Semiconductor

Orderi ng Inf ormation

Ordering Information

This prod uc t i s a va ilable in Commerc ial, In dustri al, and Ext ende d t em pera tu re vers ions.

Freescale's semiconductor products can be classified into the following tiers: “Commercial”, “Industrial”

and “Extended.” A product should only be used in applications appropriate to its tier as shown below. For

questions, please contact a Freescale sales representative.

•Commercial — Typically 5 year applications - personal computers, PDA's, portable telecom

products, consumer electronics, etc.

•Industria l, Ex tende d — Typically 10 year applications - installed telecom equipment,

workstations, servers, etc. These products can also be used in Commercial applications.

Current Part Numbering System (New Commercial, Industrial and Extended devices)

Legacy Part Nu mber i n g System (L egacy Co mmercial de vi ces)

(Order by Full Part Number )

Freescale MRAM Memory Prefix

Densit y Code (0 = 1 Mb, 1 = 2 Mb,

Timing Set (35 = 35 ns)

Revisi on (A = rev 1)

I/O Configuration (08 = 8 bit s, 16 = 16 bits)

216A A V YS 35

Memory Type ( A = async, S = syn c)

2 = 4 Mb, 4 = 16 Mb)

Package Type (YS = TSOP II)

Operati ng Tem perature Range

(Missing = 0°C to 70°C,

C = -40°C to 85 °C, V = -40 °C to 105°C)

(Order by Full Part Number )

Freescale MRAM Memory Prefix

Density Code (0 = 1 Mb, 1 = 2 Mb,

Operati ng Tem perature Range (C = 0°C to 70°C)

Revision (A = rev 1)

I/O Conf iguration (08 = 8 bits , 16 = 16 bits)

216A A TS 35 C

Memor y Type (A = async, S = sync)

2 = 4 Mb, 4 = 16 Mb)

Timing Set (35 = 35 ns)

Package Type (TS = TSOP II)

Package Information

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 17

Pack age Info r mat ion

Revision History

Mechanical Drawing

The following pages detail the package available to MR2A16A.

Tabl e 13. Packag e In fo r m ation

Device Pin

Count P ackage

Type Designator Case No. Documen t No. RoHS

Compliant

MR2A16A 44 TSOP

Type I I TS/YS1924A-02 98ASS23673W True

NOTES:

1TS and YS are both valid package codes for TSOP packages. The package is identical for both TS and YS

codes.

R evision History

Revision Date Description of Change

4 18 Jun 2007

Added new Industrial and Extended te mpera ture product information; updat ed part

ordering information; changed to 2 ms delay after pow er up; power supply

characteristics values updated to TBD for industrial and extended temperatu re

devices.

5 21 Se p 2007

Changed MR2A 16ATS35C product description to Legacy Com me rcial. Added the

New Commercial temperature product (MR2A1 6AYS35) informa tion.

Table 3: MR2A16AYS35 Hmax_write = 25 Oe.

Table 4: MR2A16AYS35 has a 2 ms power up waiting period.

Table 6: Appl ied values to TBD’s in IDD specifications.

6 12 Nov 2007

Table 2: Changed IDD A to IDDR or IDDW.

Table 13: Added note indicating that TS and YS are both valid package codes.

Current Part Numbering System: Added commercial (missing letter) temperature

range.

MR2A16A Data Sheet, Rev. 6

18 Freescale Semiconductor

Mech anical Drawing

Mecha nical Drawing

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 19

MR2A16A Data Sheet, Rev. 6

20 Freescale Semiconductor

Mech anical Drawing

Mecha nical Drawing

MR2A16A Data Sheet, Rev. 6

Freescale Semiconductor 21

MR2A16A

Rev. 6, 11/2007

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