1 of 19 081902
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata.
FEATURES
§ Real-time clock (RTC) keeps track of
hundredths of seconds, minutes, hours, days,
date of the month, months, and years
§ 32k x 8 NV SRAM directly replaces volatile
static RAM or EEPROM
§ Embedded lithium energy cell maintains
calendar operation and retains RAM data
§ Watch function is transparent to RAM
operation
§ Month and year determine the number of
days in each month; valid up to 2100
§ Full 10% operating range
§ Operating temperature range: 0°C to +70°C
§ Over 10 years of data retention in the
absence of power
§ Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
§ DIP module only
§ Standard 28-pin JEDEC pinout
§ PowerCap® module board only
– Surface mountable package for direct
connection to PowerCap containing
battery and crystal
– Replaceable battery (PowerCap)
– Pin-for-pin compatible with DS1248P
and DS1251P
§ Underwriters Laboratory (UL) recognized
PowerCap is a registered trademark of Dallas Semiconductor.
PIN ASSIGNMENT (Top View)
Package Dimension Information
http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm
DS2144
28-PDIP Module (740mil)
VCC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
14
13
28
27
26
25
24
23
22
21
20
19
18
17
15
16
A
14/RST
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ0
DQ1
GND
DQ2
3
N.C.
N.C.
WE
CE
DQ7
DQ6
DQ4
DQ3
DQ1
DQ0
4
6
7
8
10
11
12
14
15
16
N.C.33
32
31
29
27
25
24
22
21
20
18
A
12
A
11
A
9
A
8
A
6
A
5
A
2
A
4
A
0
1
VCC
28
A
1
RST 2
N.C.
OE
DQ5
DQ2
GND
5
9
13
17
A
14
30
26
23
19
A
13
A
10
A
7
A
3
34 N.C.
X1 GND VBAT X2
DS1244P
34-Pin PowerCap Module
(Uses DS9034PCX PowerCap)
DS1244/DS1244P
256k NV SRAM
with Phantom Clock
www.maxim-ic.com
www.maxim-ic.com
DS1244/DS1244P
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PIN DESCRIPTION
A0–A14 - Address Inputs
CE - Chip Enable
OE - Output Enable
WE - Write Enable
VCC - Power-Supply Input
GND - Ground
DQ0–DQ7 - Data In/Data Out
N.C. - No Connection
X1, X2 - Crystal Connection
VBAT - Battery Connection
RST - Reset
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART PIN-PACKAGE TEMP RANGE TOP MARK
DS1244Y-70 28-Module (740mil) 0°C to +70°C DS1244Y-70
DS1244YP-70 34-PowerCap*0°C to +70°C DS1244YP-70
DS1244W-120 28-Module (740mil) 0°C to +70°C DS1244W-120
DS1244W-120IND 28-Module (740mil) -40°C to +85°C DS1244W-120IND
DS1244WP-120 34-PowerCap*0°C to +70°C DS1244WP-120
DS1244WP-120IND 34-PowerCap*-40°C to +85°C DS1244WP-120IND
*DS9034PCX (PowerCap) Required. (Must be ordered separately.)
DESCRIPTION
The DS1244 256k NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)
(organized as 32k words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained
lithium energy source and control circuitry, which constantly monitors VCC for an out-of-tolerance
condition. When such a condition occurs, the lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent garbled data in both the memory and real-time
clock.
The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,
days, date, months, and years. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
PACKAGES
The DS1244 is available in two packages: 28-pin DIP and 34-pin PowerCap module. The 28-pin DIP-
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1244P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the Powercap is
DS9034PCX.
DS1244/DS1244P
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RAM READ MODE
The DS1244 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable)
is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for
CE or tOE for OE , rather than address access.
RAM WRITE MODE
The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE
active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC fall as below the VPF, access to the device is inhibited. If VPF is less than VBAT, the device
power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF. If VPF is greater
than VBAT, the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below
VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of the chip enable, output enable, and write enable. Initially, a read cycle to any memory location using
DS1244/DS1244P
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the CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer
to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other
locations outside the memory block can be interleaved with CE cycles without interrupting the pattern
recognition sequence or data transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
DS1244/DS1244P
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Figure 1. PHANTOM CLOCK REGISTER DEFINITION
Note: The pattern recognition in hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 1019. This
pattern is sent to the phantom clock LSB to MSB.
DS1244/DS1244P
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Figure 2. PHANTOM CLOCK REGISTER DEFINITION
AM/PM/12/24 MODE
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the second 10-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET
bit is set to logic 0, a low input on the RESET pin will cause the phantom clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
DS1244/DS1244P
7 of 19
BATTERY LONGEVITY
The DS1244 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1244 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1244 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF , the lithium energy source is enabled for battery-backup operation. Actual life expectancy of the
DS1244 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm.
CLOCK ACCURACY (DIP MODULE)
The DS1244 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The clock is
calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements
and does not require additional calibration. For this reason, methods of field clock calibration are not
available and not necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1244P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C.
DS1244/DS1244P
8 of 19
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V
Storage Temperature Range -40ºC to +85ºC
Soldering Temperature Range See IPC/JEDEC J-STD-020A (DIP)
(Note 13)
OPERATING RANGE
RANGE TEMP RANGE VCC
Commercial 0°C to +70°C 3.3V ±10% or 5V ±10%
Industrial -40°C to +85°C 3.3V ±10% or 5V ±10%
*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS Over the operating range
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC = 5V ±10% 2.2 VCC + 0.3V
Input Logic 1
VCC = 3.3V ±10%
VIH
2.0 VCC + 3V
V11
VCC = 5V ±15% -0.3 0.8
Input Logic 0
VCC = 3.3V ±10%
VIL
-0.3 0.6
V11
DC ELECTRICAL CHARACTERISTICS Over the operating range (5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current IIL -1.0 +1.0 mA12
I/O Leakage Current
CE ³ VIH ≤ VCC
IIO -1.0 +1.0 mA
Output Current at 2.4V IOH -1.0 mA
Output Current at 0.4V IOL 2.0 mA
Standby Current CE = 2.2V ICCS1 510mA
Standby Current
CE = VCC - 0.5V ICCS2 3.0 5.0 mA
Operating Current tCYC = 70ns ICC01 85 mA
Write Protection Voltage VPF 4.25 4.37 4.50 V 11
Battery Switchover Voltage VSO VBAT V11
DS1244/DS1244P
9 of 19
DC ELECTRICAL CHARACTERISTICS Over the operating range (3.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current IIL -1.0 +1.0 mA12
I/O Leakage Current
CE ³ VIH ≤ VCC
IIO -1.0 +1.0 mA
Output Current at 2.4V IOH -1.0 mA
Output Current at 0.4V IOL 2.0 mA
Standby Current CE = 2.2V ICCS1 57mA
Standby Current
CE = VCC - 0.5V ICCS2 2.0 3.0 mA
Operating Current tCYC = 70ns ICC01 50 mA
Write Protection Voltage VPF 2.80 2.86 2.97 V 11
Battery Switchover Voltage VSO VBAT or VPF V11
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 510pF
Input/Output Capacitance CI/O 510pF
MEMORY AC ELECTRICAL CHARACTERISTICS Over the operating range (5V)
DS1244Y-70
PARAMETER SYMBOL MIN MAX UNITS NOTES
Read Cycle Time tRC 70 ns
Access Time tACC 70 ns
OE to Output Valid tOE 35 ns
CE to Output Valid tCO 70 ns
OE or CE to Output Active tCOE 5ns5
Output High-Z from Deselection tOD 25 ns 5
Output Hold from Address Change tOH 5ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 50 ns 3
Address Setup Time tAW 0ns
Write Recovery Time tWR 0ns
Output High-Z from WE tODW 25 ns 5
Output Active from WE tOEW 5ns5
Data Setup Time tDS 30 ns 4
Data Hold Time from WE tDH 5ns4
DS1244/DS1244P
10 of 19
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
Over the operating range (5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 65 ns
CE Access Time tCO 55 ns
OE Access Time tOE 55 ns
CE to Output Low-Z tCOE 5ns
OE to Output Low-Z tOEE 5ns
CE to Output High-Z tOD 25 ns 5
OE to Output High-Z tODO 25 ns 5
Read Recovery tRR 10 ns
Write Cycle Time tWC 65 ns
Write Pulse Width tWP 55 ns 3
Write Recovery tWR 10 ns 10
Data Setup Time tDS 30 ns 4
Data Hold Time tDH 0ns4
CE Pulse Width tCW 60 ns
RESET Pulse Width tRST 65 ns
POWER-DOWN/POWER-UP TIMING Over the operating range (5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE at VIH before Power-Down tPD 0ms
VCC Slew from VPF(max) to
VPF(min)(CE at VPF)
tF300 ms
VCC Slew from VPF(min) to VSO tFB 10 ms
VCC Slew from VPF(max) to
VPF(min)(CE at VPF)
tR0ms
CE at VIH after Power-Up tREC 1.5 2.5 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time tDR 10 years 9
Warning: Under no circumstances are negative undershoots of any amplitude allowed when device is in
battery-backup mode.
DS1244/DS1244P
11 of 19
MEMORY AC ELECTRICAL CHARACTERISTICS
Over the operating range (3.3V)
DS1244W-120
PARAMETER SYMBOL MIN MAX UNITS NOTES
Read Cycle Time tRC 120 ns
Access Time tACC 120 ns
OE to Output Valid tOE 60 ns
CE to Output Valid tCO 120 ns
OE or CE to Output Active tCOE 5ns5
Output High-Z from Deselection tOD 40 ns 5
Output Hold from Address Change tOH 5ns
Write Cycle Time tWC 120 ns
Write Pulse Width tWP 90 ns 3
Address Setup Time tAW 0ns
Write Recovery Time tWR 20 ns 10
Output High-Z from WE tODW 40 ns 5
Output Active from WE tOEW 5ns5
Data Setup Time tDS 50 ns 4
Data Hold Time from WE tDH 20 ns 4
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
Over the operating range (3.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
CE Access Time tCO 100 ns
OE Access Time tOE 100 ns
CE to Output Low-Z tCOE 5ns
OE to Output Low-Z tOEE 5ns
CE to Output High-Z tOD 40 ns 5
OE to Output High-Z tODO 40 ns 5
Read Recovery tRR 20 ns
Write Cycle Time tWC 120 ns
Write Pulse Width tWP 100 ns 3
Write Recovery tWR 20 ns 10
Data Setup Time tDS 45 ns 4
Data Hold Time tDH 0ns4
CE Pulse Width tCW 105 ns
RESET Pulse Width tRST 120 ns
DS1244/DS1244P
12 of 19
POWER-DOWN/POWER-UP TIMING Over the operating range (3.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE at VIH before Power-Down tPD 0ms
VCC Slew from VPF(MAX) to
VPF(MIN)(CE at VIH)
tF300 ms
VCC Slew from VPF(MAX) to
VPF(MIN)(CE at VIH)
tR0ms
CE at VIH after Power-Up tREC 1.5 2.5 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time tDR 10 years 9
Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is
in battery-backup mode.
DS1244/DS1244P
13 of 19
MEMORY READ CYCLE (Note 1)
MEMORY WRITE CYCLE 1 (Notes 2, 6, and 7)
DS1244/DS1244P
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MEMORY WRITE CYCLE 2 (Notes 2 and 8)
RESET FOR PHANTOM CLOCK
READ CYCLE TO PHANTOM CLOCK
DS1244/DS1244P
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WRITE CYCLE TO PHANTOM CLOCK
DS1244/DS1244P
16 of 19
POWER-DOWN/POWER-UP CONDITION, 5V
POWER-DOWN/POWER-UP CONDITION, 3.3V
DS1244/DS1244P
17 of 19
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) WE is high for a read cycle.
2) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance
state.
3) tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4) tDH, tDS are measured from the earlier of CE or WE going high.
5) These parameters are sampled with a 50pF load and are not 100% tested.
6) If the CE low transition occurs simultaneously with or later than the WE low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.
7) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9) The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator
running.
10) tWR is a function of the latter occurring edge of WE or CE .
11) Voltages are referencd to ground.
12) RST (Pin 1) has an internal pullup resistor.
13) RTC modules can be successfully processed through conventional wave-soldering techniques as long
as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-
solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not
used.
In addition, for the PowerCap:
1) Dallas Semiconductor recommends that PowerCap module bases experience one pass through solder
reflow oriented with the label side up (“live-bug”).
2) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three
seconds.
– To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part,
apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove
solder.
DS1244/DS1244P
18 of 19
DS1244P WITH DS9034PCX ATTACHED
COMPONENTS AND PLACEMENT MIGHT
VARY FROM EACH DEVICE TYPE
PKG INCHES
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.955 0.960 0.965
C0.240 0.245 0.250
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.020 0.025 0.030
DS1244/DS1244P
19 of 19
RECOMMENDED POWERCAP MODULE LAND PATTERN
Note: Dallas Semiconductor recommends that PowerCap module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three
seconds.
To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part, apply flux,
heat the lead frame pad until the solder reflows, and use a solder wick to remove solder.
PKG INCHES
DIM MIN NOM MAX
A—1.050 —
B—0.826 —
C—0.050 —
D—0.030 —
E—0.112 —
