System Management Bus (SMBus)
and Configuration Registers
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. ENSMB must be pulled
high to enable SMBus mode and allow access to the config-
uration registers.
The DS64BR401 has the AD[3:0] inputs in SMBus mode.
These pins set the SMBus slave address inputs. The AD[3:0]
pins have internal pull-down. When left floating or pulled low
the AD[3:0] = 0000'b, the device default address byte is A0'h.
Based on the SMBus 2.0 specification, the DS64BR401 has
a 7-bit slave address of 1010000'b. The LSB is set to 0'b (for
a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The
bold bits indicate the AD[3:0] pin map to the slave address
bits [4:1]. The device address byte can be set with the use of
the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant.
External pull-up resistor is required on the SDA. The resistor
value can be from 1 kΩ to 5 kΩ depending on the voltage,
loading and speed. The SCL may also require an external
pull-up resistor and it depends on the Host that drives the bus.
TRANSFER OF DATA VIA THE SMBUS
During normal operation the data on SDA must be stable dur-
ing the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
SMBUS TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
When SMBus is enabled, the DS64BR401 must use one of
the following De-emphasis settings (Table 7). The driver
de-emphasis value is set on a per channel basis using 8 dif-
ferent registers. Each register (0x11, 0x18, 0x1F, 0x26, 0x2E,
0x35, 0x3C, 0x43) requires one of the following De-emphasis
settings when in SMBus mode.
TABLE 7. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value Register Setting 3 Gbps Operation 6 Gbps Operation
0.0 dB 0x01 10” trace or 1 meter 28 awg cable 5” trace or 0.5 meter 28 awg cable
-3.5 dB 0x38 20” trace or 2 meters 28 awg cable 10” trace or 1meters 28 awg cable
-6 dB 0x88 25” trace or 3 meters cable 20” trace or 2 meters cable
-9 dB 0x90 5 meters 28 awg cable 3 meters 28 awg cable
-12 dB 0xA0 8 meters 28 awg cable 5 meters 28 awg cable
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
RECOMMENDED SMBUS REGISTER SETTINGS
When SMBus mode is enabled (ENSMB = 1), the default reg-
ister are not configured to an appropriate settings. Below is
the recommended settings to configure the EQ, VOD and DE
to a medium level that supports interconnect length of 20
inches FR4 trace or 3 to 5 meters of cable length. Please refer
to , Table 1,Table 2,Table 3,Table 4, Table 7,Table 8 for ad-
ditional information and recommended settings.
1. Reset the SMBus registers to default values:
Write 01'h to address 0x00.
2. Set de-emphasis to -6 dB enhance for all channels
(CH0–CH7):
Write 88'h to address 0x11, 0x18, 0x1F, 0x26, 0x2E,
0x35, 0x3C, 0x43.
3. Set equalization to external pin level EQ[1:0] = 00 (~9 dB
at 3 GHz) for all channels (CH0–CH7):
Write 30'h to address 0x0F, 0x16, 0x1D, 0x24, 0x2C,
0x33, 0x3A, 0x41.
4. Set VOD = 1.0V for all channels (CH0–CH7):
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DS64BR401