oI 762 Am93L28 Low-Power Dual 8-Bit Shift Register Distinctive Charactoristics + 80 mW typical power dissipation 16 MHz typical shift frequency 100% reliability assurance testing In comp Mit STD 883 lance with Guaranteed tan-out of three with standard TTL circuits FUNCTIONAL DESCRIPTION The Am93L28 fow-power dual &-bit shitt register provides 148 bits of high-speed serial storage in two identical shift registers, each consisting of 8 master slave RS flip-flops. Data to each register is selected trom one of two sources, D, and D,, by a two input multiplexer controlled by DS (data select). When DS is HIGH, data is entered from the 0, input; when DS is LOW data is entered from the D, input. The two shift registers have separate clock inputs and a com- mon clock input. The common clock is ORed with the separ- ate clock inputs, so that for each register one clock input can be used as a clock line and the other as an active LOW shift enable. The registers can then be operated with a common clock and pendent shift ol or with i P jt clocks and a common shift enable. Data is entered Into the masters of the flip-flops while the clock Is LOW. During the clock pulse LOW-to-HIGH transition the masters are inhibited from further change, and the data Is transferred to the slaves. As long as the clock is HIGH, the masters cannat change and the siaves are connected to the masters. When the clock goes from HIGH to LOW, the slaves are inhibited from changing and new data is entered into the masters. An asynchronous active LOW master reset (MA) resets ail 16 bits of shift register to the 0 state independent of any other inputs to the device. LOGIC DIAGRAM LOADING RULES In Unit Loads (Notes) TTL LOADS g3L LOADS ~ Input Load Factor | HIGH LOW | HIGH LOW Wao. df os 02s | 10) to Separate CP (Pin7&10)| 0.75 0375} 15 15 Ds T4008 20 20 Gommon cP (Pin2) | 1.5 075 | 30 3.0 Output Drive HIGH Low HIGH Low Qa, 1 es 3 | 6 12 NOTES: 1) A TTL unit fond Ia specified as 0.4 V at ~1.6 mA LOW, 2.4 V at 40 2A 24 23. unit load is specitied as 6.3 V at 400 uA LOW, 2.4 V al 20 uA HIGH. 4a Enough output LOW current is available to mix TTL and 93L joadsa and Sli] meat the 93L requirement of a Vo, of 0.3 V. LOGIC SYMBOL aa H yo = PIN 16 v GNO = PING Am93L28 ORDERING INFORMATION | Package Temperature (as Order Type Range awe Number AAD 16-pin Molded DIP 0C to +7598 _, U6M93L2859X- 16-pin Hermetic DIP 0C to 475 O} U7B93L2859Xx 16-pin Hermetic DIP 59C for 129Q* ~ - U7B93L2851X 16pin Hermetic Flat Pak REL U4L93L.2851X Dice ae % Noxp UXX93L28XXD ce ok Hote: The dice suppliog gr containaits which meet both 0C to +75C and 85C to +1 temperature ranges. MAXIMUM RATINGS (Above which the usetui life may be impaired) Storage Temperature Temperature (Ambient) Under Bras Supply Voltage to Ground Potential (Put 16 to Pin 8) Continuous: OC Voltage Applied tu Outpuls for High Gutput State DC Input Voitaga Output Gurrent. Into Ourputs DC input Current(Note 1) Note 1. Maximum current detined by DC input voltage BoC to + 150C bx Ctu +125 C -OsViat?V O5Vi+ max Oavin F95V Jama 30 mA 45a mA 2-147 3 ; vere, 2-148 ELECTRICA \RACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) Am@3L2050N T, 20 + 75C Veg 4.75 10 6.28 AMOBLZESIX = T= 85C to +1289 Vc S010 $.50 0 Parametera Description Test Conditions Min, Typ. {Note 1) Max. Units Voc = MIN., lo, = 0.32 mA Vi Output HIGH Voltage ce 1 OK 24 o if _ Vv Vor Me | Voc = MIN., I, = 4.92 mA Vv, Output LOW Voltage cc ston ot Vin = Vin or Vi Guaranteed input logical HIGH oT voltage for alt inputs Guaranteed put logical Low i voltage for ail inputs Vin Input HIGH Level Viv Input LOW Level ! 83L Unit Load, iy = 0. (Hote 2) Input LOW Current Voo = MAX. Viy = 0.3. 993i Unit Load 1 Voc MAX, Ving (Nowe 2 tnput HIGH Current Input HIGH Current Ise Output Short Circuit Current lee Power Supply Current Notes: 1) Typical limite are at Veo = 5.0-V, 25C ambient and maximum loading. 2 Actual input currents are obtained by multiplying unit load current by the BIL input load factor. (see SWITCHING CHARACTERISTICS 1, = 25c) losding rules) Parameters Description Test Conditions tay Turn Off Delay (Q,, G;} tae Tum On Delay (Q,, G,) OR Turn On Delay R) urn oa (MR) (MR to Q,) cr Min. Clock ew LOW Puise Width v ov oo 5: uA Min. Reset Pulse Width co MA,W(GPH) | ith CP HIGH C, = 15 pF MA Min. Reset Pulse Width MA W(CPL) with CP LOW t, (D, D,) Data Set-up Time &, (DS) Set-up Time, Select Input f, Shitt Frequency SWITCHING TIME WAVEFORMS o\ WAVEFORM INPUTS KEY TO TMING DIAGRAM OUTPUTS MUST BE WILL BE STEADY STEADY Daor MAY CHance = WILL GE Le WL rer Bes, nan min 1 YY wi } iia May cuange ULE FROME TOW WAV Pom TO og el ADVANCED DONT CARE, CHANGING, MICRO - | WK Ses es | ior 7,07 __ f 1b 901 Thompson Place Sunnyvale California 94086 Nole: The set-up Time is defined as the time required, relative to the clock, for a LOW to HIGH aH) or a HIGH to (40B} 732-2400 LOW edge (isl) to propagate through internal delays. Logic transitions occurring betor guaranteed to be 80 Getected: those occurring etter te min are guaranteed not to be ta ind ts min may TWX: 910-330-921 OF may not be Hatected. The minimum set up time for a LOW Ie sometimes called the release time ter a HIGH. TELEX: 34-6306 Advanced Micro Devices can no! assume Fesponsibiiity for use of any circuitry described other than circultry entiely embodied In an Advanced Micro Devices product.(!) ;Preliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Stop Clock Stop Grant State STPCLK# Sampled Negated Normal (Re-entered after PLL stabilization) CLK AVAVAVAUAVAUAUAUA\\GAUAUAUAVAVAVAUB WAUAUAVAY AI313] BE[7:0|# S f ADS# S$ TL M/\O# % v_/ D/C# S S W/R# 5 s\ CACHE# $5 mr STPCLK+# SS $ D[63:0] 5 KEN# 5) BRDV# Figure 75. Stop Grant and Stop Clock Modes, Part 2 Chapter 5 Bus Cycles 169AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 INIT-Initiated Transition from Protected Mode to Real Mode INIT is typically asserted in response to a BIOS interrupt that writes to an I/O port. This interrupt is often in response to a Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar to port 64h in the keyboard controller) that asserts INIT. INIT is also used to support 80286 software that must return to Real mode after accessing extended memory in Protected mode. The assertion of INIT causes the processor to empty its pipelines, initialize most of its internal state, and branch to address FFFF_FFFOhthe same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMxX state, Model-Specific Registers (MSRs), the CD and NW bits of the CRO register, the time stamp counter, and other specific internal resources. Figure 76 shows an example in which the operating system writes to an I/O port, causing the system logic to assert INIT. The sampling of INIT asserted starts an extended microcode sequence that terminates with a code fetch from FFFF_FFF0h, the reset location. INIT is sampled on every clock edge but is not recognized until the next instruction boundary. During an I/O write cycle, it must be sampled asserted a minimum of three clock edges before BRDY# is sampled asserted if it is to be recognized on the boundary between the I/O write instruction and the following instruction. If INIT is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. 170 Bus Cycles Chapter 5Preliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet INIT Sampled Asserted Code Fetch CLK ADP DPD PPD PPS MN A133] CX % X BE[7:0]4 X S X ADSH LS SL MO# \ DICH __ \ wRe / 5 D[63:0] }+{ s (XXX }- KEN# V/ BRDY# / \ a INIT / \ Figure 76. INIT-Initiated Transition from Protected Mode to Real Mode Chapter 5 Bus Cycles 171AMDd@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 172 Bus Cycles Chapter 5Preliminary Information AMDZI 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Power-on Configuration and Initialization On power-on the system logic must reset the AMD-K6-2 processor by asserting the RESET signal. When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the MMX and 3DNow! states, and all registers. Then the processor jumps to address FFFF_FFFOh to start instruction execution. Signals Sampled During the Falling Transition of RESET FLUSH# BF[2:0] BRDYC# FLUSH# is sampled on the falling transition of RESET to determine if the processor begins normal instruction execution or enters Tri-State Test mode. If FLUSH# is High during the falling transition of RESET, the processor unconditionally runs its Built-In Self Test (BIST), performs the normal reset functions, then jumps to address FFFF_FFFOh to start instruction execution. (See Built-In Self-Test (BIST) on page 217 for more details.) If FLUSH# is Low during the falling transition of RESET, the processor enters Tri-State Test mode. (See Tri-State Test Mode on page 218 and FLUSH# (Cache Flush) on page 103 for more details.) The internal operating frequency of the processor is determined by the state of the bus frequency signals BF[2:0] when they are sampled during the falling transition of RESET. The frequency of the CLK input signal is multiplied internally by a ratio defined by BF[2:0]. (See BF[2:0] (Bus Frequency) on page 92 for the processor-clock to bus-clock ratios.) BRDYC# is sampled on the falling transition of RESET to configure the drive strength of A[20:3], ADS#, HITM#, and W/R#. If BRDYC# is Low during the fall of RESET, these outputs are configured using higher drive strengths than the standard strength. If BRDYC# is High during the fall of RESET, the standard strength is selected. (See BRDYC# (Burst Ready Copy) on page 95 for more details.) Chapter 6 Power-on Configuration and Initialization 173AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 6.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and Vcc reach specification. (See CLK Switching Characteristics on page 255 for clock specifications. See Electrical Data on page 247 for Vcc specifications.) During a warm reset while CLK and Vcc are within specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 6.3 State of Processor After RESET Output Signals Table 31 shows the state of all processor outputs and bidirectional signals immediately after RESET is sampled asserted. Table 31. Output Signal State After RESET Signal State Signal State A[31:3], AP Floating || LOCK# High ADS#, ADSC# High M/lO# Low APCHK# High PCD Low BE[7:0]# Floating || PCHK# High BREQ Low PWT Low CACHE# High SCYC Low D/C# Low SMIACT# High D[63:0], DP[7:0] Floating TDO Floating FERR# High VCC2DET Low HIT# High VCC2H/L# Low HITM# High W/R# Low HLDA Low - - Registers Table 32 on page 175 shows the state of all architecture registers and Model-Specific Registers (MSRs) after the processor has completed its initialization due to the recognition of the assertion of RESET. 174 Power-on Configuration and Initialization Chapter 6