0.1 GHz to 20 GHz, GaAs, Nonreflective, SP4T Switch HMC641ATCPZ-EP Enhanced Product FUNCTIONAL BLOCK DIAGRAM 4 NIC 5 NIC 6 RF1 GND GND RF2 GND 19 50 50 7 8 9 10 11 12 18 NIC 17 GND 16 CTRLA 15 CTRLB 14 VSS 13 NIC NIC = NOT INTERNALLY CONNECTED PACKAGE BASE GND 16174-001 GND 20 2:4 DECODER 3 21 GND RFC 22 RF3 2 23 GND 1 24 GND NIC GND GND HMC641ATCPZ-EP RF4 Broadband frequency range: 0.1 GHz to 20 GHz Nonreflective 50 design Low insertion loss: 3.0 dB up 20 GHz High isolation: 40 dB up 20 GHz High input linearity at 250 MHz to 20 GHz P1dB: 24 dBm typical, VSS = -5 V IP3: 41 dBm typical High power handling, VSS = -5 V 26.5 dBm through path 23 dBm terminated path Integrated 2 to 4 line decoder 24-lead, 4 mm x 4 mm LFCSP ESD sensitivity, HBM: 250 V (Class 1A) GND FEATURES Figure 1. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range: -55C to +125C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request APPLICATIONS Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems GENERAL DESCRIPTION The HMC641ATCPZ-EP is a general-purpose, nonreflective, single-pole, four-throw (SP4T) switch manufactured using a gallium arsenide (GaAs) process. This switch offers high isolation, low insertion loss, and on-chip termination of the isolated ports. The switch operates with a negative supply voltage range of -5 V to -3 V and requires two negative logic control voltages. Rev. A The HMC641ATCPZ includes an on-chip, binary 2 to 4 line decoder that provides logic control from two logic input lines. The HMC641ATCPZ comes in a 24-lead, 4 mm x 4 mm LFCSP and operates from 0.1 GHz to 20 GHz. Additional application and technical information can be found in the HMC641ALP4E data sheet. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC641ATCPZ-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................4 Enhanced Product Features ............................................................ 1 Pin Configuration and Function Descriptions..............................5 Applications ....................................................................................... 1 Interface Schematics .....................................................................5 Functional Block Diagram .............................................................. 1 Truth Table .....................................................................................6 General Description ......................................................................... 1 Typical Performance Charcteristics ................................................7 Revision History ............................................................................... 2 Outline Dimensions ..........................................................................8 Specifications..................................................................................... 3 Ordering Guide .............................................................................8 Absolute Maximum Ratings ............................................................ 4 Power Derating Curves ................................................................ 4 REVISION HISTORY 11/2017--Rev. 0 to Rev. A Changes to Reflow (MSL3 Rating) Parameter, Table 2................ 4 Changes to Ordering Guide ............................................................ 8 8/2017--Revision 0: Initial Version Rev. A | Page 2 of 8 Enhanced Product HMC641ATCPZ-EP SPECIFICATIONS VSS = -3 V or -5 V, control voltage (VCTRL) = 0 V or VSS, case temperature (TCASE) = 25C, and 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1 to RF4 (On) Symbol f SUPPLY Voltage Current DIGITAL CONTROL INPUTS Voltage Low 1 tRISE, tFALL tON, tOFF P1dB IP3 Typ Max 20 Unit GHz 2.0 3.0 dB dB 42 40 dB dB 0.1 GHz to 12 GHz 12 GHz to 20 GHz 0.1 GHz to 20 GHz 18 17 13 dB dB dB 10% to 90% of radio frequency (RF) output 50% VCTRL to 90% of RF output 250 MHz to 20 GHz VSS = -5 V VSS = -3 V 10 dBm per tone, 1 MHz spacing VSS = -5 V VSS = -3 V VSS pin 30 100 ns ns 24 22 dBm dBm 41 41 dBm dBm 0.1 GHz to 12 GHz 12 GHz to 20 GHz RETURN LOSS RFC and RF1 to RF4 (On) Third-Order Intercept Min 0.1 0.1 GHz to 12 GHz 12 GHz to 20 GHz ISOLATION Between RFC and RF1 to RF4 (Off ) RF1 to RF4 (Off ) SWITCHING Rise Time and Fall Time On Time and Off Time INPUT LINEARITY 1 1 dB Power Compression Test Conditions/Comments VSS ISS 30 30 20 -5 1.7 -3 5 V mA 0 0 -4.2 -2.2 V V V V CTRLA and CTRLB pins VCTRL VINL High VINH Current Low High ICTRL IINL IINH VSS = -5 V VSS = -3 V VSS = -5 V VSS = -3 V -3 -1 -5 -3 30 0.5 Input linearity performance degrades at frequencies less than 250 MHz. Rev. A | Page 3 of 8 A A HMC641ATCPZ-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS For recommended operating conditions, see Table 1. POWER DERATING CURVES Table 2. Figure 2 shows power derating vs. frequency at <250 MHz, and Figure 3 shows the maximum power dissipation vs. the case temperature. Rating -7 V VSS - 0.5 V to + 1 V 2 POWER DERATING (dB) 0 26.5 dBm 23 dBm 20 dBm 21 dBm 20 dBm 17 dBm -2 -4 -6 150C -55C to +125C -65C to +150C 260C -10 0.01 0.1 16174-002 -8 1 FREQUENCY (GHz) Figure 2. Power Derating at Frequencies Less than 250 MHz 30 VSS = -5V THROUGH 250 V (Class 1A) For power derating at frequencies less than 250 MHz, see Figure 2, and for the maximum input power vs. the case temperature, see Figure 3. 2 See the Ordering Guide section. 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 28 26 TERMINATED 24 22 20 18 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMPERATURE (C) Figure 3. Maximum Input Power vs. Case Temperature (TCASE) ESD CAUTION Rev. A | Page 4 of 8 16174-003 201C/W 321C/W MAXIMUM INPUT POWER (dBm) Parameter Negative Supply Voltage (VSS) Digital Control Input Voltage RF Input Power1 (f = 250 MHz to 20 GHz, TCASE = 85C) VSS = -5 V Through Path Terminated Path Hot Switching VSS = -3 V Through Path Terminated Path Hot Switching Temperature Junction, TJ Case, TCASE Storage Reflow (MSL3 Rating)2 Junction to Case Thermal Resistance, JC Through Path Terminated Path Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Enhanced Product HMC641ATCPZ-EP NIC 1 18 NIC 17 GND 16 CTRLA 15 CTRLB NIC 5 14 VSS NIC 6 13 NIC 7 8 9 GND RF4 GND GND 4 RF3 11 TOP VIEW (Not to Scale) GND 12 RFC 3 HMC641ATCPZ-EP GND 10 GND 2 NOTES 1. NIC = NOT INTERNALLY CONNECTED. THE PINS ARE NOT CONNECTED INTERNALLY; HOWEVER, ALL DATA SHOWN IN THIS DATA SHEET IS MEASURED WITH THESE PINS CONNECTED TO RF/DC GROUND EXTERNALLY. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PCB. 16174-004 20 RF2 19 GND 22 GND 21 GND 24 GND 23 RF1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 5, 6, 13, 18 Mnemonic NIC 2, 4, 7, 9, 10, 12, 17, 19, 21, 22, 24 3 GND 8 RF4 11 RF3 14 15 16 20 VSS CTRLB CTRLA RF2 23 RF1 RFC EPAD Description Not Internally Connected. The pins are not connected internally; however, all data shown in this data sheet is measured with these pins connected to RF/dc ground externally. Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB). RF Common Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. RF4 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. RF3 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. Negative Supply Voltage Pin. See Figure 6 for the interface schematic. Control Input 2 Pin. See Table 4 for the control voltage truth table. See Figure 6 for the interface schematic. Control Input 1 Pin. See Table 4 for the control voltage truth table. See Figure 6 for the interface schematic. RF2 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. RF1 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB. INTERFACE SCHEMATICS 500 100k VSS Figure 5. RFC to RF4 Interface Schematic 16174-006 CTRLA, CTRLB 16174-005 RFC, RF1, RF2, RF3, RF4 Figure 6. CTRLA, CTRLB, and VSS Interface Schematic Rev. A | Page 5 of 8 HMC641ATCPZ-EP Enhanced Product TRUTH TABLE Table 4. Control Voltage Truth Table Digital Control Input CTRLA CTRLB High High Low High High Low Low Low RFC to RF1 Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) RFC to RF2 Isolation (off ) Insertion loss (on) Isolation (off ) Isolation (off ) Rev. A | Page 6 of 8 RF Paths RFC to RF3 Isolation (off ) Isolation (off ) Insertion loss (on) Isolation (off ) RFC to RF4 Isolation (off ) Isolation (off ) Isolation (off ) Insertion loss (on) Enhanced Product HMC641ATCPZ-EP TYPICAL PERFORMANCE CHARCTERISTICS 0 +125C +85C +25C -55C INSERTION LOSS (dB) -1 -2 -3 -5 0 4 8 12 16 FREQUENCY (GHz) 20 24 16174-007 -4 Figure 7. Insertion Loss Between RFC and RF1 vs. Frequency for Various Temperatures Rev. A | Page 7 of 8 HMC641ATCPZ-EP Enhanced Product OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 1 0.50 BSC 2.70 2.60 SQ 2.50 EXPOSED PAD 13 0.50 0.40 0.30 TOP VIEW 0.90 0.85 0.80 PKG-005268 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 18 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8. 10-04-2016-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 8. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.85 mm Package Height (CP-24-22) Dimensions shown in millimeters ORDERING GUIDE Model 1 HMC641ATCPZ-EP-PT HMC641ATCPZ-EP-RL7 1 2 Temperature Range -55C to +125C -55C to +125C MSL Rating 2 MSL3 MSL3 Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Z = RoHS Compliant Part. See the Absolute Maximum Ratings section. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16174-0-11/17(A) Rev. A | Page 8 of 8 Package Option CP-24-22 CP-24-22