0.1 GHz to 20 GHz, GaAs,
Nonreflective, SP4T Switch
Enhanced Product
HMC641ATCPZ-EP
Rev. A Document Feedback
Information
furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Broadband frequency range: 0.1 GHz to 20 GHz
Nonreflective 50 Ω design
Low insertion loss: 3.0 dB up 20 GHz
High isolation: 40 dB up 20 GHz
High input linearity at 250 MHz to 20 GHz
P1dB: 24 dBm typical, VSS = −5 V
IP3: 41 dBm typical
High power handling, VSS = −5 V
26.5 dBm through path
23 dBm terminated path
Integrated 2 to 4 line decoder
24-lead, 4 mm × 4 mm LFCSP
ESD sensitivity, HBM: 250 V (Class 1A)
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications
(AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
NIC
NIC = NOT INT E RNALL Y CONNECTED
GND
RFC
GND
NIC
NIC NIC
V
SS
CTRLB
CTRLA
GND
NIC
GND
RF4
GND
GND
RF3
GND GND
RF2
GND
GND
RF1
GND
50Ω
50Ω
2:4 DECO DE R
HMC641ATCPZ-EP
PACKAGE
BASE
GND
1
2
3
4
5
6
24 23 22 21 20 19
78 9 10 11 12
18
17
16
15
14
13
16174-001
Figure 1.
GENERAL DESCRIPTION
The HMC641ATCPZ-EP is a general-purpose, nonreflective,
single-pole, four-throw (SP4T) switch manufactured using a
gallium arsenide (GaAs) process. This switch offers high
isolation, low insertion loss, and on-chip termination of the
isolated ports.
The switch operates with a negative supply voltage range of −5 V to
−3 V and requires two negative logic control voltages.
The HMC641ATCPZ includes an on-chip, binary 2 to 4 line
decoder that provides logic control from two logic input lines.
The HMC641ATCPZ comes in a 24-lead, 4 mm × 4 mm LFCSP
and operates from 0.1 GHz to 20 GHz.
Additional application and technical information can be found
in the HMC641ALP4E data sheet.
HMC641ATCPZ-EP Enhanced Product
Rev. A | Page 2 of 8
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Power Derating Curves ................................................................ 4
ESD Caution...................................................................................4
Pin Configuration and Function Descriptions ..............................5
Interface Schematics .....................................................................5
Truth Table .....................................................................................6
Typical Performance Charcteristics ................................................7
Outline Dimensions ..........................................................................8
Ordering Guide .............................................................................8
REVISION HISTORY
11/2017—Rev. 0 to Rev. A
Changes to Reflow (MSL3 Rating) Parameter, Table 2 ................ 4
Changes to Ordering Guide ............................................................ 8
8/2017—Revision 0: Initial Version
Enhanced Product HMC641ATCPZ-EP
Rev. A | Page 3 of 8
SPECIFICATIONS
VSS = −3 V or −5 V, control voltage (VCTRL) = 0 V or VSS, case temperature (TCASE) = 25°C, and 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE f 0.1 20 GHz
INSERTION LOSS
Between RFC and RF1 to RF4 (On) 0.1 GHz to 12 GHz 2.0 dB
12 GHz to 20 GHz 3.0 dB
ISOLATION
Between RFC and RF1 to RF4 (Off)
0.1 GHz to 12 GHz
30
42
dB
12 GHz to 20 GHz 30 40 dB
RETURN LOSS
RFC and RF1 to RF4 (On) 0.1 GHz to 12 GHz 18 dB
12 GHz to 20 GHz 17 dB
RF1 to RF4 (Off) 0.1 GHz to 20 GHz 13 dB
SWITCHING
Rise Time and Fall Time
t
RISE
, t
FALL
10% to 90% of radio frequency (RF) output
30
ns
On Time and Off Time tON, tOFF 50% VCTRL to 90% of RF output 100 ns
INPUT LINEARITY1 250 MHz to 20 GHz
1 dB Power Compression P1dB VSS = −5 V 20 24 dBm
VSS = −3 V 22 dBm
Third-Order Intercept IP3 10 dBm per tone, 1 MHz spacing
VSS = −5 V 41 dBm
VSS = −3 V 41 dBm
SUPPLY VSS pin
Voltage VSS −5 −3 V
Current ISS 1.7 5 mA
DIGITAL CONTROL INPUTS CTRLA and CTRLB pins
Voltage VCTRL
Low VINL VSS = −5 V −3 0 V
VSS = −3 V −1 0 V
High VINH VSS = −5 V −5 −4.2 V
VSS = −3 V −3 −2.2 V
Current ICTRL
Low IINL 30 µA
High IINH 0.5 µA
1 Input linearity performance degrades at frequencies less than 250 MHz.
HMC641ATCPZ-EP Enhanced Product
Rev. A | Page 4 of 8
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Negative Supply Voltage (VSS) −7 V
Digital Control Input Voltage VSS − 0.5 V to + 1 V
RF Input Power1 (f = 250 MHz to 20 GHz,
TCASE = 85°C)
VSS = −5 V
Through Path 26.5 dBm
Terminated Path
23 dBm
Hot Switching 20 dBm
VSS = −3 V
Through Path 21 dBm
Terminated Path 20 dBm
Hot Switching 17 dBm
Temperature
Junction, TJ 150°C
Case, TCASE −55°C to +125°C
Storage −65°C to +150°C
Reflow (MSL3 Rating)2 260°C
Junction to Case Thermal Resistance, θJC
Through Path 201°C/W
Terminated Path 321°C/W
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
1 For power derating at frequencies less than 250 MHz, see Figure 2, and for
the maximum input power vs. the case temperature, see Figure 3.
2 See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
POWER DERATING CURVES
Figure 2 shows power derating vs. frequency at <250 MHz,
and Figure 3 shows the maximum power dissipation vs. the case
temperature.
2
–10 0.10.01 1
POWER DE RATI NG (dB)
FREQUENCY ( GHz)
–8
–6
–4
–2
0
16174-002
Figure 2. Power Derating at Frequencies Less than 250 MHz
30
18
–60 –40 –20 020 40 60 80 100 120
MAXIMUM INPUT POWER (dBm)
CASE TEMPERATURE (°C)
20
22
24
26
28
16174-003
VSS = –5V
TERMINATED
THROUGH
Figure 3. Maximum Input Power vs. Case Temperature (TCASE)
ESD CAUTION
Enhanced Product HMC641ATCPZ-EP
Rev. A | Page 5 of 8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NIC
GND
RFC
GND
NIC
NIC NIC
V
SS
CTRLB
CTRLA
GND
NIC
GND
RF4
GND
GND
RF3
GND GND
RF2
GND
GND
RF1
GND
HMC641ATCPZ-EP
TOP VIEW
(Not to Scale)
19
20
21
22
23
24
13
14
15
16
17
18
1
3
4
2
5
6
7
8
9
10
11
12
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THE PINS ARE
NOT CONNECTED INTERNALLY; HOWEVER, ALL DATA
SHOWN IN THIS DATA SHEET IS MEASURED WITH
THESE PINS CONNECTED TO RF/DC GROUND
EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF/DC GROUND OF THE PCB.
16174-004
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 5, 6, 13, 18 NIC Not Internally Connected. The pins are not connected internally; however, all data shown in this data sheet
is measured with these pins connected to RF/dc ground externally.
2, 4, 7, 9, 10, 12, 17,
19, 21, 22, 24
GND Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB).
3 RFC
RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
8 RF4
RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
11 RF3
RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
14 VSS Negative Supply Voltage Pin. See Figure 6 for the interface schematic.
15 CTRLB Control Input 2 Pin. See Table 4 for the control voltage truth table. See Figure 6 for the interface schematic.
16 CTRLA Control Input 1 Pin. See Table 4 for the control voltage truth table. See Figure 6 for the interface schematic.
20 RF2
RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
23 RF1
RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
16174-005
Figure 5. RFC to RF4 Interface Schematic
500Ω
CTRLA,
CTRLB
V
SS
100kΩ
16174-006
Figure 6. CTRLA, CTRLB, and VSS Interface Schematic
HMC641ATCPZ-EP Enhanced Product
Rev. A | Page 6 of 8
TRUTH TABLE
Table 4. Control Voltage Truth Table
Digital Control Input RF Paths
CTRLA
CTRLB
RFC to RF1
RFC to RF2
RFC to RF3
RFC to RF4
High High Insertion loss (on) Isolation (off) Isolation (off) Isolation (off)
Low
High
Isolation (off )
Insertion loss (on)
Isolation (off )
Isolation (off )
High Low Isolation (off) Isolation (off) Insertion loss (on) Isolation (off)
Low Low Isolation (off) Isolation (off) Isolation (off ) Insertion loss (on)
HMC641ATCPZ-EP Enhanced Product
Rev. A | Page 8 of 8
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-220- V GG D- 8.
BOTTOM VIEW
TOP VIEW
4.10
4.00 SQ
3.90
0.90
0.85
0.80 0. 05 M AX
0.02 NO M
0.203 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FO R P ROPE R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
10-04-2016-A
0.30
0.25
0.18
0.20 M I N
2.70
2.60 SQ
2.50
EXPOSED
PAD
PKG-005268
SEATING
PLANE
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 8. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range
MSL
Rating2 Package Description
Package
Option
HMC641ATCPZ-EP-PT −55°C to +125°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-22
HMC641ATCPZ-EP-RL7 −55°C to +125°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-22
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16174-0-11/17(A)
