SCD8691 Rev E
11
12
10
❑Radiation performance
- Total dose: 100 krads(Si),
Dose rate = 50 - 300 rads(Si)/s
❑Output voltage adjustable: 1.0V to 3.3V
❑Output current: 7.5A
❑Dropout voltage: 0.5V at 7.5Amps
❑Voltage reference: 1.0V ±0.5%
❑Load regulation: 0.5% max
❑Line regulation: 0.2% max
❑Ripple rejection: >66dB
❑Enable Input - TTL / CMOS Compatible
❑Slow Start capability
❑Packaging – Hermetic metal
- Thru-hole or Surface mount
- 12 Leads, 1.0"W x 0.9"L x .220"Ht
- Power package
- Weight - 18 gm max
❑Designed for aerospace and high reliability space
applications
❑DSCC SMD 5962-09237 Pending
DESCRIPTION
The Aeroflex Plainview VRG869 1/92 is capable of sup plying in excess of 7.5Am ps over the output voltag e range as
defined under recommended operating conditions. The regulator is exceptionally easy to set-up, requiring only 2
external resistors to set the output voltage. The module design has been optimized for excellent regulation and low
drop-out voltage. Figures 2 through 5 illustrate settin g output voltage, set tin g current limit s and choosin g a slow start
capacitor. The VRG8691/92 serves a wide variety of appl ications including local on-card regulat ion, programmable
output voltage regulation or precision current regulation.
The VRG8691/92 has been specifically designed to meet exposure to radiation environments. The VRG8691 is
configured for a Thru-Hole 12 lead metal power package and the VRG8692 is configured for a Surface Mount 12 lead
metal power package. It is guaranteed operational from -55°C to +125°C. Available screened to MIL-STD-883, the
VRG8691/92 is ideal for demanding military and space applications.
CURRENT LIMIT (ICL)
The VRG8691/92 features internal current limiting making them virtually blowout-proof against overloads. The limit
is nominally 11.5A @ Vin = 5V (see Table 2), but may be increased or decreased with the addition of one external
resistor (see Application Note 2). When the load current exceeds the ICL setting, the o utput of the VRG869 1/92 will
be latched in an OFF state. To reset the latch condition, the ENABLE function (pin 5) can be cycled, enabled -
disabled - enabled, or the VBIAS may be cycled ON - OFF - ON (if the Figure 5 configuration is being utilized).
VRG8691/92
Radiation Tolerant
FIGURE 1 – BLOCK DIAGRAM / SCHEMATIC
June 14, 2010
www.aeroflex.com/voltreg
Standard Products
NOTE: Aeroflex Plainview does not currently have a DSCC certified Radiation Hardened Assurance Program
Adjustable 7.5A Positive LDO Regulator
FEATURES
8
VRG8691/92 9
6
5
4
V
OUT
V
SENSE
Current Limit
GND
ENABLE
V
BIAS
V
IN
7
Slow Start
2
1
3
2
SCD8691 Rev E 6/14/10 Aeroflex Plainview
ABSOLUTE MAXIMUM RATINGS
PARAMETER RANGE UNITS
Operating (Junction) Temperature Range -55 to +150 °C
Lead Temperature (soldering, 10 sec) 300 °C
St orage Temperature Range -65 to +150 °C
VBIAS, VIN 7V
Thermal Resistance (Junction to case JC)1°C/W
Power 25 1/W
1/ Based on pass transistor limitations of (VIN - VO) x IO and JC < 1°C/W with 25°C max TJ rise and TC = +125°C.
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only; functional operation beyond the “Operation Conditions” is not recommended and extended exposure beyond the “Operation
Conditions” may effect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER RANGE UNITS
Output Voltage Range 1.0 to 3.3 VDC
Case Operating Temperature Range -55 to +125 °C
Output Current 0 to 7.5 A
VBIAS 3.3 to 5.5 1/VDC
VIN 1.8 to 5.5 2/VDC
1/ VBIAS must maintain a level equal or above VIN but not fall below 3.3V
2/ Depending upon VOUT setting.
ELECTRICAL PERFORMANCE CHARACTERISTICS 1/
PARAMETER SYM CONDITIONS MIN MAX UNITS
Reference Vo ltage VREF VIN = VBIAS = 5V, ENABLE = 0, 0A < IOUT < 7.5A 0.995 1.005 V
Line Regulation 2V < VIN < 3V, VOUT = 1.0V,
4.3V < VIN < 5.3V, VOUT = 3.3V, -0.2%/V
Load Regulation 0A < IOUT < 7.5A - 0.5 %
Ripple Rejection Ratio f = 120Hz, CLOAD = 47µF 66 - dB
Dropout Voltage VDROP @VOUT = 1%, 0A < IOUT < 7.5A - 0.5 V
Adjustment Pin Current IADJ -3µA
Minimum Load Curren t IMIN -0mA
Current Limit 2/ICL 9.5 13.5 A
Long Term Stability 3/-1%
Supply Current (VBIAS)IBIAS -15mA
Notes:
1/ Unless otherwise specified, these sp ecifications apply for post radiation: V
BIAS
= V
IN
= 5V, V
OUT
= 3.3V, I
OUT
= 7.5A and -55°C < Tc <+125°C.
2/ Current Limit is adjustable as shown in Application Note 2, Figures 3 and 4.
3/ Not tested. Shall be guaran teed to the specified limits after 1 000hr life test.
VOUT
VIN
VOUT
IOUT
VOUT
TIME
3
SCD8691 Rev E 6/14/10 Aeroflex Plainview
VRG8691/92
V
IN
VOUT
VSENSE
R1
R2
VREF (=1V)
CURR. LIMIT
10
11
12
4
3
2
1
8
ENABLE
69
IADJ
7
5
0.1µF
47µF +
VBIAS
S
LOW
S
TART
VBIAS
VIN
CURR. LIMIT
GND
0.1µF
FIGURE 2 –SETTING OUTPUT VOLTAGE
ENABLE 1/
Notes:
1/ ENABLE should be asserted after both VIN and VBIAS are applied.
(See Application Note 3, Figure 5 for the configuration where a separate ENABLE control line is NOT required).
2/ ICL varies directly with VIN.
(See Application Note 2 for adjusting the Current Limit, ICL).
To set the output voltage for a particular Vout:
- Choose an R2 value. (Recommended value = 1k
- Then use the following formula to determine the value of R1.
Table 1 shows example values for R1 and R2 to achieve some standard volt ages.
Table 2 shows the nominal current limit settings if the ’CURR. LIMIT’ function (pin 8) is left open.
CLOAD
10µF
VOUT
+
Table 2
2/
VIN ICL NOM
5V 11.5A
3.3V 7.5A
2.5V 5.7A
1.8V 4.1A
Table 1
Example R1 & R2 for typical VOUT
VOUT R2 R1
3.3V 1k2.3k
2.5V 1k1.5k
1.8V 1k800
1.0V 1k0
APPLICATION NOTE 1
BASIC SET-UP
Setting the output voltage (VOUT):
VOUT - VREF
(R2 x IADJ) + VREF
R1 = R2 x , where VREF = 1v
4
SCD8691 Rev E 6/14/10 Aeroflex Plainview
VRG8691/92
V
IN
VOUT
VSENSE
R1
R2
VREF (=1V)
CURR. LIMIT
RINC
10
11
12
4
3
2
1
8
ENABLE
69
IADJ
7
5
0.1µF
47µF +
VBIAS
S
LOW
S
TART
VBIAS
VIN
GND
0.1µF
FIGURE 3 – INCREASING THE CURRENT LIMIT (ICL)
ENABLE
- If the ’CURR. LIMIT’ fu nction (pin 8) is left op en, the ICL decreases from 11.5 A(NOM) as V IN is decreased from 5V (Table 3).
- To increase the current limit above the nominal setting for any VIN and ICL combination, use the following formula:
- To maintain ICL at the 11.5 A setting , fo r com m o nly fo un d VIN voltages, apply RINC value found in Table 4.
Table 3
VIN RINC ICL NOM
5V Open 11.5 A
3.3V Open 7.5 A
2.5V Open 5.7 A
1.8V Open 4.1 A
Table 4
VIN RINC ICL NOM
5V Open 11.5 A
3.3V 56k11.5 A
2.5V 30k11.5 A
1.8V 16k11.5 A
CLOAD
10µF
VOUT
+
APPLICATION NOTE 2
SETTING THE CURRENT LIMIT
To Increase the Current Limit (ICL):
RINC(K-OHMS) = 30 x VIN
30 x ICL
69 - VIN
()
5
SCD8691 Rev E 6/14/10 Aeroflex Plainview
VRG8691/92
V
IN
VOUT
VSENSE
R1
R2
VREF (=1V)
CURR. LIMIT
10
11
12
4
3
2
1
8
ENABLE
69
IADJ
7
5
0.1µF
47µF +
VBIAS
S
LOW
S
TART
VBIAS
VIN
CURR. LIMIT
GND
0.1µF
ENABLE
- As shown in Table 3, if the ’CURR. LIMIT’ function (pin 8) is left open, the ICL decreases from 11.5 A(NOM) as VIN is
decreased from 5V.
- To achieve any ICL, less than nom i na l, use RDEC which can be calculated using the following formula:
RDEC
FIGURE 4 – DECREASING THE CURRENT LIMIT (ICL)
CLOAD
10µF
VOUT
+
APPLICATION NOTE 2 (CONTINUED)
SETTING THE CURRENT LIMIT
To Decrease the Current Limit (ICL):
RDEC(K-OHMS) = 31 x VIN
69 x VIN
30 - ICL
()
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SCD8691 Rev E 6/14/10 Aeroflex Plainview
VRG8691/92
V
IN
VOUT
VSENSE
R1
R2
VREF (=1V)
CURR. LIMIT
10
11
12
4
3
2
1
8
ENABLE
69
IADJ
7
5
CLOAD
0.1µF
47µF
+
10µF
VBIAS
S
LOW
S
TART
VOUT
VBIAS
VIN
GND
0.1µF
CDELAY
+
FIGURE 5 – DELAYED ENABLE
+
+
++
APPLICATION NOTE 3
START UP SEQUENCE
Recommended Power Supply Sequencing Options:
- OPTION 1: Controlling the ENABLE line with a Digital signal (TTL / CMOS comp atible).
- Prior to applying power, disable the regulator by setting the ENABLE control line to a HIGH state.
- Apply VIN and VBIAS. 1/
- Wait until both VIN and VBIAS supplies have reached their operating levels.
- Toggle the ENABLE control line to a LO W state to turn on VOUT of the regulator.
- OPTION 2: Controlling the ENABLE line using the CDELAY feature.
- Connect a CDELAY capacitor between VBIAS and the ENABLE as shown in Figure 5 below. 2/
- Apply VIN and VBIAS. 1/
- CDELAY causes the regulator to self-enable after VBIAS has reached operating level.
NOTE: The ENABLE should always be asserted AFTER VIN and VBIAS have reached operating level.
NOTES:
1/ VIN should be applied before VBIAS if the Slow Start feature is used.
2/ CDELAY capacitor of 10uF is adequate for VBIAS rise times of up to 50ms.
1/
2/
7
SCD8691 Rev E 6/14/10 Aeroflex Plainview
FIGURE 6 – SLOW START
VRG8691/92
V
IN
VOUT
VSENSE
R1
R2
V
REF
(=1
V
)
CURR. LIMIT
10
11
12
4
3
2
1
8
ENABLE
69
IADJ
7
5
CLOAD
0.1µF
47µF +
10µF
VBIAS
S
LOW
S
TART
VOUT
VBIAS
VIN
GND
0.1µF
+
0CSS
+
ENABLE
If it is desirable to control the output rise time, a capacitor (CSS) can be asserted on the Slow Start pin to adjust the rise
time for the following:
A. Large load capacitance will cause high surge currents which will trip the current limit circuitry.
The use of CSS will allow the output voltage to rise slowly thus mitigate the surge current phenomenon.
B. CSS may be used solely to control VOUT RISE TIME (Tr), when CLOAD is not an issue.
C. CSS is effective only when VIN is applied prior to VBIAS or ENABLE.
>
CSS
CLOAD 0.4 X VBIAS
1300
X
VOUT NOM
ICL - ILOAD NOM
Note: CSS in Farads and TR in seconds.
TR = VBIAS
VBIAS - 2.5
()
CSS X 1300 X LN
APPLICATION NOTE 4
VOUT START UP RISE TIME CONTROL
Utilizing the Slow Start option:
When the VRG8691/92 is first powered up, using the Sl ow Start function controls the rate at which VOUT rises to the
required voltage set by R1 and R2.
Note: VIN should be applied before VBIAS when the Slow Start feature is used.
8
SCD8691 Rev E 6/14/10 Aeroflex Plainview
FIGURE 3 – PACKAGE OUTLINE — VRG8691 THRU-HOLE POWER PACKAGE
PIN NUMBERS vs FUNCTION
PIN FUNCTION PIN FUNCTION
1V
IN 7Slow Start
2V
IN 8 Current Limit
3V
IN 9VSENSE
4VBIAS 10 VOUT
5ENABLE 11 VOUT
6 GROUND 12 VOUT
Notes:
1. Dimension Tolerance: ±.005 inches
2. Package contains BeO substrate
3. Case electrically isolated
9
SCD8691 Rev E 6/14/10 Aeroflex Plainview
Notes:
FIGURE 4 – PACKAGE OUTLINE — VRG8692 SURFACE MOUNT POWER PACKAGE
1. Dimension Tolerance: ±.005 inches
2. Package contains BeO substrate
3. Case electrically isolated
PIN NUMBERS vs FUNCTION
PIN FUNCTION PIN FUNCTION
1V
IN 7Slow Start
2V
IN 8 Current Limit
3V
IN 9VSENSE
4VBIAS 10 VOUT
5 ENABLE 11 VOUT
6 GROUND 12 VOUT
10
SCD8691 Rev E 6/14/10
PLAINVIEW, NEW YORK
Toll Free: 800-THE-1553
Fax: 516-694-6715
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
WEST COAST
Tel: 949-362-2260
Fax: 949-362-2266
NORTHEAST
Tel: 603-888-3975
Fax: 603-888-4585
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com info-ams@aeroflex.com
Aeroflex Microelectronic Solutions reserves t he right to
change at any time without notice the specifications, design,
function, or form of its products described herein. All
parameters must be validated for each customer's application
by engineering. No liab ility is assumed as a result of use of
this product. No patent licenses are implied.
Our passion for performance is defined by three
attributes represented by these three icons:
solution-minded, perform a nce -driven and cu stom e r-foc use d
EXPORT CONTROL: EXPOR T WARNING:
This product is controlled for export under the International Traffic in
Arms Regulations (ITAR). A license from the U.S. Department of
State is required prior to the export of this product from the United
States.
Aeroflex’s military and space products are controlled for export under
the International Traffic in Arms Regulations (ITAR) and may not be
sold or proposed or offered for sale to certain countries. (See ITAR
126.1 for complete information.)
ORDERING INFORMATION
MODEL DSCC SMD # SCREENING PACKAGE
VRG8691-S - Military Temperature, -55°C to +125°C
Screened in accordance with MIL-PRF-38534, Class K 12 Lead Thru-Hole
Power Pkg
VRG8691-7 - Commercial Fl ow, +25°C testing only
VRG8692-S - Military Temperature, -55°C to +125°C
Screened in accordance with MIL-PRF-38534, Class K 12 Lead Surface
Mount Power Pkg
VRG8692-7 - Commercial Fl ow, +25°C testing only
VRG8691-201-1S
VRG8691-201-2S 5962-0923701KXC
5962-0923701KXA In accordance with DSCC SMD 12 Lead Thru-Hole
Power Pkg
VRG8692-201-1S
VRG8692-201-2S 5962-0923701KYC
5962-0923701KYA In accordance with DSCC SMD 12 Lead Surface
Mount Power Pkg
