©2002 Fairchild Semiconductor Corporation
January 2002
Rev. B January 2002
ISL9N302AP3
ISL9N302AP3
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
Features
• Fast switching
•r
DS(ON)
= 0.0019
Ω
(Typ), V
GS
= 10V
•r
DS(ON)
= 0.0027
Ω
(Typ), V
GS
= 4.5V
•Q
g
(Typ) = 110nC, V
GS
= 5V
•Q
gd
(Typ) = 31nC
•C
ISS
(Typ) = 11000pF
MOSFET Maximum Ratings
T
A
= 25°C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
V
DSS
Drain to Source Voltage 30 V
V
GS
Gate to Source Voltage
±
20 V
I
D
Drain Current
75 A
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
= 100
o
C, V
GS
= 4.5V) 75 A
Pulsed Figure 4 A
P
D
Power dissipation
Derate above 25
o
C
345
2.3
W
W/
o
C
T
J
, T
STG
Operating and Storage Temperature -55 to 175
o
C
R
θ
JC
Thermal Resistance Junction to Case TO-220 0.43
o
C/W
R
θ
JA
Thermal Resistance Junction to Ambient TO-220 62
o
C/W
Device Marking Device Package Reel Size Tape Width Quantity
N302AP ISL9N302AP3 TO-220AB Tube N/A 50
D
G
S
TO-220AB
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
(V
GS
= 4.5V)
Switching Characteristics
(V
GS
= 10V)
Unclamped Inductive Switching
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
B
VDSS
Drain to Source Breakdown Voltage I
D
= 250
µ
A, V
GS
= 0V 30 - - V
I
DSS
Zero Gate Voltage Drain Current V
DS
= 25V - - 1
µ
A
V
GS
= 0V T
C
= 150
o
- - 250
I
GSS
Gate to Source Leakage Current V
GS
=
±
20V - -
±
100 nA
V
GS(TH)
Gate to Source Threshold Voltage V
GS
= V
DS
, I
D
= 250
µ
A1-3V
r
DS(ON)
Drain to Source On Resistance I
D
= 75A, V
GS
= 10V - 0.0019 0.0025
Ω
I
D
= 75A, V
GS
= 4.5V - 0.0027 0.0033
C
ISS
Input Capacitance V
DS
= 15V, V
GS
= 0V,
f = 1MHz
- 11000 - pF
C
OSS
Output Capacitance - 2000 - pF
C
RSS
Reverse Transfer Capacitance - 900 - pF
Q
g(TOT)
Total Gate Charge at 10V V
GS
= 0V to 10V
V
DD
= 15V
I
D
= 75A
I
g
= 1.0mA
200 300 nC
Q
g(5)
Total Gate Charge at 5V V
GS
= 0V to 5V - 110 165 nC
Q
g(TH)
Threshold Gate Charge V
GS
= 0V to 1V - 12 18 nC
Q
gs
Gate to Source Gate Charge - 25 - nC
Q
gd
Gate to Drain “Miller” Charge - 31 - nC
t
ON
Turn-On Time
V
DD
= 15V, I
D
= 28A
V
GS
= 4.5V, R
GS
= 1.5
Ω
- - 224 ns
t
d(ON)
Turn-On Delay Time - 29 - ns
t
r
Rise Time - 120 - ns
t
d(OFF)
Turn-Off Delay Time - 45 - ns
t
f
Fall Time - 34 - ns
t
OFF
Turn-Off Time - - 119 ns
t
ON
Turn-On Time
V
DD
= 15V, I
D
= 28A
V
GS
= 10V, R
GS
= 1.5
Ω
- - 204 ns
t
d(ON)
Turn-On Delay Time - 16 - ns
t
r
Rise Time - 120 - ns
t
d(OFF)
Turn-Off Delay Time - 70 - ns
t
f
Fall Time - 30 - ns
t
OFF
Turn-Off Time - - 150 ns
t
AV
Avalanche Time I
D
= 7.2A, L = 3.0mH 480 - -
µ
s
V
SD
Source to Drain Diode Voltage I
SD
= 75A - - 1.25 V
I
SD
= 40A - - 1.0 V
t
rr
Reverse Recovery Time I
SD
= 75A, dI
SD
/dt = 100A/
µ
s- - 42 ns
Q
RR
Reverse Recovered Charge I
SD
= 75A, dI
SD
/dt = 100A/
µ
s- - 34 nC
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
Typical Characteristic
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
0
20
40
60
80
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
VGS = 4.5V
VGS = 10V
0.1
1
10-5 10-4 10-3 10-2 10-1 100101
0.01
2
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
100
1000
10-5 10-4 10-3 10-2 10-1 100101
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
VGS = 5V
5000
50
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
Figure 5. Transfer Characteristics Figure 6. Saturation Characteristics
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Typical Characteristic (Continued)
0
25
50
75
100
125
150
1.5 2.0 2.5 3.0 3.5
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = -55oC
TJ = 175oC
TJ = 25oC
0
25
50
75
100
125
150
0.5 1.0 1.5 2.0
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 4.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 3.5V
TC = 25oC
VGS = 10V
VGS = 3V
0
0
2
4
6
8
10
246810
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 75A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID = 10A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-80 -40 0 40 80 120 160 200
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 75A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-80 -40 0 40 80 120 160 200
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
Figure 13. Switching Time vs Gate Resistance Figure 14. Switching Time vs Gate Resistance
Typical Characteristic (Continued)
1000
10000
0.1 1 10
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
VGS = 0V, f = 1MHz
20000
500
30
0
2
4
6
8
10
50 100 150 200 250
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15V
ID = 75A
ID = 28A
WAVEFORMS IN
DESCENDING ORDER:
0
0
200
400
600
800
1000
0 1020304050
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 15V, ID = 28A
tr
td(ON)
td(OFF)
tf
0
200
400
600
800
1000
1200
1400
10 20 30 40 50
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 10V, VDD = 15V, ID = 28A
td(ON)
tf
tr
0
td(OFF)
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
PSPICE Electrical Model
SUBCKT ISL9N302AP3 2 1 3 ; rev Nov 2001
CA 12 8 9e-9
Cb 15 14 5.5e-9
Cin 6 8 1e-8
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 30.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.618e-9
Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9
RLgate 1 9 56.1
RLdrain 2 5 15
RLsource 3 7 19.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 4e-4
Rgate 9 20 5.93e-1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 1.3e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3))}
.MODEL DbodyMOD D (IS=2e-10 N=1.05 RS=1.8e-3 TRS1=9e-4 TRS2=1e-6 + CJO=4.9e-9 M=4.9e-1 TT=1e-13 XTI=0)
.MODEL DbreakMOD D (RS=2.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=3.5e-9 IS=1e-30 N=10 M=4.7e-1)
.MODEL MstroMOD NMOS (VTO=2.1 KP=550 IS=1e-25 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=1.6 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=5.93e-1)
.MODEL MweakMOD NMOS (VTO=1.22 KP=1e-1 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=5.93 RS=1e-1)
.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7e-7)
.MODEL RdrainMOD RES (TC1=1.2e-2 TC2=2.5e-5)
.MODEL RSLCMOD RES (TC1=3.5e-9 TC2=5e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.9e-3 TC2=-9e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-1.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-3.5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-0.4)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
SABER Electrical Model
REV Nov 2001
template ISL9N302AP3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e-10,nl=1.05,rs=1.8e-3,trs1=9e-4,trs2=1e-6,cjo=4.9e-9,m=4.9e-1,tt=1e-13,xti=0)
dp..model dbreakmod = (rs=2.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=3.5e-9,isl=10e-30,nl=10,m=4.7e-1)
m..model mstrongmod = (type=_n,vto=2.1,kp=550,is=1e-25, tox=1)
m..model mmedmod = (type=_n,vto=1.6,kp=30,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.22,kp=1e-1,is=1e-40, tox=1,rs=1e-1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.5,voff=-1.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-3.5)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.1)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.1,voff=-0.4)
c.ca n12 n8 = 5e-9
c.cb n15 n14 = 5.5e-9
c.cin n6 n8 = 1e-8
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 30.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.618e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 15
res.rlsource n3 n7 = 19.8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7e-7
res.rdrain n50 n16 = 4e-4, tc1=1.2e-2,tc2=2.5e-5
res.rgate n9 n20 = 5.93e-1
res.rslc1 n5 n51 = 1e-6, tc1=3.5e-9,tc2=5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.3e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.9e-3,tc2=-9e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3))
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
SPICE Thermal Model
REV May 2001
TISL9N302AP3
CTHERM1 th 6 4.5e-3
CTHERM2 6 5 2e-2
CTHERM3 5 4 1.5e-2
CTHERM4 4 3 2.5e-2
CTHERM5 3 2 7e-2
CTHERM6 2 tl 2.5e-1
RTHERM1 th 6 2e-3
RTHERM2 6 5 8.5e-3
RTHERM3 5 4 6e-2
RTHERM4 4 3 8e-2
RTHERM5 3 2 9e-2
RTHERM6 2 tl 1e-1
SABER Thermal Model
SABER thermal model TISL9N302AP3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.5e-3
ctherm.ctherm2 6 5 = 2e-2
ctherm.ctherm3 5 4 = 1.5e-2
ctherm.ctherm4 4 3 = 2.5e-2
ctherm.ctherm5 3 2 = 7e-2
ctherm.ctherm6 2 tl = 2.5e-1
rtherm.rtherm1 th 6 =2e-3
rtherm.rtherm2 6 5 = 8.5e-3
rtherm.rtherm3 5 4 = 6e-2
rtherm.rtherm4 4 3 = 8e-2
rtherm.rtherm5 3 2 = 9e-2
rtherm.rtherm6 2 tl = 1e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
Rev. H4
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
STAR*POWER is used under license
VCX™