FLEx36TM 3.3V 32K/64K/128K/256K x 36
Synchronous Dual-Port RAM
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06070 Rev. *G Revised August 15, 2005
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 172-ball FBGA (1 mm pitch) (15 mm × 15 mm)
• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
Functional Description
The FLEx36™ family includes 1M, 2M, 4M and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address,
and data lines allow for minimal set-up and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853A device in this family has limited features.
Please see See “Address Counter and Mask Register
Operations[10]” on page 8. for details.
Table 1. Product Selection Guide
Density
1-Mbit
(32K x 36)
2-Mbit
(64K x 36)
4-Mbit
(128K x 36)
9-Mbit
(256K x 36)
Part Number CY7C0850AV CY7C0851AV CY7C0852AV CY7C0853AV
Max. Speed (MHz) 167 167 167 133
Max. Access Time - Clock to Data (ns) 4.0 4.0 4.0 4.7
Typical operating current (mA) 225 225 225 270
Package 176TQFP
172FBGA
176TQFP
172FBGA
176TQFP
172FBGA
172FBGA
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18
Synchr onous Dual-Por t RAM
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 2 of 31
Note:
1. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.
Logic Block Diagram[1]
A0L–A17L
CLKL
ADSL
CNTENL
CNTRSTL
True
RAM Array
18
Addr.
Read
Back
CNTINTL
Mask Register
Counter/
Address
Register
CNT/MSKL
Address
Decode
Dual-Ported
Interrupt
Logic
INTL
Reset
Logic JTAG TDO
TMS
TCK
TDI
MRST
DQ9L–DQ17L
DQ0L–DQ8L
I/O
Control
9
9
9
9
DQ18L–DQ26L
DQ27L–DQ35L
CE0L
CE1L
R/WL
B0L
B1L
B2L
B3L
OEL
A0R–A17R
CLKR
ADS
CNTEN
CNTRSTR
18
Addr.
Read
Back
CNTINTR
Mask Register
Counter/
Address
Register
CNT/MSKR
Address
Decode
Interrupt
Logic INTR
DQ9R–DQ17R
DQ0R–DQ8R
I/O
Control
9
9
9
9
DQ18R–DQ26R
DQ27R–DQ35R
CE0R
CE1R
R/WR
B0R
B1R
B2R
B3R
OER
Mirror Reg Mirror Reg
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 3 of 31
Pin Configurations
1234567891011121314
ADQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R
BA0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
CNC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC
DA2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R
EA4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R
FVDD A6L A7L B1L VDD VSS B1R A7R A6R VDD
GOEL B2L B3L CE0L CY7C0850V
CY7C0851V
CY7C0852V
CE0R B3R B2R OER
HVSS R/WLA8LCLKL CLKR A8R R/WRVSS
JA9L A10L VSS ADSL VSS VDD ADSR MRST A10R A9R
KA11L A12L A15L[2] CNTRSTL VDD VDD VSS VDD CNTRSTR A15R[2] A12R A11R
LCNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR
MA16L[2] A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R[2]
NDQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
PDQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R
Note:
2. For CY7C0851V, pins M1 and M14 are NC. For CY7C0850V, pins K3, K12 M1, and M14 are NC
Top View
172-ball BGA
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 4 of 31
Pin Configurations (continued)
1234567891011121314
ADQ32L DQ30L NC VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS NC DQ30R DQ32R
BA0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
CA17L A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R A17R
DA2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R
EA4L A5L VDD B0L VDD VSS VDD VDD B0R VDD A5R A4R
FVDD A6L A7L B1L VDD VSS B1R A7R A6R VDD
GOEL B2L B3L VSS CY7C0853V VSS B3R B2R OER
HVSS R/WL A8L CLKL CLKR A8R R/WRVSS
JA9L A10L VSS VSS VSS VDD VSS MRST A10R A9R
KA11L A12L A15L VDD VDD VDD VSS VDD VDD A15R A12R A11R
LVDD A13L VSS DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R VSS A13R VDD
MA16L A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R
NDQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
PDQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R
Top View
172-ball BGA
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 5 of 31
Pin Configurations (continued)
132
131
130
129
128
127
126
125
124
123
122
104
121
120
119
118
117
116
115
114
113
112
111
110
109
103
108
107
106
105
NC
A6R
A5R
A4R
VDD
VSS
DQ35R
DQ34R
A1R
A2R
A3R
A0R
A7R
B0R
B1R
CE1R
B2R
B3R
OER
CE0R
VDD
VDD
VSS
VSS
R/WR
CLKR
MRST
ADSR
CNTENR
A8R
CNTRSTR
CNT/MSKR
A9R
A10R
A11R
A12R
VSS
VDD
A13R
A14R
A15R[2]
A16R[2]
DQ24R
DQ20R
NC
A6L
A5L
A4L
VDD
VSS
DQ35L
DQ34L
A1L
A2L
A3L
A0L
A7L
B0L
B1L
CE1L
B2L
B3L
OEL
CE0L
VDD
VDD
VSS
VSS
R/WL
CLKL
VSS
ADSL
CNTENL
A8L
CNTRSTL
CNT/MSKL
A9L
A10L
A11L
A12L
VSS
VDD
A13L
A14L
A15L[2]
A16L[2]
DQ24L
DQ20L
DQ33L
DQ32L
DQ31L
VDD
VSS
DQ30L
DQ28L
DQ29L
DQ27L
INTL
CNTINTL
DQ16L
DQ15L
DQ17L
DQ14L
DQ13L
VSS
VDD
DQ12L
DQ11L
DQ10L
DQ9L
DQ9R
DQ10R
DQ11R
DQ12R
VDD
VSS
DQ13R
DQ14R
DQ17R
DQ15R
DQ16R
CNTINTR
INTR
DQ27R
DQ29R
DQ28R
DQ30R
VSS
VDD
DQ31R
DQ32R
DQ33R
DQ26L
DQ23L
DQ22L
VDD
VSS
DQ21L
DQ25L
DQ19L
DQ18L
TDI
TDO
DQ8L
DQ7L
DQ6L
DQ5L
DQ4L
VSS
VDD
DQ3L
DQ2L
DQ1L
DQ0L
DQ0R
DQ1R
DQ2R
DQ3R
VDD
VSS
DQ4R
DQ5R
DQ6R
DQ7R
DQ8R
TMS
TCK
DQ18R
DQ19R
DQ25R
DQ21R
VSS
VDD
DQ22R
DQ23R
DQ26R
102
91
101
100
99
98
97
96
90
95
94
93
92
89
1
2
3
4
5
6
7
8
9
10
11
29
12
13
14
15
16
17
18
19
20
21
22
23
24
30
25
26
27
28
31
42
32
33
34
35
36
37
43
38
39
40
41
44
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
CY7C0850V
CY7C0851V
CY7C0852V
176-pin Thin Quad Flat Pack (TQFP)
Top View
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 6 of 31
Note:
3. These pins are not available for CY7C0853AV device.
Pin Definitions
Left Port Right Port Description
A0L–A17L[1] A0R–A17R[1] Address Inputs.
ADSL[3] ADSR[3] Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
CE0L[3] CE0R[3] Active LOW Chip Enable Input.
CE1L[3] CE1R[3] Active HIGH Chip Enable Input.
CLKLCLKRClock Signal. Maximum clock input rate is fMAX.
CNTENL[3] CNTENR[3] Counter Enable Input. Asserting this signal LOW increments the burst address counter of
its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST
are asserted LOW.
CNTRSTL[3] CNTRSTR[3] Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
CNT/MSKL[3] CNT/MSKR[3] Address Counter Mask Register Enable Input. Asserting this signal LOW enables access
to the mask register. When tied HIGH, the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
DQ0L–DQ35L DQ0R–DQ35R Data Bus Input/Output.
OELOEROutput Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTLINTRMailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
CNTINTL[3] CNTINTR[3] Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
R/WLR/WRRead/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B0L–B3L B0R–B3R Byte Select Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation
is required at power-up.
TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
TCK JTAG Test Clock Input.
TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS Ground Inputs.
VDD Power Inputs.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 7 of 31
Master Reset
The FLEx36 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. The MRST initializes the
internal burst counters to zero, and the counter mask registers
to all ones (completely unmasked). The MRST also forces the
Mailbox Interrupt (INT) flags and the Counter Interrupt
(CNTINT) flags HIGH. The MRST must be performed on the
FLEx36 family devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Tab le 2
shows the interrupt operation for both ports of CY7C0853AV.
The highest memory location, 3FFFF is the mailbox for the
right port and 3FFFE is the mailbox for the left port. Tabl e 2
shows that in order to set the INTR flag, a Write operation by
the left port to address 3FFFF will assert INTR LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 3FFFF location by the right port will reset
INTR HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Table 2. Interrupt Operation Example[1, 4, 5, 6, 7]
Function
Left Port Right Port
R/WLCELA0L–17LINTLR/WRCERA0R–17R INTR
Set Right INTR Flag L L 3FFFF X X X X L
Reset Right INTR Flag X X X X H L 3FFFF H
Set Left INTL Flag X X X L L L 3FFFE X
Reset Left INTL Flag H L 3FFFE H X X X X
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)[8, 9]
CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description
X L X X X X Master Reset Reset address counter to all 0s and mask
register to all 1s.
H H L X X Counter Reset Reset counter unmasked portion to all 0s.
H H H L L Counter Load Load counter with external address value
presented on address lines.
H H H L H Counter Readback Read out counter internal value on address
lines.
H H H H L Counter Increment Internally increment address counter value.
H H H H H Counter Hold Constantly hold the address value for
multiple clock cycles.
H L L X X Mask Reset Reset mask register to all 1s.
H L H L L Mask Load Load mask register with value presented on
the address lines.
H L H L H Mask Readback Read out mask register value on address
lines.
H L H H X Reserved Operation undefined
Notes:
4. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
5. OE is “Don’t Care” for mailbox operation.
6. At least one of B0, B1, B2, or B3 must be LOW.
7. A16x is a NC for CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850AV, therefore the Interrupt Addresses
are 7FFF and 6FFF.
8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
9. Counter operation and mask register operation is independent of chip enables.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 8 of 31
Address Counter and Mask Register
Operations[10]
This section describes the features only apply to
CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not
to the CY7C0853AV device. Each port of these devices has a
programmable burst address counter. The burst counter
contains three registers: a counter register, a mask register,
and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load operation, and by the
MRST.
Table 3 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Ta ble 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap.
Counter Reset Operation
All unmasked bits of the counter are reset to “0.” All masked
bits remain unchanged. The mirror register is loaded with the
value of the burst counter. A Mask Reset followed by a Counter
Reset will reset the counter and mirror registers to 00000, as
will master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[11] An increment that results
in one or more of the unmasked bits of the counter being “0”
will deassert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset
and Mask Load operations, and by MRST.
Notes:
10. This section describes the CY7C0852V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V has 16 address bits, register
lengths of 16 bits, and a maximum address value of FFFF. The CY7C0850V has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FF
F
11. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 9 of 31
Retransmit
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. Not all values permit correct increment
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s,” one or more “1s,” or
one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values,
but 1F0FF, 003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0850AV/CY7C0851AV/CY7C0852AV as a 72-bit single
port SRAM in which the counter of one port counts even
addresses and the counter of the other port counts odd
addresses. This even-odd address scheme stores one half of
the 72-bit data in even memory locations, and the other half in
odd memory locations.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 10 of 31
From
Mask
Register
Mirror Counter
Address
Decode
RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To
Counter
Bit 0
Wrap
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
17 17
17
17
17
1
0
Load/Increment
CNT/MSK
CNTEN
ADS
CNTRST
CLK
Decode
Logic
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
From
Address
Lines To Readback
and Address
Decode
17
17
MRST
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 11 of 31
IEEE 1149.1 Serial Boundary Scan (JTAG)[13]
The CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV
incorporates an IEEE 1149.1 serial boundary scan test access
port (TAP). The TAP controller functions in a manner that does
not conflict with the operation of other devices using
1149.1-compliant TAPs. The TAP operates using
JEDEC-standard 3.3V I/O logic levels. It is composed of three
input connections and one output connection required by the
test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the devices are
operating. An MRST must be performed on the devices after
power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the devices in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
216 215 2621
2522
242320
216 215 2621
2522
242320
216 215 2621
2522
242320
216 215 2621
2522
242320
H
H
L
H
11
0s 1
01
0101
00
Xs 1
X0
X0X0
11
Xs 1
X1
X1X1
00
Xs 1
X0
X0X0
Masked Address Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 2. Programmable Counter-Mask Register Operation[1, 12]
Table 4. Identification Register Definitions
Instruction Field Value Description
Revision Number (31:28) 0h Reserved for version number.
Cypress Device ID (27:12) C001h Defines Cypress part number for the CY7C0851AV
C002h Defines Cypress part number for the CY7C0852AV and CY7C0853AV
C092h Defines Cypress part number for the CY7C0850AV
Cypress JEDEC ID (11:1) 034h Allows unique identification of the DP family device vendor.
ID Register Presence (0) 1 Indicates the presence of an ID register.
Notes:
12. The “X” in this diagram represents the counter upper bits.
13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 12 of 31
Table 5. Scan Registers Sizes
Register Name Bit Size
Instruction 4
Bypass 1
Identification 32
Boundary Scan n[14]
Table 6. Instruction Identification Codes
Instruction Code Description
EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS 1111 Places the BYR between TDI and TDO.
IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ 0111 Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/
CY7C0853AV output drivers to a High-Z state.
CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED All other codes Other combinations are reserved. Do not use other than the above.
Note:
14. See details in the device BSDL files.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 13 of 31
Maximum Ratings[15]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VDD + 0.5V
DC Input Voltage .............................. –0.5V to VDD + 0.5V[16]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2000V
(JEDEC JESD22-A114-2000B)
Latch-up Current..................................................... > 200 mA
Operating Range
Range Ambient Temperature VDD
Commercial 0°C to +70°C 3.3V ± 165 mV
Industrial –40°C to +85°C 3.3V ± 165 mV
Electrical Characteristics Over the Operating Range
Parameter Description
-167 -133 -100
UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage
(VDD = Min., IOH= –4.0 mA)
2.4 2.4 2.4 V
VOL Output LOW Voltage
(VDD = Min., IOL= +4.0 mA)
0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 0.8 V
IOZ Output Leakage Current –10 10 –10 10 –10 10 µA
IIX1 Input Leakage Current Except TDI, TMS, MRST –10 10 –10 10 –10 10 µA
IIX2 Input Leakage Current TDI, TMS, MRST –0.1 1.0 –0.1 1.0 –0.1 1.0 mA
ICC Operating Current for
(VDD = Max.,IOUT = 0 mA),
Outputs Disabled
CY7C0850AV
CY7C0851AV
CY7C0852AV
225 300 225 300 mA
CY7C0853AV 270 400 200 310
ISB1[18] Standby Current (Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
90 115 90 115 90 115 mA
ISB2[18] Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
160 210 160 210 160 210 mA
ISB3[18] Standby Current (Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
55 75 55 75 55 75 mA
ISB4[18] Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
160 210 160 210 160 210 mA
ISB5 Operating Current
(VDD = Max, IOUT = 0 mA, f = 0)
Outputs Disabled
CY7C0853AV 70 100 70 100 mA
Capacitance [17]
Part Number Parameter Description Test Conditions Max. Unit
CY7C0850AV/7C0851AV
/CY7C0852AV
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V
13 pF
COUT Output Capacitance 10 pF
CY7C0853AV CIN Input Capacitance 22 pF
COUT Output Capacitance 20 pF
Note:
15. The voltage on any input or I/O pin can not exceed the power pin during power-up.
16. Pulse width < 20 ns.
17. COUT also references CI/O.
18. ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0853AV because it can not be powered down by using chip enable pins.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 14 of 31
AC Test Load and Waveforms
Switching Characteristics Over the Operating Range
Parameter Description
-167 -133 -100
Unit
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0850AV
CY7C0851AV
CY7C0852AV CY7C0853AV CY7C0853AV
Min. Max. Min. Max. Min. Max. Min. Max.
fMAX2 Maximum Operating Frequency 167 133 133 100 MHz
tCYC2 Clock Cycle Time 6.0 7.5 7.5 10.0 ns
tCH2 Clock HIGH Time 2.7 3.0 3.0 4.0 ns
tCL2 Clock LOW Time 2.7 3.0 3.0 4.0 ns
tR[19] Clock Rise Time 2.0 2.0 2.0 3.0 ns
tF[19] Clock Fall Time 2.0 2.0 2.0 3.0 ns
tSA Address Set-up Time 2.3 2.5 2.5 3.0 ns
tHA Address Hold Time 0.6 0.6 0.6 0.6 ns
tSB Byte Select Set-up Time 2.3 2.5 2.5 3.0 ns
tHB Byte Select Hold Time 0.6 0.6 0.6 0.6 ns
tSC Chip Enable Set-up Time 2.3 2.5 NA NA ns
tHC Chip Enable Hold Time 0.6 0.6 NA NA ns
tSW R/W Set-up Time 2.3 2.5 2.5 3.0 ns
tHW R/W Hold Time 0.6 0.6 0.6 0.6 ns
tSD Input Data Set-up Time 2.3 2.5 2.5 3.0 ns
tHD Input Data Hold Time 0.6 0.6 0.6 0.6 ns
tSAD ADS Set-up Time 2.3 2.5 NA NA ns
tHAD ADS Hold Time 0.6 0.6 NA NA ns
tSCN CNTEN Set-up Time 2.3 2.5 NA NA ns
tHCN CNTEN Hold Time 0.6 0.6 NA NA ns
tSRST CNTRST Set-up Time 2.3 2.5 NA NA ns
tHRST CNTRST Hold Time 0.6 0.6 NA NA ns
tSCM CNT/MSK Set-up Time 2.3 2.5 NA NA ns
tHCM CNT/MSK Hold Time 0.6 0.6 NA NA ns
Note:
19. Except JTAG signals (tr and tf < 10 ns [max.]).
R1 = 590 Ω
R2 = 435 Ω
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0V
VSS
90%
10%
<2ns <2ns
ALL INPUT PULSES
3.3V
VTH = 1.5V
R = 50Ω
Z0 = 50Ω
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
OUTPUT
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 15 of 31
tOE Output Enable to Data Valid 4.0 4.4 4.7 5.0 ns
tOLZ[20, 21] OE to Low Z 0000ns
tOHZ[20, 21] OE to High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns
tCD2 Clock to Data Valid 4.0 4.4 4.7 5.0 ns
tCA2 Clock to Counter Address Valid 4.0 4.4 NA NA ns
tCM2 Clock to Mask Register Readback Valid 4.0 4.4 NA NA ns
tDC Data Output Hold After Clock HIGH 1.0 1.0 1.0 1.0 ns
tCKHZ[20, 21] Clock HIGH to Output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns
tCKLZ[20, 21] Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
tSINT Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
tRINT Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
tSCINT Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns
tRCINT Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Port to Port Delays
tCCS Clock to Clock Skew 5.2 6.0 6.0 8.0 ns
Master Reset Timing
tRS Master Reset Pulse Width 7.0 7.5 7.5 10.0 ns
tRSS Master Reset Set-up Time 6.0 6.0 6.0 8.5 ns
tRSR Master Reset Recovery Time 6.0 7.5 7.5 10.0 ns
tRSF Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns
tRSCNTINT Master Reset to Counter Interrupt Flag
Reset Time
10.0 10.0 NA NA ns
Notes:
20. This parameter is guaranteed by design, but it is not production tested.
21. Test conditions used are Load 2.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
-167 -133 -100
Unit
CY7C0850AV
CY7C0851AV
CY7C0852AV
CY7C0850AV
CY7C0851AV
CY7C0852AV CY7C0853AV CY7C0853AV
Min. Max. Min. Max. Min. Max. Min. Max.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 16 of 31
JTAG Switching Waveform
JTAG Timing
Parameter Description
167/133/100
UnitMin. Max.
fJTAG Maximum JTAG TAP Controller Frequency 10 MHz
tTCYC TCK Clock Cycle Time 100 ns
tTH TCK Clock HIGH Time 40 ns
tTL TCK Clock LOW Time 40 ns
tTMSS TMS Set-up to TCK Clock Rise 10 ns
tTMSH TMS Hold After TCK Clock Rise 10 ns
tTDIS TDI Set-up to TCK Clock Rise 10 ns
tTDIH TDI Hold After TCK Clock Rise 10 ns
tTDOV TCK Clock LOW to TDO Valid 30 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test D a ta- O u t
TDO
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOX tTDOV
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 17 of 31
Switching Waveforms
Master Reset
Read Cycle[4, 22, 23, 24, 25]
Notes:
22. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
23. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
24. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
25. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
MRST
tRSR
tRS
INACTIVE ACTIVE
TMS
TDO
INT
CNTINT
tRSF
tRSS
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 18 of 31
Bank Select Read[26, 27]
Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31]
Notes:
26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851AV/CY7C0852AV device from this
data sheet. ADDRESS(B1) = ADDRESS(B2).
27. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
30. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
31. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0A1A2A3A4A5
Q4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tCKHZ
tSD tHD
NO OPERATION WRITEREAD READ
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+3 An+4
QnQn+3
Qn+1
tCD2 tCD2
tCKLZ
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 19 of 31
Read-to-Write-to-Read (OE Controlled)[25, 28, 30, 31]
Read with Address Counter Advance[30]
Switching Waveforms (continued)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
AnAn+1 An+2 An+3 An+4 An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ READWRITE
Dn+3
Qn
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
OE
Qn+4
tCD2
Qn+1
tCD2
tSA tHA
tCH2 tCL2
tCYC2
CLK
ADDRESS An
COUNTER HOLD
READ WITH COUNTER
tSAD tHAD
tSCN tHCN
tSAD tHAD
tSCN tHCN
Qx–1 QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
ADS
CNTEN
DATAOUT
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 20 of 31
Write with Address Counter Advance [31]
Disabled-to-Read-to-Read-to-Read-to-Write
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
AnAn+1 An+2 An+3 An+4
Dn+1 Dn+1 Dn+2 Dn+3 Dn+4
An
Dn
tSAD tHAD
tSCN tHCN
tSD tHD
WRITE EXTERNAL WRITE WITH COUNTER
ADDRESS
WRITE WITH
COUNTER
WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
DATAIN
ADDRESS
tSA tHA
CNTEN
ADS
t
CD2
CLK
CE
R/W
ADDRESS
DATAOUT
OE
A
n
A
n+1
A
n+2
A
n+3
A
n+4
Q
n
Q
n+1
Q
n+2
t
CL2
t
CH2
t
CYC2
t
SA
t
HA
t
SC
t
HC
t
HW
t
SW
t
HW
t
SW
t
SA
t
HA
DISABLED READ WRITE READ
READREAD
DATAIN
D
n+3
t
SD
t
HD
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 21 of 31
Disabled-to-Write-to-Read-to-Write-to-Read
Disabled-to-Read-to-Disabled-to-Write
Switching Waveforms (continued)
CLK
CE
R/W
ADDRESS
OE
DATAIN
A
n
A
n+1
A
n+2
A
n+3
A
n+4
t
CL2
t
CH2
t
CYC2
t
SC
t
HC
t
HW
t
SW
t
SA
t
HA
t
CD2
D
n
D
n+2
DATAOUT
Q
n+1
t
SD
t
HD
Q
n+3
DISABLED WRITE READ WRITE READ READ
t
OE
CLK
CE
R/W
ADDRESS
OE
DATAIN
A
n
A
n+1
A
n+2
A
n+3
A
n+4
t
CL2
t
CH2
t
CYC2
DATAOUT
D
n+2
Q
n
t
SC
t
HC
t
HW
t
SW
t
SA
t
HA
t
SD
t
HD
t
CD2
DISABLED WRITE READ
READ
READ DISABLED
t
OE
t
OHZ
Q
n+3
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 22 of 31
Read-to-Readback-to-Read-to-Read (R/W = HIGH)
Switching Waveforms (continued)
CLK
ADS
ADDRESS
OE
DATAOUT
CNTEN
COUNTER
INTERNAL
ADDRESS
tCL2 tCH2
tCYC2
An+1 An+2 An+3 An+4
An
An+1
Qn+1 Qn+2 Qn+3
tSAD tHAD
tSCN tHCN tSA tHA
READ NO OPERATION READ READ READ
READBACK INCREMENT INCREMENT INCREMENT
INCREMENT
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 23 of 31
Counter Reset[32, 33]
Notes:
32. CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
34. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Switching Waveforms (continued)
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT
AnAmAp
Ax01AnAmAp
Q1Qn
Q0
D0
tCH2 tCL2
tCYC2
tSA tHA
tSW tHW
tSRST tHRST
tSD tHD
tCD2 tCD2
tCKLZ
[34]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS AnADDRESS Am
READ
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 24 of 31
Readback State of Address Counter or Mask Register[35, 36, 37, 38]
Notes:
35. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
36. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
37. Address in input mode. Host can drive address bus after tCKHZ.
38. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Switching Waveforms (continued)
CNTEN
CLK
tCH2 tCL2
tCYC2
ADDRESS
ADS
An
Qx-2 Qx-1 Qn
tSA tHA
tSAD tHAD
tSCN tHCN
LOAD
ADDRESS
EXTERNAL
tCD2
INTERNAL
ADDRESS An+1 An+2
An
tCKHZ
DATAOUT
A
n*
Q
n+3
Qn+1 Qn+2
An+3 An+4
tCKLZ
tCA2 or tCM2
READBACK
INTERNAL
COUNTER
ADDRESS
INCREMENT
EXTERNAL
A0–A16
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 25 of 31
Left_Port (L_Port) Write to Right_Port (R_Port) Read[39, 40, 41]
Notes:
39. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
40. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out.
41. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If
tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Switching Waveforms (continued)
tSA tHA
tSW tHW
tCH2 tCL2
tCYC2
CLKL
R/WL
An
Dn
tCKHZ tHD
tSA
An
tHA
Qn
tDC
tCCS
tSD tCKLZ
tCH2
tCL2
tCYC2
tCD2
L_PORT
ADDRESS
L_PORT
DATAIN
CLKR
R/WR
R_PORT
ADDRESS
R_PORT
DATAOUT
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 26 of 31
Counter Interrupt and Retransmit[34, 42, 43, 44, 45]
Notes:
42. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
43. CNTINT is always driven.
44. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
45. The mask register assumed to have the value of 1FFFFh.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
1FFFD 1FFFF
INTERNAL
ADDRESS Last_Loaded Last_Loaded +1
t
HCM
COUNTER
1FFFE
CNTINT
tSCINT tRCINT
1FFFC
CNTEN
ADS
CNT/MSK
t
SCM
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 27 of 31
MailBox Interrupt Timing[46, 47, 48, 49, 50]
Switching Waveforms (continued)
t
CH2
t
CL2
t
CYC2
CLK
L
tCH2 tCL2
tCYC2
CLKR
3FFFF
tSA tHA
An+3
AnAn+1 An+2
L_PORT
ADDRESS
AmAm+4
Am+1 3FFFF Am+3
R_PORT
ADDRESS
INTR
tSA tHA
tSINT
tRINT
Table 7. Read/Write and Enable Operation (Any Port)[1, 8, 51, 52]
Inputs Outputs
OperationOE CLK CE0CE1R/W DQ0 – DQ35
X H X X High-Z Deselected
X X L X High-Z Deselected
XLHLD
IN Write
LLHHD
OUT Read
H X L H X High-Z Outputs Disabled
Notes:
46. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
47. Address “3FFFF” is the mailbox location for R_Port of a 9M device.
48. L_Port is configured for Write operation, and R_Port is configured for Read operation.
49. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
50. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
51. OE is an asynchronous input signal.
52. When CE changes state, deselection and Read happen after one cycle of latency.
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 28 of 31
Ordering Information
256K
×
36 (9M) 3.3V Synchronous CY7C0853AV Dual-Port SRAM
Speed
(MHz) Ordering Code
Package
Name Package Type
Operating
Range
133 CY7C0853AV-133BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0853AV-133BBI BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Industrial
100 CY7C0853AV-100BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0853AV-100BBI BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Industrial
128K
×
36 (4M) 3.3V Synchronous CY7C0852AV Dual-Port SRAM
Speed
(MHz) Ordering Code
Package
Name Package Type
Operating
Range
167 CY7C0852AV-167BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0852AV-167AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
133 CY7C0852AV-133BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0852AV-133BBI BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Industrial
CY7C0852AV-133AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
CY7C0852AV-133AI A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Industrial
64K
×
36 (2M) 3.3V Synchronous CY7C0851AV Dual-Port SRAM
Speed
(MHz) Ordering Code
Package
Name Package Type
Operating
Range
167 CY7C0851AV-167BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0851AV-167AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
133 CY7C0851AV-133BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0851AV-133BBI BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Industrial
CY7C0851AV-133AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
CY7C0851AV-133AI A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Industrial
32K
×
36 (1M) 3.3V Synchronous CY7C0850AV Dual-Port SRAM
Speed
(MHz) Ordering Code
Package
Name Package Type
Operating
Range
167 CY7C0850AV-167BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0850AV-167AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
133 CY7C0850AV-133BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Commercial
CY7C0850AV-133BBI BB172
172-ball Grid Array 15 mm × 15 mm with 1.0-mm pitch (BGA)
Industrial
CY7C0850AV-133AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
CY7C0850AV-133AI A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Industrial
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 29 of 31
Package Diagrams
51-85132-**
176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 30 of 31
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Diagrams (continued)
FLEx36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114-*B
CY7C0850AV/CY7C0851AV
CY7C0852AV/CY7C0853AV
Document #: 38-06070 Rev. *G Page 31 of 31
Document History Page
Document Title: CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV FLEx36™ 3.3V 32K/64K/128K/256K x 36 Syn-
chronous Dual-Port RAM
Document Number: 38-06070
REV. ECN NO.
Issue
Date
Orig. of
Change Description of Change
** 127809 08/04/03 SPN This data sheet has been extracted from another data sheet: the 2M/4M/9M
data sheet. The following changes have been made from the original as
pertains to this device:
Updated capacitance values
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Power up requirements added to Maximum Ratings information
Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
Updated Icc numbers
Updated tHA, tHB, tHD for -100 speed
Separated out from the 4M data sheet
Added 133-MHz Industrial device to Ordering Information table
*A 210948 See ECN YDT Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF.
*B 216190 See ECN YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change
*C 231996 See ECN YDT Removed “A particular port can write to a certain location while another port
is reading that location.” from Functional Description.
*D 238938 See ECN WWZ Merged 0853 (9Mx36) with 0852 (4Mx36) and 0851(2Mx36), add 0850 (1M
x36), to the data sheet.
Added product selection table.
Added JTAG ID code for 1M device.
Added note 14.
Updated boundary scan section.
Updated function description for the merge and addition.
*E 329122 See ECN SPN Updated Marketing part numbers
*F 389877 See ECN KGH Updated Read-to-Write-to-Read timing diagram to reflect accurate bus
turnaround scheme.
Added ISB5
Changed tRSCNTINT to 10ns
Changed tRSF to 10ns
Added figure Disabled-to-Read-to-Read-to-Read-to-Write
Added figure Disabled-to-Write-to-Read-to-Write-to-Read
Added figure Disabled-to-Read-to-Disabled-to-Write
Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH)
Updated Read-to-Write-to-Read timing diagram to correct the data out
schemes
Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to
correct the chip enable, data in, and data out schemes
Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to
correct the chip enable and output enable schemes
Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct
the chip enable and output enable schemes
*G 391597 See ECN SPN Updated counter reset section to reflect mirror register behavior
