Features * Incorporates the ARM7TDMITM ARM(R) Thumb(R) Processor Core * * * * * * * * * * * * * * - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Little-endian - Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM - 32-bit Data Bus - Single-clock Cycle Access Fully-programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to Eight Chip Selects - Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller - Four External Interrupts, Including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter - Three External Clock Inputs - Two Multi-purpose I/O Pins per Channel Two USARTs - Two Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Advanced Power-saving Features - CPU and Peripheral Can be Deactivated Individually Fully Static Operation - 0 Hz to 70 MHz Internal Frequency Range at VDDCORE = 1.65V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range Available in 100-lead TQFP Package -40C to +85C Temperature Range AT91 ARM(R) Thumb(R) Microcontrollers AT91R40008 Electrical Characteristics Description The AT91R40008 microcontroller is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set and very low power consumption. Furthermore, it features 256K bytes of on-chip SRAM and a large number of internally banked registers, resulting in very fast exception handling, and making the device ideal for real-time control applications. The AT91R40008 microcontroller features a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface (EBI). An 8level priority vectored interrupt controller, in conjunction with the Peripheral Data Controller, significantly improves the real-time performance of the device. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful microcontroller that offers a flexible and high-performance solution to many computeintensive embedded control applications. Rev. 1795A-01/02 1 Absolute Maximum Ratings* Operating Temperature (Industrial) ....-40C to + 85C *NOTICE: Storage Temperature........................-60C to + 150C Voltage on Any Input Pin with Respect to Ground ..................................................-0.3V to max of VDDIO .......................................................... + 0.3V and 3.6V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage (VDDIO) ....................3.6V Maximum Operating Voltage (VDDCORE) .............1.95V DC Output Current ...............................................TBD The following characteristics are applicable to the Operating Temperature range: TA = -40C to +85C, unless otherwise specified and are certified for a Junction Temperature up to 100C. Table 1. DC Characteristics Symbol Parameter VDDIO DC Supply I/Os VDDCORE Max Units 2.7 3.6 V DC Supply Core 1.65 1.95 V VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2.0 VDDIO + 0.3 V NRD, NRW0, NWR1: IOL = 16 mA(1) 0.4 V Other EBI Output Pins: IOL = 8 mA(1) 0.4 V 0.4 V 0.2 V VOL Output Low Voltage Conditions Min (1) Other Output Pins: IOL = 2 mA (1) All Output Pins: IOL = 0 mA VOH Input Leakage Current IPULL Input Pull-up Current CIN ISC 2 VDDIO 0.4 Other EBI Output Pins: IOH = 8 mA(1) VDDIO 0.4 Other Output Pins: IOH = 2 mA(1) VDDIO 0.4 All Output Pins: IOH = 0 mA(1) VDDIO 0.2 V Output High Voltage ILEAK Note: NRD, NWR0, NWR1: IOH = 16 mA(1) Typ 10 A VDDIO = 3.6V, VIN = 0V 280 A Input Capacitance TQFP100 Package 5.3 pF A TBD TA = 25C TBD Static Current TA = 85C TBD A 1. IO = Output Current. AT91R40008 1795A-01/02 AT91R40008 Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e., VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25C) on the AT91EB40A Evaluation Board. Table 2. Power Consumption Mode Conditions Reset TBD Consumption Fetch in ARM mode out of internal SRAM All peripheral clocks activated 0.32 Fetch in ARM mode out of internal SRAM All peripheral clocks deactivated 0.23 All peripheral clocks activated 0.14 All peripheral clocks deactivated 0.05 Unit Normal mW/MHz Idle Table 3. Power Consumption per Peripheral Peripheral Consumption PIO Controller 13.7 Timer/Counter Channel 12.9 Timer/Counter Block (3 Channels) TBD USART 13.7 Unit W/MHz 3 1795A-01/02 Thermal and Reliability Considerations Thermal Data In Table 4, the device lifetime is estimated with the MIL-217 standard in the "moderately controlled" environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section "Junction Temperature" on page 5.) Note that the user must be extremely cautious with this MTBF calculation: as the MIL217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 4. MTBF Versus Junction Temperature Junction Temperature (TJ) (C) Estimated Lifetime (MTBF) (Year) 100 10 125 5 150 3 175 2 Table 5 summarizes the thermal resistance data related to the package of interest. Table 5. Thermal Resistance Data Reliability Data Symbol Parameter JA= Junction-to-ambient thermal resistance JC Junction-to-case thermal resistance Condition Package Typ Still Air TQFP100 40 TQFP100 6.4 Unit C/W The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model. Table 6. Reliability Data Parameter Data Unit Number of Logic Gates 280 K gates 12,897 K gates 21.2 mm2 Number of Memory Gates Device Die Size 4 AT91R40008 1795A-01/02 AT91R40008 Junction Temperature The average chip-junction temperature TJ in C can be obtained from the following: 1. T J = T A + ( P D x JA ) 2. T J = T A + ( P D x ( HEATSINK + JC ) ) Where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 5 on page 4. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 5 on page 4. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 3. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chipjunction temperature TJ in C 5 1795A-01/02 Conditions Timing Results The delays are given as typical values in the following conditions: * VDDIO = 3.0V * VDDCORE = 1.8V * Ambient Temperature = 25C * Load Capacitance = 0 pF * The output level change detection is 0.5 x VDDIO * The input level is 0.3 x VDDIO for a low-level detection and is 0.7 x VDDIO for a high level detection. The minimum and maximum values given in the AC characteristic tables of this datasheet take into account the process variation and the design. In order to obtain the timing for other conditions, the following equation should be used: t = T x ( ( VDDCORE x t DATASHEET ) + ( VDDIO x ( C SIGNAL x CSIGNAL ) ) ) Where: * * * * * * T is the derating factor in temperature given in Figure 1. VDDCORE is the derating factor for the Core Power Supply given in Figure 2 on page 7. tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. VDDIO is the derating factor for the I/O Power Supply given in Figure 3 on page 7. CSIGNAL is the capacitance load on the considered output pin.(1) CSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max values in this datasheet. The input delays are given as typical values. Note: Temperature Derating Factor 1. The user must take into account the package capacitance load contribution (CIN) described in Table 1 on page 2. Figure 1. Derating Curve for Different Operating Temperatures 1.2 Derating Factor 1.1 1 Derating Factor for Typ Case is 1 0.9 0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160 Operating Temperature C 6 AT91R40008 1795A-01/02 AT91R40008 Core Voltage Derating Factor Figure 2. Core Voltage Derating Factor Derating Factor 3 Derating Factor for Typ Case is 1 2.5 2 1.5 1 0.5 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 Core Supply Voltage (V) IO Voltage Derating Factor Figure 3. Derating Factor for Different VDDIO Power Supply Levels 1.6 Derating Factor for Typ Case is 1 Derating Factor 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDDIO Voltage Level 7 1795A-01/02 Clock Waveforms Table 7. Master Clock Waveform Parameters Symbol Parameter 1/(tCP) Oscillator Frequency tCP Oscillator Period 12.2 tCH High Half-period 0.45 x tCP 0.55 x tCP ns tCL Low Half-period 0.45 x tCP 0.55 x tCP ns tr MCKI Rising Edge TBD ns tf MCKI Falling Edge TBD ns Note: Conditions Min Max Units 82.1 MHz ns 1. Applicable only for Chip Select programmed with zero wait states. Table 8. Clock Propagation Times Symbol Parameter tCDLH Rising Edge Propagation Time tCDHL Falling Edge Propagation Time Conditions Min Max Units CMCKO = 0 pF 4.4 6.6 ns 0.199 0.295 ns/pF 4.5 6.7 ns 0.153 0.228 ns/pF CMCKO derating CMCKO = 0 pF CMCKO derating Figure 4. Clock Waveform tr tCH MCKI tf 0.7 VDDIO 0.3 VDDIO tCL tCP 0.5 VDDIO 0.5 VDDIO MCKO tCDLH 8 tCDHL AT91R40008 1795A-01/02 AT91R40008 Table 9. NRST to MCKO Symbol Parameter tD NRST Rising Edge to MCKO Valid Time Min Max Units 3(tCP/2) 7(tCP/2) ns Figure 5. MCKO Relative to NRST NRST tD MCKO 9 1795A-01/02 AC Characteristics EBI Signals Relative to MCKI The following tables show timings relative to operating condition limits defined in the section "Timing Results" on page 6. See Figure 6 on page 14. Table 10. General-purpose EBI Signals Symbol Parameter EBI1 MCKI Falling to NUB Valid EBI2 MCKI Falling to NLB/A0 Valid EBI3 MCKI Falling to A1 - A23 Valid EBI4 MCKI Falling to Chip Select Change EBI5 NWAIT Setup before MCKI Rising 1.7 ns EBI6 NWAIT Hold after MCKI Rising 1.7 ns 10 Conditions Min Max Units CNUB = 0 pF 4.4 8.9 ns 0.030 0.043 ns/pF 3.7 6.7 ns 0.045 0.069 ns/pF 3.4 7.8 ns 0.045 0.076 ns/pF 3.7 8.6 ns 0.045 0.078 ns/pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating AT91R40008 1795A-01/02 AT91R40008 Table 11. EBI Write Signals Symbol Parameter EBI7 MCKI Rising to NWR Active (No Wait States) EBI8 MCKI Rising to NWR Active (Wait States) EBI9 MCKI Falling to NWR Inactive (No Wait States) EBI10 MCKI Rising to NWR Inactive (Wait States) EBI11 MCKI Rising to D0 - D15 Out Valid EBI12 NWR High to NUB Change EBI13 NWR High to NLB/A0 Change EBI14 NWR High to A1 - A23 Change EBI15 NWR High to Chip Select Inactive Conditions Min Max Units CNWR = 0 pF 3.9 6.3 ns 0.029 0.043 ns/pF 4.4 7.0 ns 0.029 0.043 ns/pF 3.8 6.3 ns 0.029 0.044 ns/pF 4.2 6.7 ns 0.029 0.044 ns/pF 4.2 7.5 ns 0.045 0.080 ns/pF 3.1 7.0 ns 0.030 0.043 ns/pF 3.1 5.4 ns 0.043 0.073 ns/pF 2.9 7.0 ns 0.043 0.076 ns/pF 2.9 6.8 ns 0.052 0.067 ns/pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA = 0 pF CDATA derating CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating C = 0 pF Data Out Valid before NWR High (No Wait States) EBI16 (1) tCH - 1.8 ns CDATA derating -0.080 ns/pF CNWR derating 0.044 ns/pF n x tCP - 1.3(2) ns CDATA derating -0.080 ns/pF CNWR derating 0.044 ns/pF 2.2 ns tCH - 0.6 ns C = 0 pF Data Out Valid before NWR High (Wait States)(1) EBI17 EBI18 Data Out Valid after NWR High EBI19 NWR Minimum Pulse Width (No Wait States)(1) CNWR derating NWR Minimum Pulse Width (Wait States)(1) EBI20 Notes: CNWR = 0 pF CNWR = 0 pF CNWR derating 0 ns/pF (2) n x tCP - 0.9 0 ns ns/pF 1. The derating factor should not be applied to tCH or tCP. 2. n = number of standard wait states inserted. 11 1795A-01/02 Table 12. EBI Read Signals Symbol Parameter EBI21 MCKI Falling to NRD Active(1) EBI22 MCKI Rising to NRD Active(2) EBI23 MCKI Falling to NRD Inactive(1) EBI24 MCKI Falling to NRD Inactive(2) Max Units CNRD = 0 pF 4.5 7.9 ns 0.029 0.043 ns/pF 3.8 7.3 ns 0.029 0.043 ns/pF 4.1 6.5 ns 0.030 0.044 ns/pF 3.9 5.8 ns 0.030 0.044 ns/pF CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating D0 - D15 In Setup before MCKI Falling Edge (5) (5) EBI26 D0 - D15 In Hold after MCKI Falling Edge EBI27 NRD High to NUB Change EBI28 NRD High to NLB/A0 Change EBI29 NRD High to A1 - A23 Change EBI30 NRD High to Chip Select Inactive EBI31 Data Setup before NRD High(5) EBI32 Data Hold after NRD High(5) CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating EBI33 NRD Minimum Pulse Width(1)(3) EBI34 NRD Minimum Pulse Width(2)(3) 12 Min CNRD derating EBI25 Notes: Conditions CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating 1. 2. 3. 4. 5. 1.5 ns 1.2 ns 3.2 7.1 ns 0.030 0.043 ns/pF 3.2 4.6 ns 0.043 0.073 ns/pF 2.8 6.1 ns 0.043 0.076 ns/pF 2.9 6.2 ns 0.052 0.067 ns/pF 8.0 ns 0.044 ns/pF -3.1 ns -0.030 (n +1) tCP - 1.9 ns/pF (4) ns 0.001 ns/pF n x tCP + (tCH - 1.5)(4) ns 0.001 ns/pF Early Read Protocol. Standard Read Protocol. The derating factor should not be applied to tCH or tCP. n = number of standard wait states inserted. Only one of these two timings needs to be met. AT91R40008 1795A-01/02 AT91R40008 Table 13. EBI Read and Write Control Signals. Capacitance Limitation Symbol Parameter TCPLNRD(1) Master Clock Low Due to NRD Capacitance TCPLNWR(2) Master CLock Low Due to NWR Capacitance Notes: Conditions Min CNRD = 0 pF 7.3 ns CNRD derating 0.044 ns/pF CNWR = 0 pF 7.6 ns 0.044 ns/pF CNWR derating Max Units 1. If this condition is not met, the action depends on the read protocol intended for use. * Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle. * Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. 13 1795A-01/02 Figure 6. EBI Signals Relative to MCKI MCKI EBI4 EBI4 NCS CS EBI3 A1 - A23 EBI5 EBI6 NWAIT EBI1/EBI2 NUB/NLB/A0 EBI21 NRD(1) EBI27-30 EBI23 EBI33 EBI22 NRD(2) EBI24 EBI34 EBI31 EBI32 EBI25 EBI26 D0 - D15 Read EBI9 EBI7 EBI12-15 EBI19 NWR (No Wait States) EBI8 EBI10 EBI20 NWR (Wait States) EBI11 EBI17 EBI16 EBI18 EBI18 D0 - D15 to Write No Wait Notes: 14 Wait 1. Early Read Protocol. 2. Standard Read Protocol. AT91R40008 1795A-01/02 AT91R40008 Peripheral Signals USART Signals The inputs have to meet the minimum pulse width and period constraints shown in Table 14 and Table 15, and represented in Figure 7. Table 14. USART Input Minimum Pulse Width Symbol Parameter US1 SCK/RXD Minimum Pulse Width Min Pulse Width Units 5(tCP/2) ns Min Input Period Units 9(tCP/2) ns Table 15. USART Minimum Input Period Symbol Parameter US2 SCK Minimum Input Period Figure 7. USART Signals US1 RXD US2 US1 SCK 15 1795A-01/02 Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Table 16 and Table 17, and as represented in Figure 8. Table 16. Timer Input Minimum Pulse Width Symbol Parameter TC1 TCLK/TIOA/TIOB Minimum Pulse Width Min Pulse Width Units 3(tCP/2) ns Table 17. Timer Input Minimum Period Symbol Parameter TC2 TCLK/TIOA/TIOB Minimum Input Period Min Input Period Units 5(tCP/2) ns Figure 8. Timer Input TC2 3(tCP/2) 3(tCP/2) MCKI TC1 TIOA/ TIOB/ TCLK Reset Signals A minimum pulse width is necessary, as shown in Table 18 and as represented in Figure 9. Table 18. Reset Minimum Pulse Width Symbol Parameter RST1 NRST Minimum Pulse Width Min Pulse-width Units 10(tCP) ns Figure 9. Reset Signal RST1 NRST Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous. 16 AT91R40008 1795A-01/02 AT91R40008 Advanced Interrupt Controller Signals Inputs have to meet the minimum pulse width and minimum input period shown in Table 19 and Table 20 and represented in Figure 10. Table 19. AIC Input Minimum Pulse Width Symbol Parameter AIC1 FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width Min Pulse Width Units 3(tCP/2) ns Min Input Period Units 5(tCP/2) ns Table 20. AIC Input Minimum Period Symbol Parameter AIC2 AIC Minimum Input Period Figure 10. AIC Signals AIC2 MCKI AIC1 FIQ/IRQ0/ IRQ1/IRQ2/ IRQ3 Input Parallel I/O Signals The inputs have to meet the minimum pulse width shown in Table 21 and represented in Figure 11. Table 21. PIO Input Minimum Pulse Width Symbol Parameter PIO1 PIO Input Minimum Pulse Width Min Pulse Width Units 3(tCP/2) ns Figure 11. PIO Signal PIO1 PIO Inputs 17 1795A-01/02 ICE Interface Signals Table 22. ICE Interface Timing Specifications Symbol Parameter Conditions Min ICE0 NTRST Minimum Pulse Width 10.9 ns ICE1 NTRST High Recovery to TCK High 0.9 ns ICE2 NTRST High Removal from TCK High -0.3 ns ICE3 TCK Low Half-period 23.5 ns ICE4 TCK High Half-period 22.7 ns ICE5 TCK Period 46.1 ns ICE6 TDI, TMS Setup before TCK High 0.4 ns ICE7 TDI, TMS Hold after TCK High 0.4 ns 3.3 ns ICE8 TDO Hold Time 0.001 ns/pF ICE9 TCK Low to TDO Valid CTDO = 0 pF CTDO derating Max Units CTDO = 0 pF 7.4 ns CTDO derating 0.28 ns/pF Figure 12. ICE Interface Signal ICE0 NTRST ICE1 ICE2 ICE5 TCK ICE4 ICE3 TMS/TDI ICE6 ICE7 TDO ICE8 ICE9 18 AT91R40008 1795A-01/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 e-mail literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. ARM (R), Thumb (R) and ARM Powered (R) are the registered trademarks of ARM Limited. ARM7TDMITM is the trademark of ARM Limited. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1795A-01/02/0M