1
Features
•Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Little-endian
– Embedded ICE (In-circuit Emulation)
•8-, 16- and 32-bit Read and Write Support
•256K Bytes of On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
•Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to Eight Chip Selects
– Software Programmable 8/16-bit External Data Bus
•Eight-level Priority, Individually Maskable, Vectored Interrupt Controller
– Four External Interrupts, Including a High-priority, Low-latency Interrupt Request
•32 Programmable I/O Lines
•Three-channel 16-bit Timer/Counter
– Three External Clock Inputs
– Two Multi-purpose I/O Pins per Channel
•Two USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
•Programmable Watchdog Timer
•Advanced Power-saving Features
– CPU and Peripheral Can be Deactivated Individually
•Fully Static Operation
– 0 Hz to 70 MHz Internal Frequency Range at VDDCORE = 1.65V, 85°C
•2.7V to 3.6V I/O Operating Range
•1.65V to 1.95V Core Operating Range
•Available in 100-lead TQFP Package
•-40°C to +85°C Temperature Range
Description
The AT91R40008 microcontroller is a member of the Atmel AT91 16-/32-bit microcon-
troller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set
and very low power consumption. Furthermore, it features 256K bytes of on-chip
SRAM and a large number of internally banked registers, resulting in very fast excep-
tion handling, and making the device ideal for real-time control applications.
The AT91R40008 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully-programmable External Bus Interface (EBI). An 8-
level priority vectored interrupt controller, in conjunction with the Peripheral Data Con-
troller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combin-
ing the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a
wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful
microcontroller that offers a flexible and high-performance solution to many compute-
intensive embedded control applications.
AT91
ARM® Thumb®
Microcontrollers
AT91R40008
Electrical
Characteristics
Rev. 1795A–01/02
2AT91R40008
1795A–01/02
Absolute Maximum Ratings*
The following characteristics are applicable to the Operating Temperature range: TA = -40°C to +85°C, unless otherwise
specified and are certified for a Junction Temperature up to 100°C.
Note: 1. IO= Output Current.
Operating Temperature (Industrial) ....-40°C to + 85°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature........................-60°C to + 150°C
Voltage on Any Input Pin with Respect to Ground
..................................................-0.3V to max of VDDIO
.......................................................... + 0.3V and 3.6V
Maximum Operating Voltage (VDDIO) ....................3.6V
Maximum Operating Voltage (VDDCORE) .............1.95V
DC Output Current ...............................................TBD
Table 1. DC Characteristics
Symbol Parameter Conditions Min Typ Max Units
VDDIO DC Supply I/Os 2.7 3.6 V
VDDCORE DC Supply Core 1.65 1.95 V
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.0 VDDIO +
0.3 V
VOL Output Low Voltage
NRD, NRW0, NWR1: IOL =16mA
(1) 0.4 V
Other EBI Output Pins: IOL =8mA
(1) 0.4 V
Other Output Pins: IOL =2mA
(1) 0.4 V
All Output Pins: IOL =0mA
(1) 0.2 V
VOH Output High Voltage
NRD, NWR0, NWR1: IOH =16mA
(1) VDDIO -
0.4 V
Other EBI Output Pins: IOH =8mA
(1) VDDIO -
0.4
Other Output Pins: IOH =2mA
(1) VDDIO -
0.4
All Output Pins: IOH =0mA
(1) VDDIO -
0.2
ILEAK Input Leakage Current 10 µA
IPULL Input Pull-up Current VDDIO = 3.6V, VIN =0V 280 µA
CIN Input Capacitance TQFP100 Package 5.3 pF
ISC Static Current TBD TA = 25°CTBDµA
TA = 85°CTBDµA
3
AT91R40008
1795A–01/02
Power Consumption The values in the following tables are measured values in the operating conditions indi-
cated (i.e., VDDIO =3.3V, V
DDCORE =1.8V, T
A=25°C) on the AT91EB40A Evaluation
Board.
Table 2. Power Consumption
Mode Conditions Consumption Unit
Reset TBD
mW/MHz
Normal
Fetch in ARM mode out of internal SRAM
All peripheral clocks activated 0.32
Fetch in ARM mode out of internal SRAM
All peripheral clocks deactivated 0.23
Idle All peripheral clocks activated 0.14
All peripheral clocks deactivated 0.05
Table 3. Power Consumption per Peripheral
Peripheral Consumption Unit
PIO Controller 13.7
µW/MHz
Timer/Counter Channel 12.9
Timer/Counter Block (3 Channels) TBD
USART 13.7
4AT91R40008
1795A–01/02
Thermal and Reliability
Considerations
Thermal Data In Table 4, the device lifetime is estimated with the MIL-217 standard in the “moderately
controlled” environmental model (this model is described as corresponding to an instal-
lation in a permanent rack with adequate cooling air), depending on the device Junction
Temperature. (For details see the section “Junction Temperature” on page 5.)
Note that the user must be extremely cautious with this MTBF calculation: as the MIL-
217 model is pessimistic with respect to observed values due to the way the data/mod-
els are obtained (test under severe conditions). The life test results that have been
measured are always better than the predicted ones.
Table 5 summarizes the thermal resistance data related to the package of interest.
Reliability Data The number of gates and the device die size are provided for the user to calculate reli-
ability data with another standard and/or in another environmental model.
Table 4. MTBF Versus Junction Temperature
Junction Temperature (TJ) (°C) Estimated Lifetime (MTBF) (Year)
100 10
125 5
150 3
175 2
Table 5. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
θJA=Junction-to-ambient thermal resistance Still Air TQFP100 40 °C/W
θJC Junction-to-case thermal resistance TQFP100 6.4
Table 6. Reliability Data
Parameter Data Unit
Number of Logic Gates 280 K gates
Number of Memory Gates 12,897 K gates
Device Die Size 21.2 mm2
5
AT91R40008
1795A–01/02
Junction Temperature The average chip-junction temperature TJ in °C can be obtained from the following:
1.
2.
Where:
•θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 5
on page 4.
•θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W),
provided in Table 5 on page 4.
•θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device
datasheet.
•P
D = device power consumption (W) estimated from data provided in the section
“Power Consumption” on page 3.
•T
A = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and
thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted
on the chip, the second equation should be used to compute the resulting average chip-
junction temperature TJ in °C
TJTAPDθJA
×()+=
TJTAP(Dθ( HEATSINK
×θ
JC))++=
6AT91R40008
1795A–01/02
Conditions
Timing Results The delays are given as typical values in the following conditions:
•VDDIO = 3.0V
•VDDCORE =1.8V
• Ambient Temperature = 25°C
• Load Capacitance = 0 pF
• The output level change detection is 0.5 x VDDIO
• The input level is 0.3 x VDDIO for a low-level detection and is 0.7 x VDDIO for a high
level detection.
The minimum and maximum values given in the AC characteristic tables of this
datasheet take into account the process variation and the design.
In order to obtain the timing for other conditions, the following equation should be used:
Where:
•
δ
T° is the derating factor in temperature given in Figure 1.
•
δ
VDDCORE is the derating factor for the Core Power Supply given in Figure 2 on page
7.
•tDATASHEET is the minimum or maximum timing value given in this datasheet for a load
capacitance of 0 pF.
•
δ
VDDIO is the derating factor for the I/O Power Supply given in Figure 3 on page 7.
•CSIGNAL is the capacitance load on the considered output pin.(1)
•
δ
CSIGNAL is the load derating factor depending on the capacitance load on the related
output pins given in Min and Max values in this datasheet.
The input delays are given as typical values.
Note: 1. The user must take into account the package capacitance load contribution (CIN)
described in Table 1 on page 2.
Temperature
Derating Factor
Figure 1. Derating Curve for Different Operating Temperatures
tδT°δVDDCORE tDATASHEET
×()δ
VDDIO CSIGNAL δCSIGNAL
×()×()+()×=
0.8
0.9
1
1.1
1.2
-60 -40 -20 0 20 40 60 80 100 120 140 160
Operating Temperature °C
Derating Factor
Derating Factor for
Typ Case is 1
7
AT91R40008
1795A–01/02
Core Voltage
Derating Factor
Figure 2. Core Voltage Derating Factor
IO Voltage
Derating Factor
Figure 3. Derating Factor for Different VDDIO Power Supply Levels
0.5
1
1.5
2
2.5
3
1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95
Core Supply Voltage (V)
Derating Factor
Derating Factor
for Typ Case is 1
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDDIO Voltage Level
Derating Factor
Derating Factor for
Typ Cas e is 1
8AT91R40008
1795A–01/02
Clock Waveforms
Note: 1. Applicable only for Chip Select programmed with zero wait states.
Figure 4. Clock Waveform
Table 7. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Units
1/(tCP) Oscillator Frequency 82.1 MHz
tCP Oscillator Period 12.2 ns
tCH High Half-period 0.45 x tCP 0.55 x tCP ns
tCL Low Half-period 0.45 x tCP 0.55 x tCP ns
trMCKI Rising Edge TBD ns
tfMCKI Falling Edge TBD ns
Table 8. Clock Propagation Times
Symbol Parameter Conditions Min Max Units
tCDLH Rising Edge Propagation Time CMCKO = 0 pF 4.4 6.6 ns
CMCKO derating 0.199 0.295 ns/pF
tCDHL Falling Edge Propagation Time CMCKO = 0 pF 4.5 6.7 ns
CMCKO derating 0.153 0.228 ns/pF
tCH
tCL
tCP
MCKI
MCKO
tCDLH tCDHL
0.7 VDDIO
trtf
0.3 VDDIO
0.5 VDDIO 0.5 VDDIO
9
AT91R40008
1795A–01/02
Figure 5. MCKO Relative to NRST
Table 9. NRST to MCKO
Symbol Parameter Min Max Units
tDNRST Rising Edge to MCKO Valid Time 3(tCP/2) 7(tCP/2) ns
NRST
tD
MCKO
10 AT91R40008
1795A–01/02
AC Characteristics
EBI Signals Relative to MCKI
The following tables show timings relative to operating condition limits defined in the section “Timing Results” on page 6.
See Figure 6 on page 14.
Table 10. General-purpose EBI Signals
Symbol Parameter Conditions Min Max Units
EBI1MCKI Falling to NUB Valid CNUB = 0 pF 4.4 8.9 ns
CNUB derating 0.030 0.043 ns/pF
EBI2MCKI Falling to NLB/A0 Valid CNLB = 0 pF 3.7 6.7 ns
CNLB derating 0.045 0.069 ns/pF
EBI3MCKI Falling to A1 - A23 Valid CADD = 0 pF 3.4 7.8 ns
CADD derating 0.045 0.076 ns/pF
EBI4
MCKI Falling to Chip Select
Change
CNCS = 0 pF 3.7 8.6 ns
CNCS derating 0.045 0.078 ns/pF
EBI5NWAIT Setup before MCKI Rising 1.7 ns
EBI6NWAIT Hold after MCKI Rising 1.7 ns
11
AT91R40008
1795A–01/02
Notes: 1. The derating factor should not be applied to tCH or tCP
.
2. n = number of standard wait states inserted.
Table 11. EBI Write Signals
Symbol Parameter Conditions Min Max Units
EBI7MCKI Rising to NWR Active (No Wait States) CNWR = 0 pF 3.9 6.3 ns
CNWR derating 0.029 0.043 ns/pF
EBI8MCKI Rising to NWR Active (Wait States) CNWR = 0 pF 4.4 7.0 ns
CNWR derating 0.029 0.043 ns/pF
EBI9MCKI Falling to NWR Inactive (No Wait States) CNWR = 0 pF 3.8 6.3 ns
CNWR derating 0.029 0.044 ns/pF
EBI10 MCKI Rising to NWR Inactive (Wait States) CNWR = 0 pF 4.2 6.7 ns
CNWR derating 0.029 0.044 ns/pF
EBI11 MCKI Rising to D0 - D15 Out Valid CDATA = 0 pF 4.2 7.5 ns
CDATA derating 0.045 0.080 ns/pF
EBI12 NWR High to NUB Change CNUB = 0 pF 3.1 7.0 ns
CNUB derating 0.030 0.043 ns/pF
EBI13 NWR High to NLB/A0 Change CNLB = 0 pF 3.1 5.4 ns
CNLB derating 0.043 0.073 ns/pF
EBI14 NWR High to A1 - A23 Change CADD = 0 pF 2.9 7.0 ns
CADD derating 0.043 0.076 ns/pF
EBI15 NWR High to Chip Select Inactive CNCS = 0 pF 2.9 6.8 ns
CNCS derating 0.052 0.067 ns/pF
EBI16 Data Out Valid before NWR High (No Wait States)(1)
C = 0 pF tCH - 1.8 ns
CDATA derating -0.080 ns/pF
CNWR derating 0.044 ns/pF
EBI17 Data Out Valid before NWR High (Wait States)(1)
C = 0 pF n x tCP - 1.3(2) ns
CDATA derating -0.080 ns/pF
CNWR derating 0.044 ns/pF
EBI18 Data Out Valid after NWR High 2.2 ns
EBI19 NWR Minimum Pulse Width (No Wait States)(1) CNWR = 0 pF tCH - 0.6 ns
CNWR derating 0 ns/pF
EBI20 NWR Minimum Pulse Width (Wait States)(1) CNWR = 0 pF n x tCP - 0.9(2) ns
CNWR derating 0 ns/pF
12 AT91R40008
1795A–01/02
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
3. The derating factor should not be applied to tCH or tCP
.
4. n = number of standard wait states inserted.
5. Only one of these two timings needs to be met.
Table 12. EBI Read Signals
Symbol Parameter Conditions Min Max Units
EBI21 MCKI Falling to NRD Active(1) CNRD = 0 pF 4.5 7.9 ns
CNRD derating 0.029 0.043 ns/pF
EBI22 MCKI Rising to NRD Active(2) CNRD = 0 pF 3.8 7.3 ns
CNRD derating 0.029 0.043 ns/pF
EBI23 MCKI Falling to NRD Inactive(1) CNRD = 0 pF 4.1 6.5 ns
CNRD derating 0.030 0.044 ns/pF
EBI24 MCKI Falling to NRD Inactive(2) CNRD = 0 pF 3.9 5.8 ns
CNRD derating 0.030 0.044 ns/pF
EBI25 D0 - D15 In Setup before MCKI Falling Edge(5) 1.5 ns
EBI26 D0 - D15 In Hold after MCKI Falling Edge(5) 1.2 ns
EBI27 NRD High to NUB Change CNUB = 0 pF 3.2 7.1 ns
CNUB derating 0.030 0.043 ns/pF
EBI28 NRD High to NLB/A0 Change CNLB = 0 pF 3.2 4.6 ns
CNLB derating 0.043 0.073 ns/pF
EBI29 NRD High to A1 - A23 Change CADD = 0 pF 2.8 6.1 ns
CADD derating 0.043 0.076 ns/pF
EBI30 NRD High to Chip Select Inactive CNCS = 0 pF 2.9 6.2 ns
CNCS derating 0.052 0.067 ns/pF
EBI31 Data Setup before NRD High(5) CNRD = 0 pF 8.0 ns
CNRD derating 0.044 ns/pF
EBI32 Data Hold after NRD High(5) CNRD = 0 pF -3.1 ns
CNRD derating -0.030 ns/pF
EBI33 NRD Minimum Pulse Width(1)(3) CNRD = 0 pF (n +1) tCP - 1.9(4) ns
CNRD derating 0.001 ns/pF
EBI34 NRD Minimum Pulse Width(2)(3) CNRD = 0 pF n x tCP + (tCH - 1.5)(4) ns
CNRD derating 0.001 ns/pF
13
AT91R40008
1795A–01/02
Notes: 1. If this condition is not met, the action depends on the read protocol intended for use.
• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.
• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.
2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be
programmed.
Table 13. EBI Read and Write Control Signals. Capacitance Limitation
Symbol Parameter Conditions Min Max Units
TCPLNRD(1) Master Clock Low Due to NRD Capacitance CNRD = 0 pF 7.3 ns
CNRD derating 0.044 ns/pF
TCPLNWR(2) Master CLock Low Due to NWR Capacitance CNWR = 0 pF 7.6 ns
CNWR derating 0.044 ns/pF
14 AT91R40008
1795A–01/02
Figure 6. EBI Signals Relative to MCKI
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
NCS
A1 - A23
NRD(1)
D0 - D15 Read
MCKI
NUB/NLB/A0
NRD(2)
NWAIT
NWR (No Wait States)
D0 - D15 to Write
NWR (Wait States)
No Wait Wait
EBI1/EBI2
EBI3
EBI4
EBI5EBI6
EBI7EBI9
EBI8EBI10
EBI11
EBI21
EBI22
EBI34
EBI26
CS
EBI23 EBI27-30
EBI24
EBI12-15
EBI16 EBI18
EBI18
EBI4
EBI33
EBI25
EBI32
EBI31
EBI19
EBI17
EBI20
15
AT91R40008
1795A–01/02
Peripheral Signals
USART Signals The inputs have to meet the minimum pulse width and period constraints shown in
Table 14 and Table 15, and represented in Figure 7.
Figure 7. USART Signals
Table 14. USART Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
US1SCK/RXD Minimum Pulse Width 5(tCP/2) ns
Table 15. USART Minimum Input Period
Symbol Parameter Min Input Period Units
US2SCK Minimum Input Period 9(tCP/2) ns
SCK
RXD
US1
US1
US2
16 AT91R40008
1795A–01/02
Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event
and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection
mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the
minimum pulse width and minimum input period shown in Table 16 and Table 17, and
as represented in Figure 8.
Figure 8. Timer Input
Reset Signals
A minimum pulse width is necessary, as shown in
Table 18
and as represented in
Figure 9
.
Figure 9. Reset Signal
Only the NRST rising edge is synchronized with MCKI. The falling edge is
asynchronous.
Table 16. Timer Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
TC1TCLK/TIOA/TIOB Minimum Pulse Width 3(tCP/2) ns
Table 17. Timer Input Minimum Period
Symbol Parameter Min Input Period Units
TC2 TCLK/TIOA/TIOB Minimum Input Period 5(tCP/2) ns
MCKI
TIOA/
TIOB/
TCLK
TC1
3(tCP/2) 3(tCP/2)
TC2
Table 18. Reset Minimum Pulse Width
Symbol Parameter Min Pulse-width Units
RST1NRST Minimum Pulse Width 10(tCP)ns
NRST
RST1
17
AT91R40008
1795A–01/02
Advanced Interrupt Controller
Signals
Inputs have to meet the minimum pulse width and minimum input period shown in Table
19 and Table 20 and represented in Figure 10.
Figure 10. AIC Signals
Parallel I/O Signals The inputs have to meet the minimum pulse width shown in Table 21 and represented in
Figure 11.
Figure 11. PIO Signal
Table 19. AIC Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
AIC1FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum
Pulse Width
3(tCP/2) ns
Table 20. AIC Input Minimum Period
Symbol Parameter Min Input Period Units
AIC2AIC Minimum Input Period 5(tCP/2) ns
MCKI
FIQ/IRQ0/
IRQ1/IRQ2/
IRQ3 Input
AIC1
AIC2
Table 21. PIO Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
PIO1PIO Input Minimum Pulse Width 3(tCP/2) ns
PIO
Inputs
PIO1
18 AT91R40008
1795A–01/02
ICE Interface Signals
Figure 12. ICE Interface Signal
Table 22. ICE Interface Timing Specifications
Symbol Parameter Conditions Min Max Units
ICE0
NTRST Minimum Pulse
Width 10.9 ns
ICE1
NTRST High Recovery
to TCK High 0.9 ns
ICE2
NTRST High Removal
from TCK High -0.3 ns
ICE3TCK Low Half-period 23.5 ns
ICE4TCK High Half-period 22.7 ns
ICE5TCK Period 46.1 ns
ICE6
TDI, TMS Setup before
TCK High 0.4 ns
ICE7
TDI, TMS Hold after
TCK High 0.4 ns
ICE8TDO Hold Time CTDO = 0 pF 3.3 ns
CTDO derating 0.001 ns/pF
ICE9TCK Low to TDO Valid CTDO = 0 pF 7.4 ns
CTDO derating 0.28 ns/pF
TCK
ICE3ICE4
ICE7
ICE6
ICE9
ICE8
TMS/TDI
TDO
ICE0
ICE5
NTRST
ICE1ICE2
© Atmel Corporation 2001.
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1795A–01/02/0M
