Unity-Gain Stable, Ultralow Distortion,
1 nV/Hz Voltage Noise, High Speed Op Amp
Data Sheet ADA4899-1
Rev. C Document Feedback
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FEATURES
Unity-gain stable
Ultralow noise: 1 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion −117 dBc at 1 MHz
High speed
−3 dB bandwidth: 600 MHz (G = +1)
Slew rate: 310 V/μs
Offset voltage: 230 μV maximum
Low input bias current: 100 nA
Wide supply voltage range: 5 V to 12 V
Supply current: 14.7 mA
High performance pinout
Disable mode
APPLICATIONS
Analog-to-digital drivers
Instrumentation
Filters
IF and baseband amplifiers
DAC buffers
Optical electronics
CONNECTION DIAGRAMS
DISABLE
05720-001
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE.
3–IN
4+IN
1
2FEEDBACK
6NIC
5–V
S
8+V
S
7V
OUT
A
DA4899-1
Figure 1. 8-Lead LFCSP (CP-8-13)
05720-002
FEEDBACK
ADA4899-1
TOP VIEW
(Not to Scale)
–IN
+IN
–V
S
DISABLE
+V
S
V
OUT
–V
S
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE.
1
2
3
4
8
7
6
5
Figure 2. 8-Lead SOIC (RD-8-1)
GENERAL DESCRIPTION
The ADA4899-1 is an ultralow noise (1 nV/√Hz) and distortion
(<−117 dBc at 1 MHz) unity-gain stable voltage feedback op
amp, the combination of which makes it ideal for 16-bit and
18-bit systems. The ADA4899-1 features a linear, low noise
input stage and internal compensation that achieves high slew
rates and low noise even at unity gain. The Analog Devices,
Inc., proprietary next-generation XFCB process and innovative
circuit design enable such high performance amplifiers.
The ADA4899-1 drives 100 Ω loads at breakthrough performance
levels with only 15 mA of supply current. With the wide supply
voltage range (4.5 V to 12 V), low offset voltage (230 μV maxi-
mum), wide bandwidth (600 MHz), and slew rate (310 V/μs),
the ADA4899-1 is designed to work in the most demanding
applications. The ADA4899-1 also features an input bias current
cancellation mode that reduces input bias current by a factor of 60.
The ADA4899-1 is available in a 3 mm × 3 mm LFCSP and an
8-lead SOIC package. Both packages feature an exposed metal
paddle that improves heat transfer to the ground plane, which is
a significant improvement over traditional plastic packages. The
ADA4899-1 is rated to work over the extended industrial
temperature range, −40°C to +125°C.
05720-071
1001010.1
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40 G = +1
V
S
= ±5V
R
L
= 1kΩ
V
OUT
= 2V p-p
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD3
HD2
Figure 3. Harmonic Distortion vs. Frequency
ADA4899-1 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications with ±5 V Supply ..................................................... 3
Specifications with +5 V Supply ..................................................... 4
Absolute Maximum Ratings ............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 13
Packaging Innovation ................................................................ 13
DISABLE Pin .............................................................................. 13
Applications Information .............................................................. 14
Unity-Gain Operation ............................................................... 14
Recommended Values for Various Gains ................................ 14
Noise ............................................................................................ 15
ADC Driver ................................................................................. 15
DISABLE Pin Operation ........................................................... 16
ADA4899-1 Mux ........................................................................ 16
Circuit Considerations .............................................................. 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
5/2016—Rev. B to Rev. C
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 1 and Figure 2 ................................................... 1
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
6/2007—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 21 and Figure 22 ............................................... 8
Changes to Packaging Innovation Section .................................. 13
Changes to Figure 49 and Figure 50 ............................................. 15
Updated Outline Dimensions ....................................................... 18
4/2006—Rev. 0 to Rev. A
Changes to Figure 2 .......................................................................... 1
10/2005—Revision 0: Initial Version
Data Sheet ADA4899-1
Rev. C | Page 3 of 20
SPECIFICATIONS WITH ±5 V SUPPLY
TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
V
OUT
= 25 mV p-p
600
MHz
VOUT = 2 V p-p 80 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p 35 MHz
Slew Rate VOUT = 5 V step 310 V/µs
Settling Time to 0.1% VOUT = 2 V step 50 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3 (dBc) fC = 500 kHz, VOUT = 2 V p-p −123/−123 dBc
fC = 10 MHz, VOUT = 2 V p-p −80/−86 dBc
Input Voltage Noise
f = 100 kHz
1.0
nV/√Hz
Input Current Noise f = 100 kHz, DISABLE pin floating 2.6 pA/√Hz
f = 100 kHz, DISABLE pin = +VS 5.2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 35 230 µV
Input Offset Voltage Drift 5 µV/°C
Input Bias Current DISABLE pin floating −6 −12 µA
DISABLE pin = +VS −0.1 −1 µA
Input Bias Current Drift 3 nA/°C
Input Bias Offset Current 0.05 0.7 µA
Open-Loop Gain 82 85 dB
INPUT CHARACTERISTICS
Input Resistance Differential mode 4 kΩ
Common mode 7.3 MΩ
Input Capacitance 4.4 pF
Input Common-Mode Voltage Range −3.7 to +3.7 V
Common-Mode Rejection Ratio 98 130 dB
DISABLE PIN
DISABLE Input Threshold Voltage Output disabled <2.4 V
Turn-Off Time 50% of DISABLE voltage to 10% of VOUT,
VIN = 0.5 V
100 ns
Turn-On Time 50% of DISABLE voltage to 90% of VOUT,
VIN = 0.5 V
40 ns
Input Bias Current DISABLE = +VS (enabled) 17 21 µA
DISABLE = −VS (disabled) −35 −44 µA
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time (Rise/Fall) VIN = −2.5 V to +2.5 V, G = +2 30/50 ns
Output Voltage Swing RL = 1 kΩ −3.65 to +3.65 −3.7 to +3.7 V
R
L
= 100 Ω
−3.13 to +3.15
−3.25 to +3.25
V
Short-Circuit Current Sinking/sourcing 160/200 mA
Off Isolation f = 1 MHz, DISABLE = −VS −48 dB
POWER SUPPLY
Operating Range 4.5 12 V
Quiescent Current 14.7 16.2 mA
Quiescent Current (Disabled) DISABLE = −VS 1.8 2.1 mA
Positive Power Supply Rejection Ratio +VS = 4 V to 6 V (input referred) 84 90 dB
Negative Power Supply Rejection Ratio
−V
S
= −6 V to −4 V (input referred)
87
93
dB
ADA4899-1 Data Sheet
Rev. C | Page 4 of 20
SPECIFICATIONS WITH +5 V SUPPLY
VS = 5 V at TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
V
OUT
= 25 mV p-p
535
MHz
VOUT = 2 V p-p 60 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p 25 MHz
Slew Rate VOUT = 2 V step 185 V/µs
Settling Time to 0.1% VOUT = 2 V step 50 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3 (dBc) fC = 500 kHz, VOUT = 1 V p-p −100/−113 dBc
fC = 10 MHz, VOUT = 1 V p-p −89/−100 dBc
f = 100 kHz
1.0
nV/√Hz
Input Current Noise f = 100 kHz, DISABLE pin floating 2.6 pA/√Hz
f = 100 kHz, DISABLE pin = +VS 5.2 pA/√Hz
Input Offset Voltage 5 210 µV
Input Offset Voltage Drift 5 µV/°C
Input Bias Current DISABLE pin floating −6 −12 µA
DISABLE pin = +VS −0.2 −1.5 µA
Input Bias Offset Current 0.05 µA
Input Bias Offset Current Drift 2.5 nA/°C
Open-Loop Gain 76 80 dB
Input Resistance Differential mode 4 kΩ
Common mode 7.7 MΩ
Input Capacitance 4.4 pF
Input Common-Mode Voltage Range 1.3 to 3.7 V
Common-Mode Rejection Ratio 90 114 dB
DISABLE PIN
DISABLE Input Threshold Voltage Output disabled <2.4 V
Turn-Off Time 50% of DISABLE voltage to 10% of VOUT,
VIN = 0.5 V
100 ns
Turn-On Time 50% of DISABLE voltage to 90% of VOUT,
VIN = 0.5 V
60 ns
Input Bias Current DISABLE = +VS (enabled) 16 18 µA
DISABLE = −VS (disabled) −33 −42 µA
OUTPUT CHARACTERISTICS
Overdrive Recovery Time (Rise/Fall) VIN = 0 V to 2.5 V, G = +2 50/70 ns
Output Voltage Swing RL = 1 kΩ 1.25 to 3.75 1.2 to 3.8 V
R
L
= 100 Ω
1.4 to 3.6
1.35 to 3.65
V
Short-Circuit Current Sinking/sourcing 60/80 mA
Off Isolation f = 1 MHz, DISABLE = −VS −48 dB
Operating Range 4.5 12 V
Quiescent Current 14.3 16 mA
Quiescent Current (Disabled) DISABLE = −VS 1.5 1.7 mA
Positive Power Supply Rejection Ratio +VS = 4.5 V to 5.5 V, −VS = 0 V (input referred) 84 90 dB
+V
S
= 5 V, −V
S
= −0.5 V to +0.5 V (input referred)
86
90
dB
Data Sheet ADA4899-1
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 12.6 V
Power Dissipation
See Figure 4
Differential Input Voltage ±1.2 V
Differential Input Current ±10 mA
Storage Temperature Range –65°C to +150°C
Operating Temperature Range –40°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4899-1
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4899-1.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power – Load Power)
( )
L
OUT
L
OUTS
SSD R
V
R
VV
IVP 2
–
2
×+×=
RMS output voltages should be considered. If RL is referenced to
VS–, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
( ) ( )
L
S
SS
DR
/V
IVP
2
4
+×=
In single-supply operation with RL referenced to VS–, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. Soldering the exposed paddle to the ground
plane significantly reduces the overall thermal resistance of the
package.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(EPAD) 8-lead SOIC (70°C/W) and 8-lead LFCSP (70°C/W)
packages on a JEDEC standard 4-layer board. θJA values are
approximations.
05720-003
AMBI E NT TE M P E RATURE ( °C) 120–40 –20 020 40 60 80 100
MAXIMUM POWER DISSIPATIO N (W)
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LFCSP AND S OI C
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ADA4899-1 Data Sheet
Rev. C | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
05720-004
1000110010
–12
–9
–6
–3
0
3
VS = ±5V
RL = 1kΩ
VOUT = 25mV p-p G = –1
G = +1
G = +2
G = +5
G = +10
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Gains, RL = 1 kΩ
05720-005
1000110010
–12
–9
–6
–3
0
3V
S
= ±5V
R
L
= 100Ω
V
OUT
= 25mV p - p G = –1
G = +1
G = +2
G = +5
G = +10
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Gains, RL = 100 Ω
05720-006
100010 100
–12
–9
–6
–3
0
3
G = +1
VS = ±5V
RL = 1kΩ
VOUT = 25mV p-p
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
T = + 125°C
T = –40°C
Figure 7. Small Signal Frequency Response for Various Temperatures
05720-007
100010 100
–12
–9
–6
–3
0
3G = +1
RL = 100Ω
VOUT = 25mV p-p
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
VS = ±5V
VS = +5V
Figure 8. Small Signal Frequency Response for Various Supply Voltages
C
L
= 15pF
R
SNUB
= 10Ω C
L
= 15pF
C
L
= 5pF
C
L
= 2pF
C
L
= 0pF
05720-032
100010010
–12
–9
–6
–3
0
3
6
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
G = +1
R
L
= 1kΩ
V
OUT
= 25mV p - p
Figure 9. Small Signal Frequency Response for Capacitive Loads
05720-031
45403530
2520151050
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
PEAKI NG (dB)
CAPACITIVE LOAD (pF)
V
S
= ±5V
V
OUT
= 25mV p - p
G = +1
R
L
= 1kΩ
G = +1
R
L
= 100Ω
G = +2
R
L
= 1kΩ
G = +1
R
L
= 1kΩ
R
SNUB
= 10Ω
Figure 10. Small Signal Frequency Response Peaking vs.
Capacitive Load for Various Gains
Data Sheet ADA4899-1
Rev. C | Page 7 of 20
05720-010
100110
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
G = +2
VS = ±5V
RL = 150Ω
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
VOUT = 2V p-p
VOUT = 100mV p-p
Figure 11. 0.1 dB Flatness for Various Output Voltages
05720-011
100010 100
–12
0
–3
–6
–9
3G = +1
RL = 1kΩ
VOUT = 2V p-p
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
VS = ±5V
VS = +5V
Figure 12. Large Signal Frequency Response for Various Supply Voltages
05720-027
100M10M
1M100k10k1k10010
0.1
1
10
VOLTAGE NOISE (nV/ Hz)
FREQUENCY ( Hz )
Figure 13. Voltage Noise vs. Frequency
05720-009
1000
110 100
–12
–9
–6
–3
0
3G = +1
V
S
= ±5V
R
L
= 100Ω
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
V
OUT
= 1V p-p
V
OUT
= 4V p-p
V
OUT
= 7V p-p
Figure 14. Large Signal Frequency Response for Various Output Voltages
05720-030
10001001010.10.010.001
–20
0
20
40
60
80
100
0
30
60
90
120
150
180
OPEN-LOOP GAIN (dB)
OPE N- LO OP PHAS E ( Degrees)
FREQUENCY (MHz)
V
S
= ±5V
R
L
= 100Ω
Figure 15. Open-Loop Gain/Phase vs. Frequency
05720-028
100M10M
1M100k10k1k10010
1
10
100
1k
CURRENT NOI S E ( pA/ Hz )
FREQUENCY ( Hz )
DISABLE = NC
DISABLE = 5V
Figure 16. Input Current Noise vs. Frequency
ADA4899-1 Data Sheet
Rev. C | Page 8 of 20
05720-021
1001010.1
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40 G = +1
V
S
= ±5V
R
L
= 1kΩ
V
OUT
= 2V p-p
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD3
HD2
Figure 17. Harmonic Distortion vs. Frequency
05720-022
87654321
–120
–110
–100
–90
–80
–70
–60
–50
–
40 G = +1
R
L
= 1kΩ
f = 5MHz
HARMONIC DISTORTION (dBc)
OUTPUT AMPLITUDE (V p-p)
HD3
HD2
Figure 18. Harmonic Distortion vs. Output Amplitude
05720-023
1001010.1
–120
–110
–100
–90
–80
–70
–60
–50
–
40 G = +1
R
L
= 1kΩ
V
S
= 5V
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
V
OUT
= 2V p-p
V
OUT
= 1V p-p
HD3
HD2
HD3
HD2
Figure 19. Harmonic Distortion vs. Frequency
05720-024
1001010.1
–120
–110
–100
–90
–80
–70
–60
–50
–
40 G = +5
R
L
= 1kΩ
V
S
= ±5V
V
OUT
= 2V p-p
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD2
HD3
Figure 20. Harmonic Distortion vs. Frequency
G = +5
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 2V p-p
05720-043
1001010.1
–120
–110
–100
–90
–80
–70
–60
–50
–
40
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD2
SOIC
–V
S
ON PIN 5
HD2
SOIC
–V
S
ON PIN 4
HD3
SOIC
–V
S
ON PIN 4 OR PIN 5
HD2
LFCSP
HD3
LFCSP
Figure 21. Harmonic Distortion vs. Frequency for
Various Pinouts and Packages
G = +1
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 2V p-p
05720-044
1001010.1
–120
–110
–100
–90
–80
–70
–60
–50
–
40
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD3
LFCSP OR SOIC
HD2
SOIC
HD2
LFCSP
Figure 22. Harmonic Distortion vs. Frequency for Both Packages
Data Sheet ADA4899-1
Rev. C | Page 9 of 20
05720-041
151050
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
OUTPUT VOLTAGE (V)
TIME (ns)
G = +1
V
S
= ±5V
R
L
= 1kΩ
C
L
= 0pF
C
L
= 15pF C
L
= 5pF
C
L
= 15pF
R
SNUB
= 10Ω
Figure 23. Small Signal Transient Response for
Various Capacitive Loads (Rising Edge)
05720-019
1009080706050403020100
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08 R
L
= 1kΩ
V
S
= ±5V
G = +2
G = +5
G = +10
OUTPUT VOLTAGE (V)
TIME (ns)
Figure 24. Small Signal Transient Response for Various Gains
05720-017
1009080706050403020100
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
G = +1
R
L
= 100Ω
V
S
= ±5V
V
S
= +5V
OUTPUT VOLTAGE (V)
TIME (ns)
Figure 25. Large Signal Transient Response for
Various Supply Voltages, RL = 100 Ω
05720-042
151050
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
OUTPUT VOLTAGE (V)
TIME (ns)
G = +1
V
S
= ±5V
R
L
= 1kΩ
C
L
= 0pF
C
L
= 15pF
C
L
= 5pF
C
L
= 15pF
R
SNUB
= 10Ω
Figure 26. Small Signal Transient Response for
Various Capacitive Loads (Falling Edge)
05720-013
1009080706050403020100
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
R
L
= 1kΩ
V
S
= ±5V
OUTPUT VOLTAGE (V)
TIME (ns)
G = +2
G = +5
G = +10
Figure 27. Large Signal Transient Response for Various Gains
05720-018
1009080706050403020100
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
G = +1
R
L
= 1kΩ
V
S
= ±5V
V
S
= +5V
OUTPUT VOLTAGE (V)
TIME (ns)
Figure 28. Large Signal Transient Response for
Various Supply Voltages, RL = 1 kΩ
ADA4899-1 Data Sheet
Rev. C | Page 10 of 20
OUTPUT SETTLING (%)
05720-025
1500 25 50 75 100 125
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
G = +1
V
S
= ±5V
R
L
= 1kΩ
VOLTAGE (V)
TIME (ns)
INPUT
OUTPUT
ERROR
Figure 29. Settling Time, G = +1
OUTPUT SETTLING (%)
05720-026
1500 25 50 75 100 125
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
G = +5
V
S
= ±5V
R
L
= 1kΩ
VOLTAGE (V)
TIME (ns)
INPUT
OUTPUT ERROR
Figure 30. Settling Time, G = +5
05720-016
10001001010.1
10
100
1k
10k
100k
INPUT IMPEDANCE (Ω)
FREQUENCY (MHz)
G = +1
V
S
= ±5V
DISABLE = NC
Figure 31. Input Impedance vs. Frequency
05720-015
10001001010.10.010.001
0.001
0.01
0.1
1
10
OUTPUT IMPEDANCE (Ω)
FREQUENCY (MHz)
G = +1
V
S
= ±5V
DISABLE = NC
Figure 32. Output Impedance vs. Frequency
05720-014
10001001010.1
10
100
1k
10k
100k
OUTPUT IMPEDANCE (Ω)
FREQUENCY (MHz)
G = +1
V
S
= ±5V
DISABLE = –5V
Figure 33. Output Impedance vs. Frequency (Disabled)
05720-020
1G100M10M1M100k10k1k10010
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–
20 G = +1
R
L
= 1kΩ
R
F
= 1kΩ
COMMON-MODE REJECTION (dB)
FREQUENCY (Hz)
V
S
= +5V
V
S
= ±5V
Figure 34. Common-Mode Rejection vs. Frequency
Data Sheet ADA4899-1
Rev. C | Page 11 of 20
05720-029
10001001010.10.010.001
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
SUPPLY REJECTION (dB)
FREQUENCY (MHz)
–PSR
+PSR
Figure 35. Power Supply Rejection
05720-012
10000.1 1 10 100
–70
–64
–58
–52
–46
–40
–34
–28
–
22 V
S
= ±5V
DISABLE = –5V
ISOLATION (dB)
FREQUENCY (MHz)
Figure 36. Off Isolation vs. Frequency
05720-033
0.9–0.9 –0.6 –0.3 0 0.3 0.6
0
700
600
500
400
300
200
100
COUNT
INPUT BIAS CURRENT (µA)
N: 4653
MEAN: –0.083µA
SD: 0.13µA
V
S
= ±5V
Figure 37. Input Bias Current Distribution
05720-034
200–200 –150 –100 –50 0 50 100 150
0
500
400
300
200
100
COUNT
VOLTAGE OFFSET (µV)
N: 4651
MEAN: –4.92µV
SD: 29.22µV
V
S
= 5V
Figure 38. Input Offset Voltage Distribution (VS = 5 V)
05720-035
200–200 –150 –100 –50 0 50 100 150
0
500
400
300
200
100
COUNT
VOLTAGE OFFSET (µV)
N: 4655
MEAN: –34.62µV
SD: 28.94µV
V
S
= ±5V
Figure 39. Input Offset Voltage Distribution (VS = ±5 V)
ADA4899-1 Data Sheet
Rev. C | Page 12 of 20
TEST CIRCUITS
05720-045
VOUT
–VS
+
V
S
RL
10µF
10µF
24.9Ω
49.9Ω
V
IN
0.1µF
0.1µF
Figure 40. Typical Noninverting Load Configuration
05720-038
V
OUT
+
V
S
AC
–V
S
10µF
1kΩ10Ω
49.9Ω
R
L
10Ω
0.1µF
Figure 41. Positive Power Supply Rejection
05720-036
VOUT
+
V
S
–VS
RL
10µF
10µF
1kΩ
1kΩ
1kΩ
1kΩ
53.6Ω
VIN
0.1µF
0.1µF
Figure 42. Common-Mode Rejection
05720-040
V
OU
T
V
IN
+
V
S
–V
S
R
F
R
G
R
SNUB
R
T
10µF
10µF
R
L
C
L
0.1µF
0.1µF
Figure 43. Typical Capacitive Load Configuration
05720-039
V
OUT
+
V
S
–V
S
1kΩ10Ω
49.9Ω
10Ω
0.1µF
10µF
AC
R
L
Figure 44. Negative Power Supply Rejection
Data Sheet ADA4899-1
Rev. C | Page 13 of 20
THEORY OF OPERATION
The ADA4899-1 is a voltage feedback op amp that combines
unity-gain stability with a 1 nV/√Hz input noise. It employs a
highly linear input stage that can maintain greater than −80 dBc
(at 2 V p-p) distortion out to 10 MHz while in a unity-gain
configuration. This rare combination of low gain stability,
input-referred noise, and extremely low distortion is the result
of Analog Devices proprietary op amp architecture and high
speed complementary bipolar processing technology.
The simplified ADA4899-1 topology, shown in Figure 45, is a
single gain stage with a unity-gain output buffer. It has over
80 dB of open-loop gain and maintains precision specifications
such as CMRR, PSRR, and offset to levels that are normally
associated with topologies having two or more gain stages.
BUFFERgm
C
C
R1 R
L
V
OUT
05720-060
Figure 45. ADA4899-1 Topology
A pair of internally connected diodes limits the differential
voltage between the noninverting input and the inverting input
of the ADA4899-1. Each set of diodes has two series diodes
connected in antiparallel, which limits the differential voltage
between the inputs to approximately ±1.2 V. All of the ADA4899-1
pins are ESD protected with voltage-limiting diodes connected
between both rails. The protection diodes can handle 10 mA.
Currents should be limited through these diodes to 10 mA or less
by using a series limiting resistor.
PACKAGING INNOVATION
The ADA4899-1 is available in both a SOIC and an LFCSP, each
of which has a thermal pad that allows the device to run cooler,
thereby increasing reliability. To help avoid routing around the
pad when laying out the board, both packages have a dedicated
feedback pin on the opposite side of the package for ease in
connecting the feedback network to the inverting input. The
secondary output pin also isolates the interaction of any
capacitive load on the output and the self-inductance of the
package and bond wire from the feedback loop. When using the
dedicated feedback pin, inductance in the primary output helps to
isolate capacitive loads from the output impedance of the
amplifier.
Both the SOIC and LFCSP have modified pinouts to improve
heavy load second harmonic distortion performance. The intent
of both is to isolate the negative supply pin from the noninverting
input. The LFCSP accomplishes this by rotating the standard
8-lead package pinout counterclockwise by one pin, which puts
the supply and output pins on the right side of the package and
the input pins on the left side of the package. The SOIC is
slightly different with the intent of both isolating the inputs
from the supply pins and giving the user the option of using the
ADA4899-1 in a standard SOIC board layout with little or no
modification. Taking the unused Pin 5 and making it a second
negative supply pin allows for both an input isolated layout and
a traditional layout to be supported.
DISABLE PIN
A three-state input pin is provided on the ADA4899-1 for a
high impedance disable and an optional input bias current
cancellation circuit. The high impedance output allows several
ADA4899-1 devices to drive the same ADC or output line time
interleaved. Pulling the DISABLE pin low activates the high
impedance state (see Table 7 for threshold levels). When the
DISABLE pin is left floating (open), the ADA4899-1 operates
normally. With the DISABLE pin pulled within 0.7 V of the
positive supply, an optional input bias current cancellation
circuit is turned on, which lowers the input bias current to less
than 200 nA. In this mode, the user can drive the ADA4899-1
from a high dc source impedance and still maintain minimal
output-referred offset without having to use impedance matching
techniques. In addition, the ADA4899-1 can be ac-coupled
while setting the bias point on the input with a high dc impedance
network. The input bias current cancellation circuit doubles the
input-referred current noise, but this effect is minimal as long
as the wideband impedances are kept low (see Figure 16).
ADA4899-1 Data Sheet
Rev. C | Page 14 of 20
APPLICATIONS INFORMATION
UNITY-GAIN OPERATION
The ADA4899-1 schematic for unity-gain configuration is
nearly a textbook example (see Figure 46). The only exception is
the small 24.9 Ω series resistor at the noninverting input. The
series resistor is only required in unity-gain configurations;
higher gains negate the need for the resistor. In Table 4, it can be
seen that the overall noise contribution of the amplifier and the
24.9 Ω resistor is equivalent to the noise of a single 87 Ω resistor.
Figure 47 shows the small signal frequency response for the
unity-gain amplifier shown in Figure 46.
05720-037
V
OUT
+
V
S
–V
S
0.1µF
24.9Ω
V
IN
0.1µF
Figure 46. Unity-Gain Schematic
05720-063
100001 10010 1000
–12
–9
–6
–3
0
3G = +1
R
L
= 100Ω
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
25mV p-p
50mV p-p
200mV p-p
100mV p-p
Figure 47. Small Signal Frequency Response for Various Output Voltages
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 4 provides a handy reference for determining various
gains and associated performance. For noise gains greater than
one, the Series Resistor RS is not required. Resistor RF and
Resistor RG are kept low to minimize their contribution to the
overall noise performance of the amplifier.
Table 4. Conditions: VS = ±5 V, TA = 25°C, RL = 1 kΩ
Gain RF (Ω) RG (Ω) RS (Ω)
−3 dB SS BW (MHz)
(25 mV p-p)
Slew Rate (V/μs)
(2 V Step)
ADA4899-1 Voltage
Noise (nV/√Hz)
Total Voltage
Noise (nV/√Hz)
+1 0 Not applicable 24.9 605 274 1 1.2
−1 100 100 0 294 265 2 2.7
+2 100 100 0 277 253 2 2.7
+5 200 49.9 0 77 227 5 6.5
+10 453 49.9 0 37 161 10 13.3
Data Sheet ADA4899-1
Rev. C | Page 15 of 20
NOISE
To analyze the noise performance of an amplifier circuit, first
identify the noise sources, then determine if the source has a
significant contribution to the overall noise performance of the
amplifier. To simplify the noise calculations, noise spectral
densities were used, rather than actual voltages to leave bandwidth
out of the expressions (noise spectral density, which is generally
expressed in nV/Hz, is equivalent to the noise in a 1 Hz
bandwidth).
The noise model shown in Figure 48 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the amplifier.
Each noise source has its own contribution to the noise at the
output. Noise is generally specified referred to input (RTI), but
it is often simpler to calculate the noise referred to the output
(RTO) and then divide by the noise gain to obtain the RTI noise.
GAIN FROM
B TO OUTPUT = – R2
R1
GAIN FROM
A TO OUTPUT =
NOISE GAIN =
NG = 1 + R2
R1
I
N–
V
N
V
N, R1
V
N, R3
R1
R2
I
N+
R3
4kTR2
4kTR1
4kTR3
V
N, R2
B
A
V
N2
+ 4kTR3 + 4kTR1 R2
2
R1 + R2
I
N+2
R3
2
+ I
N–2
R1 × R2
2
+ 4kTR2 R1
2
R1 + R2 R1 + R2
RTI NOISE =
RTO NOISE = NG × RTI NOISE
V
OUT
+
0
5720-070
Figure 48. Op Amp Noise Analysis Model
All resistors have a Johnson noise that is calculated by
)(4kBTR
where:
k is Boltzmann’s Constant (1.38 × 10–23 J/K).
B is the bandwidth in Hz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.
A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nVHz at 25°C.
In applications where noise sensitivity is critical, take care not to
introduce other significant noise sources to the amplifier. Each
resistor is a noise source. Attention to design, layout, and
component selection is critical to maintain low noise
performance. A summary of noise performance for the
amplifier and associated resistors can be seen in Table 4.
ADC DRIVER
The ultralow noise and distortion performance of the
ADA4899-1 makes it an excellent candidate for driving 16-bit
ADCs. The schematic for a single-ended input buffer using the
ADA4899-1 and the AD7677, a 1 MSPS, 16-bit ADC, is shown
in Figure 49. Table 5 shows the performance data of the
ADA4899-1 and the AD7677.
05720-062
+5V
A
NALO
G
INPUT ADA4899-1
–5V
2.7nF
25Ω
15Ω
+5V
A
NALO
G
INPUT
+
–ADA4899-1
–5V
2.7nF
25Ω
15Ω
AD7677
IN+
IN–
Figure 49. Single-Ended Input ADC Driver
Table 5. ADA4899-1, Single-Ended Driver for AD7677 16-Bit,
1 MSPS, fC = 50 kHz
Parameter Measurement (dB)
Second Harmonic Distortion −116.5
Third Harmonic Distortion −111.9
THD −108.6
SFDR +101.4
SNR +92.6
The ADA4899-1 configured as a single-ended-to-differential
driver for the AD7677 is shown in Figure 50. Table 6 shows the
associated performance.
05720-061
+5V
+2.5V REF
A
NALO
G
INPUT ADA4899-1
–5V
590Ω
590Ω
+5V
+2.5V
REF ADA4899-1
–5V
2.7nF
2.7nF
590Ω
590Ω
590Ω15Ω
15Ω
590Ω
AD7677
IN+
IN–
Figure 50. Single-Ended-to-Differential ADC Driver
Table 6. ADA4899-1, Single Ended-to-Differential Driver for
AD7677 16-Bit, 1 MSPS, fC = 500 kHz
Parameter Measurement (dB)
THD −92.7
SFDR +91.8
SNR +90.6
ADA4899-1 Data Sheet
Rev. C | Page 16 of 20
DISABLE PIN OPERATION
The ADA4899-1 DISABLE pin performs three functions:
enable, disable, and reduction of the input bias current. When
the DISABLE pin is brought to within 0.7 V of the positive
supply, the input bias current circuit is enabled, which reduces
the input bias current by a factor of 100. In this state, the input
current noise doubles from 2.6 pA/Hz to 5.2 pA/Hz. Table 7
outlines the DISABLE pin operation.
Table 7. DISABLE Pin Truth Table
Supply Voltage ±5 V +5 V
Disable −5 V to +2.4 V 0 V to 2.4 V
Enable Open Open
Low Input Bias Current 4.3 V to 5 V 4.3 V to 5 V
ADA4899-1 MUX
With a true output disable, the ADA4899-1 can be used in
multiplexer applications. The outputs of two ADA4899-1
devices are wired together to form a 2:1 mux. Figure 51 shows
the 2:1 mux schematic.
05720-064
1MHz
0
V TO 5V
+5V
–5V +5V
–5V
0.1µF
0.1µF
ADA4899-1
2V p-p
15MHz
+5
V
–5V
0.1µF
0.1µF
ADA4899-1
0.1µF2.2µF
0.1µF2.2µF
+
+
2kΩ
1kΩ50Ω
1.02kΩ
50Ω
V
REF
= 2.50V
2kΩ
1V p-p
15MHz
DISABLE
AD8137
DISABLE
50Ω
R
T
50Ω
V
OUT
Figure 51. ADA4899-1 2:1 Mux Schematic
An AD8137 differential amplifier is used as a level translator
that converts the TTL input to a complementary ±3 V output to
drive the DISABLE pins of the ADA4899-1 devices. The
transient response for the 2:1 mux is shown in Figure 52.
05720-065
2
1
CH1 = 500mV/DIV
CH2 = 5V/DIV
200ns/DIV
Figure 52. ADA4899-1 2:1 Mux Transient Response
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the
ADA4899-1 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.
PCB Layout
Because the ADA4899-1 can operate up to 600 MHz, it is
essential that RF board layout techniques be employed. All
ground and power planes under the pins of the ADA4899-1
should be cleared of copper to prevent the formation of parasitic
capacitance between the input pins to ground and the output
pins to ground. A single mounting pad on a SOIC footprint can
add as much as 0.2 pF of capacitance to ground if the ground
plane is not cleared from under the mounting pads. The low
distortion pinout of the ADA4899-1 reduces the distance
between the output and the inverting input of the amplifier.
This helps minimize the parasitic inductance and capacitance
of the feedback path, which reduces ringing and second harmonic
distortion.
Power Supply Bypassing
Power supply bypassing for the ADA4899-1 has been optimized
for frequency response and distortion performance. Figure 40
shows the recommended values and location of the bypass
capacitors. Power supply bypassing is critical for stability,
frequency response, distortion, and PSR performance. The
0.1 μF capacitors shown in Figure 40 should be as close to the
supply pins of the ADA4899-1 as possible. The electrolytic
capacitors should be directly adjacent to the 0.1 μF capacitors.
The capacitor between the two supplies helps improve PSR and
distortion performance. In some cases, additional paralleled
capacitors can help improve frequency and transient response.
Data Sheet ADA4899-1
Rev. C | Page 17 of 20
Grounding
Use ground and power planes where possible. Ground and
power planes reduce the resistance and inductance of the power
planes and ground returns. The returns for the input, output
terminations, bypass capacitors, and RG should all be kept as
close to the ADA4899-1 as possible. The output load ground
and the bypass capacitor grounds should be returned to the
same point on the ground plane to minimize parasitic trace
inductance, ringing, and overshoot and to improve distortion
performance.
The ADA4899-1 packages feature an exposed paddle. For
optimum electrical and thermal performance, solder this
paddle to ground. For more information on high speed circuit
design, see A Practical Guide to High-Speed Printed-Circuit-
Board Layout.
ADA4899-1 Data Sheet
Rev. C | Page 18 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDE C S TANDARDS MS-012-AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 M AX
0.05 NO M
3.81 REF
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BSC
SEATING
PLANE
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
Figure 53. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-1)
Dimensions shown in millimeters
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN 1
INDICATOR
(R 0.15)
Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding Ordering Quantity
ADA4899-1YRDZ –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1
ADA4899-1YRDZ-R7 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1,000
ADA4899-1YRDZ-RL
–40°C to +125°C
8-Lead SOIC_N_EP
RD-8-1
2,500
ADA4899-1YCPZ-R2 –40°C to +125°C 8-Lead LFCSP CP-8-13 250
ADA4899-1YCPZ-R7 –40°C to +125°C 8-Lead LFCSP CP-8-13 HBC 1,500
ADA4899-1YCPZ-RL –40°C to +125°C 8-Lead LFCSP CP-8-13 HBC 5,000
1 Z = RoHS Compliant Part.
Data Sheet ADA4899-1
Rev. C | Page 19 of 20
NOTES
ADA4899-1 Data Sheet
Rev. C | Page 20 of 20
NOTES
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