Revision 1.1
Jan. 2004
1
R0201-BS616LV2017
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 60mA (@55ns) operating current
I -grade: 62mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
1.0uA(Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
The BS616LV2017 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.0uA at 5.0V /25oC and maximum access time of 55ns at 5.0V/ 85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2017 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
BS616LV2017
SPEED
( ns ) STANDBY
( ICCSB1, Max )
Operating
( ICC, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=5.0V Vcc=5.0V
PKG TYPE
BS616LV2017DC DICE
BS616LV2017EC TSOP2-44
BS616LV2017AC
+0 O C to +70 O C4.5V ~5.5V 55/70 10uA 53mA
BGA-48-0608
BS616LV2017DI DICE
BS616LV2017EI TSOP2-44
BS616LV2017AI
-40 O C to +85 O C4.5V ~ 5.5V 55/70 30uA 62mA
BGA-48-0608
BSI
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A3 A2 A1
Data
Buffer
Input
Control
Gnd
Vcc
OE
WE
CE
DQ15
DQ0
A16
A5
A6
A7
A15
A13
16
16
16
16
14
128
2048
1024
20
A14
A12
A9
A4
A0
A11
A8
Address
Input
Buffer
A10
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
G
H
F
E
D
C
B
A
123456
D15
D14
VSS
D9
D8
LB
VCC
N.C. A8 A9
D13
A12
A14
D12
D11
D10 A5
UB
OE
A3
A0
A11
A10
A13
A15
WE
D5
A16
A7
A6
D4
D3
D1
D7
D6
D2
A4
A1 A2
D0
N.C. VSS
VCC
N.C.
CE
N.C.
N.C.
N.C.
• I/O Configuration x8/x16 selectable by LB and UB pin
60mA
55mA
55ns 70ns
POWER DISSIPATION
55ns: 4.5~5.5V
70ns: 4.5~5.5V
• Easy expansion with CE and OE options
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BS616LV2017EC
BS616LV2017EI
Revision 1.1
Jan. 2004
2
R0201-BS616LV2017
PIN DESCRIPTIONS
BSI BS616LV2017
Name Function
A0-A16 Address Input These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power Supply
Gnd Ground
TRUTH TABLE
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
MODE CE WE OE LB UB D0~D7 D8~D15 Vcc CURRENT
HX X X X High Z High Z ICCSB , ICCSB1
Not selected
(Power Down) X X X H H High Z High Z ICCSB , ICCSB1
Output Disabled LH H X X High Z High Z ICC
L L Dout Dout ICC
H L High Z Dout ICC
Read L H L
L H Dout High Z ICC
LL Din Din I
CC
HL X Din I
CC
Write L L X
LH Din X I
CC
LXXHHHigh Z High Z ICC
Revision 1.1
Jan. 2004
3
R0201-BS616LV2017
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VDR Vcc for Data Retention CE ≧ Vcc - 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V
ICCDR Data Retention Current CE ≧ Vcc - 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.1 1.0 uA
tCDR Chip Deselect to Data
Retention Time 0 -- -- ns
tR Operation Recovery Time
See Retention Waveform
TRC
(2) -- -- ns
SYMBOL PARAMETER CONDITIONS MAX. UNIT
CIN Input
Capacitance VIN=0V 6 pF
CDQ Input/Output
Capacitance VI/O=0V 8 pF
RANGE AMBIENT
TEMPERATURE Vcc
Commercial 0 O C to +70 O C4.5V ~ 5.5V
Industrial -40 O C to +85 O C4.5V ~ 5.5V
1. Typical characteristics are at TA= 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC. 4.IccsB1_Max. is 10uA at Vcc=5.0V and TA=70oC.
5. Icc_Max. is 60mA(@55ns) / 53mA(@70ns) at Vcc=5.0 and TA=0~70oC.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
1. Vcc = 1.5V, TA= + 25OC2.t
RC = Read Cycle Time
3. IccDR_MAX. is 0.7uA at TA=70oC.
ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL PARAMETER RATING UNITS
VTERM Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5 V
TBIAS Temperature Under Bias -40 to +85 O C
TSTG Storage Temperature -60 to +150 O C
PTPower Dissipation 1.0 W
IOUT DC Output Current 20 mA
BSI BS616LV2017
(3)
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VIL Guaranteed Input Low
Voltage(2) Vcc =5.0V -0.5 -- 0.8 V
VIH Guaranteed Input High
Voltage(2) Vcc =5.0V 2.2 -- Vcc+0.3 V
IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA
ILO Output Leakage Current Vcc = Max,CE = VIH or OE = VIH,
VI/O = 0V to Vcc -- -- 1 uA
VOL Output Low Voltage Vcc = Max, IOL = 2.0mA Vcc =5.0V -- -- 0.4 V
VOH Output High Voltage Vcc = Min, IOH = -1.0mA Vcc =5.0V 2.4 -- -- V
70ns 55
ICC(5) Operating Power Supply
Current
CE = VIL,
IDQ = 0mA, F = Fmax(3) Vcc =5.0V
55ns
-- --
62
mA
ICCSB Standby Current-TTL
CE=VIH
IDQ = 0mA Vcc =5.0V -- -- 1.0 mA
ICCSB1(4) Standby Current-CMOS
CE≧Vcc-0.2V,
VIN≧Vcc-0.2V or VIN≦0.2V Vcc =5.0V -- 1.0 30 uA
Revision 1.1
Jan. 2004
4
R0201-BS616LV2017
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION (Vcc = 4.5~5.5V) (Vcc = 4.5~5.5V) UNIT
tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns
tAVQV tAA Address Access Time -- -- 55 -- -- 70 ns
tELQV tACS Chip Select Access Time (CE) -- -- 55 -- -- 70 ns
tBA tBA Data Byte Control Access Time (LB,UB)----30----35 ns
tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns
tE1LQX tCLZ Chip Select to Output Low Z (CE) 10 -- -- 10 -- -- ns
tBE tBE Data Byte Control to Output Low Z (LB,UB)10----10---- ns
tGLQX tOLZ Output Enable to Output in Low Z 5----5---- ns
tEHQZ tCHZ Chip Deselect to Output in High Z (CE) -- -- 30 -- -- 35 ns
tBDO tBDO Data Byte Control to Output High Z (LB,UB) -- -- 30 -- -- 35 ns
tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns
tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIHVIH
Vcc VDR 1.5V
≥
CE Vcc - 0.2V
≥
BSI BS616LV2017
(1)
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
NOTE :
MIN. TYP. MAX. MIN. TYP. MAX.
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 100pF+1TTL
CL = 30pF+1TTL
CYCLE TIME : 55ns CYCLE TIME : 70ns
Revision 1.1
Jan. 2004
5
R0201-BS616LV2017
BSI BS616LV2017
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
t OH
t AA
DOUT
ADDRESS
t OH
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
t OH
READ CYCLE3 (1,4)
tRC
t OE
D OUT
LB,UB
CE
OE
ADDRESS
t CLZ
(5) tACS
t CHZ
(1,5)
t OHZ (5)
t OLZ
tAA
READ CYCLE2 (1,3,4)
tCLZ
tCHZ
(5)
D OUT
LB,UB
CE
(5)
t BA
t ACS
t BE t BDO
t BDO
t BA
t BE
Revision 1.1
Jan. 2004
6
BSI BS616LV2017
R0201-BS616LV2017
SWITCHING WAVEFORMS (WRITE CYCLE)
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION (Vcc = 4.5~5.5V) (Vcc = 4.5~5.5V) UNIT
tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns
tE1LWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns
tAVWL tAS Address Setup Time 0----0---- ns
tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns
tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns
tWHAX tWR Write recovery Time (CE,WE) 0----0---- ns
tBW tBW Date Byte Control to End of Write (LB,UB)25----30---- ns
tWLQZ tWHZ Write to Output in High Z -- -- 25 -- -- 30 ns
tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns
tWHDX tDH Data Hold from Write Time 0----0---- ns
tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns
tWHOX tOW End of Write to Output Active 5----5---- ns
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
(1)
NOTE :
(CE)
MIN. TYP. MAX. MIN. TYP. MAX.
t WR
WRITE CYCLE1 (1)
t WC
(3)
t CW
(11)
t BW
(2)
t WP
t AW
t OHZ
(4,10)
t AS
(3)
t DH
t DW
DIN
D OUT
WE
LB,UB
CE
OE
ADDRESS
(5)
CYCLE TIME : 55ns CYCLE TIME : 70ns
Revision 1.1
Jan. 2004
7
R0201-BS616LV2017
BSI BS616LV2017
WRITE CYCLE2 (1,6)
t WC
t CW
(11)
(2)
t WP
t AW
t WHZ
(4,10)
t AS
t WR
(3)
t DH
t DW
DIN
D OUT
WE
CE
ADDRESS
(5)
t OW (7) (8)
(8,9)
t BW
LB,UB
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 1.1
Jan. 2004
8
R0201-BS616LV2017
ORDERING INFORMATION
BSI BS616LV2017
PACKAGE DIMENSIONS
48 mini-BGA (6 x 8)
D1
VIEW A
1.4 Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0 6.0
EN
48 3.75
E1D1
5.25
NOTES:
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
BS616LV2017 X X ZY Y
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
PACKAGE
E: TSOP2-44
A: BGA-48-0608
D: DICE
Revision 1.1
Jan. 2004
9
R0201-BS616LV2017
BSI BS616LV2017
PACKAGE DIMENSIONS
TSOP2-44
