Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Stereo 280mW 8Ω Speaker Driver with Mute
APA4801
Package Code
J : PDIP-8 K : SOP-8
Temp. Range
I : - 40 to 85 C
Handling Code
TU : Tube
TR : Tape & Reel
Handling Code
Temp. Range
Package Code
°
••
••
• Operating Voltage
Single Supply 3V to 7V
Dual Supply ±1.5V to ± 3.5V
••
••
• High Signal-to-Noise Ratio 100dB
••
••
• High Slew Rate 5V/ µs
••
••
• Low Distortion -65dB
••
••
• Output Power at 10% THD+N
into 8Ω 280mW
into 16Ω 160mW
••
••
• Large Output Voltage Swing
••
••
•Excellent Power Supply Ripple Rejection
••
••
•Flexible Mute Function
••
••
•Integrated Voltage Divider (VDD/2) to Elimi-
nate External Resistors
••
••
•Low Power Consumption
••
••
•Short-circuit Elimination
••
••
•Wide Temperature Range
••
••
•No Switch ON/OFF Clicks
••
••
•Available in 8 pin SOP or DIP Package
Ordering Information
Features
The APA4801 is an integrated class AB stereo head-
phone amplifier contained in an SO-8 or a DIP-8 plas-
tic package with Mute feature . Besides the common
Mute feature , the APA4801 further integrates a volt-
age divider inside the chip . Thus , the external resis-
tors can be eliminated . The device has been prima-
rily developed for portable digital audio applications .
Applications
General Description
Block Diagram
Input B
Out B
BIAS
Mute
Out A
Input A BIAS
0dB
+
AB
+
1
2
3
4
V
SS
5
6
7
8V
DD
130k
Ω
130k
Ω
0dB
MUTE
••
••
•Portable Digital Audio
••
••
•Personal Computers
••
••
•Microphone Preamplifier
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw2
Absolute Maximum Ratings
Thermal Characteristics
Symbol Parameter Value Unit
RTHJA The r mal Resistanc e from J u n c ti on to Ambient in Fr ee Air
DIP-8
SO-8
109
210
K/W
K/W
Note: 1. Human body model : C=100pF, R=1500Ω, 3 positive pulses plus 3 negative pulses
Electrical Characteristics VIN=0dBV, VDD=5V, TA=25°C, f=1kHz (unless otherwise noted)
Symbol Parameter Rating Unit
VDD Supply Voltage 8 V
tSC(O) Output Short-circuit Duration, at TA=25°C, Ptot=1W 20 S
TAOper ating Ambient Temperature range -40 to 85 °C
TJMaximum Junction Temperature 150 °C
TSTG Storage Temperature Range -65 to +150 °C
TSSolder ing Temp eratur e ,10 second s 260 °C
VESD Electrostatic Discharge -3000 to 3000 *1 V
Function Pin Description
Pin Name I/O Function Description
Out A O A channel output pin
Mute I Chip disable control input, high active and low for normal
operating
Input A I A channel input terminal
VSS Power ground pin
Input B I B channel input terminal
BIAS I Right channel bias input pin
OUT B O B channel output pin
VDD Power input pin
APA4801Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Power Supply Voltage 2.7 5.5 V
VDD=5V
IDD Supply Current No Load 2.5 mA
VI(OS) Input Offset Vo ltage 5 50 mV
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw3
Electrical Characteristics Cont.
APA4801Symbol Parameter Test C onditions Min. Typ. Max. Unit
ISD Shunt Current 200 µA
M u tel M u te In pu t Volta ge 0.8 V
AV1- A V2 D ifferentia l C hann el
Volt age Gain -0.5 0 0.5 dB
ATT M ute Attenuation fIN=1k, VIN =1 Vrms 75 70 dB
AC Characteristics
(THD+N
)/S Total Har monic
D istortion plu s N oise to
Signal Ratio
PO =160mW, RL=8Ω, f= 1 k H z
PO =100mW, RL=16Ω, f = 1 k Hz 0.05
0.05 %
POOutput Power (THD+N)/S=0.1%, f=1kHz,
BW<80kHz mW
RL=8Ω170
RL=16Ω100
POOutput Power (THD+N)/S=10%, f=1kHz,
BW<80kHz mW
RL=8Ω280
RL=16Ω160
PSRR Power Supply
Re jec tion Ratio CB=4.7 µF,VRIPPLE=200mVrms,
f=120Hz 76 dB
S/N Signal to Noise Ratio RL=8Ωµ
Vrms
VDD=3V
IDD Supply C urrent No Load 2.2 m A
VI(OS) Input Offset Voltage 5 m V
ISD 200 µA
AC Characteristics
ISD Shunt Current 150 µA
M u tel M ute Inp u t Vo lta ge 0.8 V
AV1- A V2 D ifferentia l C hann el
Volt age Gain -0.5 0 0.5 dB
ATT Mute Attenuation fIN=1k ,VIN = 0.5Vrms 70 dB
(THD+
N)/S Total Harmonic
D istortion plu s N oise to
Signal Ratio
PO =50mW, RL=8Ω, f= 1 k Hz
PO =25mW, RL=16Ω, f= 1 kHz 0.1
0.1 %
S/N Signal to Noise Ratio µVrms
POOutput Power (THD+N)/S=0.1%, f=1kHz,
BW<80kHz mW
RL=8Ω45
RL=16Ω25
POOutput Power (THD+N)/S=10%, f=1kHz,
BW<80kHz mW
RL=8Ω80
RL=16Ω45
PSRR Power Supply
Re jec tion Ratio CB=4.7µF,VRIPPLE=200mVrms,
f=120Hz 76 dB
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw4
Test and Application Circuit
+
BIAS
57
MUTE
68
V
DD
0dB
0dB
B
A
APA4801
220
µ
F
1
µ
F
1
µ
F
100
µ
F
220
µ
F
4.7
µ
F
1
µ
F
100k
Ω
V
INA
V
DD
Out BInput B BIAS
V
INB
V
MUTE
H : Speaker Action
L : Mute on
Out A
Mute
V
SS
+
Input A
432 1
Typical Characteristics
THD+N vs Output Power
THD+N (%)
V
DD
=
5V
R
L
=16
Ω
f=20Hz
f=20kHz
f=1kHz
Output Power (W)
0.01
10
0.1
1
10m 200m
100m
THD+N vs Output Power
0.01
10
0.1
1
10m 500m
Output Power (W)
200m
V
DD
=
5V
R
L
=8
Ω
f=20Hz
f=20kHz
f=1kHz
THD+N (%)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw5
THD+N vs Frequency
THD+N (%)
Frequency (Hz)
20 20k100 1k 10k
10
0.01
0.1
1
V
DD
=
5V
P
O
=160mW
R
L
=8
Ω
NO FILTERS
THD+N vs Frequency
Frequency (Hz)
10
0.01
0.1
1
20 20k100 1k 10k
THD+N (%)
V
DD
=
5V
P
O
=100mW
R
L
=16
Ω
NO FILTERS
THD+N (%)
0.01
10
0.1
1
10m 100m50m
f=20Hz
f=20kHz
f=1kHz
Output Power (W)
THD+N vs Output Power
V
DD
=
3V
R
L
=8
Ω
10m 100m50m
THD+N (%)
0.01
10
0.1
1
Output Power (W)
THD+N vs Output Power
f=20Hz
f=20kHz
f=1kHz
V
DD
=
3V
R
L
=16
Ω
Typical Characteristics Cont.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw6
THD+N vs Frequency
10
0.01
0.1
1
Frequency (Hz)
THD+N (%)
V
DD
=
3V
P
O
=50mW
R
L
=8
Ω
NO FILTERS
20 20k100 1k 10k
20 20k100 1k 10k
10
0.01
0.1
1
V
DD
=
3V
P
O
=25mW
R
L
=16
Ω
NO FILTERS
THD+N vs Frequency
Frequency (Hz)
THD+N (%)
Power Dissipation vs Output Power
V
DD
=
5V
f=1kHz
THD+N<1%
BW<80kHz
R
L
=
8
Ω
R
L
=
16
Ω
0
50
100
150
200
0 50 100 150 200
Output Power (mW)
Power Dissipation (mW)
Power Dissipation vs Output Power
020 4060
R
L
=
8
Ω
R
L
=
16
Ω
Output Power (mW)
V
DD
=
3V
f=1kHz
THD+N<1%
BW<80kHz
0
20
40
60
80
70
50
30
10
Power Dissipation (mW)
Typical Characteristics Cont.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw7
Typical Characteristics Cont.
Supply Current (mA)
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
2.5 3 3.5 4 4.5 5 5.5
Supply Current vs Supply Voltage
NO LOAD
Supply Voltage (V)
Output Voltage (Mute Attenuation)
-100
+0
-80
-40
-20
-60
20 100k100 1k 10k
Frequency (Hz)
R
L
=
8
Ω
V
DD
=5V
V
IN
=1Vrms
BW<80kHz
(shutdown)
Output Voltage (dBV)
10% THD+N
0.1% THD+N
1% THD+N
Output Power vs Supply Voltage
Supply Voltage (V)
Output Power (mW)
2.5 3 3.5 4 4.5 5 5.5
f=1kHz
R
L
=8
Ω
BW<80kHz
0
50
100
150
200
250
350
300
2.5 3 3.5 4 4.5 5 5.5
0
50
100
150
200
250
f=1kHz
R
L
=16
Ω
BW<80kHz
10% THD+N
0.1% THD+N
1% THD+N
Output Power vs Supply Voltage
Output Power (mW)
Supply Voltage (V)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw8
Supply Voltage (V)
Output Power vs Load Resistance
f=1kHz
V
DD
=5V
BW<80kHz
10% THD+N
1% THD+N
Output Power (mW)
816243240485664
0
50
100
150
200
250
300
Output Power vs Load Resistance
f=1kHz
V
DD
=3V
BW<80kHz
816243240485664
10% THD+N
1% THD+N
100
0
30
50
70
60
40
20
10
Output Power (mW)
Supply Voltage (V)
Noise Floor
V
DD
=5V
R
L
=8
Ω
BW<80kHz
1m
100
µ
10
µ
1
µ
Output Noise Voltage (µV)
Frequency (Hz)
20 20k100 1k
Frequency (Hz)
20 20k100 1k 10k
Channel B to A
Channel A to B
R
L
=8
Ω
A
V
= -1
P
O
=160mW
V
DD
=5V
Output Level (dB)
Channel Separation
Typical Characteristics Cont.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw9
Power Supply Rejection Ratio
Frequency (Hz)
10 100k100 1k 10k
-80
-70
PSRR (dB)
-60
-50
-40
-30
-20
-10
+0 R
L
=8
Ω
A
V
= -1
V
Ripple
= 200mVrms
V
DD
=5V
C
B
=1
µ
F
C
B
=2.2
µ
F
C
B
=4.7
µ
F
Output Level (dB)
Frequency Response vs Output Capacitor Size
C
I
=10
µ
F
V
DD
=5V
R
L
=8
Ω
C
O
=1000
µ
F
C
O
=470
µ
F
C
O
=220
µ
F
C
O
=100
µ
F
Frequency (Hz)
-20
+5
-15
-10
-5
+0
20 100k100 1k 10k
-20
+5
-15
-10
-5
+0
20 100k100 1k 10k
Frequency (Hz)
Output Level (dB)
Typical Application vs Frequency Response
V
DD
=5V R
L
=8
Ω
C
O
=470
µ
F
C
I
=0.1
µ
F
C
O
=470
µ
F
C
I
=1.0
µ
F
Typical Characteristics Cont.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw10
Input Capacitor, Ci
In the typical application an input capacitor , Ci , is
required to allow the amplifier to bias the input signal
to the proper DC level for optimum operation . In this
case , the external capacitor Ci and the internal re-
sistance Ri form a high-pass filter with the corner fre-
quency determined in the follow equation :
fc (highpass)= 1/ (2πRiCi) (1)
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit .
Consider the APA4801 where Ri is 130kΩ internal
fixed . Equation is reconfigured as follow :
Ci= 1/(2π*130kΩ*fc) (2)
And the ceramic capacitor is recommanded
Bias Capacitor, Cb
As with any power amplifier , proper supply bypass-
ing is critical for low noise performance and high
power supply rejection . The capacitor location on
both the bypass and power supply pins should be as
close to the device as possible . The effect of a larger
half supply bias capacitor is improved PSRR due to
increased half-supply stability . Typical applications
employ a 5V regulator with 10µF and a 0.1µF bias
capacitors which aid in supply filtering . This does
not eliminate the need for bypassing the supply nodes
of the APA4801 . The selection of bias capacitors ,
especially Cb , is thus dependent upon desired PSRR
requirements , click and pop performance . The ca-
pacitor is fed from a 50kΩ source inside the amplifier.
To keep the start-up pop as low as possible , the
relationship shown in equation should be maintained.
1/(Cb*50kΩ)≤ 1/{Ci*Ri} (3)
As an example , consider a circuit where Cb is
4.7µF , Ci is 1µF and Ri is 130kΩ . Inserting these
values into the equation we get 4.26≤ 7.69 which
satisfies the rule . Bias capacitor , Cb , values of
2.2µF to 10µF ceramic or tantalum low-ESR capaci-
tors are recommended for the best THD and noise
performance.
Output Coupling Capacitor, Cc
In the typical single-supply SE configuration , an out-
put coupling capacitor (Cc) is required to block the
DC bias at the output of the amplifier thus preventing
DC currents in the load . As with the input coupling
capacitor , the output coupling capacitor and imped-
ance of the load form a high-pass filter governed by
equation .
fc(highpass)= 1/(2πRLCc) (4)
For example , a 220µF capacitor with an 32Ω speaker
would attenuate low frequencies below 22Hz . The
main disadvantage , from a performance standpoint,
is the load impedance is typically small , which drives
the low-frequency corner higher degrading the bass
response . Large values of Cc are required to pass
low frequencies into the load .
Optimizing Depop Circuitry
When the amplifier is in mute mode , both of the out-
put stage and input bypass continues to be biased .
And no pop noise will be heard during the transition
out of mute mode .
Power Supply Decoupling , Cs
APA4801 is a high-performance CMOS audio ampli-
fier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD)
is as low as possible . Power supply decoupling also
prevents the oscillations causing by long lead length
between the amplifier and the speaker . The optimum
decoupling is achieved by using two different type
capacitors that target on different type of noise on
the power supply leads . For higher frequency tran-
sients , spikes , or digital hash on the line , a good
low equivalent-series-resistance (ESR) ceramic ca-
pacitor , typically 0.1µF placed as close as possible
to the device VDD lead works best . For filtering lower-
frequency noise signals , a large aluminum electro-
lytic capacitor of 10µF or greater placed near the audio
power amplifier is recommended .
Application Note
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw11
Packaging Information
1
D
E1
A2
A1
A
L
e2
e 3 e 1
E
E3
1
PDIP-8 pin ( Reference JEDEC Registration MS-001)
Millimeters InchesDim Min. Max. Min. Max.
A5.33 0.210
A1 0.38 0.015
A2 2.92 3.68 0.115 0.145
D9.02 10.16 0.355 0.400
e1 2.54BSC 0.100BSC
e2 0.36 0.56 0.014 0.022
e3 1.14 1.78 0.045 0.070
E7.62 BSC 0.300 BSC
E1 6.10 7.11 0.240 0.280
E3 10.92 0.430
L2.92 3.81 0.115 0.150
φ
115
°15°
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw12
Pack ag ing Inform ation
SO P -8 pin ( Reference JED E C R egistration MS -012)
Millimeters InchesDim Min. Max. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
H 5.80 6.20 0.228 0.244
L 0.40 1.27 0.016 0.050
e1 0.33 0.51 0.013 0.020
e2 1.27BSC 0.50BSC
φ
10
°8°0°8°
HE
e1 e2
D
A
A1
0.004max.
1
L
e
0.015X45
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw13
Reference JEDEC Standard J-STD-020A APRIL 1999
Reflow Condition (IR/Convection or VPR Reflow)
Physical Specifications
Terminal Material S older-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Lead Solderability Meets EIA Specification RSI86-91, ANS I/J-ST D-002 Cate gory 3.
Packaging 2500 devices per reel
Pre-heat temperature
183 C
Peak temperature
Time
°
temperature
Clas sification Reflow Profile s
Convection or IR/
Convection VPR
Average ramp-up rate(183°C to Peak) 3°C/second max. 10 °C /second max.
Preheat temp erature 125 ± 25°C) 120 seco nds max
Temperature maintained above 183°C60 – 150 seconds
Time within 5°C of actual peak tem perat ure 10 –20 secon ds 60 seconds
Peak temp erature r ang e 220 +5/-0°C or 235 +5/-0°C 215-219°C or 23 5 +5/-0°C
Ramp-down rate 6 °C /second max. 10 °C /second max .
Time 2 5°C to peak temp erature 6 minutes max .
Package Reflow Conditions
pkg. thickness ≥
≥≥
≥ 2.5mm
and all bgas pkg. thickne ss < 2.5m m an d
pkg. volume ≥
≥≥
≥ 350 mm³ pkg. thickne ss < 2.5m m an d pkg.
volume < 350mm ³
Convection 2 20 +5/-0 °C Convection 235 +5/-0 °C
VPR 215-219 °C VPR 235 +5/-0 °C
IR/Convection 22 0 +5/-0 °C IR/Convection 23 5 +5/-0 °C
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw14
Re liability test p rog ram
Test item M ethod Descrip tion
SOLDERABILITY MIL-STD-883D-2003 245°C , 5 SEC
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @ 125 °C
PCT JESD-22-B, A102 168 Hrs, 100 % RH , 121°C
TST MIL-STD-883D-1011.9 -65°C ~ 150°C, 20 0 C ycles
ESD MIL-STD-883D-3 015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
Application AEBCJKFP1D
SOP 8N 12 + 0.3
12 - 0.1 8.0 ± 0.1 1.75± 0.1 5 .5 ± 0 .1 1.55± 0.11.5± 0.25 4.0 ± 0.1 2.0 ± 0.1 6 .4 ± 0.1
Application GIHLVWMT1T2
SOP 8N 5.2 ±0.1 2.1 ± 0.1 0.3±0.013 330±1100
±113+0.5
13 -0 .1 2.2±0.1 12.5± 0.5 2.0 ± 0.2
(mm)
L
M
V
T2
T1
W
H
D
B
A
FE
I
G
K
J
C
P1
Cover Tape Dimensions
Ca rrier Width 12
Cover Tap e W idth 9.3 (mm)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
APA4801
www.anpec.com.tw15
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Customer Service
