Features
•Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
•Latch-Up Protected
•High Peak Output Current: 4A Peak
•Wide Operating Range: 4.5V to 35V
•Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 1800pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
•Low Output Impedance
•Low Supply Current
•Two identical drivers in single chip
Applications
•Driving MOSFETs and IGBTs
•Limiting di/dt under Short Circuit
•Motor Controls
•Line Drivers
•Pulse Generators
•Local Power ON/OFF Switch
•Switch Mode Power Supplies (SMPS)
•DC to DC Converters
•Pulse Transformer Driver
•Class D Switching Amplifiers
IXDD404
First Release
Copyright © IXYS CORPORATION 2004
General Description
The IXDD404 is comprised of two 4 Amp CMOS high speed
MOSFET drivers. Each output can source and sink 4 A of
peak current while producing voltage rise and fall times of less
than 15ns to drive the latest IXYS MOSFETS & IGBT's. The
input of the driver is compatible with TTL or CMOS and is fully
immune to latch up over the entire operating range. Designed
with small internal delays, cross conduction/current shoot-
through is virtually eliminated in the IXDD404. Improved speed
and drive capabilities are further enhanced by very low,
matched rise and fall times.
Additionally, each driver in the IXDD404 incorporates a unique
ability to disable the output under fault conditions. When a
logical low is forced into the Enable input of a driver, both of it's
final output stage MOSFETs (NMOS and PMOS) are turned
off. As a result, the respective output of the IXDD404 enters a
tristate mode and achieves a Soft Turn-Off of the MOSFET/
IGBT when a short circuit is detected. This helps prevent
damage that could occur to the MOSFET/IGBT if it were to be
switched off abruptly due to a dv/dt over-voltage transient.
The IXDD404 is available in the standard 8 pin P-DIP (PI),
SOIC-8 (SIA) and SOIC-16 (SIA-16) packages. For enhanced
thermal performance, the SOP-8 and SOP-16 are also avail-
able with an exposed grounded metal back package as the SI
and SI-16 respectively.
Figure 1 - Functional Diagram
INB
ENA
ENB
OUTA
OUTB
200k
200k
GND
Vcc
4 Amp Dual Low-Side Ultrafast MOSFET Driver
Part Number Package Type Temp. Range Configuration
IXDD404PI 8-Pin PDIP
IXDD404SI 8-Pin SOIC with Grounded Metal Back
IXDD404SIA 8-Pin SOIC
IXDD404SI-16 16-Pin SOIC with Grounded Metal Back
IXDD404SIA-16 16-Pin SOIC
-55°C to
+125°C
Dual Non
Inverting With
Enable
Ordering Information
NOTE: Mounting or solder tabs on all packages are connected to ground
DS99046D(11/10)
2
IXDD404
Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel.
Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
VIH High input voltage 4.5V ≤ VIN ≤ 18V 2.5 V
VIL Low input voltage 4.5V ≤ VIN ≤ 18V 0.8 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V ≤ VIN ≤ VCC
-10 10 µA
VOH High output voltage VCC - 0.025
V
VOL Low output voltage 0.025 V
ROH Output resistance
@ Output high
VCC = 18V
2 2.5 Ω
ROL Output resistance
@ Output Low
VCC = 18V 1.5 2 Ω
IPEAK Peak output current VCC = 18V
4 A
IDC Continuous output
current
1 A
VEN Enable voltage range - 0.3 Vcc + 0.3 V
VENH High En Input Voltage 2/3 Vcc V
VENL Low En Input Voltage 1/3 Vcc V
tR Rise time CL=1800pF Vcc=18V 16 18 ns
tF Fall time CL=1800pF Vcc=18V 13 17 ns
tONDLY On-time propagation
delay
CL=1800pF Vcc=18V 36 40 ns
tOFFDLY Off-time propagation
delay
CL=1800pF Vcc=18V 35 39 ns
tENOH Enable to output high
delay time
30 ns
tDOLD Disable to output low
Disable delay time
30 ns
VCC Power supply voltage 4.5 18 35 V
ICC
Power supply current VIN = 3.5V
VIN = 0V
VIN = + VCC
1
0
3
10
10
mA
µA
µA
REN Enable Pull-up Resistor 200 kΩ
Absolute Maximum Ratings (Note 1)
Parameter
Value
Supply Voltage 40 V
All Other Pins -0.3 V to VCC + 0.3 V
Junction Temperature 150 oC
Storage Temperature -65 oC to 150 oC
Lead Temperature (10 sec) 300 oC
Operating Ratings
Param eter
Value
Operating Temperature Range -55 oC to 125 oC
Thermal Impedance (Junction to Ambient)
8 Pin PDIP (PI) (θJA) 120 oC/W
8 Pin SOIC (SIA) (θJA) 110 oC/W
8 Pin SOIC (SI) (θJA) with heat sink**
Heat sink area of 1cm2 71 oC/W
16 Pin SOIC (SIA-16) (θJA) 110 oC/W
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Specifications to change without notice
**Heat sink area is 1 oz. copper on one side of .06" thick
FR4 soldered to metal back plane.
3
IXDD404
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
VIH High input voltage 2 V
VIL Low input voltage 2.4 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V ≤ VIN ≤ VCC
-10 10 µA
VOH High output voltage VCC - 0.025
V
VOL Low output voltage 0.025 V
ROH Output resistance
@ Output high
VCC = 18V
3.4 Ω
ROL Output resistance
@ Output Low
VCC = 18V 2 Ω
IPEAK Peak output current VCC = 18V
3.2 A
IDC Continuous output
current
1 A
tR Rise time CL=1000pF Vcc=18V 11 ns
tF Fall time CL=1000pF Vcc=18V 13 ns
tONDLY On-time propagation
delay
CL=1000pF Vcc=18V 60 ns
tOFFDLY Off-time propagation
delay
CL=1000pF Vcc=18V 59 ns
VCC Power supply voltage 4.5 18 35 V
ICC
Power supply current VIN = 3.5V
VIN = 0V
VIN = + VCC
1
0
3
10
10
mA
µA
µA
Unless otherwise noted, temperature over -55 oC to 150 oC, 4.5V ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel.
Electrical Characteristics
Specifications to change without notice
4
IXDD404
Pin Description
SYMBOL FUNCTION DESCRIPTION
EN A A Channel Enable The Channel A enable pin. This pin, when driven low, disables the A
Channel, forcing a high impedance state to the A Channel Output.
IN A A Channel Input A Channel Input signal-TTL or CMOS compatible.
GND Ground
The system ground pin. Internally connected to all circuitry, this pin provides
ground reference for the entire chip. This pin should be connected to a low
noise analog ground plane for optimum performance.
IN B B Channel Input B Channel Input signal-TTL or CMOS compatible.
OUT B B Channel Output B Channel Driver output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
VCC Supply Voltage Positive power-supply voltage input. This pin provides power to the entire
chip. The range for this voltage is from 4.5V to 35V.
OUT A A Channel Output A Channel Driver output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
EN B B Channel Enable The Channel B enable pin. This pin, when driven low, disables the B
Channel, forcing a high impedance state to the B Channel Output.
Figure 2 - Characteristics Test Diagram
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when
handling and assembling this component.
V
IN
EN A
IN A
GND
IN B
EN B
OUT A
OUT B
VCC
1
2
3
4
8
7
6
5
I
X
D
D
4
0
4
SO8 (SI)
8 PIN DIP (PI) SO16 (SI-16)
Pin Configurations
5
IXDD404
Max / M in Input vs. Temperature
CL = 1000pF, Vcc = 18V
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
-60 -10 40 90 140 190
Tem perature (C )
Max / Min Input Voltage
Min Input H igh
Max Input Low
Rise And Fall Times vs. Temperature
CL = 1000pF, Vcc = 18V
0
2
4
6
8
10
12
14
-60 -10 40 90 140 190
Temperature (C)
Time (ns)
tF
tR
Rise Times vs. Load Capacitance
0
10
20
30
40
50
60
70
80
0 2000 4000 6000 8000 10000
Load Capacitance (pF)
Rise Time (ns)
8V
10V
12V
18V
25V
35V
Rise Times vs. Supply Voltage
0
10
20
30
40
50
60
70
80
5 10 15 20 25 30 35
Supply Voltage (V)
Rise Time (ns)
200pF
1000pF
1800pF
4700pF
6800pF
10000pF
Fall Times vs. Supply Voltage
0
10
20
30
40
50
60
70
80
5 10 15 20 25 30 35
Supply Voltage (V)
Fall Times (ns)
200pF
1000pF
1800pF
4700pF
6800pF
10000pF
Typical Performance Characteristics
Fig. 3 Fig. 4
Fig. 5 Fig. 6
Fig. 7 Fig. 8
Fall Times vs. Load Capacitance
0
10
20
30
40
50
60
70
80
0 2000 4000 6000 8000 10000
Load Capacitance (pF)
Fall Time (ns)
8V
10V
12V
18V
25V
35V
6
IXDD404
Supply Current vs. Frequency
Vcc = 8V
0.01
0.1
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (ma)
200 pF
1000 pF
1800 pF
4700 pF
6800 pF
10000 pF
Fig. 10
Fig. 12
Fig. 14
Supply Current vs. Load Capacitance
Vcc = 8V
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
10 kHz
50 kHz
Hz
100 kHz
500 kHz
1 MHz
2 MHz
Supply Current vs. Load Capacitance
Vcc = 12V
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
10 kHz
50 kHz
100 kHz
500 kHz
1 Mhz
2 MHz
Supply Current vs. Load Capacitance
Vcc = 18V
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
10 kHz
50 kHz
100 kHz
500 kHz
1 MHz
2 MHz
Supply Current vs. Frequency
Vcc = 12V
0.01
0.1
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (ma)
200 pF
1000 pF
1800 pF
4700 pF
6800 pF
10000 pF
Supply Current vs. Frequency
Vcc = 18V
0.01
0.1
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (ma)
200 pF
1000 pF
1800 pF
6800 pF
10000 pF
4700 pF
Fig. 9
Fig. 11
Fig. 13
7
IXDD404
Quiescent Supply Current vs. Temperature
V
cc
= 18V, V
in
= 5V@1kHz, C
L
= 1000pF
0
0.05
0.1
0.15
0.2
0.25
0.3
-60 -10 40 90 140 190
Temperature (C)
Quiescent V
cc
Input Current(mA)
Propagation Delay vs. Input Voltage
CL = 1800pF Vcc = 15V
20
25
30
35
40
45
50
2 4 6 8 10 12
Input Voltage (V)
Propagation Delay (ns)
tONDLY
tOFFDLY
Propagation Delay vs. Supply Voltage
CL = 1800pF Vin = 5V@1kHz
0
10
20
30
40
50
60
70
5 10 15 20 25 30 35
Supply Voltage (V)
Propagation Delay (ns)
tONDLY
tOFFDLY
Supply Current vs. Frequency
Vcc = 35V
0.01
0.1
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (mA)
200 pF
1000 pF
1800 pF
4700 pF
6800 pF
10000 pF
Supply Current vs. Load Capacitance
Vcc = 35V
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
10 kHz
50 kHz
100 kHz
1 MHz
500 kHz
2 MHz
Fig. 16
Fig. 15
Fig. 17 Fig. 18
Fig. 19
Fig. 20
Supply Current vs. Frequency
tONDLY
Propagation Delay Times vs. Temperature
CL = 1000pF, Vcc = 18V
20
25
30
35
40
45
50
55
60
-60 -10 40 90 140 190
Temperature (C)
Time (ns)
tONDL Y
tOFFD LY
8
IXDD404
Vcc vs. N Channel Ouput Current
0
2
4
6
8
10
12
14
5 10 15 20 25 30 35
Vcc (V)
N Channel Output Current (A)
P Channel Output Current vs. Temperature
Vcc = 18V, CL = 1000pF
0
1
2
3
4
5
6
-80 -30 20 70 120 170
Temperature (C)
P Channel Output Current (A)
Vcc vs. P Channel Output Current
-12
-10
-8
-6
-4
-2
0
5 10 15 20 25 30 35
Vcc (V)
P Channel Output Current (A)
Low State Output Resistance vs. Supply Voltage
0
1
2
3
4
5
6
5 10 15 20 25 30 35
Supply Voltage (V)
Low State Output Resistance (Ohms)
High State Ouput Resistance vs. Supply Voltage
0
1
2
3
4
5
6
5 10 15 20 25 30 35
Supply Voltage (V)
High State Output Resistance (Ohms)
Fig. 21 Fig. 22
Fig. 23 Fig. 24
Fig. 25
N Channel Output Current vs. Temperature
Vcc = 18V CL = 1000pF
0
1
2
3
4
5
6
-80 -30 20 70 120 170
Temperature (C)
N Channel Output Current (A)
Fig. 26
9
IXDD404
Figure 28 - Typical Application Short Circuit di/dt Limit
Enable Threshold vs. Supply Voltage
0
2
4
6
8
10
12
14
16
18
20
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Enable Threshold (V)
Fig. 27
10
IXDD404
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET such as the IXFN100N20,
(20A, 1000V), as shown in Figure 26, can cause the current
through the module to flow in excess of 60A for 10µs or more
prior to self-destruction due to thermal runaway. For this
reason, some protection circuitry is needed to turn off the
MOSFET module. However, if the module is switched off too
fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
The IXDD404 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.
Thus, the IXDD404 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
The IXDD404 is designed to not only provide ±4A per output
under normal conditions, but also to allow it's outputs to go into
a high impedance state. This permits the IXDD404 output to
control a separate weak pull-down circuit during detected
overcurrent shutdown conditions to limit and separately con-
trol dVGS/dt gate turnoff. This circuit is shown in Figure 27.
Referring to Figure 27, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the IXFD100N20. A low pass filter should be added to the
input of the comparator to eliminate any glitches in voltage
caused by the inductance of the wire connecting the source
resistor to ground. (Those glitches might cause false triggering
of the comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000-
series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the IXFN100N20 gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the IXFN100N20.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD404 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD408 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD404 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD404 output. The
SRFF also turns on the low power MOSFET, (2N7000).
In this way, the high-power MOSFET module is softly turned off
by the IXDD404, preventing its destruction.
10uH
Ld
0.1ohm
Rd
Rs
20nH
Ls
1ohm
Rg
10kohm
R+
IXFN100N20
High_Power
5kohm
Rcomp
100pF
C+
+
-
V+
V-
Comp
LM339
1600ohm
Rsh
Ccomp
1pF
VCC
VCCA
IN
EN
DGND
SUB
OUT
IXDD404
+
-
VIN
+
-
VCC
+
-
REF
+
-
VB
CD4001A
NOR2
1Mohm
Ros
NOT2
CD4049A
CD4011A
NAND
CD4049A
NOT1
CD4001A
NOR1
CD4049A
NOT3
Low_Power
2N7002/PLP
1pF
Cos
0
S
R
EN
Q
One Shot Circuit
SR Flip-Flop
Figure 29 - Application Test Diagram
11
IXDD404
10K
R3
3.3K R2
Q1
2N3904
EN
Output
CC
(From Gate Driver
Power Supply)
Input)
TTL
CMOS
3.3K R1
V
DD
(From Logic
Power Supply)
or
High Voltage
(To IXDD404
EN Input)
Supply Bypassing and Grounding Practices,
Output Lead inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD404, it is very important to keep certain design
criteria in mind, in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
Say, for example, we are using the IXDD404 to charge a 2500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=2500pF &
∆t=25ns we can determine that to charge 2500pF to 25 volts in
25ns will take a constant current of 2.5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
4A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD404
must be able to draw this 2.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is a magnitude
larger than the load capacitance. Usually, this would be
achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of
the leads between these bypass capacitors and the IXDD404
to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXDD404
must be able to drain this 2.5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD404
and it’s load. Path #2 is between the IXDD404 and it’s power
supply. Path #3 is between the IXDD404 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD404.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the
load.
TTL to High Voltage CMOS Level Translation
The enable (EN) input to the IXDD404 is a high voltage
CMOS logic level input where the EN input threshold is ½
VCC, and may not be compatible with 5V CMOS or TTL input
levels. The IXDD404 EN input was intentionally designed
for enhanced noise immunity with the high voltage CMOS
logic levels. In a typical gate driver application, VCC =15V
and the EN input threshold at 7.5V, a 5V CMOS logical high
input applied to this typical IXDD404 application’s EN input
will be misinterpreted as a logical low, and may cause
undesirable or unexpected results. The note below is for
optional adaptation of TTL or 5V CMOS levels.
The circuit in Figure 28 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic
input to high voltage CMOS logic levels needed by the
IXDD404 EN input. From the figure, VCC is the gate driver
power supply, typically set between 8V to 20V, and VDD is the
logic power supply, typically between 3.3V to 5.5V.
Resistors R1 and R2 form a voltage divider network so that
the Q1 base is positioned at the midpoint of the expected
TTL logic transition levels.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied
to the Q1 emitter will drive it on. This causes the level
translator output, the Q1 collector output to settle to VCESATQ1
+ VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V
for VCC =15V given in the IXDD404 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 28 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage
CMOS logical EN output applied to the IXDD404 EN input
will enable it, allowing the gate driver to fully function as a
±4 Amp output driver.
The total component cost of the circuit in Figure 28 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 30 - TTL to High Voltage CMOS Level Translator
12
IXDD404
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: sales@ixys.net
Dimenional Outline: IXDD404PI
Dimenional Outlines: IXDD404SI-CT and IXDD404SIA
Dimenional Outlines: IXDD404SI-16CT and IXDD404SIA-16
