Photometric Front End ADPD103 Data Sheet FEATURES GENERAL DESCRIPTION Multifunction photometric front end Fully integrated AFE, ADC, LED drivers, and timing core Usable in a broad range of optical measurement applications, including photoplethysmography Enables best-in-class ambient light rejection capability without the need for photodiode optical filters Three 8 mA to 250 mA LED drivers Separate data registers for each LED/photodiode combination 1 to 8 optical inputs Flexible, multiple, short LED pulses per optical sample 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator, enabling up to 27 bits per data read Low power operation I2C interface and 1.8 V analog/digital core Flexible sampling frequency ranging from 0.122 Hz to 3.820 kHz FIFO data operation The ADPD103 is a highly efficient photometric front end with an integrated 14-bit analog-to-digital converter (ADC) and a 20-bit burst accumulator that works in concert with flexible light emitting diode (LED) drivers. It is designed to stimulate an LED and measure the corresponding optical return signal. The data output and functional configuration occur over a 1.8 V I2C interface. The control circuitry includes flexible LED signaling and synchronous detection. The analog front end (AFE) features best-in-class rejection of signal offset and corruption due to modulated interference commonly caused by ambient light. Couple the ADPD103 with a low capacitance photodiode of <100 pF for optimal performance. The ADPD103 can be used with any LED. APPLICATIONS Body worn health and fitness monitors, for example, heart rate monitoring Clinical measurements, for example, SpO2 Industrial monitoring Background light measurements Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2015-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADPD103 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 AFE Integration Offset Adjustment ......................................... 18 Applications ....................................................................................... 1 I2C Serial Interface ..................................................................... 20 General Description ......................................................................... 1 Typical Connection Diagram ................................................... 21 Revision History ............................................................................... 2 LED Driver Pins and LED Supply Voltage .............................. 23 Functional Block Diagram .............................................................. 3 LED Driver Operation ............................................................... 23 Specifications..................................................................................... 4 Determining the Average Current ........................................... 23 Temperature and Power Specifications ..................................... 4 Determining CVLED ..................................................................... 23 Performance Specifications ......................................................... 5 LED Inductance Considerations .............................................. 24 Analog Specifications ................................................................... 6 Recommended Start-Up Sequence .......................................... 24 Digital Specifications ................................................................... 7 Reading Data ............................................................................... 24 Timing Specifications .................................................................. 8 Clocks and Timing Calibration ................................................ 26 Absolute Maximum Ratings............................................................ 9 Calculating Current Consumption .......................................... 27 Thermal Resistance ...................................................................... 9 Optimizing SNR per Watt ......................................................... 27 Recommended Soldering Profile ............................................... 9 Single AFE channel mode ......................................................... 28 ESD Caution .................................................................................. 9 TIA_ADC Mode ......................................................................... 28 Pin Configurations and Function Descriptions ......................... 10 Digital Integrate Mode............................................................... 30 Typical Performance Characteristics ........................................... 12 Register Listing ............................................................................... 34 Theory of Operation ...................................................................... 13 LED Control Registers ............................................................... 38 Introduction ................................................................................ 13 AFE Configuration Registers .................................................... 41 Dual Time Slot Operation ......................................................... 13 System Registers ......................................................................... 46 Time Slot Switch ......................................................................... 14 ADC Registers ............................................................................ 50 Adjustable Sampling Frequency ............................................... 15 Data Registers ............................................................................. 51 State Machine Operation ........................................................... 16 Outline Dimensions ....................................................................... 52 Normal Mode Operation and Data Flow ................................ 16 Ordering Guide .......................................................................... 52 AFE Operation ............................................................................ 18 REVISION HISTORY 2/16--Revision B: Initial Version Rev. B | Page 2 of 52 Data Sheet ADPD103 FUNCTIONAL BLOCK DIAGRAM AVDD TIME SLOT SWITCH DVDD ANALOG BLOCK PDC AFE: SIGNAL CONDITIONING PD1 TIA PD5 BPF ADPD103 1 INTEGRATOR VBIAS VREF AFE: SIGNAL CONDITIONING PD2 TIA BPF PD6 14-BIT ADC VBIAS AFE: SIGNAL CONDITIONING PD3 TIA BPF PD7 AFE CONFIGURATION 1 INTEGRATOR VBIAS AFE: SIGNAL CONDITIONING PD4 TIA PD8 1F TIME SLOT A DATA 1 INTEGRATOR BPF TIME SLOT B DATA SDA SCL INT A PDSO B DGND SLOT SELECT DIGITAL DATAPATH AND INTERFACE CONTROL 1 INTEGRATOR AGND VBIAS LEDX3 LED3 LEDX2 LED2 LED3 DRIVER LED3 LEVEL AND TIMING CONTROL LED2 DRIVER LED2 LEVEL AND TIMING CONTROL LED1 DRIVER LED1 LEVEL AND TIMING CONTROL LEDX1 LED1 VLED 12722-001 LGND Figure 1. Typical Functional Block Diagram Rev. B | Page 3 of 52 ADPD103 Data Sheet SPECIFICATIONS TEMPERATURE AND POWER SPECIFICATIONS Table 1. Operating Conditions Parameter TEMPERATURE RANGE Operating Range Storage Range POWER SUPPLY VOLTAGES VDD Test Conditions/Comments Min Typ -40 -65 Applied at the AVDD and DVDD pins 1.7 1.8 Max Unit +85 +150 C C 1.9 V AVDD = DVDD = 1.8 V, ambient temperature, unless otherwise noted. Table 2. Current Consumption 1, 2 Parameter POWER SUPPLY (VDD) CURRENT VDD Supply Current Symbol LED_OFFSET = 25 s; LED_PERIOD =19 s; LED peak current = 25 mA, 4 channels active 100 Hz data rate; Time Slot A only 100 Hz data rate; Time Slot B only 100 Hz data rate; both Time Slot A and Time Slot B 100 Hz data rate; Time Slot A only 100 Hz data rate; Time Slot B only 100 Hz data rate; both Time Slot A and Time Slot B 1 Pulse 10 Pulses Peak VDD Supply Current (1.8 V) 4-Channel Operation 1-Channel Operation Standby Mode Current VLEDA AND VLEDB SUPPLY CURRENT Average Supply Current VLEDA or VLEDB 1 Pulse 10 Pulses 1 2 Test Conditions/Comments Min Typ Max Unit 106 94 151 258 246 455 A A A A A A 9.3 2.3 3.5 mA mA A 15 30 60 150 300 600 A A A A A A IVDD_PEAK IVDD_STANDBY Peak LED current = 100 mA; LED_PULSE width = 3 s 50 Hz data rate 100 Hz data rate 200 Hz data rate 50 Hz data rate 100 Hz data rate 200 Hz data rate LEDA or LEDB is one of LED1, LED2, or LED3. VLEDA or VLEDB is one of VLED1, VLED2, or VLED3. VDD is the voltage applied at the AVDD and DVDD pins. Rev. B | Page 4 of 52 Data Sheet ADPD103 PERFORMANCE SPECIFICATIONS AVDD = DVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted. Table 3. Parameter DATA AQUISITION Resolution Resolution/Sample Resolution/Data Read LED DRIVER LED Current Slew Rate 1 Rise Fall LED Peak Current Driver Compliance Voltage LED PERIOD Sampling Frequency 2 CATHODE PIN (PDC) VOLTAGE During All Sampling Periods During Slot A Sampling During Slot B Sampling During Sleep Periods Test Conditions/Comments Min Typ Max Unit Single pulse 64 to 255 pulses 64 to 255 pulses and sample average = 128 14 20 27 Bits Bits Bits Slew rate control setting = 0; TA = 25C; ILED = 70 mA Slew rate control setting = 7; TA = 25C; ILED = 70 mA Slew rate control setting = 0, 1, 2; TA = 25C; ILED = 70 mA Slew rate control setting = 6, 7; TA = 25C; ILED = 70 mA LED pulse enabled Voltage above ground required for LED driver operation AFE width = 4 s AFE width = 3 s Time Slot A only; normal mode; 1 pulse; OFFSET_LEDA = 23 s; PERIOD_LEDA = 19 s Time Slot B only; normal mode; 1 pulse; OFFSET_LEDA = 23 s; PERIOD_LEDA = 19 s Both time slots; normal mode; 1 pulse; OFFSET_LEDA = 23 s; PERIOD_LEDA = 19 s Time Slot A only; normal mode; 8 pulses; OFFSET_LEDA = 23 s; PERIOD_LEDA = 19 s Time Slot B only; normal mode; 8 pulses; OFFSET_LEDA = 23 s; PERIOD_LEDA = 19 s Both time slots; normal mode; 8 pulses; OFFSET_LEDA = 23 s; PERIOD_LEDA = 19 s 240 1400 3200 4500 mA/s mA/s mA/s mA/s mA V s s Hz Hz Hz Hz Hz Hz Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 3 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x03 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x3 4 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x03 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x34 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0 Register 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x3 PHOTODIODE INPUT PINS/ ANODE VOLTAGE During All Sampling Periods During Sleep Periods 8 0.2 19 17 0.122 0.122 0.122 0.122 0.122 0.122 250 3230 3820 1750 2257 2531 1193 1.8 1.3 1.8 1.3 1.55 0 1.8 1.3 1.55 0 1.8 1.3 1.8 1.3 1.55 0 V V V V V V V V V V V V V V V V 1.3 Cathode voltage V V LED inductance is negligible for these values. The effective slew rate slows with increased inductance. The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the actual output data rate of the device 3 This mode may induce additional noise and is not recommended unless absolutely necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode of the magnitude C x dV/dt. 4 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode. 1 2 Rev. B | Page 5 of 52 ADPD103 Data Sheet ANALOG SPECIFICATIONS AVDD = DVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted. Compensation of the AFE offset is explained in the AFE Operation section. Table 4. Parameter INPUT CAPACITANCE PULSED SIGNAL CONVERSIONS, 3 s WIDE LED PULSE 1 ADC Resolution 2 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal PULSED SIGNAL CONVERSIONS, 2 s WIDE LED PULSE1 ADC Resolution2 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal FULL SIGNAL CONVERSIONS 3 TIA Saturation Level of Pulsed Signal and Ambient Level Test Conditions/Comments 4 s wide AFE integration; normal operation, Register 0x43 (Time Slot A) and Register 0x45 (Time Slot B) = 0xADA5 Transimpedance amplifier (TIA) feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k 3 s wide AFE integration; normal operation, Register 0x43 (Time Slot A) and Register 0x45 (Time Slot B) = 0xADA5 TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k Rev. B | Page 6 of 52 Min Typ Max 100 Unit pF 1.64 0.82 0.41 0.2 nA/LSB nA/LSB nA/LSB nA/LSB 13.4 6.7 3.35 1.67 A A A A 37 18.5 9.25 4.63 A A A A 2.31 1.15 0.58 0.29 nA/LSB nA/LSB nA/LSB nA/LSB 18.9 9.46 4.73 2.37 A A A A 31.5 15.7 7.87 3.93 A A A A 50.4 25.2 12.6 6.3 A A A A Data Sheet ADPD103 Parameter SYSTEM PERFORMANCE Total Output Noise Floor Test Conditions/Comments Min Normal mode; per pulse; per channel; no LED; CPD = 70 pF 25 k; referred to ADC input 25 k; referred to peak input signal for 2 s LED pulse 25 k; referred to peak input signal for 3 s LED pulse 25 k; saturation signal-to-noise ratio (SNR) per pulse per channel 4 50 k; referred to ADC input 50 k; referred to peak input signal for 2 s LED pulse 50 k; referred to peak input signal for 3 s LED pulse 50 k; saturation SNR per pulse per channel4 100 k; referred to ADC input 100 k; referred to peak input signal for 2 s LED pulse 100 k; referred to peak input signal for 3 s LED pulse 100 k; saturation SNR per pulse per channel4 200 k; referred to ADC input 200 k; referred to peak input signal for 2 s LED pulse 200 k; referred to peak input signal for 3 s LED pulse 200 k; saturation SNR per pulse per channel4 DC Power Supply Rejection Ratio (DC PSRR) Typ Max Unit 2.0 4.6 3.3 72.3 LSB rms nA rms nA rms dB 2.4 2.8 2.0 70.6 3.4 1.9 1.4 67.6 5.5 1.6 1.1 63.5 -37 LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB dB This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage. ADC resolution is listed per pulse when the AFE offset is correctly compensated per the AFE Operation section. If using multiple pulses, divide by the number of pulses. 3 This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal. 4 The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself. 1 2 DIGITAL SPECIFICATIONS DVDD = 1.7 V to 1.9 V, unless otherwise noted. Table 5. Parameter LOGIC INPUTS (SCL, SDA) Input Voltage Level High Low Input Current Level High Low Input Capacitance LOGIC OUTPUTS INT Output Voltage Level High Low PDSO Output Voltage Level High Low SDA Output Voltage Level Low SDA Output Current Level Low Symbol Test Conditions/Comments Min Typ Max Unit VIH VIL 0.7 x DVDD 3.6 0.3 x DVDD V V IIH IIL CIN -10 -10 +10 +10 A A pF 10 VOH VOL 2 mA high level output current 2 mA low level output current DVDD - 0.5 VOH VOL 2 mA high level output current 2 mA low level output current DVDD - 0.5 VOL1 2 mA low level output current IOL VOL1 = 0.6 V Rev. B | Page 7 of 52 6 0.5 V V 0.5 V V 0.2 x DVDD V mA ADPD103 Data Sheet TIMING SPECIFICATIONS Table 6. I2C Timing Specifications Parameter I2C PORT 1 SCL Frequency Minimum Pulse Width High Low Start Condition Hold Time Setup Time SDA Setup Time SCL and SDA Rise Time Fall Time Stop Condition Setup Time Test Conditions/Comments See Figure 2 Min Typ Max 400 t1 t2 600 1300 ns ns t3 t4 t5 600 600 100 ns ns ns t6 t7 1000 300 t8 600 t5 t3 t3 SDA t6 t1 SCL t7 t4 Figure 2. I2C Timing Rev. B | Page 8 of 52 t8 ns ns ns Guaranteed by design. t2 Unit kHz 12722-002 1 Symbol Data Sheet ADPD103 ABSOLUTE MAXIMUM RATINGS RECOMMENDED SOLDERING PROFILE Table 7. Figure 3 and Table 9 provide details about the recommended soldering profile. Rating -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +3.6 V -0.3 V to +3.9 V -0.3 V to +3.9 V 150C RAMP-UP tL TSMAX TSMIN tS RAMP-DOWN 1500 V 1250 V 100 V t25C TO PEAK TIME Figure 3. Recommended Soldering Profile Table 9. Recommended Soldering Profile 1500 V 500 V 100 V THERMAL RESISTANCE Table 8. Thermal Resistance JA 54.9 60 12722-003 TL PREHEAT Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Package Type 28-Lead LFCSP_WQ 16-Ball WLCSP CRITICAL ZONE TL TO TP tP TP TEMPERATURE Parameter AVDD to AGND DVDD to DGND INT to DGND PDSO to DGND LEDXx to LGND SCL to DGND SDA to DGND Junction Temperature ESD 28-Lead LFCSP Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) 16-Ball WLCSP Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) Unit C/W C/W Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (tS) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous Temperature Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tP) Ramp-Down Rate Time from 25C to Peak Temperature ESD CAUTION Rev. B | Page 9 of 52 Condition (Pb-Free) 3C/sec max 150C 200C 60 sec to 180 sec 3C/sec maximum 217C 60 sec to 150 sec +260 (+0/-5)C <30 sec 6C/sec maximum 8 minutes maximum ADPD103 Data Sheet 22 NIC 25 LEDX2 24 LEDX3 23 LEDX1 28 SDA 27 SCL 26 LGND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 21 NIC 20 NIC INT 1 PDSO 2 DVDD 3 ADPD103 19 NIC AGND 4 TOP VIEW (Not to Scale) 18 NIC PD7 14 PD6 13 PD3 PD2 PD5 12 15 PD8 PD4 10 PD1 7 PDC 11 17 NIC 16 NIC 8 9 AVDD 6 NOTES 1. NIC = NONBONDED PAD, CAN BE GROUNDED. 2. EXPOSED PAD (DIGITAL GROUND). CONNECT THE EXPOSED PAD TO GROUND. 12722-004 VREF 5 Figure 4. 28-Lead LFCSP Pin Configuration Table 10. 28-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 22 23 24 25 26 27 28 1 Mnemonic INT PDSO DVDD AGND VREF AVDD PD1 PD2 PD3 PD4 PDC PD5 PD6 PD7 PD8 NIC LEDX1 LEDX3 LEDX2 LGND SCL SDA EPAD (DGND) Type 1 DO DO S S REF S AI AI AI AI AO AI AI AI AI R AO AO AO S DI DIO S Description Interrupt Output. Power-Down Status Output. 1.8 V Digital Supply. Analog Ground. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 F capacitor to AGND. 1.8 V Analog Supply. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Common Cathode Bias. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Not Internally Connected (Nonbonded Pad). This pin can be grounded. LED Driver 1 Current Sink. If not in use, leave this pin floating. LED Driver 3 Current Sink. If not in use, leave this pin floating. LED Driver 2 Current Sink. If not in use, leave this pin floating. LED Driver Ground. I2C Clock Input. I2C Data Input/Output. Exposed Pad (Digital Ground). Connect the exposed pad to ground. DO means digital output, S means supply, REF means voltage reference, AI means analog input, AO means analog output, R means reserved, DI means digital input, and DIO means digital input/output. Rev. B | Page 10 of 52 Data Sheet ADPD103 ADPD103 TOP VIEW, BALL SIDE DOWN (Not to Scale) 2 A LGND LEDX2 B LEDX3 LEDX1 SDA C SCL INT DVDD DGND AGND D 3 E PDSO VREF AVDD F PD5-8 PDC PD1-4 12722-005 1 Figure 5. 16-Ball WLCSP Pin Configuration Table 11. 16-Ball WLCSP Pin Function Descriptions Pin No. A1 A2 B1 B2 B3 C1 C2 C3 D2 D3 E1 E2 E3 F1 F2 F3 1 Mnemonic LGND LEDX2 LEDX3 LEDX1 SDA SCL INT DVDD DGND AGND PDSO VREF AVDD PD5-8 PDC PD1-4 Type 1 S AO AO AO DIO S DO S S S DO REF S AI AO AI Description LED Driver Ground. LED Driver 2 Current Sink. If not in use, leave this pin floating. LED Driver 3 Current Sink. If not in use, leave this pin floating. LED Driver 1 Current Sink. If not in use, leave this pin floating. I2C Data Input/Output. I2C Clock Input. Interrupt Output. 1.8 V Digital Supply. Digital Ground. Analog Ground. Power-Down Status Output. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 F capacitor to AGND. 1.8 V Analog Supply. Photodiode Combined Current Input of PD5 to PD8. If not in use, leave this pin floating. Photodiode Common Cathode Bias. Photodiode Combined Current Input of PD1 to PD4. If not in use, leave this pin floating. S means supply, AO means analog output, DIO means digital input/output, DO means digital output, REF means voltage reference, and AI means analog input. Rev. B | Page 11 of 52 ADPD103 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 4.0 3.5 25 25k 3.0 20 NOISE (nA rms) PERCENT OF POPULATION (%) 30 15 10 2.5 50k 2.0 100k 1.5 200k 1.0 5 -25 -20 -15 -10 -5 0 5 10 SAMPLE FREQUENCY DEVIATION FROM NOMINAL (%) 15 0 12722-006 0 0 20 40 60 80 100 120 140 160 180 PHOTODIODE CAPACITANCE (pF) Figure 6. 32 kHz Clock Frequency Distribution (Default Settings, Before User Calibration: Register 0x4B = 0x2612) 12722-200 0.5 Figure 8. Input Referred Noise vs. Photodiode Capacitance, LED Pulse Width = 3 s 5 20 NOISE (nA rms) 25k 15 10 4 50k 3 100k 2 200k 5 0 0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 FREQUENCY (MHz) 0 20 40 60 80 100 120 140 160 180 PHOTODIODE CAPACITANCE (pF) Figure 9. Input Referred Noise vs. Photodiode Capacitance, LED Pulse Width = 2 s Figure 7. 32 MHz Clock Frequency Distribution (Default Settings, Before User Calibration: Register 0x4D = 0x425E) Rev. B | Page 12 of 52 12722-201 1 12722-007 PERCENT OF POPULATION (%) 6 Data Sheet ADPD103 THEORY OF OPERATION INTRODUCTION DUAL TIME SLOT OPERATION The ADPD103 operates as a complete optical transceiver stimulating up to three LEDs and measuring the return signal on up to eight separate current inputs. The core consists of a photometric front end coupled with an ADC, digital block, and three independent LED drivers. The core circuitry stimulates the LEDs and measures the return in the analog block through one to eight photodiode inputs, storing the results in discrete data locations. The eight inputs are broken into two blocks of four simultaneous input channels. Data can be read directly by a register, or through a FIFO. This highly integrated system includes an analog signal processing block, digital signal processing block, I2C communication interface, and programmable pulsed LED current sources. The ADPD103 operates in two independent time slots, Time Slot A and Time Slot B, which are carried out sequentially. The entire signal path from LED stimulation to data capture and processing is executed during each time slot. Each time slot has a separate datapath that uses independent settings for the LED driver, AFE setup, and the resulting data. Time Slot A and Time Slot B operate in sequence for every sampling period, as shown in Figure 10. The timing parameters are defined as follows: tA (s) = SLOTA_LED_OFFSET + nA x SLOTA_LED_PERIOD where nA is the number of pulses for Time Slot A (Register 0x31, Bits[15:8]). tB (s) = SLOTB_LED_OFFSET + nB x SLOTB_LED_PERIOD The LED driver is a current sink and is agnostic to LED supply voltage and LED type. The photodiode (PDx) inputs can accommodate any photodiode with an input capacitance of less than 100 pF. The ADPD103 is purposefully designed to produce a high SNR for relatively low LED power while greatly reducing the effect of ambient light on the measured signal. where nB is the number of pulses for Time Slot B (Register 0x36, Bits[15:8]). Calculate the LED period using the following equation: LED_PERIOD, minimum = 2 x AFE_WIDTH + 11 t1 and t2 are fixed and based on the computation time for each slot. If a slot is not in use, these times do not add to the total active time. Table 12 defines the values for these LED and sampling time parameters. ACTIVE ACTIVE tA nA PULSES t1 tB t2 nB PULSES TIME SLOT A 12722-008 SLEEP TIME SLOT B 1/fSAMPLE Figure 10. Time Slot Timing Diagram Table 12. LED Timing and Sample Timing Parameters Parameter SLOTA_LED_OFFSET 1 SLOTB_LED_OFFSET1 SLOTA_LED_PERIOD 2 SLOTB_LED_PERIOD2 t1 t2 tSLEEP 1 2 Register 0x30 0x35 0x31 0x36 Bits [7:0] [7:0] [7:0] [7:0] Test Conditions/Comments Delay from power-up to LEDA rising edge Delay from power-up to LEDB rising edge Time between LED pulses in Time Slot A; SLOTx_AFE_WIDTH = 4 s Time between LED pulses in Time Slot B; SLOTx_AFE_WIDTH = 4 s Compute time for Time Slot A Compute time for Time Slot B Sleep time between sample periods Min 23 23 19 19 68 20 222 Setting the SLOTx_LED_OFFSET below the specified minimum value may cause failure of ambient light rejection for large photodiodes. Setting the SLOTx_LED_PERIOD below the specified minimum value can cause invalid data captures. Rev. B | Page 13 of 52 Typ Max 63 63 63 63 Unit s s s s s s s ADPD103 Data Sheet TIME SLOT SWITCH PD1 Up to eight photodiodes (PD1 to PD8) can be connected to the ADPD103. The photodiode anodes are connected to the PD1 to PD8 input pins; the photodiode cathodes are connected to the cathode pin, PDC. The anodes are assigned in three different configurations depending on the settings of Register 0x14 (see Figure 11, Figure 12, and Figure 13). CH1 PD2 PD3 CH2 A switch sets which photodiode group is connected during Time Slot A and Time Slot B. See Table 13 for the time slot switch registers. When using less than eight photodiodes, it is important to leave the unused inputs floating for proper operation of the device. The photodiode inputs are current inputs and as such, these pins are also considered to be voltage outputs. Tying these inputs to a voltage may saturate the analog block. PD4 Register 0x14, PD1 to PD8 Input Configurations PD7 PD5 CH3 PD6 CH4 PD1 PD8 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 4 REGISTER 0x14[7:4] = 4 12722-110 CH1 PD2 Figure 12. PD5 to PD8 Connection PD3 PD1 CH2 PD4 CH1 PD2 PD5 PD3 CH3 PD6 CH2 PD4 PD7 PD5 CH4 PD8 CH3 PD7 Figure 11. PD1 to PD4 Connection CH4 PD8 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 1 REGISTER 0x14[7:4] = 1 12722-111 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 5 REGISTER 0x14[7:4] = 5 12722-109 PD6 Figure 13. 2-to-1 PD Current Summation Rev. B | Page 14 of 52 Data Sheet ADPD103 Table 13. Time Slot Switch (Register 0x14) Address 0x14 Bits [11:8] Name SLOTB_PD_SEL [7:4] SLOTA_PD_SEL Description Selects connection of photodiode for Time Slot B as shown in Figure 11, Figure 12, and Figure 13. 0x0: inputs are floating in Time Slot B. 0x1: all PDx pins (PD1 to PD8) are connected during Time Slot B. 0x4: PD5 to PD8 are connected during Time Slot B. 0x5: PD1 to PD4 are connected during Time Slot B. Other: reserved. Selects connection of photodiode for Time Slot A as shown in Figure 11, Figure 12, and Figure 13. 0x0: inputs are floating in Time Slot A. 0x1: All PDx pins (PD1 to PD8) are connected during Time Slot A. 0x4: PD5 to PD8 are connected during Time Slot A. 0x5: PD1 to PD4 are connected during Time Slot A. Other: reserved. ADJUSTABLE SAMPLING FREQUENCY Register 0x12 controls the sampling frequency setting of the ADPD103 and Register 0x4B, Bits[5:0] further tunes this clock for greater accuracy. The sampling frequency is governed by an internal 32 kHz sample rate clock that also drives the transition of the internal state machine. The maximum sampling frequencies for some sample conditions are listed in Table 3. The maximum sample frequency for all conditions is determined by the following equation: fSAMPLE, MAX = 1/(tA + t1 + tB + t2 + tSLEEP, MIN) If a given time slot is not in use, elements from that time slot do not factor into the calculation. For example, if Time Slot A is not in use, tA and t1 do not add to the sampling period and the new maximum sampling frequency is calculated as follows: fSAMPLE, MAX = 1/( tB + t2 + tSLEEP, MIN) where tSLEEP, MIN is the minimum sleep time required between samples. See the Dual Time Slot Operation section for the definitions of tA, t1, tB, and t2. 4. 5. The maximum frequency constraints also apply in this case. Providing an External 32kHz Clock The ADPD103 has an option for the user to provide an external 32 kHz clock to the device for system synchronization or for situations where a clock with better accuracy than the internal 32 kHz clock is required. The external 32 kHz clock is provided on the PDSO pin. To enable the 32 kHz external clock, use the following procedure at startup: 1. External Sync for Sampling The ADPD103 provides an option to use an external sync signal to trigger the sampling periods. This external sample sync signal can be provided either on the INT pin or the PDSO pin. This functionality is controlled by Register 0x4F, Bits[3:2]. When enabled, a rising edge on the selected input specifies when the next sample cycle occurs. When triggered, there is a delay of one to two internal sampling clock (32 kHz) cycles, and then the normal start-up sequence occurs. This sequence is the same as if the normal sample timer provided the trigger. To enable the external sync signal feature, use the following procedure: 1. 2. 3. Write 0x1 to Register 0x10 to enter program mode. Write the appropriate value to Register 0x4F, Bits[3:2] to select whether the INT pin or the PDSO pin specifies when the next sample cycle occurs. Also, enable the appropriate input buffer using Register 0x4F, Bit 1, for the INT pin, or Register 0x4F, Bit 5, for the PDSO pin. Write b1 to EXT_SYNC_ENA, Register 0x38, Bit 14 to enable the external sampling trigger. Write 0x2 to Register 0x10 to start the sampling operations. Apply the external sync signal on the selected pin at the desired rate; sampling occurs at that rate. As with normal sampling operations, read the data using the FIFO or the data registers. 2. 3. 4. 5. 6. Rev. B | Page 15 of 52 Drive the PDSO pin to a valid logic level or with the desired 32 kHz clock prior to enabling the PDSO pin as an input. Do not leave the pin floating prior to enabling it. Write b1 to Register 0x4F, Bit 5 to enable the PDSO pin as an input. Write b11 to register 0x4B, Bit 7 and Bit 8 (CLK32K_EN and CLK32K_BYP, respectively) to configure the device to use an external 32 kHz clock. Write 0x1 to Register 0x10 to enter program mode. Write additional control registers in any order while the device is in program mode to configure the device as required. Write 0x2 to Register 0x10 to start the normal sampling operation. ADPD103 Data Sheet STATE MACHINE OPERATION Program mode is used for programming registers. Always cycle the ADPD103 through program mode when writing registers or changing modes. Because no power cycling occurs in this mode, the device may consume higher current in program mode than in normal operation. To place the device in program mode, write 0x1 to Register 0x10, Bits[1:0]. During each time slot, the ADPD103 operates according to a state machine. The state machine operates in the following sequence, shown in Figure 14. STANDBY REGISTER 0x10 = 0x0000 ULTRALOW POWER MODE In normal operation, the ADPD103 pulses light and collects data. Power consumption in this mode depends on the pulse count and data rate. To place the device in normal sampling mode, write 0x2 to Register 0x10, Bits[1:0]. NO DATA COLLECTION ALL REGISTER VALUES ARE RETAINED. NORMAL MODE OPERATION AND DATA FLOW PROGRAM In normal mode, the ADPD103 follows a specific pattern set up by the state machine. This pattern is shown in the corresponding data flow in Figure 15. The pattern is as follows: REGISTER 0x10 = 0x0001 SAFE MODE FOR PROGRAMING REGISTERS NO DATA COLLECTION DEVICE IS FULLY POWERED IN THIS MODE. 1. NORMAL OPERATION 12722-016 REGISTER 0x10 = 0x0002 LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED STANDARD DATA COLLECTION DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE. 2. Figure 14. State Machine Operation Flowchart The ADPD103 operates in one of three modes: standby, program, and normal sampling mode. 3. Standby mode is a power saving mode in which no data collection occurs. All register values are retained in this mode. To place the device in standby mode, write 0x0 to Register 0x10, Bits[1:0]. The device powers up in standby mode. 4. LED pulse and sample.The ADPD103 pulses external LEDs. The response of a photodiode or photodiodes to the reflected light is measured by the ADPD103. Each data sample is constructed from the sum of n individual pulses, where n is user configurable between 1 and 255. Intersample averaging. If desired, the logic can average n samples, from 2 to 128 in powers of 2, to produce output data. New output data is saved to the output registers every N samples. Data read. The host processor reads the converted results from the data register or the FIFO. Repeat. The sequence has a few different loops that enable different types of averaging while keeping both time slots close in time relative to each other. [14 + LOG2(nA x NA)] BITS UP TO 27 BITS [14 + LOG2(nA)] BITS UP TO 20 BITS NA NA 14 BITS 1 14 BITS nA nA nA 14-BIT ADC 1 ADC OFFSET 20-BIT CLIP IF VAL (220 - 1) VAL = VAL ELSE VAL = 2 20 - 1 0 16-BIT CLIP 16 BITS IF VAL (216 - 1) VAL = VAL ELSE VAL = 216 - 1 1 REGISTER 0x11[13] [14 + LOG2(nA)] BITS UP TO 22 BITS 32-BIT DATA REGISTERS FIFO 16-BIT DATA REGISTERS SAMPLE 1: TIME SLOT A SAMPLE 1: TIME SLOT B 0 1 SAMPLE N A: TIME SLOT A SAMPLE N B: TIME SLOT B NB NOTES 1. nA AND nB = NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B. 2. NA AND NB = NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B. NB 1 [14 + LOG2(nB)] BITS UP TO 20 BITS [14 + LOG2(nB x NB)] BITS UP TO 27 BITS Figure 15. ADPD103 Datapath Rev. B | Page 16 of 52 16-BIT CLIP IF VAL (216 - 1) VAL = VAL ELSE VAL = 2 16 - 1 16 BITS 12722-009 TIME SLOT A TIME SLOT B Data Sheet ADPD103 select from 2, 4, 8 ... up to 128 samples to be averaged. Pulse data is still acquired by the AFE at the sampling frequency, fSAMPLE (Register 0x12), but new data is written to the registers at the rate of fSAMPLE/N every Nth sample. This new data consists of the sum of the previous N samples. The full 32-bit sum is stored in the 32-bit registers. However, before sending this data to the FIFO, a divide by N operation occurs. This divide operation maintains bit depth to prevent clipping on the FIFO. LED Pulse and Sample At each sampling period, the selected LED driver drives a series of LED pulses, as shown in Figure 16. The magnitude, duration, and number of pulses are programmable over the I2C interface. Each LED pulse coincides with a sensing period so that the sensed value represents the total charge acquired on the photodiode in response to only the corresponding LED pulse. Charge, such as ambient light, that does not correspond to the LED pulse is rejected. After each LED pulse, the photodiode output relating the pulsed LED signal is sampled and converted to a digital value by the 14-bit ADC. Each subsequent conversion within a sampling period is summed with the previous result. Up to 255 pulse values from the ADC can be summed in an individual sampling period. There is a 20-bit maximum range for each sampling period. Use this between sample averaging to lower the noise while maintaining 16-bit resolution. If the pulse count registers are kept to 8 or less, the 16-bit width is never exceeded. Therefore, when using Register 0x15 to average subsequent pulses, many pulses can be accumulated without exceeding the 16-bit word width. This can reduce the number of FIFO reads required by the host processor. Averaging Data Read The ADPD103 offers sample accumulation and averaging functionality to increase signal resolution. The host processor reads output data from the ADPD103, via the I2C protocol, from the data registers or from the FIFO. New output data is made available every N samples, where N is the user configured averaging factor. The averaging factors for Time Slot A and Time Slot B are configurable independently of each other. If they are the same, both time slots can be configured to save data to the FIFO. If the two averaging factors are different, only one time slot can save data to the FIFO; data from the other time slot can be read from the output registers. Within a sampling period, the AFE can sum up to 256 sequential pulses. As shown in Figure 15, samples acquired by the AFE are clipped to 20 bits at the output of the AFE. Additional resolution, up to 27 bits, can be achieved by averaging between sampling periods. This accumulated data of N samples is stored as 27-bit values and can be read out directly by using the 32-bit output registers or the 32-bit FIFO configuration. The data read operations are described in more detail in the Reading Data section. When using the averaging feature set up by the register, subsequent pulses can be averaged by powers of 2. The user can SHOWN WITH fSAMPLE = 10 Hz OPTICAL SAMPLING LOCATIONS 0.5 1.0 1.5 2.0 2.5 3.0 TIME (s) LED CURRENT (ILED) NUMBER OF LED PULSES (nA OR nB) Figure 16. Example of a Photoplethysmography (PPG) Signal Sampled at a Data Rate of 10 Hz Using Five Pulses per Sample Rev. B | Page 17 of 52 12722-010 0 ADPD103 Data Sheet AFE OPERATION The timing within each pulse burst is important for optimizing the operation of the ADPD103. Figure 17 shows the timing waveforms for a single time slot as an LED pulse response propagates through the analog block of the AFE. The first graph, shown in green, shows the ideal LED pulsed output. The filtered LED response, shown in blue, shows the output of the analog integrator. The third graph, shown in orange, illustrates an optimally placed integration window. When programmed to the optimized value, the full signal of the filtered LED response can be integrated. The AFE integration window is then applied to the output of the bandpass filter (BPF) and the result is sent to the ADC and summed for N pulses. If the AFE window is not correctly sized or located, all of the receive signal is not properly reported and system perfor- mance is not optimal; therefore, it is important to verify proper AFE position for every new hardware design or the LED width. AFE INTEGRATION OFFSET ADJUSTMENT The AFE integration width must be equal or larger than the LED width. As AFE width increases, the output noise increases and the ability to suppress high frequency content from the environment decreases. It is therefore desirable to keep the AFE integration width small. However, if the AFE width is too small, the LED signal is attenuated. With most hardware selections, the AFE width produces the optimal SNR at 1 s more than the LED width. After setting LED width, LED offset, and AFE width, the ADC offset can then be optimized. The AFE offset must be manually set such that the falling edge of the first segment of the integration window matches the zero crossing of the filtered LED response. Figure 17. AFE Operation Diagram Rev. B | Page 18 of 52 Data Sheet ADPD103 LED_FALLING_EDGE = LED_OFFSET + LED_WIDTH and, AFE_INTEGRATION_FALLING_EDGE = 9 + AFE_OFFSET + AFE_WIDTH If both falling edges are set equal to each other, solve for AFE_OFFSET to obtain the following equation: AFE_OFFSET_STARTING_POINT = LED_OFFSET + LED_WIDTH - 9 - AFE_WIDTH Setting the AFE offset to any point in time earlier than the starting point is equivalent to setting the integration in the future; the AFE cannot integrate the result from an LED pulse that has not yet occurred. As a result, an AFE_OFFSET value less than the AFE_OFFSET_STARTING_POINT is an erroneous setting. Such a result may indicate that current in the TIA is operating in the reverse direction from the intended schematic, where the LED pulse is causing the current to leave the TIA rather than enter it. Because, for most setups, the AFE_WIDTH is 1 s wider than the LED_WIDTH, the AFE_OFFSET_STARTING_POINT value is typically 10 s less than the LED_OFFSET value. Any value less than LED_OFFSET - 10 is erroneous. The optimal AFE offset is some time after the AFE_OFFSET_STARTING_ POINT. The band-pass filter response, LED response, and photodiode response each add some delay. In general, the component choice, board layout, LED_OFFSET, and LED_WIDTH are the variables that can change the AFE_OFFSET. After a specific design is set, the AFE_OFFSET can be locked down and does not need to be optimized further. Sweeping the AFE Position The AFE offsets for Time Slot A and Time Slot B are controlled by Bits[10:0] of Register 0x39 and Register 0x3B, respectively. Each LSB represents one cycle of the 32 MHz clock, or 31.25 ns. 100 0.687 95 90 85 80 75 0 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 AFE OFFSET FROM STARTING POINT (s) 1.35 1.50 12722-113 The starting point of this offset, as expressed in microseconds, is set such that the falling edge of the integration window aligns with the falling edge of the LED. The register can be thought of as 211 - 1 of these 31.25 ns steps, or it can be broken into an AFE_COARSE setting using Bits[10:5] to represent 1 s steps and Bits[4:0] to represent 31.25 ns steps. Sweeping the AFE position from the starting point to find a local maximum is the recommended way to optimize the AFE offset. The setup for this test is to allow the LED light to fall on the photodiode in a static way. This is typically done with a reflecting surface at a fixed distance. The AFE position can then be swept to look for changes in the output level. When adjusting the AFE position, it is important to sweep the position using the 31.25 ns steps. Typically, a local maximum is found within 2 s of the starting point for most systems. Figure 18 shows an example of an AFE sweep, where 0 on the x-axis represents the AFE starting point defined previously. Each data point in the plot corresponds to one 31.25 ns step of the AFE_OFFSET. The optimal location for AFE_OFFSET in this example is 0.687 s from the AFE starting point. RELATIVE OUTPUT VALUE (%) AFE Integration Offset Starting Point Figure 18. AFE Sweep Example Table 14 lists some typical LED and AFE values after optimization. In general, it is not recommended to use the AFE_OFFSET numbers in Table 14 without first verifying them against the AFE sweep method. Repeat this method for every new LED width and with every new set of hardware made with the ADPD103. For maximum accuracy, it is recommended that the 32 MHz clock be calibrated prior to sweeping the AFE. Table 14. AFE Window Settings LED Register 0x30 or Register 0x35 0x0219 0x0319 AFE Register 0x39 or Register 0x3B 0x19FB 0x21F4 Rev. B | Page 19 of 52 Comment 2 s LED pulse, 3 s AFE width, 25 s LED delay 3 s LED pulse, 4 s AFE width, 25 s LED delay ADPD103 Data Sheet I2C SERIAL INTERFACE 4. The ADPD103 supports an I C serial interface via the SDA (data) and SCL (clock) pins. All internal registers are accessed through the I2C interface. 2 The ADPD103 conforms to the UM10204 I2C-Bus Specification and User Manual, Rev. 05--9 October 2012, available from NXP Semiconductors. It supports a fast mode (400 kbps) data transfer. Register read and write are supported, as shown in Figure 19. Figure 2 shows the timing diagram for the I2C interface. Slave Address The default 7-bit I2C slave address for the device is 0x64, followed by the R/W bit. For a write, the default I2C slave address is 0xC8; for a read, the default I2C address is 0xC9. The slave address is configurable by writing to Register 0x09, Bits[7:1]. When multiple ADPD103 devices are on the same bus lines, the INT and PDSO pins can be used to select specific devices for the address change. Register 0x0D can be used to select a key to enable address changes in specific devices. Use the following procedure to change the slave address when multiple ADPD103 devices are connected to the same I2C bus lines: 1. 2. 3. Using Register 0x4F, enable the input buffer of the PDSO pin, the INT pin, or both, depending on the key being used. For the device identified as requiring an address change, set the INT and/or PDSO pins high or low to match the key being used. Write the SLAVE_ADDRESS_KEY using Register 0x0D, Bits[15:0] to match the desired function. The allowed keys are shown in Table 24. 5. 6. Write the desired SLAVE_ADDRESS using Register 0x09, Bits[7:1]. While writing to Register 0x09, Bits[7:1], write 0xAD to Register 0x09, Bit[15:8]. Register 0x09 must be written to immediately after writing to Register 0x0D. Repeat Step 1 to Step 4 for all the devices that need the SLAVE_ADDRESS changed. Set the INT and PDSO pins as desired for normal operation using the new SLAVE_ADDRESS for each device. I2C Write and Read Operations Figure 19 illustrates the ADPD103 I2C write and read operations. Single word and multiword read operations are supported. For a single register read, the host sends a no acknowledge after the second data byte is read and a new register address is needed for each access. For multiword operations, each pair of data bytes is followed by an acknowledge from the host until the last byte of the last word is read. The host indicates the last read word by sending a no acknowledge. When reading from the FIFO (Register 0x60), the data is automatically advanced to the next word in the FIFO and the space is freed. When reading from other registers, the register address is automatically advanced to the next register, except at Register 0x5F or Register 0x7F, where the address does not increment. This allows lower overhead reading of sequential registers. All register writes are single word only and require 16 bits (one word) of data. The software reset (Register 0x0F, Bit 0) is the only command that does not return an acknowledge because the command is instantaneous. Table 15. Definition of I2C Terminology Term SCL SDA Master Slave Start (S) Start (Sr) Stop (P) ACK NACK Slave Address Read (R) Write (W) Description Serial clock. Serial address and data. The master is the device that initiates a transfer, generates clock signals, and terminates a transfer. The slave is the device addressed by a master. The ADPD103 operates as a slave device. A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition. Repeated start condition. A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions. During the acknowledge or no acknowledge clock pulse, the SDA line is pulled low and remains low. During the acknowledge or no acknowledge clock pulse, the SDA line remains high. After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write). A 1 indicates a request for data. A 0 indicates a transmission. Rev. B | Page 20 of 52 Data Sheet ADPD103 I2C WRITE REGISTER WRITE MASTER START SLAVE ADDRESS + WRITE SLAVE DATA[15:8] REGISTER ADDRESS ACK ACK DATA[7:0] STOP ACK ACK I2C SINGLE WORD READ MODE REGISTER READ MASTER START SLAVE ADDRESS + WRITE SLAVE REGISTER ADDRESS ACK ACK SLAVE ADDRESS + READ Sr ACK ACK DATA[15:8] ACK DATA[15:8] NACK STOP DATA[7:0] I2C MULTIWORD READ MODE REGISTER READ SLAVE SLAVE ADDRESS + WRITE REGISTER ADDRESS ACK ACK/NACK ACK SLAVE ADDRESS + READ Sr ACK STOP DATA[7:0] 12722-012 MASTER START DATA TRANSFERRED n (DATA[15:8]+ACK+DATA[7:0] + ACK/NACK) NOTES 1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. Figure 19. I2C Write and Read Operations A B Provide the 1.8 V supply, VDD, to AVDD and DVDD. Use single (VLED) or multiple (VLED1, VLED2, and VLED3) sources for the LED supply using standard regulator circuits according to the peak current requirements specified in Table 3 and calculated in the Calculating Current Consumption section. C LGND LEDX2 LEDX3 LEDX1 SDA SCL INT DVDD 3 AGND DGND PDSO VREF AVDD F PD5-8 PDC PD1-4 12722-014 E Figure 20. WLCSP Package Connection and PCB Layout Diagram (Top View) VLED3 VLED2 VLED1 4.7F 4.7F NIC LEDX1 LEDX3 LEDX2 LGND SCL 22 28 POWER-DOWN CONTROL The current input pins (PD1 to PD8) have a typical voltage of 1.3 V during the sampling period. During the sleep period, Rev. B | Page 21 of 52 21 1 PDSO NIC DVDD 0.1F NIC ADPD103 AGND NIC TOP VIEW (Not to Scale) 0.1F VREF NIC AVDD 0.1F PD1 NIC NIC 7 15 PD8 14 PD7 PD6 PD5 8 12722-017 Figure 20 shows the recommended connection diagram and printed circuit board (PCB) layout for the ADPD103 WLCSP package. See Figure 21 or Figure 22 for connection details. INT PDC 1.8V 4.7F I2C BUS SDA TO/FROM HOST PROCESSOR PD2 With large photodiodes, the dynamic range can be increased by splitting the current between multiple inputs. As a result, if only one large photodiode is used and the receive signal is expected to be large, the diode can be branched across all four inputs in a given time slot. This type of configuration is shown in Figure 21. For situations where the photodiode is small or the signal is greatly attenuated, the photodiode can be connected directly to a single channel such as PD1 or PD5. This connection, shown in Figure 22, maximizes SNR for low signals. Do not connect the same photodiode to all eight input channels. It is important to leave the unused input channels floating for proper device operation. The WLCSP package is internally wired for high dynamic range mode. 2 D For best noise performance, connect AGND, DGND (exposed pad), and LGND together at a large conductive surface such as a ground plane, a ground pour, or a large ground trace. The number of photodiodes or LEDs used varies. There are multiple ways to connect photodiodes to the input channels, as shown in Table 16 and Figure 23. The photodiode anodes are connected to the PD1 to PD8 input pins, and the photodiode cathodes are connected to the cathode pin. 1 PD4 Figure 21 and Figure 22 show two possible photodiode input connections for the ADPD103. The 1.8 V I2C communication lines, SCL and SDA, along with the INT line, connect to a system microprocessor or sensor hub. The I2C signals can have pull-up resistors connected to a 1.8 V or a 3.3 V power supply. The INT and PDSO signals are only compatible with a 1.8 V supply and may need a level translator. these pins are connected to the cathode pin. The cathode and anode voltages are listed in Table 3. PD3 TYPICAL CONNECTION DIAGRAM Figure 21. Connection Diagram for Increased Dynamic Range ADPD103 Data Sheet VLED2 VLED1 VLED3 4.7F NIC LEDX1 LEDX3 LEDX2 LGND SCL 22 28 POWER-DOWN CONTROL INT 0.1F NIC 21 1 PDSO NIC DVDD 1.8V NIC ADPD103 AGND NIC TOP VIEW (Not to Scale) 0.1F VREF NIC AVDD 0.1F 4.7F 4.7F I2C BUS SDA TO/FROM HOST PROCESSOR PD1 NIC 7 14 12722-013 PD7 PD6 PD5 PDC PD4 PD3 8 PD2 PD8 15 Figure 22. Connection Options for Individual Single Channel Diodes 14 PD8 14 PD7 PD6 PD4 PDC PD5 PD2 15 PD8 14 8 12722-020 PDC PD4 PD3 15 8 PDC PD5 7 15 8 PD2 14 8 7 PD7 7 PD1 15 PD6 PD4 PDC 7 PD3 14 8 PD1 PD1 15 PD5 14 8 7 PDC PD1 PDC 15 PD3 7 PD2 PD1 Figure 23. Typical Photodiode Connection Diagram Table 16. Typical Photodiode Anode to Input Channel Connections Input Channel Photodiode Anode Configuration Single Photodiode (D1) Two Photodiodes (D1, D2) Four Photodiodes (D1 to D4) Eight Photodiodes (D1 to D8) 1 PD1 D1 NC 1 D1 NC1 D1 D1 D1 NC1 D1 PD2 NC1 NC1 D1 NC1 NC1 D1 D2 NC1 D2 PD3 NC1 NC1 D1 NC1 NC1 D1 D3 NC1 D3 NC means do not connect under the conditions provided in Table 16. Leave all unused inputs floating. Rev. B | Page 22 of 52 PD4 NC1 NC1 D1 NC1 NC1 D1 D4 NC1 D4 PD5 NC1 D1 NC1 D1 D2 D2 NC1 D1 D5 PD6 NC1 NC1 NC1 D1 NC1 D2 NC1 D2 D6 PD7 NC1 NC1 NC1 D1 NC1 D2 NC1 D3 D7 PD8 NC1 NC1 NC1 D1 NC1 D2 NC1 D4 D8 Data Sheet ADPD103 LED DRIVER PINS AND LED SUPPLY VOLTAGE The LEDx1, LEDx2, and LEDx3 pins have an absolute maximum voltage rating of 3.6 V. Any voltage exposure over this rating affects the reliability of the device operation and, in certain circumstances, causes the device to cease proper operation. The voltage of the LEDx pins must not be confused with the supply voltages for the LED themselves (VLEDx). VLEDx is the voltage applied to the anode of the external LED, whereas the LEDx pin is the input of the internal current driver, and the pins are connected to the cathode of the external LED. LED DRIVER OPERATION The LED driver for the ADPD103 is a current sink requiring 0.2 V of compliance above ground to maintain the programmed current level. Figure 24 shows the basic schematic of how the ADPD103 connects to an LED through the LED driver. The Determining the Average Current and the Determining CVLED sections define the requirements for the bypass capacitor (CVLED) and the supply voltages of the LEDs (VLEDx). DETERMINING CVLED To determine the CVLED capacitor value, determine the maximum forward-biased voltage, VFB_LED_MAX, of the LED in operation. The LED current, IFB_LED_MAX, converts to VFB_LED_MAX as shown in Figure 26. In this example, 250 mA of current through two green LEDs in parallel yields VFB_LED_MAX = 3.95 V. Any series resistance in the LED path must also be included in this voltage. When designing the LED path, keep in mind that small resistances can add up to large voltage drops due to the LED peak current being very large. In addition, these resistances can be unnecessary constraints on the VLEDx supply. 4.5 Figure 24. VLEDx Supply Schematic DETERMINING THE AVERAGE CURRENT The ADPD103 drives an LED in a series of short pulses. Figure 25 shows the typical ADPD103 configuration of a pulse burst sequence. 19s 3s TWO 528nm LEDs ONE 850nm LED 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 50 100 150 200 LED DRIVER CURRENT SETTING (mA) ILED_MAX 12722-119 Figure 26. Example of the Average LED Forward-Biased Voltage Drop as a Function of the Driver Current Figure 25. Typical LED Pulse Burst Sequence Configuration In this example, the LED pulse width, tLED_PULSE, is 3 s, and the LED pulse period, tLED_PERIOD, is 19 s. The LED being driven is a pair of green LEDs driven to a 250 mA peak. The goal of CVLED is to buffer the LED between individual pulses. In the worst case scenario, where the pulse train shown in Figure 25 is a continuous sequence of short pulses, the VLEDx supply must supply the average current. Therefore, calculate ILED_AVERAGE as follows: ILED_AVERAGE = (tLED_PULSE/tLED_PERIOD) x ILED_PEAK 250 12722-120 LEDx VLEDx SUPPLY For the numbers shown in Equation 1, ILED_AVERAGE = 3/19 x ILED_PEAK. For typical LED timing, the average VLEDx supply current is 3/19 x 250 mA = 39.4 mA, indicating that the VLEDx supply must support a dc current of 40 mA. LED FORWARD-BIAS VOLTAGE DROP (V) LGND CVLED 12722-118 ADPD103 where: ILED_AVERAGE is the average current needed from the VLEDx supply during the pulse period, and it is also the VLEDx supply current rating. ILED_PEAK is peak current setting of the LED. (1) To correctly size the CVLED capacitor, do not deplete it during the pulse of the LED to the point where the voltage on the capacitor is less than the forward bias on the LED. To calculate the minimum value for the VLEDx bypass capacitor, use the following equation: CVLED = t LED_PULSE x I FB _ LED _ MAX VLED _ MIN - (VFB _ LED _ MAX + 0.2) (2) where: tLED_PULSE is the LED pulse width. IFB_LED_MAX is the maximum forward-biased current on the LED used in operating the device. VLED_MIN is the lowest voltage from the VLEDx supply with no load. VFB_LED_MAX is the maximum forward-biased voltage required on the LED to achieve ILED_PEAK. Rev. B | Page 23 of 52 ADPD103 Data Sheet The numerator of the CVLED equation sets up the total discharge amount in coulombs from the bypass capacitor to satisfy a single programmed LED pulse of the maximum current. The denominator represents the difference between the lowest voltage from the VLEDx supply and the LED required voltage. The LED required voltage is the voltage of the anode of the LED such that the 0.2 V compliance of the LED driver and the forward-biased voltage of the LED operating at the maximum current is satisfied. For a typical ADPD103 example, assume that the lowest value for the VLEDx supply is 4.4 V, and that the peak current is 250 mA for two 528 nm LEDs in parallel. The minimum value for CVLED is then equal to 3 F. CVLED = (3 x 10-6 x 0.250)/(4.4 - (3.95 + 0.2)) = 3 F (3) As shown in the Equation 3, as the minimum supply voltage drops close to the maximum anode voltage, the demands on CVLED become more stringent, forcing the capacitor value higher. It is important to insert the correct values into these equations. For example, using an average value for VLED_MIN instead of the worst case value for VLED_MIN can cause a serious design deficiency, resulting in a CVLED value that is too small and that causes insufficient optical power in the application. Therefore, adding a sufficient margin on CVLED is strongly recommended. Add additional margin to CVLED to account for derating of the capacitor value over voltage, bias, temperature and other factors over the life of the component. LED INDUCTANCE CONSIDERATIONS The LED drivers (LEDXx) on the ADPD103 have configurable slew rate settings (Register 0x22, Bits[6:4], Register 0x23, Bits[6:4], and Register 0x24, Bits[6:4]). These slew rates are defined in Table 3. Even at the lowest setting, careful consideration must be taken in board design and layout. If a large series inductor, such as a long PCB trace, is placed between the LED cathode and one of the LEDXx pins, voltage spikes from the switched inductor can cause violations of absolute maximum and minimum voltages on the LEDXx pins during the slew portion of the LED pulse. To verify that there are no voltage spikes on the LEDXx pins due to parasitic inductance, use an oscilloscope on the LEDXx pins to monitor the voltage during normal operation. Any positive spike >3.6 V may damage the device. In addition, a negative spike <-0.3 V may also damage the device. RECOMMENDED START-UP SEQUENCE At power-up, the device is in standby mode (Register 0x10 = 0x0), as shown in Figure 14. The ADPD103 does not require a particular power-up sequence. From standby mode, to begin measurement, initiate the ADPD103 as follows: 1. 2. 3. 4. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the sample clock (32 kHz clock). This clock controls the state machine. If this clock is off, the state machine is not able to transition as defined by Register 0x10. Write 0x1 to Register 0x10 to force the device into program mode. Step 1 and Step 2 can be swapped, but the actual state transition does not occur until both steps occur. Write additional control registers in any order while the device is in program mode to configure the device as required. Write 0x2 to Register 0x10 to start normal sampling operation. To terminate normal operation, follow this sequence to place the ADPD103 in standby mode: 1. 2. 3. 4. 5. Write 0x1 to Register 0x10 to force the device into program mode. Write to the registers in any order while the device is in program mode. Write 0x00FF to Register 0x00 to clear all interrupts. If desired, clear the FIFO as well by setting the DIGITAL_ CLOCK_ENA bit (Register 0x5F, Bit 0) and writing 0x80FF to Register 0x00. Write 0x0 to Register 0x10 to force the device into standby mode. Optionally, stop the 32 kHz clock by resetting the CLK32K_ EN bit (Register 0x4B, Bit 7). Register 0x4B, Bit 7 = 0 is the only write that must be written when the device is in standby mode (Register 0x10 = 0x0). If 0 is written to this bit while in program mode or normal mode, the device becomes unable to transition into any other mode, including standby mode, even if it is subsequently written to do so. As a result, the power consumption in what appears to be standby mode is greatly elevated. For this reason, and due to the very low current draw of the 32 kHz clock while in operation, it is recommended from an ease of use perspective to keep the 32 kHz clock running after it is turned on. READING DATA The ADPD103 provides multiple methods for accessing the sample data. Each time slot can be independently configured to provide data access using the FIFO or the data registers. Interrupt signaling is also available to simplify timely data access. The FIFO is available to loosen the system timing requirements for data accesses. Reading Data Using the FIFO The ADPD103 includes a 128-byte FIFO memory buffer that can be configured to store data from either or both time slots. Register 0x11 selects the kind of data from each time slot to be Rev. B | Page 24 of 52 Data Sheet ADPD103 c. Read a complete packet using one or more multiword accesses using Register 0x60. Reading the FIFO automatically frees the space for new samples. d. Write 0 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bit 0). written to the FIFO. Note that both time slots can be enabled to use the FIFO, but only if their output data rate is the same. Output data rate = fSAMPLE/N where: fSAMPLE is the sampling frequency. N is the averaging factor for each time slot (NA for Time Slot A and NB for Time Slot B). In other words, NA = NB must be true to store data from both time slots in the FIFO. Data packets are written to the FIFO at the output data rate. A data packet for the FIFO consists of a complete sample for each enabled time slot. Data for each photodiode channel can be stored as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of data per sample, depending on the mode and data format. To ensure that data packets are intact, new data is only written to the FIFO if there is sufficient space for a complete packet. Any new data that arrives when there is not enough space is lost. The FIFO continues to store data when sufficient space exists. Always read FIFO data in complete packets to ensure that data packets remain intact. The number of bytes currently stored in the FIFO is available in Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also available and automatically generates when a specified amount of data is written to the FIFO. Interrupt-Based Method To read data from the FIFO using an interrupt-based method, use the following procedure: 1. 2. 3. 4. 5. 6. In program mode, set the configuration of the time slots as desired for operation. Write Register 0x11 with the desired data format for each time slot. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the interrupt threshold. A good value for this is the number of 16-bit words in a data packet, minus 1. This causes an interrupt to generate when there is at least one complete packet in the FIFO. Enable the FIFO interrupt by writing a 0 to the FIFO_ INT_MASK in Register 0x01, Bit 8. Also, configure the interrupt pin (INT) by writing the appropriate value to the bits in Register 0x02. Enter normal operation mode by setting Register 0x10 to 0x2. When an interrupt occurs a. There is no requirement to read the FIFO_SAMPLES register, because the interrupt is generated only if there is one or more full packets. Optionally, the interrupt routine can check for the presence of more than one available packet by reading this register. b. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bit 0) twice in two consecutive write operations. The interrupt automatically clears when enough data is read from the FIFO to bring the data level below the threshold. Polling Method To read data from the FIFO in a polling method, use the following procedure: 1. 2. 3. In program mode, set the configuration of the time slots as desired for operation. Write Register 0x11 with the desired data format for each time slot. Enter normal operation mode by setting Register 0x10 to 2. Next, begin the polling operations. 1. Wait for the polling interval to expire. 2. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]). 3. If FIFO_SAMPLES the packet size, read a packet using the following steps: a. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bit 0) twice in two consecutive write operations. b. Read a complete packet using one or more multiword accesses using Register 0x60. Reading the FIFO automatically frees the space for new samples. c. Write 0 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bit 0). d. Repeat Step 1. When a mode change is required, or any other disruption to normal sampling is necessary, the FIFO must be cleared. Use the following procedure to clear the state and empty the FIFO: 1. 2. 3. 4. Enter program mode by setting Register 0x10 to 0x1. Write 1 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bit 0) twice in two consecutive write operations. Write 1 to Register 0x00, Bit 15. Write 0 to the FIFO_ACCESS_ENA bit (Register 0x5F, Bit 0). Reading Data from Registers Using Interrupts The latest sample data is always available in the data registers and is updated simultaneously at the end of each time slot. The data value for each photodiode channel is available as a 16-bit value in Register 0x64 through Register 0x67 for Time Slot A, and Register 0x68 through Register 0x6B for Time Slot B. If allowed to reach their maximum value, Register 0x64 through Register 0x6B clip. If Register 0x64 through Register 0x6B saturate, the unsaturated (up to 27 bits) values for each channel are available in Register 0x70 through Register 0x77 for Time Slot A and Register 0x78 through Register 0x7F for Time Slot B. Sample interrupts are available to Rev. B | Page 25 of 52 ADPD103 Data Sheet indicate when the registers are updated and can be read. To use the interrupt for a given time slot, use the following procedure: 1. 2. 3. 4. Enable the sample interrupt by writing a 0 to the appropriate bit in Register 0x01. To enable the interrupt for Time Slot A, write 0 to Bit 5. To enable the interrupt for Time Slot B, write 0 to Bit 6. Either or both interrupts can be set. Configure the interrupt pin by writing the appropriate value to the bits in Register 0x02. An interrupt generates when the data registers are updated. The interrupt handler must perform the following: a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm which interrupt has occurred. This step is not required if only one interrupt is in use. b. Read the data registers before the next sample can be written. The system must have interrupt latency and service time short enough to respond before the next data update, based on the output data rate. c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the interrupt. If both time slots are in use, it is possible to use only the Time Slot B interrupt to signal when all registers can be read. It is recommended to use the multiword read to transfer the data from the data registers. Reading Data from Registers Without Interrupts Heart rate monitoring applications require an accurate time base to achieve an accurate count of beats per minute. The ADPD103 provides a simple calibration procedure for both clocks. 1. 2. If the system interrupt response is not fast or predictable enough to use the interrupt method, or if the interrupt pin is not used, it is possible to get reliable data access by using the data hold mechanism. To guarantee that the data read from the registers is from the same sample time, it is necessary to prevent the update of samples while reading the current values. The method for doing register reads without interrupt timing is as follows: 1. 2. 3. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the time slot requiring access (both time slots can be accessed). This prevents sample updates. Read the registers as desired. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively) previously set. Sample updates are allowed again. Because a new sample may arrive while the reads are occurring, this method prevents the new sample from partially overwriting the data being read. CLOCKS AND TIMING CALIBRATION The ADPD103 operates using two internal time bases: a 32 kHz clock sets the sample timing, and a 32 MHz clock controls the timing of the internal functions such as LED pulsing and data capture. Both clocks are internally generated and exhibit deviceto-device variation of approximately 10% (typical). Calibrating the 32 kHz clock. This calibrates items associated with the output data rate. Calibration of this clock is important for applications where an accurate data rate is important, such as heart rate measurements. a. Set the sampling frequency to the highest the system can handle, such as 2000 Hz. Because the 32 kHz clock controls sample timing, its frequency is readily accessible via the INT pin. Configure the interrupt by writing the appropriate value to the bits in Register 0x02 and set the interrupt to occur at the sampling frequency by writing 0 to Register 0x01, Bit 5 or Bit 6. Monitor the INT pin. The interrupt frequency must match the set sample frequency. b. If the monitored interrupt frequency is less than the set sampling frequency, increase the CLK32K_ADJUST bit (Register 0x4B, Bits[5:0]). If the monitored interrupt frequency is larger than the set sampling frequency, decrease the CLK32K_ADJUST bits. c. Repeat Step b until the monitored interrupt signal frequency is close enough to the set sampling frequency. Calibrate the 32 MHz clock. This calibrates items associated with the fine timing within a sample period, such as LED pulse width and spacing, assuming that the 32 kHz clock has been calibrated. a. Write 0x1 to Register 0x5F, Bit 0. b. Enable the CLK_RATIO calculation by writing 0x1 to Register 0x50, Bit 5. This function counts the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. With this function enabled, this cycle value is stored in Register 0xA, Bits[11:0] and nominally this ratio is 2000 (0x7D0). c. Calculate the 32 MHz clock error as follows: Clock Error = 32 MHz x (1 - CLK_RATIO/2000) d. Adjust the frequency by setting Bits[7:0] in Register 0x4D per the following equation: CLK32M_ADJUST = Clock Error/109 kHz e. Write 0x0 to Register 0x50, Bit 5 to reset the CLK_RATIO function. Repeat Step 2b through Step 2e until the desired accuracy is achieved. Write 0x0 to Register 0x5F, Bit 0. Also, set the INT pin back to the mode desired for normal operation. Rev. B | Page 26 of 52 Data Sheet ADPD103 CALCULATING CURRENT CONSUMPTION The current consumption of the ADPD103 depends on the user selected operating configuration, as described in the following equations. where LEDAPEAK is LED1PEAK, LED2PEAK, or LED3PEAK, expressed in mA, for whichever LED is selected for Time Slot A. Average VLEDB Supply Current To calculate the average VLEDB supply current, use Equation 9. Total Power Consumption ILED_AVG_B = (SLOTB_LED_WIDTH/1 x 106) x LEDBPEAK x DR x PULSE_COUNT (9) To calculate the total power consumption, use Equation 4. Total Power = IVDD _ AVG x VDD + I LEDA _ AVG x VLEDA + (4) I LEDB _ AVG x VLEDB where LEDBPEAK is LED1PEAK, LED2PEAK, or LED3PEAK, expressed in mA, for whichever LED is selected for Time Slot B. Average VDD Supply Current OPTIMIZING SNR PER WATT To calculate the average VDD supply current, use Equation 5. The ADPD103 offers a variety of parameters that the user can adjust to achieve the best signal. One of the key goals of system performance is to obtain the best system SNR for the lowest total power. This is often referred to as optimizing SNR/watt. Even in systems where only the SNR matters and power is a secondary concern, there may be a lower power or a high power means of achieving the same SNR. IVDD _ AVG = DR x (( I AFE _ A x t SLOTA ) + ( I AFE _ B x t SLOTB ) (5) + QPROC ) + IVDD _ STANDBY where: DR = the data rate in Hz. IVDD_STANDBY = 3.5 x 10-3 mA. QPROC is an average charge associated with a processing time, as follows: * * * Only Time Slot A enabled: QPROC = 0.64 x 10 mC Only Time Slot B enabled: QPROC = 0.51 x 10-3 mC Time Slot A and Time Slot B enabled: QPROC = 0.69 x 10-3 mC -3 I AFE _ x (mA) = 2.9 + (1.5 x NUM _ CHANNELS) + (6) (LEDx PEAK - 25) / 225 t SLOTx (sec) = LEDx _ OFFSET + LEDx _ PERIOD x (7) PULSE _ COUNT where: NUM_CHANNELS is the number of active channels. LEDxPEAK is the peak LED current expressed in mA. LEDx_OFFSET is the pulse start time offset expressed in seconds. LEDx_PERIOD is the pulse period expressed in seconds. PULSE_COUNT is the number of pulses. Note that if either Time Slot A or Time Slot B are disabled, IAFE_x = 0 for that respective time slot. Additionally, if operating in digital integrate mode, power savings can be realized by setting Register 0x3C, Bits[8:3] = b010010. This setting disables the band-pass filters that are bypassed in digital integrate mode, changing the AFE power contribution calculation to: I AFE _ x ( mA) = 2.9 + (1.0 x NUM _ CHANNELS ) + ( LEDx PEAK - 25) / 225 Average VLEDA Supply Current To calculate the average VLEDA supply current, use Equation 8. ILED_AVG_A = (SLOTA_LED_WIDTH/1 x 106) x LEDAPEAK x DR x PULSE_COUNT (8) Optimizing for Peak SNR The first step in optimizing for peak SNR is to find a TIA gain and LED level that gives the best performance where the number of LED pulses remains constant. If peak SNR is the goal, the noise section of Table 3 can be used as a guide. It is important to note that the SNR improves as a square root of the number of pulses averaged together, whereas the increase in the LED power consumed is directly proportional to the number of LED pulses. In other words, for every doubling of the LED pulse count, there is a doubling of the LED power consumed and a 3 dB SNR improvement. As a result, avoid any change in the gain configuration that provides less than 3 dB of improvement for a 2x power penalty; any TIA gain configuration that provides more than 3 dB of improvement for a 2x power penalty is a good choice. If peak SNR is the goal and there is no issue saturating the photodiode with LED current at any gain, the 50k TIA gain setting is an optimal choice. After the SNR per pulse per channel is optimized, the user can then increase the number of pulses to achieve the desired system SNR. Optimizing SNR per Watt in a Signal Limited System In practice, optimizing for peak SNR is not always practical. One scenario in which the photoplethysmography (PPG) signal has a poor SNR is the signal limited regime. In this scenario, the LED current reaches an upper limit before the desired dc return level is achieved. Tuning in this case starts where the peak SNR tuning stops. The starting point is nominally a 50k gain, as long as the lowest LED current setting of 8 mA does not saturate the photodiode and the 50k gain provides enough protection against intense background light. In these cases, use a 25k gain as the starting point. The goal of the tuning process is to bring the dc return signal to a specific ADC range, such as 50% or 60%. The ADC range Rev. B | Page 27 of 52 ADPD103 Data Sheet choice is a function of the margin of headroom needed to prevent saturation as the dc level fluctuates over time. The SNR of the PPG waveform is always some percentage of the dc level. If the target level cannot be achieved at the base gain, increase the gain and repeat the procedure. The tuning system may need to place an upper limit on the gain to prevent saturation from ambient signals. Tuning the Pulse Count After the LED peak current and TIA gain are optimized, increasing the number of pulses per sample increases the SNR by the square root of the number of pulses. There are two ways to increase the pulse count. The pulse count registers (Register 0x31, Bits[15:8], and Register 0x36, Bits[15:8]) change the number of pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8], controls the number of internal samples that are averaged together before the data is sent to the output. Therefore, the number of pulses per sample is the pulse count register multiplied by the number of subsequent samples being averaged. In general, the internal sampling rate increases as the number of internal sample averages increase to maintain the desired output data rate. The SNR/watt is most optimal with pulse count values of 16 or less. Above pulse count values of 16, the square root relationship does not hold in the pulse count register. However, this relationship continues to hold when averaged between samples using Register 0x15. Note that increasing LED peak current increases SNR almost directly proportional to LED power, whereas increasing the number of pulses by a factor of n results in only a nominal(n) increase in SNR. When using the sample sum/average function (Register 0x15), the output data rate decreases by the number of summed samples. To maintain a static output data rate, increase the sample frequency (Register 0x12) by the same factor as that selected in Register 0x15. For example, for a 100 Hz output data rate and a sample sum/average of four samples, set the sample frequency to 400 Hz. SINGLE AFE CHANNEL MODE When using a single photodiode in an application, and that photodiode is connected to a single AFE channel (see Table 16), the ADPD103 has an option to power down Channel 2, Channel 3, and Channel 4, which places the device in single AFE channel mode. Because three of the four AFE channels are turned off in this mode, the power consumption is considerably reduced. It is important to leave the unused input channels floating for proper device operation. To run the device in single AFE channel mode, write 0x38 to Register 0x3C, Bits[8:3]. If it is not required to run the device in single AFE channel mode, leave Register 0x3C, Bits[8:3] at 0x00. TIA_ADC MODE There is a way to put the device into a mode that effectively runs the TIA directly in the ADC without using the analog band-pass filter and integrator. This mode is referred to as TIA_ADC mode. There are two basic applications of TIA_ADC mode. In normal operation, all of the background light is blocked from the signal chain, and therefore cannot be measured. TIA_ADC mode can be used to measure the amount of background/ambient light. This mode can also be used to measure other dc input currents, such as leakage resistance. When the device is in TIA_ADC mode, the band-pass filter and the integrator stage are bypassed. This effectively wires the TIA directly into the ADC. At the set sampling frequency, the ADC samples Channel 1 through Channel 4 (or Channel 5 through Channel 8) in sequential order, and each sample is taken at 1 s intervals. The TIA is in an inverting configuration; therefore, the signal drops as more light hits the photodiode. Zero light or dark conditions result in approximately 13,000 LSBs from the ADC. To put the ADPD103 in TIA_ADC mode during Time Slot A, write 0xB065 to Register 0x43 to bypass the band-pass filter and integrator. Similarly, to place the ADPD103 in TIA_ADC mode during Time Slot B, write 0xB065 to Register 0x45. One way to monitor dc and pulsed signal at the same time is to operate TIA_ADC mode in one time slot and pulse mode in the other time slot. In TIA_ADC mode, increasing light level causes a decrease in ADC codes because the TIA stage is inverting. Protecting Against TIA Saturation in Normal Operation One of the reasons to monitor TIA_ADC mode is to protect against environments that may cause saturation. One concern when operating in high light conditions, especially with larger photodiodes, is that the TIA stage may become saturated and the ADPD103 continues to communicate data. The resulting saturation is not typical. The TIA, based on its settings, can only handle a certain level of photodiode current. Based on the way the ADPD103 is configured, if there is a current level from the photodiode that is larger than the TIA can handle, the TIA output during the LED pulse effectively extends the current pulse, making it wider. The AFE timing is then violated because the positive portion of the band-pass filter output extends into the negative section of the integration window. Thus, the photosignal is subtracted from itself, causing the output signal to decrease when the effective light signal increases. To measure the response from the TIA and verify that this stage is not saturating, place the device in TIA_ADC mode and slightly modify the timing. Specifically, sweep SLOTx_AFE_OFFSET until two or three of the four channels reach a minimum value (note that TIA is in an inverting configuration). All four channels do not reach this minimum value because, typically, 3 s LED pulse widths are used and the ADC samples the four channels sequentially at 1 s intervals. This procedure aligns the ADC Rev. B | Page 28 of 52 Data Sheet ADPD103 sampling time with the LED pulse to measure the total amount of light falling on the photodetector (for example, background light + LED pulse). If this minimum value is above 0 LSB, the TIA is not saturated. However, take care, because even if the result is not 0 LSB, operating the device near saturation can quickly result in saturation if light conditions change. A safe operating region is typically at 3/4 full scale and lower. Use Table 17 to determine how the input codes map to ADC levels on a per channel per pulse basis. These codes are not the same as in normal mode because the band-pass filter and integrator are not unity-gain elements. Coarse Ambient Light Measurement Using the typical values in Table 17, TIA_ADC mode can be used to measure or quantify the amount of background or ambient light present on the photodetector. The settings are the same in the method described in the Protecting Against TIA Saturation in Normal Operation section, except the timing used in the normal operating mode is sufficient for this mode. There is no need to sweep AFE_OFFSET. If AFE_OFFSET is in the same place as the normal mode operation, the TIA_ADC mode does not return the same value, regardless of whether the LED is on or off. In TIA_MODE, the dark level is a high level near 13,000 LSBs per channel per pulse (see Table 17). To measure this value, select no PD by writing a 0x0 to Register 0x14, Bits[11:8] for Time Slot B or Register 0x14, Bits[7:4] for Time Slot A. This setting internally opens the photodiode connection. This gives a baseline LSB value that coincides with a zero signal input. After Register 0x14 is restored to its normal value, while connecting the photodiode to the TIA, this TIA_ADC result can be subtracted from the open photodiode case to yield a background light measurement. Use Table 17 to translate this measurement into an input photocurrent. Use this result for coarse absolute measurements only, because it is typically only accurate to within 10%. Measuring PCB Parasitic Input Resistance During the process of mounting the ADPD103, undesired resistance can develop on the inputs through assembly errors or debris on the PCB. These resistances can form between the anode and cathode, or between the anode and some other supply or ground. In normal operation, the ambient rejection feature of the ADPD103 masks the primary effects of these resistances, making it very difficult to detect them. However, even at 1 M to 10 M, such resistance can impact performance significantly through added noise or decreased dynamic range. TIA_ADC mode can be used to screen for these assembly issues. Measuring Shunt Resistance on the Photodiode A shunt resistor across the photodiode does not generally affect the output level of the device in operation because the effective impedance of the TIA is very low. This is especially true if the photodiode is held to 0 V in operation. However, such resistance can add noise to the system, degrading performance. The best way to detect photodiode leakage, also called photodiode shunt resistance, is to place the device in TIA_ADC mode in the dark and vary the operation mode cathode voltage. When the cathode is at 1.3 V, this places 0 V across the photodiode because the anode is always at 1.3 V while in operation. When the cathode is at 1.8 V, this places 0.5 V across the photodiode. Using the register settings in Table 3 to control the cathode voltage, measure the TIA_ADC value at both voltages. Next, divide the voltage difference of 0.5 V by the difference of the ADC result after converting it to a current. This result is the approximate shunt resistance. Values greater than 10 M may be difficult to measure, but this method is useful in identifying gross failures. Table 17. Analog Specifications for TIA_ADC and Digital Integrate Modes Parameter TIA_ADC/Digital Integration Saturation Levels TIA_ADC Resolution Output with No Input Current Test Conditions/Comments Values expressed per channel, per sample TIA Feedback Resistor: 25 k 50 k 100 k 200 k Values expressed per channel, per sample TIA Feedback Resistor: 25 k 50 k 100 k 200 k ADC offset (Register 0x18 to Register 0x21) = 0x0 Rev. B | Page 29 of 52 Typ Unit 38.32 19.16 9.58 4.79 A A A A 2.92 1.5 0.73 0.37 13000 nA/LSB nA/LSB nA/LSB nA/LSB LSB ADPD103 Data Sheet Measuring TIA Input Shunt Resistance Another problem that can occur is for a resistance to develop between the TIA input and another supply or ground on the PCB. These resistances can force the TIA into saturation prematurely. This, in turn, takes away dynamic range from the device in operation and adds a Johnson noise component to the input. To measure these resistances, place the device in TIA_ADC mode in the dark and start by measuring the TIA_ADC offset level with the photodiode inputs disconnected (Register 0x14, Bits[11:8] = 0 or Register 0x14, Bits[7:4] = 0). From this, subtract the value of TIA_ADC mode with the darkened photodiode connected and convert the difference into a current. If the value is positive, and the ADC signal decreased, the resistance is to a voltage higher than 1.3 V, such as VDD. Current entering the TIA causes the output to drop. If the output difference is negative due to an increase of codes at the ADC, current is being pulled out of the TIA and there is a shunt resistance to a lower potential than 1.3 V, such as ground. DIGITAL INTEGRATE MODE Digital integrate mode is built into the ADPD103 and allows the device to accommodate longer LED/AFE pulse widths and different types of sensors at the input. The analog integration mode described in the AFE Operation section is ideally suited for applications requiring a large LED duty cycle, or applications that require customization of the sampling scheme. Digital integrate mode allows the integration function to be performed after the ADC in the digital domain. This mode enables the device to handle a much wider range of sensors at the input. In digital integrate mode, the ADC performs a conversion every 1 s during the integration window. During the integration window, the digital engine either adds to or subtracts from the previous sample. The band-pass filter is bypassed and the integrator is converted to a voltage buffer, allowing the digital engine to perform the integration function. In this mode, after the timing is optimized, the output of the ADC increases as the light level on the photodiode increases. The integration window is a combination of negative and positive windows where the duration of these windows is set by SLOTx_ AFE_WIDTH. At the end of the digital integration window, the resulting sum is sent to the decimate unit as the sample for that LED pulse. There is one sample per time slot for every sample cycle. Table 18 lists the registers required for placing the device in digital integrate mode. There may also be changes needed in the SLOTx_AFE_OFFSET registers and FIFO configuration register (0x11). To read the final value through the FIFO, set the appropriate values in Register 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. Alternatively, the final output is also available through the data registers; Register 0x64, Register 0x70, and Register 0x74 for Time Slot A, and Register 0x68, Register 0x78, and Register 0x7C for Time Slot B. To put the ADPD103 into digital integration mode during Time Slot A, write 0x1 to Register 0x58, Bit 12. To put the ADPD103 into digital integration mode in Time Slot B, write 0x1 to Register 0x58, Bit 13. The other writes required to switch to digital integration mode are listed in Table 18. When using digital integrate mode, up to two photodiodes can be connected to the ADPD103 inputs; one photodiode per PDx input group (PD1/PD2/PD3/PD4 or PD5/PD6/PD7/PD8). Never connect the same photodiode across the two PDx groups. In digital integrate mode, there are options to connect the photodiode to all four AFE channels (PD1/PD2/PD3/PD4 or PD5/PD6/PD7/PD8), or just a single AFE channel (PD1 or PD5). When connecting to a single AFE channel, write 0x1 to Register 0x54, Bit 14 for Time Slot A, or, for Time Slot B, write 0x1 to Register 0x54, Bit 15. When connecting to a single AFE channel, there is also an option to turn off Channel 2, Channel 3, and Channel 4 (and to save power) by writing 0x7 to Register 0x55, Bits[15:13]. When connecting to all four channels (PD1/PD2/PD3/PD4 or PD5/PD6/PD7/PD8), write 0x0 (default)to Register 0x54, Bit 14 for Time Slot A, or write 0x0 (default) to Register 0x54, Bit 15 for Time Slot B. Ensure that all AFE channels are powered up by writing 0x0 to Register 0x55, Bits[15:13]. Connecting the single photodiode to a single AFE channel offers the best SNR performance in cases where signal is limited, whereas connecting the single photodiode to all four AFE channels offers the best dynamic range in cases where signal is large. Digital Integration Sampling Modes There are two sampling modes that can be used while the device is in digital integration mode. These modes are singlesample pair mode and double-sample pair mode. In single-sample pair mode, there is a single negative sample region and a single positive sample region, shown in Figure 29 and Figure 30. To use single-sample pair mode, write 0x1 to Register 5A, Bit 5 for Time Slot A, or Register 5A, Bit 6 for Time Slot B. The negative sample region starts at SLOTx_AFE_ OFFSET + 9 and its duration (the number of samples taken) is set by SLOTx_AFE_WIDTH. The positive sample region starts at SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH, and its duration is also set by SLOTx_AFE_WIDTH. Set the timing such that the negative sample region falls entirely in the flat (dark) portion of the LED response, whereas the positive sample region falls in the pulsed region of the LED response. Placing the LED pulse offset, SLOTx_LED_OFFSET, at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH achieves this timing. The output is the difference of the signals in the two regions. Rev. B | Page 30 of 52 Data Sheet ADPD103 Double-sample pair mode is another way to sample. In this mode, there are two negative sample regions and one long positive sample region (see Figure 27 and Figure 28). To use double-sample pair mode, write 0x0 to Register 0x5A, Bit 5 for Time Slot A, or Bit 6 for Time Slot B. The first negative sample region starts at SLOTx_AFE_OFFSET + 9 and its duration is set by SLOTx_AFE_WIDTH. The positive sample region starts at SLOTx_AFE_OFFSET + 9+ SLOTx_AFE_WIDTH and its duration is twice the SLOTx_AFE_WIDTH. After this, there is another negative sample region that starts at SLOTx_AFE_OFFSET + 9+ 3 x SLOTx_AFE_WIDTH, and its duration is SLOTx_AFE_ WIDTH. Set the timing such that both of the negative sample regions fall in the flat (dark) portion of the LED response and the positive sample region falls in the pulsed portion of the LED response. Placing the LED pulse offset, SLOTx_LED_OFFSET at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_ WIDTH achieves this timing. The output is calculated by summing the response of all the regions in a negative/positive/ negative manner. The double-sample pair mode is useful for cases when the background light is not constant because it has better background rejection, but it also uses more power than singlesample pair mode. Sample Timing Modes There are two options for timing the sample regions: gapped mode and continuous mode. In gapped timing mode, there is a space between the negative and positive sample regions. The width of this region is specified by SLOTA_AFE_FOFFSET for Time Slot A and SLOTB_AFE_ FOFFSET for Time Slot B in microseconds. To enable this feature, write 0x1 to Register 0x5A, Bit 7. This bit enables gapped timing for the time slot (or time slots) that are in digital integrate mode. This mode is helpful when there are unwanted transients in the LED response that must be ignored for an accurate output. If there are no concerns about LED response transients, select continuous timing mode. In this mode, there is no space between the negative and positive sample regions. Write 0x0 to Register 0x5A, Bit 7 for continuous timing of the sample regions. Both gapped and continuous sample timing modes can be used with single-sample pair or double-sample pair mode. Some example timing diagrams are shown in Figure 27, Figure 28, Figure 29, and Figure 30. Background Values In digital integrate mode, the digital integration background value, DI_BACKGROUND, or dark values are also stored and available as output data. This is in addition to the output value during the LED pulse, DI_OUTPUT, which has the dark value subtracted. DI_BACKGROUND is the sum of the negative region samples. To include these values in the FIFO, set Register 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. For 16-bit data, set this value to 0x3; for 32-bit data, set this value to 0x04. These settings are also available through the data registers; Register 0x65, Register 0x71, and Register 0x75 for Time Slot A, and Register 0x69, Register 0x79, and Register 0x7D for Time Slot B. It is recommended that the channel offsets (Register 0x18 to Register 0x21) be set to 0x1F00 when including the background values in the FIFO in digital integration mode. These channel offsets do not affect the sample values, but do provide more headroom for the background values. Saturation Detection in Digital Integrate Mode In normal operation, when using the band-pass filter and the integrator, the ADC almost always saturates before the TIA. Unlike in normal operation, saturation of the TIA or the ADC cannot be detected solely by looking at the signal value where the signal value is the positive sample region minus the reference region in digital integrate mode. This is because the integrated value does not by itself contain any information indicating if one of the ADC conversions during the integration period exceeded the ADC output range. As a result, the realtime output may have saturated only for a fraction of the ADC conversions within a sample and the final accumulated sum may not reflect this. To detect TIA saturation in digital integration mode, both the background values, DI_BACKGROUND, and the signal values, DI_OUTPUT, must be collected. Refer to the Background Values section for the correct settings for Register 0x11 that provide these values. For single-sample pair mode, saturation has occurred when (DI_OUTPUT/(min(LED_WIDTH, AFE_WIDTH)) + DI_BACKGROUND/AFE_WIDTH)/NUM_PULSES > 0x3FFF For double-sample pair mode, saturation has occurred when Rev. B | Page 31 of 52 (DI_OUTPUT/(min(LED_WIDTH, 2 x AFE_WIDTH)) + DI_BACKGROUND/(2 x AFE_WIDTH))/NUM_PULSES > 0x3FFF ADPD103 Data Sheet LED SLOTx_AFE_OFFSET + 9 SUB ADD SUB 12722-021 SAMPLE Figure 27. Digital Integration Mode in Double-Sample Pair Mode with Continuous Sample Timing LED SAMPLE SUB ADD AFE_FOFFSET SUB AFE_FOFFSET 12722-022 SLOTx_AFE_OFFSET + 9 Figure 28. Digital Integration Mode in Double-Sample Pair Mode with Gapped Sample Timing LED SAMPLE SUB ADD AFE_FOFFSET 12722-023 SLOTx_AFE_OFFSET + 9 Figure 29. Digital Integration Mode in Single-Sample Pair Mode with Gapped Sample Timing LED SLOTx_AFE_OFFSET + 9 SUB ADD Figure 30. Digital Integration Mode in Single-Sample Pair Mode with Continuous Sample Timing Rev. B | Page 32 of 52 12722-024 SAMPLE Data Sheet ADPD103 Table 18. Configuration Registers to Switch Between the Normal Sample Mode, TIA_ADC Mode, and Digital Integration Mode Bit Name SLOTA_AFE_MODE Normal Mode Value 0x1C TIA_ADC Mode Value Not applicable Digital Integration Mode Value 0x1D [15:0] SLOTA_AFE_CFG 0xADA5 0xB065 0xAE65 0x44 [15:8] SLOTB_AFE_MODE 0x1C Not applicable 0x1D 0x45 [15:0] SLOTB_AFE_CFG 0xADA5 0xB065 0xAE65 0x4E [15:0] ADC_TIMING Not applicable 0x0040 0x58 13 SLOTB_DIGITAL_INT_EN Not applicable 0x0 0x0 0x1 12 SLOTA_DIGITAL_INT_EN 0x0 0x0 0x1 [15:0] DIG_INT_CFG Not applicable Not applicable Variable Address 0x42 Data Bits [15:8] 0x43 0x5A Rev. B | Page 33 of 52 Description In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA_ADC mode. Time Slot A AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 bypasses the band-pass filter and the integrator. In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA_ADC mode. Time Slot B AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 bypasses the BPF and the integrator. Set ADC Clock to 1 MHz in TIA_ADC mode. Digital integrate mode enable Time Slot B. 0: disable. 1: enable. Digital integrate mode enable Time Slot A. 0: disable. 1: enable. Configuration of digital integration depends on the use case. This register is ignored for other modes. ADPD103 Data Sheet REGISTER LISTING Table 19. Numeric Register Listing 1 Hex Addr Name Bits 0x00 Status [15:8] [7:0] 0x01 0x02 0x06 0x08 0x09 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SLOTB_ INT SLOTA_INT [15:8] INT_IO_ CTL [15:8] FIFO_ THRESH [15:8] [7:0] Reserved[7:0] DEVID [15:8] REV_NUM[15:8] [7:0] DEV_ID[7:0] I2CS_ID Reserved[15:9] Reserved SLOTB_INT_ SLOTA_INT_ MASK MASK 0x0D 0x0F 0x10 CLK_ RATIO Reserved[7:3] INT_ENA Reserved[15:14] 0x12 FSAMPLE [15:8] [7:0] 0x15 0x18 0x19 0x1A 0x1B 0x1E 0x1F 0x20 0x21 0x0416 R 0x00C8 R/W 0x0000 R 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x1000 R/W 0x0028 R/W 0x0541 R/W 0x0600 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 RW SLAVE_ADDRESS_KEY[15:8] SLAVE_ADDRESS_KEY[7:0] Reserved[15:8] Reserved[7:1] SW_RESET Reserved[15:8] Reserved[7:2] Reserved[15:14] RDOUT_M ODE SLOTB_FIFO_MODE[7:6] SLOTB_EN Mode[1:0] FIFO_OVRN_ PREVENT Reserved[11:9] SLOTA_FIFO_MODE[4:2] SLOTB_FIFO_ MODE Reserved SLOTA_EN FSAMPLE[15:8] FSAMPLE[7:0] PD_LED_ [15:8] SELECT [7:0] Reserved[15:12] SLOTA_PD_SEL[7:4] SLOTB_PD_SEL[11:8] SLOTB_LED_SEL[3:2] NUM_ AVG [15:8] SLOTA_ CH1_ OFFSET [15:8] SLOTA_CH1_OFFSET[15:8] [7:0] SLOTA_CH1_OFFSET[7:0] SLOTA_ CH2_ OFFSET [15:8] SLOTA_CH2_OFFSET[15:8] [7:0] SLOTA_CH2_OFFSET[7:0] SLOTA_ CH3_ OFFSET [15:8] SLOTA_CH3_OFFSET[15:8] [7:0] SLOTA_CH3_OFFSET[7:0] SLOTA_ CH4_ OFFSET [15:8] SLOTA_CH4_OFFSET[15:8] [7:0] SLOTA_CH4_OFFSET[7:0] SLOTB_ CH1_ OFFSET [15:8] SLOTB_CH1_OFFSET[15:8] [7:0] SLOTB_CH1_OFFSET[7:0] SLOTB_ CH2_ OFFSET [15:8] SLOTB_CH2_OFFSET[15:8] [7:0] SLOTB_CH2_OFFSET[7:0] SLOTB_ CH3_ OFFSET [15:8] SLOTB_CH3_OFFSET[15:8] [7:0] SLOTB_CH3_OFFSET[7:0] SLOTB_ CH4_ OFFSET [15:8] SLOTB_CH4_OFFSET[15:8] [7:0] SLOTB_CH4_OFFSET[7:0] [7:0] R/W CLK_RATIO[11:8] [7:0] 0x14 0x0000 CLK_RATIO[7:0] [7:0] SLOT_EN [15:8] R/W Reserved Reserved[15:12] [7:0] 0x11 0x0000 INT_POL ADDRESS_WRITE_KEY[15:8] SLAVE_ [15:8] ADDRESS [7:0] _KEY [15:8] INT_DRV FIFO_THRESH[13:8] [7:0] Mode R/W SLAVE_ADDRESS[7:1] [15:8] [15:8] FIFO_INT_MASK 0x00FF Reserved[4:0] [15:8] SW_ RESET R/W Reserved[15:8] [7:0] [7:0] 0x0A RW 0x0000 Reserved[4:0] INT_ MASK [7:0] Reset FIFO_SAMPLES[15:8] Reserved Reserved SLOTA_LED_SEL[1:0] SLOTB_NUM_AVG SLOTA_NUM_AVG Reserved Rev. B | Page 34 of 52 Data Sheet Hex ADPD103 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr Name Bits 0x22 ILED3_ COARSE [15:8] 0x23 ILED1_ COARSE 0x24 ILED2_ COARSE [15:8] 0x25 ILED_ FINE [15:8] SLOTA_ LED_ PULSE [15:8] [7:0] SLOTA_LED_OFFSET[7:0] SLOTA_ NUMPULSES [15:8] SLOTA_LED_NUMBER[15:8] [7:0] SLOTA_LED_PERIOD[7:0] [7:0] [15:8] [7:0] [7:0] 0x30 0x31 [7:0] Reserved[15:14] ILED3_ SCALE Reserved Reserved[12:8] ILED3_SLEW[6:4] Reserved[15:14] Reserved[12:8] ILED1_SLEW[6:4] Reserved[15:14] Reserved[12:8] ILED2_SLEW[6:4] ILED2_FINE[10:8] Reserved Reserved[15:13] SLOTA_LED_WIDTH[12:8] LED_ [15:8] DISABLE 0x35 SLOTB_ LED_ PULSE Reserved[15:10] [15:8] [7:0] SLOTB_LED_OFFSET[7:0] SLOTB_ NUMPULSES [15:8] SLOTB_LED_NUMBER[15:8] [7:0] SLOTB_LED_PERIOD[7:0] [7:0] SLOTA_ [15:8] AFE_ [7:0] WINDOW Reserved EXT_SYNC_ ENA Reserved[13:8] SLOTA_AFE_OFFSET[10:5] SLOTB_ [15:8] AFE_ [7:0] WINDOW SLOTB_AFE_OFFSET[10:5] [7:0] 0x42 SLOTA_ [15:8] TIA_CFG [7:0] 0x44 0x45 0x4B 0x4D 0x4E Reserved[15:14] 0x4F SLOTA_AFE_OFFSET[10:8] SLOTB_AFE_OFFSET[10:8] Reserved AFE_POWERDOWN[7:3] V_ CATHODE AFE_ POWER-DOWN 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x0320 R/W 0x0818 R/W 0x000 R/W 0x22FC R/W 0x22FC R/W 0x3006 R/W 0x1C38 R/W 0xADA5 R/W 0x1C38 R/W 0xADA5 R/W 0x2612 R/W 0x425E R/W 0x0060 R/W 0x2090 R/W Reserved[2:0] SLOTA_AFE_MODE[15:8] Reserved Reserved[5:2] (write 0xD) SLOTA_ TIA_ IND_EN SLOTA_TIA_GAIN[1:0] SLOTA_AFE_CFG[15:8] SLOTA_AFE_CFG[7:0] SLOTB_AFE_MODE[15:8] Reserved Reserved[5:2] (write 0xD) SLOTB_ TIA_ IND_EN SLOTB_TIA_GAIN[1:0] SLOTB_AFE_CFG[15:8] SLOTB_AFE_CFG[7:0] SAMPLE_ [15:8] CLK [7:0] CLK32K_EN Reserved[15:8] Reserved CLK32K_ADJUST[5:0] CLK32M_ [15:8] ADJUST [7:0] RESERVED[15:8] CLK32M_ADJUST[7:0] [15:8] ADC_CLOCK[15:8] [7:0] ADC_CLOCK[7:0] EXT_ [15:8] SYNC_SEL [7:0] R/W SLOTB_AFE_FOFFSET[4:0] Reserved[13:11] SLOTB_ [15:8] AFE_CFG [7:0] ADC_ CLOCK 0x630C SLOTA_AFE_FOFFSET[4:0] SLOTB_AFE_WIDTH[15:11] SLOTA_ [15:8] AFE_CFG [7:0] SLOTB_ [15:8] TIA_CFG [7:0] R/W Reserved[7:0] SLOTA_AFE_WIDTH[15:11] [7:0] 0x43 SLOTA_ LED_DIS SLOTB_LED_WIDTH[12:8] 0x39 AFE_PWR [15:8] _CFG1 0x3000 Reserved[7:0] TIMING_ [15:8] CFG 0x3C SLOTB_LED_ DIS Reserved[15:13] 0x38 0x3B R/W ILED1_FINE[4:0] 0x34 0x36 0x3000 ILED2_COARSE[3:0] ILED3_FINE[15:11] ILED2_FINE[7:6] R/W ILED1_COARSE[3:0] ILED2_ SCALE Reserved RW 0x3000 ILED3_COARSE[3:0] ILED1_ SCALE Reserved Reset Reserved[15:8] Reserved PDSO_ OE PDSO_IE Reserved EXT_SYNC_SEL[3:2] Rev. B | Page 35 of 52 INT_IE Reserved ADPD103 Data Sheet Hex Addr Name 0x50 CLK32M_ [15:8] CAL_EN [7:0] 0x54 Bits AFE_PWR [15:8] _CFG2 [7:0] 0x55 TIA_INDEP_ GAIN [15:8] [7:0] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SLOTB_SINGLE_CH_ DIG_INT PDSO_ CTRL SLOTA_ SINGLE_ CH_DIG_ INT DIG_INT_ [15:8] CFG [7:0] DIG_INT_ GAPMODE Reserved[15:14] 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 Reserved SLOTA_TIA_GAIN_4[5:4] SLOTB_ DIGITAL_ INT_EN [7:0] 0x64 SLOTA_V_CATHODE[9:8] 0x0020 R/W SLOTB_TIA_GAIN_4 [11:10] SLOTB_TIA_GAIN_3[9:8] 0x0000 R/W SLOTA_TIA_GAIN_3[3:2] SLOTA_TIA_GAIN_2[1:0] 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Reserved[4:0] SLEEP_V_CATHODE[13:12] DIGINT_POWER[15:13] 0x5A 0x60 R/W SLOTB_V_ CATHODE[11:10] Reserved[6:0] SLOTB_TIA_GAIN_2[7:6] DIGITAL_ [15:8] INT_EN DATA_AC [15:8] CESS_ [7:0] CTL RW 0x0000 CLK32M_ CAL_EN REG54_VCAT_ ENABLE 0x58 0x5F Reset Reserved[15:8] Reserved[11:8] SLOTA_ DIGITAL_INT_ EN Reserved[7:0] Reserved[15:8] SLOTB_ DIG_INT_ SAMPLEMODE Reserved[4:0] SLOTA_ DIG_INT_ SAMPLEMODE Reserved[15:8] Reserved[7:3] SLOTB_ DATA_ HOLD FIFO_ ACCESS [15:8] FIFO_DATA[15:8] [7:0] FIFO_DATA[7:0] SLOTA_ PD1_ 16BIT [15:8] SLOTA_CH1_16BIT[15:8] [7:0] SLOTA_CH1_16BIT[7:0] SLOTA_ PD2_ 16BIT [15:8] SLOTA_CH2_16BIT[15:8] [7:0] SLOTA_CH2_16BIT[7:0] SLOTA_ PD3_ 16BIT [15:8] SLOTA_CH3_16BIT[15:8] [7:0] SLOTA_CH3_16BIT[7:0] SLOTA_ PD4_ 16BIT [15:8] SLOTA_CH4_16BIT[15:8] [7:0] SLOTA_CH4_16BIT[7:0] SLOTB_ PD1_ 16BIT [15:8] SLOTB_CH1_16BIT[15:8] [7:0] SLOTB_CH1_16BIT[7:0] SLOTB_ PD2_ 16BIT [15:8] SLOTB_CH2_16BIT[15:8] [7:0] SLOTB_CH2_16BIT[7:0] SLOTB_ PD3_ 16BIT [15:8] SLOTB_CH3_16BIT[15:8] [7:0] SLOTB_CH3_16BIT[7:0] SLOTB_ PD4_ 16BIT [15:8] SLOTB_CH4_16BIT[15:8] [7:0] SLOTB_CH4_16BIT[7:0] A_PD1_ LOW [15:8] SLOTA_CH1_LOW[15:8] [7:0] SLOTA_CH1_LOW[7:0] A_PD2_ LOW [15:8] SLOTA_CH2_LOW[15:8] [7:0] SLOTA_CH2_LOW[7:0] A_PD3_ LOW [15:8] SLOTA_CH3_LOW[15:8] [7:0] SLOTA_CH3_LOW[7:0] A_PD4_ LOW [15:8] SLOTA_CH4_LOW[15:8] [7:0] SLOTA_CH4_LOW[7:0] A_PD1_ HIGH [15:8] SLOTA_CH1_HIGH[15:8] [7:0] SLOTA_CH1_HIGH[7:0] Rev. B | Page 36 of 52 SLOTA_DAT A_HOLD DIGITAL_ CLOCK_ENA Data Sheet Hex ADPD103 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr Name Bits 0x75 A_PD2_ HIGH [15:8] SLOTA_CH2_HIGH[15:8] [7:0] SLOTA_CH2_HIGH[7:0] A_PD3_ HIGH [15:8] SLOTA_CH3_HIGH[15:8] [7:0] SLOTA_CH3_HIGH[7:0] A_PD4_ HIGH [15:8] SLOTA_CH4_HIGH[15:8] [7:0] SLOTA_CH4_HIGH[7:0] B_PD1_ LOW [15:8] SLOTB_CH1_LOW[15:8] [7:0] SLOTB_CH1_LOW[7:0] B_PD2_ LOW [15:8] SLOTB_CH2_LOW[15:8] [7:0] SLOTB_CH2_LOW[7:0] B_PD3_ LOW [15:8] SLOTB_CH3_LOW[15:8] [7:0] SLOTB_CH3_LOW[7:0] B_PD4_ LOW [15:8] SLOTB_CH4_LOW[15:8] [7:0] SLOTB_CH4_LOW[7:0] B_PD1_ HIGH [15:8] SLOTB_CH1_HIGH[15:8] [7:0] SLOTB_CH1_HIGH[7:0] B_PD2_ HIGH [15:8] SLOTB_CH2_HIGH[15:8] [7:0] SLOTB_CH2_HIGH[7:0] B_PD3_ HIGH [15:8] SLOTB_CH3_HIGH[15:8] [7:0] SLOTB_CH3_HIGH[7:0] B_PD4_ HIGH [15:8] SLOTB_CH4_HIGH[15:8] [7:0] SLOTB_CH4_HIGH[7:0] 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 1 Reset RW 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Recommended values not shown. Only power-on reset values are in Table 19. The recommended values are largely dependent on use case. See Table 20 to Table 26 for the recommended values. Rev. B | Page 37 of 52 ADPD103 Data Sheet LED CONTROL REGISTERS Table 20. LED Control Registers Address 0x14 0x22 Data Bit [15:12] [11:8] Default Value 0x0 0x5 Access R/W R/W Name Reserved SLOTB_PD_SEL [7:4] 0x4 R/W SLOTA_PD_SEL [3:2] 0x0 R/W SLOTB_LED_SEL [1:0] 0x1 R/W SLOTA_LED_SEL [15:14] 13 0x0 0x1 R/W R/W Reserved ILED3_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED3_SLEW [3:0] 0x0 R/W ILED3_COARSE Description Write 0x0 to these bits for proper operation. PDx connection selection for Time Slot B. See Figure 13. 0x1: All photodiode inputs are connected during Time Slot B. 0x4: PD5/PD6/PD7/PD8 are connected during Time Slot B. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot B. Other: reserved. PDx connection selection for Time Slot A. See Figure 13. 0x1: All photodiode inputs are connected during Time Slot A. 0x4: PD5/PD6/PD7/PD8 are connected during Time Slot A. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot A. Other: reserved. Time Slot B LED configuration. These bits determine which LED is associated with Time Slot B. 0x0: reserved. 0x1: LEDX1 pulses during Time Slot B. 0x2: LEDX2 pulses during Time Slot B. 0x3: LEDX3 pulses during Time Slot B. Time Slot A LED configuration. These bits determine which LED is associated with Time Slot A. 0x0: reserved. 0x1: LEDX1 pulses during Time Slot A. 0x2: LEDX2 pulses during Time Slot A. 0x3: LEDX3 pulses during Time Slot A. Write 0x0. LEDX3 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX3 driver in low power mode. LEDX3 Current Scale = 0.4 + 0.6 x (Register 0x22, Bit 13). Write 0x1. Write 0x0. LEDX3 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. ... 7: the fastest slew rate. LEDX3 coarse current setting. Coarse current sink target value of LEDX3 in standard operation. 0: 25 mA. 1: 40 mA. 2: 55 mA. ... 15: 250 mA. LED3PEAK = LED3COARSE x LED3FINE x LED3SCALE where: LED3PEAK is the LEDX3 peak target value (mA). LED3COARSE = 28 + 15.46 x (Register 0x22, Bits[3:0]). LED3FINE = 0.71 + 0.024 x (Register 0x25, Bits[15:11]). LED3SCALE = 0.4 + 0.6 x (Register 0x22, Bit 13). Rev. B | Page 38 of 52 Data Sheet Address 0x23 0x24 ADPD103 Data Bit [15:14] 13 Default Value 0x0 0x1 Access R/W R/W Name Reserved ILED1_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED1_SLEW [3:0] 0x0 R/W ILED1_COARSE [15:14] 13 0x0 0x1 R/W R/W Reserved ILED2_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED2_SLEW [3:0] 0x0 R/W ILED2_COARSE Description Write 0x0. LEDX1 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX1 driver in low power mode. LEDX1 Current Scale = 0.4 + 0.6 x (Register 0x23, Bit 13). Write 0x1. Write 0x0. LEDX1 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. ... 7: the fastest slew rate. LEDX1 coarse current setting. Coarse current sink target value of LEDX1 in standard operation. 0: 25 mA. 1: 40 mA. 2: 55 mA. ... 15: 250 mA. LED1PEAK = LED1COARSE x LED1FINE x LED1SCALE where: LED1PEAK is the LEDX1 peak target value (mA). LED1COARSE = 28 + 15.46 x (Register 0x23, Bits[3:0]). LED1FINE = 0.71 + 0.024 x (Register 0x25, Bits[4:0]). LED1SCALE = 0.4 + 0.6 x (Register 0x23, Bit 13). Write 0x0. LEDX2 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX2 driver in low power mode. LED2 Current Scale = 0.4 + 0.6 x (Register 0x24, Bit 13) Write 0x1. Write 0x0. LEDX2 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. ... 7: the fastest slew rate. LEDX2 coarse current setting. Coarse current sink target value of LED2 in standard operation. See Register 0x23, Bits[3:0] for values. LED2PEAK = LED2COARSE x LED2FINE x LED2SCALE where: LED2PEAK is the LEDX2 peak target value (mA). LED2COARSE = 28 + 15.46 x (Register 0x24, Bits[3:0]). LED2FINE = 0.71 + 0.024 x (Register 0x25, Bits[10:6]). LED2SCALE = 0.4 + 0.6 x (Register 0x24, Bit 13). Rev. B | Page 39 of 52 ADPD103 Address 0x25 0x30 0x31 0x34 0x35 0x36 0x3C Data Sheet Data Bit [15:11] Default Value 0xC Access R/W Name ILED3_FINE [10:6] 0xC R/W ILED2_FINE 5 [4:0] 0x0 0xC R/W R/W Reserved ILED1_FINE [15:13] [12:8] [7:0] [15:8] 0x0 0x3 0x20 0x08 R/W R/W R/W R/W Reserved SLOTA_LED_WIDTH SLOTA_LED_OFFSET SLOTA_LED_NUMBER [7:0] [15:10] 9 0x18 0x00 0x0 R/W R/W R/W SLOTA_LED_PERIOD Reserved SLOTB_LED_DIS 8 0x0 R/W SLOTA_LED_DIS [7:0] [15:13] [12:8] [7:0] [15:8] 0x00 0x0 0x3 0x20 0x08 R/W R/W R/W Reserved Reserved SLOTB_LED_WIDTH SLOTB_LED_OFFSET SLOTB_LED_NUMBER [7:0] [15:14] [13:11] 10 9 0x18 0x0 0x6 0x0 0x0 R/W R/W R/W R/W R/W SLOTB_LED_PERIOD RESERVED RESERVED Reserved V_CATHODE [8:3] 0x0 R/W AFE_POWERDOWN [2:0] 0x6 R/W Reserved Description LEDX3 fine adjust. Current adjust multiplier for LED3. LEDX3 fine adjust = 0.71 + 0.024 x (Register 0x25, Bits[15:11]). See Register 0x22, Bits[3:0], for the full LED3 formula. LEDX2 fine adjust. Current adjust multiplier for LED2. LEDX2 fine adjust = 0.71 + 0.024 x (Register 0x25, Bits[10:6]). See Register 0x24, Bits[3:0], for the full LED2 formula. Write 0x0. LEDX1 fine adjust. Current adjust multiplier for LED1. LEDX1 fine adjust = 0.71 + 0.024 x (Register 0x25, Bits[4:0]). See Register 0x23, Bits[3:0], for the full LED1 formula. Write 0x0. LED pulse width (in 1 s step) for Time Slot A. LED offset width (in 1 s step) for Time Slot A. LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A. This is typically LED1. Adjust in the application. A setting of six pulses (0x06) is typical. LED Time Slot A pulse period (in 1 s step). Write 0x0. Time Slot B LED disable. 1: disables the LED assigned to Time Slot B. Register 0x34 keeps the drivers active and prevents them from pulsing current to the LEDs. Disabling both LEDs via this register is often used to measure the dark level. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Time Slot A LED disable. 1: disables the LED assigned to Time Slot A. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Write 0x00. Write 0x0. LED pulse width (in 1 s step) for Time Slot B. LED offset width (in 1 s step) for Time Slot B. LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B. This is typically LED2. A setting of six pulses (0x06) is typical. LED Time Slot B pulse period (in 1 s step). Write 0x0. Write 0x6. Write 0x0. 0x0: 1.3 V (identical to anode voltage); recommended setting. 0x1: 1.8 V (reverse bias photodiode by 550 mV; this setting may add noise). AFE channels power-down select. 0x38: powers down AFE Channel 2, Channel 3, and Channel 4. 0x0: keeps all channels on. Write 0x6. Rev. B | Page 40 of 52 Data Sheet ADPD103 AFE CONFIGURATION REGISTERS Table 21. AFE Global Configuration Registers Address 0x3C 0x54 Data Bit [15:14] [13:11] Default Value 0x0 0x6 Access R/W R/W Name RESERVED RESERVED Description Write 0x0. Write 0x6. 10 0x0 R/W Reserved Write 0x0. 9 0x0 R/W V_CATHODE [8:3] 0x0 R/W AFE_POWERDOWN 0x0: 1.3 V (identical to anode voltage); recommended setting. 0x1: 1.8 V (reverse bias photodiode by 550 mV. This setting may add noise). AFE channels power-down select. 0x38: powers down AFE Channel 2, Channel 3, and Channel 4. 0x0: keeps all channels on. [2:0] 0x6 R/W Reserved Write 0x6. 15 0x0 R/W SLOTB_SINGLE_CH_DIG_INT 14 0x0 R/W SLOTA_SINGLE_CH_DIG_INT [13:12] 0x0 R/W SLEEP_V_CATHODE 0: In Time Slot B, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range) 1: In Time Slot B, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. 0: In Time Slot A, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range) 1: In Time Slot A, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in sleep mode. The anode voltage is always set to the cathode voltage in sleep mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V. [11:10] 0x0 R/W SLOTB_V_CATHODE If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot B operation. The anode voltage is always 1.3 V in Time Slot B mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). [9:8] 0x0 R/W SLOTA_V_CATHODE If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot A operation. The anode voltage is always 1.3 V in Time Slot A mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). 7 0x0 R/W REG54_VCAT_ENABLE [6:0] 0x20 R/W Reserved 0: use the cathode voltage settings defined by Register 0x3C, Bit 9. 1: override Register 0x3C, Bit 9 with cathode settings defined by Register 0x54, Bits[13:8]. Write 0x20. Rev. B | Page 41 of 52 ADPD103 Address 0x58 0x5A Data Sheet Data Bit [15:14] 13 Default Value 0x0 0x0 Access R/W R/W Name Reserved SLOTB_DIGITAL_INT_EN 12 0x0 R/W SLOTA_DIGITAL_INT_EN [11:0] [15:8] 7 0x000 0x00 0x0 R/W R/W R/W Reserved Reserved DIG_INT_GAPMODE 6 0x0 R/W SLOTB_DIG_INT_SAMPLE_MODE 5 0x0 R/W SLOTA_DIG_INT_SAMPLE_MODE [4:0] 0x00 R/W Reserved Description Write 0x0. 0x0: Time Slot B operating in normal mode. 0x1: Time Slot B operating in digital integration mode. 0x0: Time Slot A operating in normal mode. 0x1: Time Slot A operating in digital integration mode. Write 0x000. Write 0x00. Digital integrate gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in s. Digital integrate single sample pair mode for Time Slot B. 0: double sample pair mode. 1: single sampled pair mode. Digital integrate single sample pair mode for Time Slot A. 0: double sample pair mode. 1: single sampled pair mode. Write 0x00. Table 22. AFE Configuration Registers, Time Slot A Address 0x39 0x42 Data Bit [15:11] [10:5] Default Value 0x4 0x17 Access R/W R/W Name SLOTA_AFE_WIDTH SLOTA_AFE_OFFSET [4:0] 0x1C R/W SLOTA_AFE_FOFFSET [15:8] 0x1C R/W SLOTA_AFE_MODE 7 6 0x0 0x0 R/W R/W Reserved SLOTA_TIA_IND_EN [5:2] [1:0] 0xE 0x0 R/W R/W Reserved SLOTA_TIA_GAIN Description AFE integration window width (in 1 s step) for Time Slot A. AFE integration window coarse offset (in 1 s step) for Time Slot A. AFE integration window fine offset (in 31.25 ns step) for Time Slot A. 0x1C: Time Slot A AFE setting for normal mode. All four blocks of the signal chain are in use during normal mode (the TIA, the BPF, followed by the integrator (INT), and finally the ADC). 0x1D: Time Slot A AFE setting for digital integrate mode. Write 0x0. Enable Time Slot A TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x42, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[5:0]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Reserved. Write 0xD. Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is for all four Time Slot A channel TIA gain settings. 0: 200 k. 1: 100 k. 2: 50 k. 3: 25 k. Rev. B | Page 42 of 52 Data Sheet ADPD103 Address 0x43 Data Bit [15:0] Default Value 0xADA5 Access R/W Name SLOTA_AFE_CFG 0x55 [15:13] 0x0 R/W DIGINT_POWER 12 [11:10] 0x0 0x0 R/W R/W Reserved SLOTB_TIA_GAIN_4 [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 [7:6] 0x0 R/W SLOTB_TIA_GAIN_2 [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 [3:2] 0x0 R/W SLOTA_TIA_GAIN_3 [1:0] 0x0 R/W SLOTA_TIA_GAIN_2 Description AFE connection in Time Slot A. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xB065: TIA_ADC mode. 0xAE65: digital integration mode. Others: reserved. Power-down for Channel 2, Channel 3, and Channel 4 in digital integration mode. 0: keep all channels powered up. 7: powers down Channel 2, Channel 3, and Channel 4. Write 0x0. TIA gain for Time Slot B, Channel 4 (PD4). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot B, Channel 3 (PD3). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot B, Channel 2 (PD2). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 4 (PD4). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 3 (PD3). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 2 (PD2). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. Rev. B | Page 43 of 52 ADPD103 Address 0x5A Data Sheet Data Bit [15:8] 7 Default Value 0x0 0x0 Access R/W R/W Name Reserved DIG_INT_GAPMODE 6 0x0 R/W SLOTB_DIG_INT_SAMPLEMODE 5 0x0 R/W SLOTA_DIG_INT_SAMPLEMODE [4:0] 0x0 R/W Reserved Description Write 0x0. Digital integration gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in s. Digital integration single-sample pair mode for Time Slot B. 0: double sample pair mode. 1: single-sampled pair mode. Digital integration single-sample pair mode for Time Slot A. 0: double sample pair mode. 1: single-sampled pair mode. Write 0x0. Table 23. AFE Configuration Registers, Time Slot B Address 0x3B 0x44 0x45 Data Bit [15:11] [10:5] Default Value 0x4 0x17 Access R/W R/W Name SLOTB_AFE_WIDTH SLOTB_AFE_OFFSET [4:0] 0x1C R/W SLOTB_AFE_FOFFSET [15:8] 0x1C R/W SLOTB_AFE_MODE 7 6 0x0 0x0 R/W R/W Reserved SLOTB_TIA_IND_EN [5:2] [1:0] 0xE 0x0 R/W R/W Reserved SLOTB_TIA_GAIN [15:0] 0xADA5 R/W SLOTB_AFE_CFG Rev. B | Page 44 of 52 Description AFE integration window width (in 1 s step) for Time Slot B. AFE integration window coarse offset (in 1 s step) for Time Slot B. AFE integration window fine offset (in 31.25 ns step) for Time Slot B. 0x1C: Time Slot B AFE setting for normal mode (TIA_BPF_INT_ADC). 0x1D: Time Slot B AFE setting for digital integrate mode. Write 0x0. Enable Time Slot B TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x44, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[11:6]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Write 0xD. Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain settings. 0: 200 k. 1: 100 k. 2: 50 k. 3: 25 k. AFE connection in Time Slot B. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xB065: TIA_ADC mode. 0xAE65: digital integration mode. Others: reserved. Data Sheet Address 0x58 ADPD103 Data Bit [15:14] 13 Default Value 0x0 0x0 Access R/W R/W Name Reserved DIG_INT_EN_B 12 0x0 R/W DIG_INT_EN_A [11:0] 0x0000 R/W Reserved Rev. B | Page 45 of 52 Description Write 0x0. Digital integration mode, enable Time Slot B. 0: disable. 1: enable. Digital integration mode, enable Time Slot A. 0: disable. 1: enable. Write 0x0000. ADPD103 Data Sheet SYSTEM REGISTERS Table 24. System Registers Address 0x00 0x01 0x02 0x06 0x08 Data Bit [15:8] Default 0x00 Access R/W Name FIFO_SAMPLES 7 6 0x0 0x0 R/W R/W Reserved SLOTB_INT 5 0x0 R/W SLOTA_INT [4:0] [15:9] 8 0x00 0x00 0x0 R/W R/W R/W Reserved Reserved FIFO_INT_MASK 7 6 0x1 0x1 R/W R/W Reserved SLOTB_INT_MASK 5 0x1 R/W SLOTA_INT_MASK [4:0] [15:3] 2 0x1F 0x0000 0x0 R/W R/W R/W Reserved Reserved INT_ENA 1 0x0 R/W INT_DRV 0 0x0 R/W INT_POL [15:14] [13:8] 0x0 0x00 R/W R/W Reserved FIFO_THRESH [7:0] [15:8] [7:0] 0x00 0x04 0x16 R/W R R Reserved REV_NUM DEV_ID Description FIFO status. Number of available bytes to be read from the FIFO. When comparing this to the FIFO length threshold (Register 0x06, Bits[13:8]), note that the FIFO status value is in bytes and the FIFO length threshold is in words, where one word = two bytes. With the FIFO_ACCESS_ENA bit set, write 1 to Bit 15 of FIFO_SAMPLES to clear the contents of the FIFO. Write 0x1 to clear this bit to 0x0. Time Slot B interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect. Time Slot A interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect Write 0x1F to clear these bits to 0x00. Write 0x00. Sends an interrupt when the FIFO data length has exceeded the FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt. Write 0x1. Sends an interrupt on the Time Slot B sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Sends an interrupt on the Time Slot A sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Write 0x1F. Write 0x0000. INT pin enable. 0: disable the INT pin. The INT pin floats regardless of interrupt status. The status register (Address 0x00) remains active. 1: enable the INT pin. INT drive. 0: the INT pin is always driven. 1: the INT pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices need to share the INT pin. INT polarity. 0: the INT pin is active high. 1: the INT pin is active low. Write 0x0. FIFO length threshold. An interrupt is generated when the number of data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt pin automatically deasserts when the number of data-words available in the FIFO no longer exceeds the value in FIFO_THRESH. Write 0x00. Revision number. Device ID. Rev. B | Page 46 of 52 Data Sheet ADPD103 Data Bit [15:8] [7:1] 0 [15:12] [11:0] Default 0x0 0x64 0x0 0x0 0x000 Access W R/W R R R Name ADDRESS_WRITE_KEY SLAVE_ADDRESS Reserved Reserved CLK_RATIO 0x0D [15:0] 0x0 R/W SLAVE_ADDRESS_KEY 0x0F [15:1] 0 0x0000 0x0 R R/W Reserved SW_RESET 0x10 [15:2] [1:0] 0x000 0x0 R/W R/W Reserved Mode 0x11 [15:14] 13 0x0 0x0 R/W R/W Reserved RDOUT_MODE 12 0x1 R/W FIFO_OVRN_PREVENT [11:9] [8:6] 0x0 0x0 R/W R/W Reserved SLOTB_FIFO_MODE 5 0x0 R/W SLOTB_EN Address 0x09 0x0A Description Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access. I2C slave address. Do not access. Reserved. Read only. When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits. Enable changing the I2C address using Register 0x09. 0x04AD: enable address change always. 0x44AD: enable address change if INT is high. 0x84AD: enable address change if PDSO is high. 0xC4AD: enable address change if both INT and PDSO are high. Reserved. Read only. Software reset. Write 0x1 to reset the device. This bit clears itself after a reset. This command does not return an acknowledge because the command is instantaneous. Write 0x000. Determines the operating mode of the ADPD103. 0x0: standby. 0x1: program. 0x2: normal operation. Write 0x0. Readback data mode for extended data registers 0x0: Block sum of N samples 0x1: Block average of N samples 0x0: wrap around FIFO, overwriting old data with new. 0x1: new data if FIFO is not full (recommended setting). Write 0x0. Time Slot B FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all 4 channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all 4 channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode 4: 32-bit sample and 32-bit background value in digital integration mode or 4 channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: 4 channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. The selected Time Slot B data is saved in the FIFO. Available only if Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0). Time Slot B enable. 1: enables Time Slot B. Rev. B | Page 47 of 52 ADPD103 Data Sheet Data Bit [4:2] Default 0x0 Access R/W Name SLOTA_FIFO_MODE 1 0 15 14 0x0 0x0 0x0 0x0 R/W R/W R/W R/W Reserved SLOTA_EN Reserved EXT_SYNC_ENA [13:0] [15:9] 8 0x0 0x13 0x0 R/W R/W R/W Reserved Reserved CLK32K_BYP 7 0x0 R/W CLK32K_EN 6 [5:0] 0x0 0x12 R/W R/W Reserved CLK32K_ADJUST 0x4D [15:8] [7:0] 0x42 0x5E R/W R/W Reserved CLK32M_ADJUST 0x4E 1 [15:0] 0x0060 R/W ADC_TIMING1 Address 0x38 0x4B Description Time Slot A FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all 4 channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all 4 channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode 4: 32-bit sample and 32-bit background value in digital integration mode or 4 channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: 4 channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. Write 0x0. Time Slot A enable. 1: enables Time Slot A. Write 0x0. Enables external sampling trigger. 0x0: samples triggered internally. 0x1: samples triggered externally. Must be set to 1 if EXT_SYNC_SEL is b01 or b10. Write 0x0. Write 0x13. Bypass internal 32 kHz clock oscillator. 0x0: normal operation. 0x1: use an external clock on the PDSO pin. Sample clock power-up. Enables the data sample clock. 0x0: clock disabled. 0x1: normal operation. Write 0x0. Data sampling (32 kHz) clock frequency adjust. This register is used to calibrate the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz. Note that a larger value produces a lower frequency. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center frequency. 11 1111: minimum frequency. Write 0x42. Internal timing (32 MHz) clock frequency adjust. This register is used to calibrate the internal clock of the device to achieve precisely timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 0000 0000: minimum frequency. 0101 1110: default frequency. 1111 1111: maximum frequency. 0x0040: ADC clock speed = 1 MHz. 0x0060: ADC clock speed = 500 kHz. Rev. B | Page 48 of 52 Data Sheet Address 0x4F 0x50 0x5F 1 ADPD103 Data Bit [15:7] 6 5 4 [3:2] Default 0x41 0x0 0x0 0x1 0x0 Access R/W R/W R/W R/W R/W Name Reserved PDSO_OE PDSO_IE Reserved EXT_SYNC_SEL 1 0 [15:7] 6 0x0 0x0 0x000 0x0 R/W R/W R/W R/W INT_IE Reserved Reserved PDSO_CTRL 5 0x0 R/W CLK32M_CAL_EN [4:0] [15:3] 2 0x0 0x0000 0x0 R/W R/W R/W Reserved Reserved SLOTB_DATA_HOLD 1 0x0 R/W SLOTA_DATA_HOLD 0 0x0 R/W FIFO_ACCESS_ENA Description Write 0x41. PDSO pin output enable. PDSO pin input enable. Write 0x1. Sample sync select. 00: use the internal 32 kHz clock with FSAMPLE to select sample timings. 01: use the INT pin to trigger sample cycle. 10: use the PDSO pin to trigger sample cycle. 11: reserved. INT pin input enable. Write 0x0. Write 0x000. Controls the PDSO output when the PDSO output is enabled (PDSO_OE = 0x1). 0x0: PDSO output driven low. 0x1: PDSO output driven by the AFE power-down signal. As part of the 32 MHz clock calibration routine, write 1 to begin the clock ratio calculation. Read the result of this calculation from the CLK_RATIO bits in Register 0x0A. Reset this bit to 0 prior to reinitiating the calculation. Write 0x0. Write 0x0000. Setting this bit prevents the update of the data registers corresponding to Time Slot B. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot B. 0: allow data register update. Setting this bit prevents the update of the data registers corresponding to Time Slot A. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot A. 0: allow data register update. Set to 1 twice to enable FIFO access. It is necessary to write 1 to the FIFO_ACCESS_ENA bit in two consecutive write operations in order to read data from the FIFO. During clock calibration, set to 1 to force the 32 MHz clock to run. For power savings, reset to 0 when the previously described operations are complete. Clock speed setting is only relevant during digital integrate mode. Rev. B | Page 49 of 52 ADPD103 Data Sheet ADC REGISTERS Table 25. ADC Registers Data Bits [15:0] Default 0x0028 Access R/W Name FSAMPLE [15:11] [10:8] 0x0 0x6 R/W R/W Reserved SLOTB_NUM_AVG 7 [6:4] 0x0 0x0 R/W R/W Reserved SLOTA_NUM_AVG 0x18 [3:0] [15:0] 0x0 0x2000 R/W R/W Reserved SLOTA_CH1_OFFSET 0x19 [15:0] 0x2000 R/W SLOTA_CH2_OFFSET 0x1A [15:0] 0x2000 R/W SLOTA_CH3_OFFSET 0x1B [15:0] 0x2000 R/W SLOTA_CH4_OFFSET 0x1E [15:0] 0x2000 R/W SLOTB_CH1_OFFSET 0x1F [15:0] 0x2000 R/W SLOTB_CH2_OFFSET 0x20 [15:0] 0x2000 R/W SLOTB_CH3_OFFSET 0x21 [15:0] 0x2000 R/W SLOTB_CH4_OFFSET Address 0x12 0x15 Description Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] x 4). For example, 100 Hz = 0x0050; 200 Hz = 0x0028. Write 0x0. Sample sum/average for Time Slot B. Specifies the averaging factor, NB, which is the number of consecutive samples that is summed and averaged after the ADC. Register 0x70 to Register 0x7F hold the data sum. Register 0x64 to Register 0x6B and the data buffer in Register 0x60 hold the data average, which can be used to increase SNR without clipping, in 16-bit registers. The data rate is decimated by the value of the SLOTB_NUMB_AVG bits. 0: 1. 1: 2. 2: 4. 3: 8. 4: 16. 5: 32. 6: 64. 7: 128. Write 0x0. Sample sum/average for Time Slot A. NA: same as Bits[10:8] but for Time Slot A. See description in Register 0x15, Bits[10:8]. Write 0x0. Time Slot A Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Rev. B | Page 50 of 52 Data Sheet ADPD103 DATA REGISTERS Table 26. Data Registers Address 0x60 Data Bits [15:0] Access R Name FIFO_DATA 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] R R R R R R R R R R R R R R R R R R R R R R R R SLOTA_CH1_16BIT SLOTA_CH2_16BIT SLOTA_CH3_16BIT SLOTA_ CH4_16BIT SLOTB_ CH1_16BIT SLOTB_CH2_16BIT SLOTB_CH3_16BIT SLOTB_CH4_16BIT SLOTA_CH1_LOW SLOTA_CH2_LOW SLOTA_CH3_LOW SLOTA_CH4_LOW SLOTA_CH1_HIGH SLOTA_CH2_HIGH SLOTA_CH3_HIGH SLOTA_CH4_HIGH SLOTB_CH1_LOW SLOTB_CH2_LOW SLOTB_CH3_LOW SLOTB_CH4_LOW SLOTB_CH1_HIGH SLOTB_CH2_HIGH SLOTB_CH3_HIGH SLOTB_CH4_HIGH Description Next available word in FIFO. Prior to reading this register, set the FIFO_ACCESS_ENA bit to 0x1 twice with two consecutive write operations to enable FIFO access (Register 0x5F, Bit 0). Reset this bit to 0 when the FIFO access sequence is complete. 16-bit value of Channel1 in Time Slot A. 16-bit value of Channel 2 in Time Slot A. 16-bit value of Channel 3 in Time Slot A. 16-bit value of Channel 4 in Time Slot A. 16-bit value of Channel 1 in Time Slot B. 16-bit value of Channel 2 in Time Slot B. 16-bit value of Channel 3 in Time Slot B. 16-bit value of Channel 4 in Time Slot B. Low data-word for Channel 1 in Time Slot A. Low data-word for Channel 2 in Time Slot A. Low data-word for Channel 3 in Time Slot A. Low data-word for Channel 4 in Time Slot A. High data-word for Channel 1 in Time Slot A. High data-word for Channel 2 in Time Slot A. High data-word for Channel 3 in Time Slot A. High data-word for Channel 4 in Time Slot A. Low data-word for Channel 1 in Time Slot B. Low data-word for Channel 2 in Time Slot B. Low data-word for Channel 3 in Time Slot B. Low data-word for Channel 4 in Time Slot B. High data-word for Channel 1 in Time Slot B. High data-word for Channel 2 in Time Slot B. High data-word for Channel 3 in Time Slot B. High data-word for Channel 4 in Time Slot B. Table 27. Required Start-Up Load Sequence Step Number 1 2 3 4 Address 0x4B, Bit 7 0x10 Other registers 0x10 Comment Write to 0x1 to enable the clock that drives the state machine. Write 0x0001 to enter program mode. Register order is not important while the device is in program mode. Write 0x0002 to start normal sampling operation. Rev. B | Page 51 of 52 ADPD103 Data Sheet OUTLINE DIMENSIONS 0.25 0.20 0.15 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 22 0.40 BSC PIN 1 INDICATOR 28 1 21 2.70 2.60 SQ 2.50 EXPOSED PAD 7 15 0.80 0.75 0.70 14 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-003523 SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-23-2015-B 0.45 0.40 0.35 TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGE. Figure 31. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-28-5) Dimensions shown in millimeters 1.44 1.40 1.36 0.225 3 2 1 A BALL A1 IDENTIFIER B 2.00 REF 2.50 2.46 2.42 C D 0.40 BSC E F TOP VIEW 0.235 0.300 (BALL SIDE DOWN) 0.560 0.500 0.440 0.300 0.260 0.220 1 0.230 0.200 0.170 02-03-2015-B COPLANARITY 0.05 PKG-004659 Model 1 ADPD103BCPZ ADPD103BCPZRL ADPD103BCBZRL7 EVAL-ADPD103Z-GEN (BALL SIDE UP) 0.330 0.300 0.270 END VIEW SEATING PLANE ORDERING GUIDE BOTTOM VIEW Figure 32. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-18) Dimensions shown in millimeters Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead LFCSP_WQ 28-Lead LFCSP_WQ 16-Ball WLCSP Generic ADPD103 Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2015-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12722-0-2/16(B) Rev. B | Page 52 of 52 Package Option CP-28-5 CP-28-5 CB-16-18