CY25404
Quad PLL Programmable Clock Generator
with Spread Spectrum
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-43258 Rev. *C Revised July 11, 201 1
Features
■Four fully integrated phase-locked loops (PLLs)
■Input frequency range
❐External crystal: 8 to 48 MHz
❐External reference: 8 to 166 MHz clock
■Wide operating output frequency range
❐3 to 166 MHz
■Programmable spread spectrum with center and down
spread option and lexmark and linear modulation profiles
■Selectable VDD supply voltage options:
❐2.5 V, 3.0 V, and 3.3 V
■Selectable output clock voltages, independent of VDD supply:
❐2.5 V, 3.0 V, and 3.3 V
■Frequency select feature with option to select eight different
frequencies over nine clock outputs
■Output enable, and SS ON/OFF contro ls
■Low jitter, high accuracy outputs
■Ability to synthesize nonstandard frequencies with
Fractional-N capability
■Up to nine clock outputs with programmable drive strength
■Glitch-free outputs while frequency switching
■20-pin TSSOP package
■Commercial and Industrial temperature ranges
Benefits
■Multiple high performance PLLs allow synthesis of unrelated
frequencies
■Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■Application specific programmable electromagneti c
interference (EMI) reduction using spread spectrum for
clocks
■Programmable PLLs for system frequency margin tests
■Meets critical timing requirement s in complex system
designs
■Suitability for PC, consumer, portable, and networking
applications
■Capable of zero parts per million (PPM) frequency synthesis
error
■Uninterrupted system operation during clock frequency
switch
■Application compatibility in standard and low power systems
OSC PLL1
PLL2
PLL3
(SS)
PLL4
(SS)
Output
Dividers
and
Drive
Strength
Control
CLK1
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
FS 2
FS 1
FS 0
SSON
XOUT
XIN/
EXCLKIN
OE
Bank
1
Bank
3
Bank
2
MUX
and
Control
Logic
Crossbar
Switch
Block Diagram
CY25404
Document #: 001-43258 Rev. *C Page 2 of 13
Contents
General Description .........................................................4
Four Configurable PLLs ..............................................4
Input Reference Clocks ...............................................4
VDD Power Supply Options .........................................4
Output Bank Settings ..................................................4
Output Source Selection .............................................4
Spread Spectrum Control ............................................4
Frequency Select ........................................................4
Glitch-Free Frequency Switch .....................................4
Output Enable Mode ...................................................4
Output Drive Strength ..................................................4
Generic Configuration and Custom Frequency ...........4
Absolute Maximum Conditions....................................... 5
Recommended Operating Conditions ............................5
DC Electrical Specificati on s ............. ... .. ..........................6
Recommended Crystal Sp ecification
for SMD Package ..............................................................7
Recommended Crystal Specification
for Thru-Hole Package .....................................................7
AC Electrical Specifications .................... ... .............. .. ... ..7
Test and Measurement Setup ..........................................8
Voltage and Timing Definiti ons .................. .. .............. ... ..8
Ordering Information ........................................................9
Possible Configurations ........... ............... .. ... .............. ..9
Ordering Code Definitions ...........................................9
Package Drawing and Dimensions ...............................10
Acronyms ........................................................................ 11
Document Conventions ........................ ... .............. ... .....11
Units of Measure ................................. ... .............. .. ...11
Document History Page ..................... .............. ... ... ........12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support .......................13
Products .................................................................... 13
PSoC Solutions .................. ... .. ............... .. ... ..............13
CY25404
Document #: 001-43258 Rev. *C Page 3 of 13
Figure 1. Pin Diagram - CY25404 20 LD TSSOP
Table 1. Pin Definition - CY25404 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number Name IO Description
1V
DD Power Power supply: 2.5 V/3.0 V/3.3 V
2 XOUT Output Crysta l ou tp u t
3 XIN/EXCLKIN Input Crystal Input or 1.8 V external clock input
4V
SS Power Power supply ground
5 CLK1 Output Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
6V
DD_CLK_B1 Power Power supply for Bank1, (CLK1, CLK2, CLK3) outputs: 2.5 V/3.0 V/3.3 V
7 CLK2 Output Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
8V
SS Power Power supply ground
9 CLK3/FS0 Output/Input Multifunction programmable pin: Programmable clock output or frequency select
input pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
10 OE/FS1 Input Multifunction programmable pin: High-true output enable or frequency select pin
1 1 CLK4/FS2 Output/Input Multifunction programmable pin: Programmable clock output or frequency select
input pin. Output voltage of CLK4 depends on VDD_CLK_B2 Voltage
12 CLK5 Output Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
13 VSS Power Power supply ground
14 CLK6 Output Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
15 VDD_CLK_B2 Power Power supply for Bank2, (CLK4, CLK5, CLK6) outputs: 2.5 V/3.0 V/3.3 V
16 CLK7/SSON Output/Input Multifunction programmable pin. Programmable clock output or spread spectrum
On/OFF control input pin. Output voltage of CLK7 depends on VDD_CLK_B3
voltage
17 VDD_CLK_B3 Power Power supply for Bank3, (CLK7, CLK8, CLK9) outputs: 2.5 V/3.0 V/3.3 V
18 CLK8 Output Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
19 VSS Power Power supply ground
20 CLK9 Output Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
VDD
XOUT
XIN/EXCLKIN
VSS
CLK1
VDD_CLK_B1
CLK2
VSS
CLK3/FS0
OE/FS1
CLK5
CLK6
VSS
CLK7/SSON
VDD_CLK_B2
VDD_CLK_B3
CLK9
VSS
CLK4/FS2
CY25404
11
CLK8
CY25404
Document #: 001-43258 Rev. *C Page 4 of 13
General Description
Four Configurable PLLs
The CY25404 has four programmable PLLs that can be used to
generate output frequencies ranging from 3 to 166 MHz. The
advantage of having four PLLs is that a single device generates
up to four independent frequencies from a single crystal.
Input Reference Clocks
The input to the CY25404 can be either a crystal or a clock
signal. The input freque ncy range for crystals is 8 MHz to 48
MHz, while that for clock signals is 8 MHz to 166 MHz. The
required voltage level for the input reference clock (EXCLKIN) is
shown in the DC and AC Electrical Speci fi c ation tables.
VDD Power Supply Options
This device has programmable power supply option and it can
be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V.
Output Bank Settings
There are nine clock outputs grouped in three output driver
banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1,
CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9)
respectively. Separate power supplies are used for each of these
banks and they can be any of 2.5 V, 3.0 V, or 3.3 V. These
voltages are independent of VDD power supply used, giving user
multiple choice of output cloc k voltage level s.
Output Source Selection
These devices have programmable input sources for each of its
nine clock outputs (CLK1–9). There are five available clock
sources for these outputs. These clock sources are:
XIN/EXCLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source
selection is done using four out of five crossbar switch. Thus, any
one of these five available clock sources can be arbitrarily
selected for the clock outputs. This gives user a flexibility to have
up to four independent clock outputs.
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.12 5% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Frequency Select
There are three multifunction frequency select pins (FS0, FS1
and FS2) that provide an option to select eight different sets of
frequencies among each of the four PLLs. Each output has
programmable output divider options.
Glitch-Free Frequen cy Switch
When the frequency select pin (FS) is used to switch frequency ,
the outputs are glitch-free provided frequency is switched using
output dividers. This feature enables uninterrupted system
operation while clock frequency is being switched.
Output Enable Mode
There is a multifunction programmable pin 10, OE/FS1 that can
be programmed to operate as output enable (OE) mode. OE is
a high-true input and individual clock outputs can be
programmed to be sensitive to this OE pin. If activated it shuts
off the output drivers, resulting in minimum power consump tion
for the device.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 2 shows the typical rise
and fall times for different drive strength settings.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY25404 can be custom programmed to any desired
frequencies and listed features. For customer specific
programming, please contact local cypress field applica ti on
engineer (FAE) or sales representative.
Table 2. Output Drive Streng th
Output Drive Strength Rise/Fall Time (ns)
(Typical Value)
Low 6.8
Mid Low 3.4
Mid High 2.0
High 1.0
CY25404
Document #: 001-43258 Rev. *C Page 5 of 13
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
VDD Supply voltage – –0.5 4.5 V
VDD_CLK_BX Output bank supply voltage – –0.5 4.5 V
VIN Input voltage Relative to VSS –0.5 VDD+0.5 V
TSTemperature, storage Non functional –65 +150 °C
ESDHBM ESD protection (human body model) JEDEC EIA/JESD22-A114-E 2000 volts
UL-94 Flammability rating V-0 at 1/8 in. – 10 ppm
MSL Moisture sensitivity level – 3
Recommended Operating Conditions
Parameter Description Min Typ Max Unit
VDD VDD operating voltage 2.25 – 3.60 V
VDD_CLK_BX Output driver voltage for Bank 1, 2 and 3 2.25 – 3.60 V
TAC Commercial ambient temperature 0 – +70 °C
TAI Industrial ambient temperature –40 -- +85 °C
CLOAD Maximum load capacitance – – 15 pF
tPU Power-up time for all VDD to reach minimum specified voltage (power ramps must
be monotonic) 0.05 – 500 ms
Notes
1. Guaranteed by design but no t 100% tested.
2. Configuration dependent.
CY25404
Document #: 001-43258 Rev. *C Page 6 of 13
DC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
VOL Output low voltage IOL = 2 mA, drive strength = [00] – – 0.4 V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH Output high voltage IOH = –2 mA, drive strength = [00] VDD_CLK_BX
– 0.4 ––V
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VIL1 Input low voltage of FS0, OE/FS1, FS2,
and SSON –––0.2*V
DD V
VIL2 Input low voltage of EXCLKIN – – – 0.18 V
VIH1 Input high voltage of FS0, OE/FS1,
FS2, and SSON –0.8*V
DD ––V
VIH2 Input high voltage of EXCLKIN – 1.62 – 2.2 V
IIL1 Input low current of OE/FS1 pin VIL = 0V – – 10 µA
IIH1 Input high current of OE/FS1 pin VIH = VDD – – 10 µA
IIL2 Input low current of SSON, FS0 and
FS2 pins VIL = 0V (Internal pull dn = 160k typ) – – 10 µA
IIH2 Input high current of SSON, FS0, and
FS2 pins VIH = VDD (Internal pull dn = 160k typ) 14 – 36 µA
RDN Pull down resistor of SSON, FS0, and
FS2 and off state (CLK1-CLK9) pins Clock outputs in off-state by setting OE
= Low 100 160 250 k
IDD[1,2] Supply current for CY25404 OE = High, No load – 22 – mA
CIN[1] Input capacitance SSON, CLKIN, FS0, OE/FS1, and FS2
pins –7pF
CY25404
Document #: 001-43258 Rev. *C Page 7 of 13
AC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
FIN (crystal) Crystal frequency, XIN – 8 – 48 MHz
FIN (clock) Input clock frequency, EXCLKIN –8–166MHz
FCLK Output clock frequency – 3 – 166 MHz
DC1 Output duty cycle, All clocks
except Ref Out Duty cycle is defined in Figu re 3 on page 8; t1/t2,
measured at 50% of VDD_CLK_BX 45 50 55 %
DC2 Ref out duty cycle Ref In Min 45%, Max 55% 40 – 60 %
TRF1[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [00]
–6.8–ns
TRF2[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [01]
–3.4–ns
TRF3[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [10]
–2.0–ns
TRF4[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [11]
–1.0–ns
TCCJ[1,2] Cycle-to-cycle jitter (peak) Configuration dependent. See Table 3 –100– ps
TLOCK[1] PLL lock time Measured from 90% of the applied power suppl y
level –13ms
Table 3. Configuration Example for C-C Jitter
Ref. Freq.
(MHz)
CLK1 Output CLK2 Output CLK3 Output CLK4 Output CLK5 Output
Freq.
(MHz) C-C Jitter
Typ (ps) Freq.
(MHz) C-C Jitter
Typ (ps) Freq.
(MHz) C-C Jitter
Typ (ps) Freq.
(MHz) C-C Jitter
Typ (ps) Freq.
(MHz) C-C Jitter
Typ (ps)
14.3181 8.0 134 166 103 48 92 74.25 81 Not Used
19.2 74.25 99 166 94 8 91 27 110 48 75
27 48 67 27 109 166 103 74.25 97 Not Used
48 48 93 27 123 166 137 166 138 8 103
Recommended Crystal Specification for SMD Package
Parameter Description Range 1 Range 2 Range 3 Unit
FIN Crystal frequency 8 – 14 14 – 28 28 – 48 MHz
R1 Maximum motional resistance (ESR) 135 50 30
CL Parallel load capacitance (device has internal load capacitance adjustment
feature) 8 – 18 8 – 14 8 – 12 pF
DL(max) Maximum crystal drive level 300 300 300 µW
Recommended Crystal Specification for Thru-Hole Package
Parameter Description Range 1 Range 2 Range 3 Unit
FIN Crystal frequency 8 – 14 14 – 24 24 – 32 MHz
R1 Maximum motional resistance (ESR) 90 50 30
CL Parallel load capacitance (device has internal load capacitance
adjustment feature) 8 – 18 8 – 12 8 – 12 pF
DL(max) Maximum crystal drive level 1000 1000 1000 µW
CY25404
Document #: 001-43258 Rev. *C Page 8 of 13
Test and Measurement Setup
Figure 2. Test and Measurement Setu p
Voltage and Timing Definitions
Figure 3. Duty Cycle Definition
Figure 4. Rise Time = TRF, Fall Time = TRF
0.1 F
VDD Outputs
CLOAD
GND
DUT
Clock
Output
V
DD_CLK_B
X
50% o f V
DD_CLK_B
X
0V
t
1
t
2
Clock
Output
TRF
TRF
V DD_CLK_BX
80% of V
DD_CLK_BX
20% of V
DD_CLK_BX
0V
CY25404
Document #: 001-43258 Rev. *C Page 9 of 13
Ordering Code Definitions
Ordering Information
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales
representative for more information.
Possible Configurations
Part Number[3] Type Production Flow
Pb-free
CY25404ZXC-xxx 20-pin TSSOP Commercial, 0 °C to 70 °C
CY25404ZXC-xxxT 20-pin TSSOP -Tape and Reel Commercial, 0 °C to 70 °C
CY25404ZXI-xxx 20-pin TSSOP Industrial, –40 °C to +85 °C
CY25404ZXI-xxxT 20-pin TSSOP -Tape and Reel Industrial, –40 °C to +85 °C
Note
3. xxx indicates Factory Programmable and are fa ctory programmed configu rations. For more deta ils, contact your local Cypress FAE or Cypress Sales Representative.
Package Type: (T = Tape and Reel)
Customer specific identification code
Temperature code (C= Commercial or I= Industrial)
20-Pin TSSOP package
Marketing Code: CY25404 = Device Number
ZX C/I - xxx T
CY25404
CY25404
Document #: 001-43258 Rev. *C Page 10 of 13
Package Drawing and Dimensions
Figure 5. 20-LD TSSOP, Thin Shru nk Small Outline Package (4.40 mm Body) ZZ2
51-85118 *C
CY25404
Document #: 001-43258 Rev. *C Page 11 of 13
Acronyms
Document Conventions
Units of Measure
Acronym Description
DL drive level
EMI electromagnetic interference
ESD electrostatic discharge
FAE field application engineer
FS frequency select
JEDEC EIA joint electron devices
engineering council electronic
industries alliance
OE output enable
OSC oscillator
PD power-down
PLL phase-locked loop
PPM parts per million
SS spread spectrum
SSC spread spectrum cloc k
SSON spread spectrum on
TSSOP thin shrunk small outline
package
Symbol Unit of Measure
°C degrees Celsius
fF femtofarads
mA milliampere
MHz megahertz
smicroseconds
ms millisecond
Wmicrowatts
ns nanoseconds
pF picofarads
ppm parts per million
ps picoseconds
Vvolts
ohms
Wwatts
CY25404
Document #: 001-43258 Rev. *C Page 12 of 13
Document History Page
Document Title: CY25404 Quad PLL Program mable Clock Generator with Spread Spectrum
Document Number: 001-43258
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 1793805 See ECN DPF/AESA New data sheet
*A 2748211 08/10/09 TSAI Posting to external web.
*B 2899300 03/26/2010 CXQ Updated Ordering Information. Added note regarding Possible Configura-
tions in Ordering Information section.
Added Possible Configurations table for “xxx’ parts.
Updated Package Drawing and Dime nsions
*C 3308261 07/11/2011 BASH Added Ordering Code Definitions
Updated Package Drawing and Di mensions
Added Acronyms
Added Units of Measure
Added Contents
Document #: 001-43258 Rev. *C Revised July 11, 2011 Page 13 of 13
CY25404
© Cypress Semico nducto r Co rpor ation , 20 07-2 011. The info rmati on con ta ined her ein is subje ct to cha nge w ith out no tice. Cypress S emiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n exp re ss wr i tte n ag re em en t w it h C ypress. Furthermore, Cypre ss does not auth ori ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modi fy, create derivative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conj unction with a Cypre ss
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABI LITY AND FITNESS FOR A PARTICULAR PURP OSE. Cypress reserves the right to make changes without further notice to the materials described h erein. Cypre ss does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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