M65608 128 K x 8 Ultimate CMOS SRAM Introduction The M 65608 is a very low power CMOS static RAM organized as 131072 x 8 bits. It is manufactured using the TEMIC high performance CMOS technology named SCMOS. current (Typical value = 0.2 A) with a fast access time at 25 ns over the full commercial temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. With this process, TEMIC brings the solution to applications where fast computing is as mandatory as low consumption, such as aerospace electronics, portable instruments, or embarked systems. For military/space applications that demand superior levels of performance and reliability the M 65608 is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000. Utilizing an array of six transistors (6T) memory cells, the M 65608 combines an extremely low standby supply Features Access time : commercial : 25/30/35/45 ns industrial and military : 25/30/35/45 ns Very low power consumption active : 250 mW (Typ) standby : 1 W (Typ) data retention : 0.5 W (Typ) Wide temperature Range : -55 To +125C 400 Mils width package TTL compatible inputs and outputs Asynchronous Single 5 volt supply Equal cycle and access time Gated inputs : no pull-up/down resistors are required Interface Block Diagram MATRA MHS Rev. B (23/03/96) 1 M65608 Pin Configuration 32 pins DLCC ceramic 400 MILS 32 pins DIL side-brazed 400 MILS 32 pins Flatpack 400 MILS 32 pins PDIL 400 MILS 32 pins SOIC and SOJ 400 MILS Pin Names Truth Table A0-A16 Address inputs I/O0-I/O7 Data Input/Output CS1 Chip select 1 CS2 Chip select 2 W Write Enable OE CS1 CS2 W OE INPUTS/ OUTPUTS H X X X Z Deselect/ Power-down X L X X Z Deselect/ Power Down Output Enable L H H L Data Out Read VCC Power L H L X Data In Write GND Ground L H H H Z Output Disable MODE L = low, H = high, X = H or L, Z = high impedance. 2 MATRA MHS Rev. B (23/03/96) M65608 Electrical Characteristics Absolute Maximum Ratings Supply voltage to GND potential : . . . . . . . . . . . . . . . - 0.5 V + 7.0 V DC input voltage : . . . . . . . . . . . . . . . . . GND - 0,3 V to VCC + 0,3 DC output voltage high Z state : . . . . . . GND - 0,3 V to VCC + 0,3 Storage temperature : . . . . . . . . . . . . . . . . . . . . . . -65 C to + 150 C Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . 20 mA Electro statics discharge voltage : . . . . . . . . . . . . . . . . . . . > 2 001 V (MIL STD 883D method 3015.3) Operating Range OPERATING VOLTAGE OPERATING TEMPERATURE Military 5 V 10 % - 55 _C to + 125 _C Industrial 5 V 10 % - 40 _C to + 85 _C Commercial 5 V 10 % 0 _C to + 70 _C Recommended DC Operating Conditions PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT Vcc Supply voltage 4.5 5.0 5.5 V Gnd Ground 0.0 0.0 0.0 V VIL Input low voltage GND - 0.3 0.0 0.8 V VIH Input high voltage 2.2 - VCC + 0.3 V MINIMUM TYPICAL MAXIMUM UNIT Capacitance PARAMETER DESCRIPTION Cin (1) Input low voltage - - 8 pF Cout (1) Output high volt - - 8 pF MINIMUM TYPICAL MAXIMUM UNIT Note : 1. Guaranteed but not tested. DC Parameters PARAMETER DESCRIPTION IIX (2) Input leakage current -1 - 1 A IOZ (2) Output leakage current -1 - 1 A VOL (3) Output low voltage - - 0.4 V VOH (4) Output high voltage 2.4 - - Notes : 2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled. 3. Vcc min. IOL = 8.0 mA. 4. Vcc min. IOH = -4.0 mA. MATRA MHS Rev. B (23/03/96) 3 M65608 Consumption for Commercial SYMBOL DESCRIPTION 65608L/V - 25 65608L/V - 30 65608L/V - 35 65608L/V - 45 UNIT VALUE ICCSB (5) Standby supply current 5/2 5/2 5/2 5/2 mA max ICCSB1 (6) Standby supply current 500/50 500/50 500/50 500/50 A max ICCOP (7) Dynamic operating current 150 140 130 120 mA max 65608L/V - 25 65608L/V - 30 65608L/V - 35 65608L/V - 45 UNIT VALUE Consumption for Industrial SYMBOL DESCRIPTION ICCSB (5) Standby supply current 5/2 5/2 5/2 5/2 mA max ICCSB1 (6) Standby supply current 700/100 700/100 700/100 700/100 A max ICCOP (7) Dynamic operating current 160 150 140 120 mA max 65608L/V - 25 65608L/V - 30 65608L/V - 35 65608L/V - 45 UNIT VALUE Consumption for Military SYMBOL DESCRIPTION ICCSB (5) Standby supply current 5/2.5 5/2.5 5/2.5 5/2.5 mA max ICCSB1 (6) Standby supply current 1 000/300 1 000/300 1 000/300 1 000/300 A max ICCOP (7) Dynamic operating current 160 150 140 120 mA max Notes : 5. CS1 VIH or CS2 VIL and CS1 VIL. 6. CS1 Vcc - 0.3 V or, CS2 < Gnd + 0.3 V and CS1 0.2 V 7. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd/Vcc, Vcc max. AC Parameters Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output loading IOL/IOH (see figure 1a and 1b) : . . . . . . . . . + 30 pF AC Test Loads Waveforms Figure 1a 4 Figure 1b Figure 2 MATRA MHS Rev. B (23/03/96) M65608 RAM outputs high impedance, minimizing power dissipation. Data Retention Mode MHS CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention : 3. During power up and power down transitions CS1 and OE must be kept between VCC + 0.3 V and 70 % of VCC, or with CS2 between GND and GND - 0.3 V. 1. . During data retention chip select CS1 must be held high within VCC to VCC -0.2 V or, chip select CS2 must be held low within GND to GND + 0.2 V. 4. The RAM can begin operation > 45 ns after Vcc reaches the minimum operation voltages (4.5 V). 2. Output Enable (OE) should be held high to keep the Timing Data Retention Characteristics PARAMETER DESCRIPTION MINIMUM TYPICAL TA = 25 _C MAXIMUM UNIT VCCDR Vcc for data retention 2.0 - - V TCDR Chip deselect to data retention time 0.0 - - ns TR Operation recovery time TAVAV (9) - - ns Data retention current @ 2.0 V : M-65608-V M-65608-L - - 0.1 0.1 COM 20 200 IND 40 300 MIL 150 500 A A Data retention current @ 3.0 V : M-65608-V M-65608-L - - 0.2 0.2 COM 30 300 IND 60 450 MIL 200 600 A A ICCDR1 (10) ICCDR2 (10) Notes : 9. TAVAV = Read cycle time. 10. CS1 = Vcc or CS2 = CS1 = GND, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V. MATRA MHS Rev. B (23/03/96) 5 M65608 Write Cycle SYMBOL PARAMETER 65608L/V 65608L/V 65608L/V 65608L/V - 25 - 30 - 35 - 45 UNIT VALUE TAVAW Write cycle time 25 30 35 45 ns min TAVWL Address set-up time 0 0 0 0 ns min TAVWH Address valid to end of write 20 22 25 35 ns min TDVWH Data set-up time 15 18 20 25 ns min TE1LWH CS1 low to write end 20 22 25 35 ns min TE2HWH CS2 high to write end 20 22 25 35 ns min TWLQZ Write low to high Z (11) 8 8 10 15 ns max TWLWH Write pulse width 20 22 25 35 ns min TWHAX Address hold from to end of write 0 0 0 0 ns min TWHDX Data hold time 0 0 0 0 ns min TWHQX Write high to low Z (11) 0 0 0 0 ns min UNIT VALUE Read Cycle SYMBOL PARAMETER 65608L/V 65608L/V 65608L/V 65608L/V - 25 - 30 - 35 - 45 TAVAV Read cycle time 25 30 35 45 ns min TAVQV Address access time 25 30 35 45 ns max TAVQX Address valid to low Z 3 5 5 5 ns min TE1LQV Chip-select1 access time 25 30 35 45 ns max TE1LQX CS1 low to low Z (11) 3 3 3 3 ns min TE1HQZ CS1 high to high Z (11) 15 18 20 20 ns max TE2HQV Chip-select2 access time 25 30 35 45 ns max TE2HQX CS2 high to low Z (11) 3 3 3 3 ns min TE2LQZ CS2 low to high Z (11) 15 18 20 20 ns max TGLQV Output Enable access time 10 12 12 15 ns max TGLQX OE low to low Z (11) 0 0 0 0 ns min TGHQZ OE high to high Z (11) 8 8 10 15 ns max Notes : 11. Parameters guaranteed, not tested, with output loading 5 pF. (see fig. 1.b.). 6 MATRA MHS Rev. B (23/03/96) M65608 Write Cycle 1. W Controlled. OE High During Write Write Cycle 2. W Controlled. OE Low MATRA MHS Rev. B (23/03/96) 7 M65608 Write Cycle 3. CS1 or CS2 Controlled. Note : 8 12. The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH. MATRA MHS Rev. B (23/03/96) M65608 Read Cycle nb 1 Read Cycle nb 2 Read Cycle nb 3 MATRA MHS Rev. B (23/03/96) 9 M65608 Ordering Information C = Commercial I = Industrial M = Military S = Space 0 -40 -55 -55 C9 = DJ = 4J = 39 = T1 = U1 = to to to to 25 ns 30 ns L = Low power V = Very low power 35 ns EV = Very low power 45 ns and rad tolerant (*) +70C +85C +125C +125C Side Brazed 32 pins 400 mils Flat Package 32 pins 400 mils Dual LCC 32 pins Plastic DIL 32 pins 400 mils 32 pins SOIC 400 mils 32 pins SOJ 400 mils 128K x 8 STATIC RAM * Preview blank = MHS standards /883 = MIL-STD 883 Class B or S SHXXX = Special customer request FHXXX = Flight models (space) MHXXX = Mechanical parts (space) LHXXX = Life test parts (space) P883 = /883 + PIND TEST : R = Tape & Reel : RD = Tape & Reel and Dry pack : D = Dry pack The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use. 10 MATRA MHS Rev. B (23/03/96)