MC34166, MC33166
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INTRODUCTION
The MC34166, MC33166 series are monolithic power
switching regulators that are optimized for dc−to−dc
converter applications. These devices operate as fixed
frequency, voltage mode regulators containing all the active
functions required to directly implement step−down and
voltage−inverting converters with a minimum number of
external components. They can al s o be us ed cost effectively
in step−up converter applications. Potential markets include
automotive, computer, industrial, and cost sensitive
consumer products. A description of each section of the
device i s given below with the representative block diagram
shown in Figure 14.
Oscillator
The oscillator frequency is internally programmed to
72 kHz by capacitor CT and a trimmed current source. The
charge to discharge ratio is controlled to yield a 95%
maximum duty cycle at the Switch Output. During the
dischar ge of C T, t he os cillator generates a n i nternal blanking
pulse that holds the inverting input of the AND gate high,
disabling t he o utput switch t ransistor. The n ominal oscillator
peak and valley thresholds a re 4.1 V and 2.3 V respect ivel y.
Pulse Width Modulator
The Pulse Width Modulator consists o f a c omparat or w it h
the oscillator ramp v oltage a pplied to t he n oninverting i nput,
while the error amplifier output is applied into the inverting
input. Output switch conduction is initiated when CT is
discharged to the oscillator valley voltage. As CT charges to
a voltage that exceeds the error amplifier output, the latch
resets, terminating output transistor conduction for the
duration of the oscillator ramp−up period. This PWM/Latch
combination preven ts multip le ou tput pulses during a given
oscillator clock cycle. Fig ures 7 and 1 5 illu strate the switch
output duty cycle versus the compensation voltage.
Current Sense
The MC34166 series utilizes cycle−by−cycle current
limiting as a means of protecting the output switch transistor
from overstress. Each on−cycle is treated as a separate
situation. Current limiting is implemented by monitoring the
output s witch t ransistor c urrent buildup d uring c onduction, a nd
upon sensing an overcurrent condition, immediately turning
off t he s witch f or t he duration o f t he o scillator ramp−up p eriod.
The c ollector c urrent i s c onverted t o a v oltage b y a n internal
trimmed resistor and compared against a reference by the
Current S ense comparator. When t he c urrent l i mit t hres hold i s
reached, the comparator resets the PWM latch. The current
limit threshold is typically set at 4.3 A. Figure 10 illustrates
switch output current limit threshold versus temperature.
Error Amplifier and Reference
A high gain E rror A mplifier is p rovided with a ccess t o t he
inverting i nput a nd output. This a mplifier f eatures a t ypical d c
voltage gain of 8 0 d B , a nd a u nity gain b andwidth of 6 00 kHz
with 7 0 d egrees o f p hase margin ( Figure 4). T he n oninverting
input is biased to the internal 5.05 V reference and is not
pinned o ut. T he r eference h as a n a ccuracy o f ±2.0% a t room
temperature. To provide 5.0 V at the load, the reference is
programmed 50 mV above 5.0 V to compensate for a 1.0%
voltage drop in the cable and connector from the converter
output. If the converter design requires an output voltage
greater than 5.05 V, resistor R1 must be added to form a
divider n etwork a t t he feedback i nput as s hown in F igures 14
and 19. The e quation for determining t he o utput v oltage w ith
the divider network is:
Vout +5.05 ǒR2
R1)1Ǔ
External loop compensation is required for converter
stability. A simple low−pass filter is formed by connecting a
resistor (R2) from the regulated output to the inverting input,
and a series resistor−capacitor (RF, CF) between Pins 1 and 5.
The compensation network component values shown in each
of the applications circuits were selected to provide stability
over t he t ested o perat ing c onditions . T he s tep−down convert er
(Figure 19) is the easiest to compensate for stability. The
step−up (Figure 21) and voltage−inverting (Figure 23)
configurations operate as continuous conduction flyback
converters, a nd a re m ore d i ffic ult t o c ompensat e. T he s impl est
way to optimize the compensation network is to observe the
response of the output voltage to a step load change, while
adjusting RF and CF for critical damping. The final circuit
should be v erified for s tability u nder f our b oundary c onditions.
These condit ions are m ini mum and maximum input vol t ages ,
with min imu m and maximum loads.
By clamping the voltage on the error amplifier output
(Pin 5) to less than 150 mV, the internal circuitry will be
placed into a low power standby mode, reducing the power
supply c urrent t o 3 6 mA w ith a 1 2 V supply v oltage. F igure 1 1
illustrates the standby supply current versus supply voltage.
The Error Amplifier output has a 100 mA current source
pullup that can be used to implement soft−start. Figure 18
shows the current source charging capacitor CSS through a
series diode. The diode disconnects CSS from the feedback
loop when the 1.0 M resistor charges it above the operating
range of Pin 5.
Switch Output
The output transistor is designed to switch a maximum of
40 V, wit h a minimum peak collector current of 3.3 A. When
configured f or step−down or v oltage− inverting a pplications, a s
in Figures 19 and 23, t he inductor w ill forward bi as the output
rectifier when the switch turns off. Rectifiers with a high
forward v oltage d rop o r l ong turn−on delay t ime should n ot be
used. If the emitter is allowed to go sufficiently negative,
collector current will flow, causing additional device heating
and reduced conversion efficiency. Figure 9 shows that by
clamping the emitter to 0.5 V, the collector curren t will be in
the range of 100 mA over temperature. A 1N5822 or