FN6052 Rev.5.00 Page 1 of 19
Nov 21, 2018
FN6052
Rev.5.00
Nov 21, 2018
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
3.3V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers
DATASHEET
These Renesas RS-485/RS-422 devices are BiCMOS 3.3V
powered, single transceivers that meet both the RS-485 and
RS-422 standards for balanced communication. Unlike
competitive devices, this Renesas family is specified for 10%
tolerance supplies (3V to 3.6V).
The ISL83483 and ISL83488 use slew rate limited drivers
which reduce EMI, and minimize reflections from improperly
terminated transmission lines, or unterminated stubs in
multidrop and multipoint applications.
Data rates up to 10Mbps are achievable by using the
ISL83485, ISL83490, or ISL83491, which feature higher
slew rates.
Logic inputs (for example, DI and DE) accept signals in
excess of 5.5V, making them compatible with 5V logic
families.
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high output if Rx inputs are floating. All
devices present a “single unit load” to the RS-485 bus, which
allows up to 32 transceivers on the network.
Driver (Tx) outputs are short-circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
The ISL83488, ISL83490, and ISL83491 are configured for
full duplex (separate Rx input and Tx output pins)
applications. The ISL83488 and ISL83490 are offered in
space saving 8 Ld packages for applications not requiring Rx
and Tx output disable functions (for example, point-to-point
and RS-422). Half duplex configurations (ISL83483,
ISL83485) multiplex the Rx inputs and Tx outputs to provide
transceivers with Rx and Tx disable functions in 8 Ld
packages.
Features
• Operate from a single +3.3V supply (10% tolerance)
• Interoperable with 5V logic
• High data rates. . . . . . . . . . . . . . . . . . . . . . up to 10Mbps
• Single unit load allows up to 32 devices on the bus
• Slew rate limited versions for error free data transmission
(ISL83483, ISL83488) . . . . . . . . . . . . . . . . .up to 250kbps
• Low current Shutdown mode (ISL83483, ISL83485,
ISL83491). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15nA
• -7V to +12V common-mode input voltage range
• Three-state Rx and Tx outputs (except ISL83488,
ISL83490)
• 10ns propagation delay, 1ns skew (ISL83485, ISL83490,
ISL83491)
• Full duplex and half duplex pinouts
• Current limiting and thermal shutdown for driver overload
protection
• Pb-free (RoHS compliant)
Applications
• Factory automation
• Security networks
• Building environmental control systems
• Industrial/process control networks
• Level translators (for example, RS-232 to RS-422)
• RS-232 “Extension Cords”
Related Literature
For a full list of related documents, visit our website:
•ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
device pages
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
HALF/FULL
DUPLEX
DATA RATE
(Mbps)
SLEW-RATE
LIMITED?
RECEIVER/DRIVER
ENABLE?
QUIESCENT ICC
(mA)
LOW POWER
SHUTDOWN? PIN COUNT
ISL83483 Half 0.25 Yes Yes 0.65 Yes 8
ISL83485 Half 10 No Yes 0.65 Yes 8
ISL83488 Full 0.25 Yes No 0.65 No 8
ISL83490 Full 10 No No 0.65 No 8
ISL83491 Full 10 No Yes 0.65 Yes 14
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 2 of 19
Nov 21, 2018
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING TEMP. RANGE (°C)
TAPE AND REEL
(UNITS) (Note 1) PACKAGE
PKG.
DWG. #
ISL83483IBZ 83483 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15
ISL83483IBZ-T 83483 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15
ISL83483IBZ-T7A 83483 IBZ -40 to +85 250 8 Ld SOIC (RoHS compliant) M8.15
ISL83483IP (No longer available or supported) ISL 83483IP -40 to +85 - 8 Ld PDIP E8.3
ISL83485IBZ 83485 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15
ISL83485IBZ-T 83485 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15
ISL83485IBZ-T7A 83485 IBZ -40 to +85 250 8 Ld SOIC (RoHS compliant) M8.15
ISL83488IBZ 83488 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15
ISL83488IBZ-T 83488 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15
ISL83490IBZ 83490 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15
ISL83490IBZ-T 83490 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15
ISL83491IBZ 83491IBZ -40 to +85 - 14 Ld SOIC (RoHS compliant) M14.15
ISL83491IBZ-T 83491IBZ -40 to +85 2.5k 14 Ld SOIC (RoHS compliant) M14.15
ISL83491IBZ-T7A 83491IBZ -40 to +85 250 14 Ld SOIC (RoHS compliant) M14.15
ISL83491IP (No longer available, recommended
replacement: ISL83491IBZ)
ISL83491IP -40 to +85 - 14 Ld PDIP E14.3
NOTES:
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), refer to the ISL83483, ISL83485, ISL83488, ISL83490, and ISL83491 device pages. For more information
about MSL, refer to TB363.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 3 of 19
Nov 21, 2018
Pinouts
ISL83483, ISL83485 (PDIP, SOIC)
TOP VIEW
ISL83488, ISL83490 (SOIC)
TOP VIEW
ISL83491 (PDIP, SOIC)
TOP VIEW
NOTE: PDIP packages are no longer supported
RO
RE
DE
DI
1
2
3
4
8
7
6
5
VCC
B/Z
A/Y
GND
D
R
VCC
RO
DI
GND
1
2
3
4
8
7
6
5
A
B
Z
Y
D
R
NC
RO
RE
DE
DI
GND
GND
VCC
VCC
A
B
Z
Y
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
D
R
Truth Tables
TRANSMITTING
INPUTS OUTPUTS
RE DE DI Z Y
X1101
X1010
0 0 X High-Z High-Z
1 0 X High-Z * High-Z *
NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491
RECEIVING
INPUTS OUTPUT
RE DE
Half Duplex
DE
Full Duplex
A-B RO
0 0 X ≥ +0.2V 1
0 0 X ≤ -0.2V 0
0 0 X Inputs Open 1
100XHigh-Z *
1 1 1 X High-Z
NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491
Pin Descriptions
PIN FUNCTION
RO Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND Ground connection.
A/Y Noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1.
B/Z Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1.
A Noninverting receiver input.
B Inverting receiver input.
Y Noninverting driver output.
Z Inverting driver output.
VCC System power supply input (3V to 3.6V).
NC No Connection.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 4 of 19
Nov 21, 2018
Typical Operating Circuits
For calculating the resistor values refer to TB509, “Detecting Bus Signals Correctly with Failsafe Biased RS-485 Receivers”
FIGURE 1. ISL83483, ISL83485
FIGURE 2. ISL83488, ISL83490
FIGURE 3. ISL83491
3.3V
RB
RT2
RB
VFS
RO
RE
DE
DI
A/Y
B/Z
1
2
3
4
5
GND
VCC
7
6
8100nF
RPU
3.3V
RT1
RO
RE
DE
DI
A/Y
B/Z
1
2
3
4
5
GND
VCC
7
6
8
100nF
RPU
3.3V
RT
RO
DI
A
B
2
3
GND
VCC
7
8
1100nF
RT
4
Z
Y5
6
3.3V
RO
DI
A
B
2
3
GND
VCC
7
8
1
100nF
4
Z
Y5
6
3.3V
RO
DI
A
B
2
5
GND
VCC
11
12
13, 14 100nF
6, 7
Z
Y9
10
3.3V
100nF
RE
DE
3
4
RO
DI
A
B
2
5
GND
VCC
11
10
13,14
6, 7
Z
Y9
12
RE
DE
3
4
RPU
RPU RB
RT
RB
RB
RT
RB
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 5 of 19
Nov 21, 2018
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltages
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input/Output Voltages
A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Short-Circuit Duration
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Conditions
Temperature Range
ISL834xxIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Note 4)θJA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . 140
14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 130
14 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile (SOIC only). . . . . . . . . . . . . . . . . see TB493
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
4. θJA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379.
Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C,
Note 5.
PARAMETER SYMBOL TEST CONDITIONS
TEMP
(°C) MIN TYP MAX UNIT
DC CHARACTERISTICS
Driver Differential VOUT (no load) VOD1 Full - - VCC V
Driver Differential VOUT (with load) VOD2 RL = 100Ω (RS-422) (Figure 4A) Full 2 2.7 - V
RL = 54Ω (RS-485) (Figure 4A) Full 1.5 2.3 VCC V
RL = 60Ω, -7V ≤ VCM ≤ 12V (Figure 4B) Full 1.5 2.6 - V
Change in Magnitude of Driver
Differential VOUT for
Complementary Output States
ΔVOD RL = 54Ω or 100Ω (Figure 4A) Full - 0.01 0.2 V
Driver Common-Mode VOUT VOC RL = 54Ω or 100Ω (Figure 4A) Full - 1.8 3 V
Change in Magnitude of Driver
Common-Mode VOUT for
Complementary Output States
ΔVOC RL = 54Ω or 100Ω (Figure 4A) Full - 0.01 0.2 V
Logic Input High Voltage VIH DE, DI, RE Full 2 - - V
Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V
Logic Input Current IIN1 DE, DI Full -2 - 2 µA
RE Full -25 - 25 µA
Input Current (A, B) IIN2 DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 0.6 1 mA
VIN = -7V Full - -0.3 -0.8 mA
Output Leakage Current (Y, Z)
(ISL83491)
IIN3 RE = 0V, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 14 20 µA
VIN = -7V Full -20 -11 - µA
Output Leakage Current (Y, Z)
in Shutdown Mode (ISL83491)
IIN3 RE = VCC, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 0.03 1 µA
VIN = -7V Full -1 -0.01 - µA
Receiver Differential Threshold
Voltage
VTH -7V ≤ VCM ≤ 12V Full -0.2 - 0.2 V
Receiver Input Hysteresis ΔVTH VCM = 0V +25 - 50 - mV
Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full VCC -
0.4
--V
Receiver Output Low Voltage VOL IO = -4mA, VID = 200mV Full - - 0.4 V
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 6 of 19
Nov 21, 2018
Three-State (high impedance)
Receiver Output Current
IOZR 0.4V ≤ VO ≤ 2.4V Full -1 - 1 µA
Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V Full 12 19 - kΩ
No-Load Supply Current (Note 6)I
CC DI = 0V or VCC DE = VCC,
RE = 0V
or VCC
Full - 0.75 1.2 mA
DE = 0V,
RE = 0V
Full - 0.65 1 mA
Shutdown Supply Current
(Except ISL83488 and ISL83490)
ISHDN DE = 0V, RE = VCC, DI = 0V or VCC Full - 15 100 nA
Driver Short-Circuit Current,
VO = High or Low
IOSD1 DE = VCC, -7V ≤ VY or VZ ≤ 12V (Note 7) Full - - 250 mA
Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC Full 8 - 60 mA
DRIVER SWITCHING CHARACTERISTICS (ISL83485, ISL83490, ISL83491)
Maximum Data Rate fMAX Full 12 15 - Mbps
Driver Differential Output Delay tDD RDIFF = 60Ω, CL = 15pF (Figure 5A) Full 1 10 35 ns
Driver Differential Rise or Fall Time tR, tFRDIFF = 60Ω, CL = 15pF (Figure 5A)Full3520ns
Driver Input to Output Delay tPLH, tPHL RL = 27Ω, CL = 15pF (Figure 5C) Full 6 10 35 ns
Driver Output Skew tSKEW RL = 27Ω, CL = 15pF (Figure 5C)Full-18ns
Driver Enable to Output High
(Except ISL83490)
tZH RL = 110Ω, CL = 50pF, SW = GND (Figure 6),
(Note 8)
Full - 45 90 ns
Driver Enable to Output Low
(Except ISL83490)
tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure 6),
(Note 8)
Full - 45 90 ns
Driver Disable from Output High
(Except ISL83490)
tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure 6)+25- 6580ns
Full - - 110 ns
Driver Disable from Output Low
(Except ISL83490)
tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure 6)+25-6580ns
Full - - 110 ns
Driver Enable from Shutdown to
Output High (Except ISL83490)
tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Figure 6),
(Notes 10, 11)
Full - 115 150 ns
Driver Enable from Shutdown to
Output Low (Except ISL83490)
tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure 6),
(Notes 10, 11)
Full - 115 150 ns
DRIVER SWITCHING CHARACTERISTICS (ISL83483, ISL83488)
Maximum Data Rate fMAX Full 250 - - kbps
Driver Differential Output Delay tDD RDIFF = 60Ω, CL = 15pF (Figure 5A) Full 600 930 1400 ns
Driver Differential Rise or Fall Time tR, tFRDIFF = 60Ω, CL = 15pF (Figure 5A) Full 400 900 1200 ns
Driver Input to Output Delay tPLH, tPHL RL = 27Ω, CL = 15pF (Figure 5C) +25 600 930 1500 ns
Full 400 - 1500 ns
Driver Output Skew tSKEW RL = 27Ω, CL = 15pF (Figure 5C) Full - 140 - ns
Driver Enable to Output High
(Except ISL83488)
tZH RL = 110Ω, CL = 50pF, SW = GND (Figure 6),
(Note 8)
Full - 385 800 ns
Driver Enable to Output Low
(Except ISL83488)
tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure 6),
(Note 8)
Full - 55 800 ns
Driver Disable from Output High
(Except ISL83488)
tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure 6)+25- 6380ns
Full - - 110 ns
Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C,
Note 5. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
TEMP
(°C) MIN TYP MAX UNIT
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 7 of 19
Nov 21, 2018
Driver Disable from Output Low
(Except ISL83488)
tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure 6)+25-7080ns
Full - - 110 ns
Driver Enable from Shutdown to
Output High (Except ISL83488)
tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Notes 10, 11) Full - 450 2000 ns
Driver Enable from Shutdown to
Output Low (Except ISL83488)
tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure 6),
(Notes 10, 11)
Full - 126 2000 ns
RECEIVER SWITCHING CHARACTERISTICS (All Versions)
Receiver Input to Output Delay tPLH, tPHL (Figure 7) Full254590ns
Receiver Skew | tPLH - tPHL | tSKD (Figure 7) +25 - 2 10 ns
Full - 2 12 ns
Receiver Enable to Output High
(Except ISL83488 and ISL83490)
tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure 8),
(Note 9)
Full - 11 50 ns
Receiver Enable to Output Low
(Except ISL83488 and ISL83490)
tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8),
(Note 9)
Full - 11 50 ns
Receiver Disable from Output High
(Except ISL83488 and ISL83490)
tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 8)Full-745ns
Receiver Disable from Output Low
(Except ISL83488 and ISL83490)
tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8)Full-745ns
Time to Shutdown
(Except ISL83488 and ISL83490)
tSHDN (Note 10) Full 80 190 300 ns
Receiver Enable from Shutdown to
Output High
(Except ISL83488 and ISL83490)
tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 8),
(Notes 10, 11)
Full - 240 600 ns
Receiver Enable from Shutdown to
Output Low
(Except ISL83488 and ISL83490)
tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8),
(Notes 10, 11)
Full - 240 600 ns
NOTES:
5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
6. Supply current specification is valid for loaded drivers when DE = 0V.
7. Applies to peak current. See “Typical Performance Curves” on page 11 for more information.
8. When testing the ISL83483, ISL83485, and ISL83491, keep RE = 0 to prevent the device from entering SHDN.
9. When testing the ISL83483, ISL83485, and ISL83491, the RE signal high time must be short enough (typically <100ns) to prevent the device
from entering SHDN.
10. The ISL83483, ISL83485, and ISL83491 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns,
the parts are ensured not to enter shutdown. If the inputs are in this state for at least 300ns, the parts are ensured to have entered shutdown.
See “Low Power Shutdown Mode (ISL83483, ISL83485, ISL83491 Only)” on page 11.
11. Keep RE = VCC, and set the DE signal low time >300ns to ensure that the device enters SHDN.
12. Set the RE signal high time >300ns to ensure that the device enters SHDN.
Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C,
Note 5. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
TEMP
(°C) MIN TYP MAX UNIT
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 8 of 19
Nov 21, 2018
Test Circuits and Waveforms
FIGURE 4A. VOD AND VOC FIGURE 4B. VOD WITH COMMON MODE LOAD
FIGURE 4. DC DRIVER TEST CIRCUITS
FIGURE 5A. DIFFERENTIAL TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5C. SINGLE ENDED TEST CIRCUIT
FIGURE 5. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
D
DE
DI
VCC
VOD
VOC
RL/2
RL/2
Z
Y
D
DE
DI
VCC
VOD
375Ω
375Ω
Z
Y
RL = 60Ω
VCM
-7V to +12V
D
DE
DI
3V
SIGNAL
GENERATOR
CL = 15pF
RDIFF = 60Ω
Z
YCL = 15pF
OUT (Y)
3V
0V
tPLH
1.5V1.5V
VOH
VOL
50% 50%
tPHL
OUT (Z)
tPHL
VOH
VOL
50% 50%
tPLH
DIFF OUT (Y - Z)
tR
+VOD
-VOD
90% 90%
tF
10% 10%
DI
tDD
50%
tDD
50%
SKEW = |tPLH (Y or Z) - tPHL (Z or Y)|
D
DE
DI
3V
SIGNAL
GENERATOR
Z
Y
CL = 15pF
RL = 27Ω
VOM
OUT
VOH + VOL
2
≈1.5VVOM =
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 9 of 19
Nov 21, 2018
FIGURE 6A. TEST CIRCUIT
FIGURE 6B. MEASUREMENT POINTS
FIGURE 6. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS
FIGURE 7. RECEIVER PROPAGATION DELAY
FIGURE 8A. TEST CIRCUIT FIGURE 8B. MEASUREMENT POINTS
FIGURE 8. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
Test Circuits and Waveforms (Continued)
D
DE
DI Z
Y
VCC
GND
SW
PARAMETER OUTPUT RE DI SW
tHZ Y/Z X 1/0 GND
tLZ Y/Z X 0/1 VCC
tZH Y/Z 0 (Note 8)1/0 GND
tZL Y/Z 0 (Note 8)0/1 V
CC
tZH(SHDN) Y/Z 1 (Note 11)1/0 GND
tZL(SHDN) Y/Z 1 (Note 11)0/1 V
CC
SIGNAL
GENERATOR
110Ω
CL = 50pF
OUT (Y, Z)
3V
0V
1.5V1.5V
VOH
0V
VOH - 0.25V
tHZ
OUT (Y, Z)
VCC
VOL
VOL + 0.25V
tLZ
DE
OUTPUT HIGH
OUTPUT LOW
tZL, tZL(SHDN)
tZH, tZH(SHDN)
50%
50%
Note 10
Note 10
Note 10
SIGNAL
GENERATOR
RRO
RE
A
B
GND
+1.5V
15pF
RO
3V
0V
tPLH
1.5V1.5V
VCC
0V
50% 50%
tPHL
A
1kΩ VCC
GND
SW
PARAMETER DE A SW
tHZ 0 +1.5V GND
tLZ 0-1.5VV
CC
tZH (Note 9)0+1.5VGND
tZL (Note 9)0-1.5VV
CC
tZH(SHDN) (Note 12)0 +1.5VGND
tZL(SHDN) (Note 12)0 -1.5VV
CC
SIGNAL
GENERATOR
RRO
RE
A
B
GND
15pF
RO
3V
0V
1.5V1.5V
VOH
0V
1.5V
VOH - 0.25V
tHZ
RO
VCC
VOL
1.5V
VOL + 0.25V
tLZ
RE
OUTPUT HIGH
OUTPUT LOW
tZL, tZL(SHDN)
tZH, tZH(SHDN)
Note 10
Note 10
Note 10
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 10 of 19
Nov 21, 2018
Application Information
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a
point-to-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices) receivers
on each bus. RS-485 is a true multipoint standard, which
allows up to 32 one unit load devices (any combination of
drivers and receivers) on each bus. To allow for multipoint
operation, the RS-485 specification requires that drivers must
handle bus contention without sustaining any damage.
Another important advantage of RS-485 is the extended
Common-Mode Range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as long
as 4000’, so the wide CMR is necessary to handle ground
potential differences, as well as voltages induced in the cable
by external fields.
Receiver Featu r es
These devices use a differential input receiver for maximum
noise immunity and common-mode rejection. Input sensitivity is
±200mV, as required by the RS422 and RS-485 specifications.
Receiver input impedance surpasses the RS-422 spec of 4kΩ,
and meets the RS-485 “Unit Load” requirement of 12kΩ
minimum.
Receiver inputs function with common-mode voltages as great
as +9V/-7V outside the power supplies (that is, +12V and -7V),
making them ideal for long networks where induced voltages
are a realistic concern.
All the receivers include a “fail-safe if open” function that
ensures a high level receiver output if the receiver inputs are
unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver.
ISL83483, ISL83485, ISL83491 receiver outputs are tri-statable
using the active low RE input.
Driver Features
The RS-485, RS-422 driver is a differential output device that
delivers at least 1.5V across a 54Ω load (RS-485), and at least
2V across a 100Ω load (RS-422) even with VCC = 3V. The
drivers feature low propagation delay skew to maximize bit
width, and to minimize EMI.
Drivers of the ISL83483, ISL83485, and ISL83491 are
tri-statable using the active high DE input.
ISL83483 and ISL83488 driver outputs are slew rate limited to
minimize EMI, and to minimize reflections in unterminated or
improperly terminated networks. Data rate on these slew rate
limited versions is a maximum of 250kbps. Outputs of
ISL83485, ISL83490, and ISL83491 drivers are not limited, so
faster output transition times allow data rates of at least
10Mbps.
Data Rate, Cables, and Terminations
RS-485 and RS-422 are intended for network lengths up to
4000’, but the maximum system data rate decreases as the
transmission length increases. Devices operating at 10Mbps
are limited to lengths of a few hundred feet, while the 250kbps
versions can operate at full data rates with lengths in excess of
1000’.
Twisted pair is the cable of choice for RS-485 and RS-422
networks. Twisted pair cables tend to pick up noise and other
electromagnetically induced voltages as common-mode
signals, which are effectively rejected by the differential
receivers in these ICs.
Proper termination is imperative, when using the 10Mbps
devices, to minimize reflections. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120Ω) at the end farthest
from the driver. In multi-receiver applications, stubs connecting
receivers to the main cable should be kept as short as
possible. Multipoint (multi-driver) systems require that the main
cable be terminated in its characteristic impedance at both
ends. Stubs connecting a transceiver to the main cable should
be kept as short as possible.
Built-In Driver Overload Protection
As stated previously, the RS-485 specification requires that
drivers survive worst case bus contentions undamaged. The
ISL834xx devices meet this requirement through driver output
short-circuit current limits, and on-chip thermal shutdown
circuitry.
The driver output stages incorporate short-circuit current
limiting circuitry, which ensures that the output current never
exceeds the RS-485 specification, even at the common-mode
voltage range extremes. Additionally, these devices use a
foldback circuit which reduces the short-circuit current, and
thus the power dissipation, whenever the contending voltage
exceeds either supply.
In the event of a major short-circuit condition, the ISL834xx
devices also include a thermal shutdown feature that disables
the drivers whenever the die temperature becomes excessive.
This eliminates the power dissipation, allowing the die to cool.
The drivers automatically re-enable after the die temperature
drops about 15°. If the contention persists, the thermal
shutdown/re-enable cycle repeats until the fault is cleared.
Receivers stay operational during thermal shutdown.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 11 of 19
Nov 21, 2018
Low Power Shutdown Mode (ISL83483, ISL83485,
ISL83491 Only)
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL83483,
ISL83485, and ISL83491 include a shutdown feature that
reduces the already low quiescent ICC to a 15nA trickle. They
enter shutdown whenever the receiver and driver are
simultaneously disabled (RE =V
CC and DE = GND) for a
period of at least 300ns. Disabling both the driver and the
receiver for less than 80ns ensures that shutdown is not
entered.
Note that receiver and driver enable times increase when
these devices enable from shutdown. For more information
refer to Notes 8 through 12 on page 7 at the end of the
Electrical Specification table.
Typical Performance Curves VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified
FIGURE 9. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 10. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
FIGURE 11. DRIVER OUTPUT CURRENT vs SHORT-CIRCUIT
VOLTAGE
FIGURE 12. SUPPLY CURRENT vs TEMPERATURE
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
00.511.522.533.5
0
10
20
30
40
50
60
70
80
90
100
110
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
-40 0 50 85
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT VOLTAGE (V)
-25 25 75
RDIFF = 54Ω
RDIFF = 100Ω
OUTPUT VOLTAGE (V)
-7 -6 -4 -2 0 2 4 6 8 10 12
OUTPUT CURRENT (mA)
-60
-40
-20
0
20
40
60
80
100
120
140
160
-80
-100
-120
Y OR Z = HIGH
Y OR Z = LOW
-40 0 50 85
TEMPERATURE (°C)
ICC (µA)
-25 25 75
ISL83483/85, DE = VCC, RE = X
ISL83483/85, DE = RE = GND; ISL83491, DE = X, RE = GND;
ISL83488/90
600
650
700
750
800
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 12 of 19
Nov 21, 2018
FIGURE 13. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL83483, ISL83488)
FIGURE 14. DRIVER SKEW vs TEMPERATURE
(ISL83483, ISL83488)
FIGURE 15. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL83485, ISL83490, ISL83491)
FIGURE 16. DRIVER SKEW vs TEMPERATURE
(ISL83485, ISL84390, ISL83491)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL83483, ISL83488)
FIGURE 18. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL83483, ISL83488)
Typical Performance Curves VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued)
-40 0 50 85
TEMPERATURE (°C)
-25 25 75
PROPAGATION DELAY (ns)
700
800
900
1000
1100
1200
tPLHZ
tPHLY
tPLHY
tPHLZ
RDIFF = 54Ω
-40 0 50 85
TEMPERATURE (°C)
SKEW (ns)
-25 25 75
0
50
100
150
200
250
300
|tPLHY - tPHLZ|
|tPHLY - tPLHZ|
|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|
RDIFF = 54Ω
Figure 5A
-40 0 50 85
TEMPERATURE (°C)
-25 25 75
PROPAGATION DELAY (ns)
8
9
10
11
12
13
14
15
16
tPHLY
tPHLZ
tPLHZ
tPHLY
tPLHY
RDIFF = 54Ω
-40 0 50 85
TEMPERATURE (°C)
SKEW (ns)
-25 25 75
0.5
1
1.5
2
2.5
3
3.5
4
|tPLHY - tPHLZ|
|tPHLY - tPLHZ|
|CROSSING PT. OF Y↑ & Z↓ -
CROSSING PT. OF Y↓ & Z↑|
RDIFF = 54Ω
Figure 5A
TIME (400ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V)
DI
RO
0
0.5
1
1.5
2
2.5
3
B/Z
A/Y
TIME (400ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V)
DI
RO
0
0.5
1
1.5
2
2.5
3
B/Z
A/Y
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 13 of 19
Nov 21, 2018
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
528
PROCESS:
Si Gate CMOS
FIGURE 19. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL83485, ISL83490, ISL83491)
FIGURE 20. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL83485, ISL83490, ISL83491)
Typical Performance Curves VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued)
TIME (10ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V)
DI
RO
0
0.5
1
1.5
2
2.5
3
B/Z
A/Y
TIME (10ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V)
DI
RO
0
0.5
1
1.5
2
2.5
3
A/Y
B/Z
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 14 of 19
Nov 21, 2018
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please
visit our website to make sure you have the latest revision.
DATE REVISION CHANGE
Nov 21, 2018 FN6052.5 Updated part marking in the ordering information table to represent what the brand has been on the products.
Added PDIP note in the thermal information section and specified the Pb-free reflow note is applicable to SOIC
pages only.
Updated disclaimer.
Jul 27, 2018 FN6052.4 Added Related Literature on page 1.
Updated Ordering Information table.
Removed Retired parts, added tape and reel quantity column, and added MSL note.
Updated Typical Operating Circuits on page 4.
Thermal Information on page 5:
Removed Maximum Lead Temperature (Soldering 10s)+300°C (SOIC - Lead Tips Only)
Added Pb-Free Reflow information
Updated POD M8.15 from rev 0 to rev 4. Changes since rev 0:
Removed "u" symbol from drawing (overlaps the "a" on Side View).
Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changed Note 1 "1982" to "1994"
Updated POD M14.15 from rev 0 to rev 1. Changes since rev 0:
Added land pattern and moved dimensions from table onto drawing
Added Revision History.
Updated disclaimer.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 15 of 19
Nov 21, 2018
Package Outline Drawings
eA
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
For the most recent package outline drawing, see E8.3.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 16 of 19
Nov 21, 2018
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen-
dicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N14 149
Rev. 0 12/93
For the most recent package outline drawing, see E14.3.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 17 of 19
Nov 21, 2018
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
8°
0°
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
45
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)
For the most recent package outline drawing, see M8.15.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
FN6052 Rev.5.00 Page 18 of 19
Nov 21, 2018
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
A
D
4
0.25 A-BMC
C
0.10 C
5B
D
3
0.10 A-BC
4
0.20 C 2X
2X
0.10 DC 2X
H
0.10 C
6
36
ID MARK
PIN NO.1 (0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
1.27
0.31-0.51
4° ± 4°
DETAIL"A" 0.22±0.03
0.10-0.25
1.25 MIN
1.75 MAX
(1.27) (0.6)
6.0
8.65
3.9
7
14 8
Dimensioning and tolerancing conform to AMSEY14.5m-1994.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Datums A and B to be determined at Datum H.
4.
5.
3.
2.
Dimensions are in millimeters.
NOTES:
1.
The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
7. Reference to JEDEC MS-012-AB.
shall be 0.10mm total in excess of lead width at maximum condition.
DETAIL "A"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
For the most recent package outline drawing, see M14.15.
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Notice
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"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
All trademarks and registered trademarks are the property of their respective owners.