EVALUATION KIT AVAILABLE MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs General Description The MAX17058/MAX17059 ICs are tiny fuel gauges for lithium-ion (Li+) batteries in handheld and portable equipment. The MAX17058 operates with a single Li+ cell and the MAX17059 with two Li+ cells in series. The ICs use the sophisticated Li+ battery-modeling algorithm ModelGaugeK to track the battery relative state-of-charge (SOC) continuously over a widely varying charge/discharge conditions. The ModelGauge algorithm eliminates current-sense resistor and battery-learn cycles required by other fuel gauges. Temperature compensation is implemented using the system microcontroller. On battery insertion, the ICs debounce initial voltage measurements to improve the initial SOC estimate, allowing them to be located on system side. SOC and voltage information is accessed using the I2C interface. The ICs are available in a tiny 0.9mm x 1.7mm, 8-bump wafer-level package (WLP) or a 2mm x 2mm, 8-pin TDFN package. Applications Wireless Handsets Smartphones/PDAs Features and Benefits S MAX17058: 1 Cell, MAX17059: 2 Cells S Precision 7.5mV/Cell Voltage Measurement S ModelGauge Algorithm Provides Accurate State-of-Charge Compensates for Temperature/Load Variation Does Not Accumulate Errors, Unlike Coulomb Counters Eliminates Learning Eliminates Current-Sense Resistor S Low Quiescent Current: 23A S Battery-Insertion Debounce Best of 16 Samples Estimates Initial SOC S Programmable Reset for Battery Swap 2.28V to 3.48V Range S Low SOC Alert Indicator S I2C Interface Ordering Information appears at end of data sheet. Simplified Operating Circuit Tablets and Handheld Computers Portable Game Players e-Readers MAX17058 Digital Still and Video Cameras Portable Medical Equipment ONLY ONE EXTERNAL COMPONENT VDD ALRT CELL SDA CTG SCL GND QSTRT SYSTEM P ModelGauge is a trademark of Maxim Integrated Products, Inc. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maximintegrated.com. 19-6172; Rev 5; 8/13 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs ABSOLUTE MAXIMUM RATINGS Storage Temperature Range............................. -55NC to +125NC Lead Temperature (TDFN only) (soldering, 10s) ............+300NC Soldering Temperature (reflow).......................................+260NC CELL to GND..........................................................-0.3V to +12V All Pins (excluding CELL) to GND...........................-0.3V to +6V Continuous Sink Current, SDA, ALRT.................................20mA Operating Temperature Range........................... -40NC to +85NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (2.5V < VDD < 4.5V, -20NC < TA < +70NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Supply Voltage Fuel-Gauge SOC Reset (VRESET Register) Data I/O Pins Supply Current Time Base Accuracy SYMBOL VDD VRST SCL, SDA, ALRT IDD0 MIN (Note 2) Configuration range, in 40mV steps Trimmed at 3V 2.85 (Note 2) -0.3 IDD1 Sleep mode, TA < +50NC Active mode tERR Active mode (Note 3) ADC Sample Period Voltage Error CONDITIONS MAX UNITS 2.5 4.5 V 2.28 3.48 V 3.15 V +5.5 V -3.5 Active mode VERR 3.0 0.5 2 23 40 Q1 +3.5 250 -7.5 +7.5 -20NC < TA < +70NC -20 +20 MAX17058: VDD pin MAX17059: CELL pin 2.5 5 5 10 1.25 Voltage-Measurement Range SDA, SCL, QSTRT Input Logic-High VIH SDA, SCL, QSTRT Input Logic-Low VIL SDA, ALRT Output Logic-Low VOL IOL = 4mA SDA, SCL Bus Low-Detection Current IPD VSDA = VSCL = 0.4V (Note 5) tSLEEP % mV/cell mV/cell 1.4 (Note 6) FA ms VCELL = 3.6V, TA = +25NC (Note 4) Voltage-Measurement Resolution Bus Low-Detection Timeout TYP V V 0.2 1.75 0.5 V 0.4 V 0.4 FA 2.5 s MAX UNITS 400 kHz ELECTRICAL CHARACTERISTICS (I2C INTERFACE) (2.5V < VDD < 4.5V, -20NC < TA < +70NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL SCL Clock Frequency fSCL Bus Free Time Between a STOP and START Condition tBUF START Condition (Repeated) Hold Time Low Period of SCL Clock Maxim Integrated tHD:STA tLOW CONDITIONS (Note 7) (Note 8) MIN 0 TYP 1.3 Fs 0.6 Fs 1.3 Fs 2 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs ELECTRICAL CHARACTERISTICS (I2C INTERFACE) (continued) (2.5V < VDD < 4.5V, -20NC < TA < +70NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS tHIGH 0.6 Fs Setup Time for a Repeated START Condition tSU:STA 0.6 Fs Data Hold Time tHD:DAT (Notes 9, 10) Data Setup Time tSU:DAT (Note 9) High Period of SCL Clock 0 0.9 100 Fs ns Rise Time of Both SDA and SCL Signals tR 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 Spike Pulse Widths Suppressed by Input Filter tSP (Note 11) Capacitive Load for Each Bus Line CB (Note 12) Fs 0.6 50 ns 400 pF SCL, SDA Input Capacitance CB,IN 60 pF Note 1: Specifications are tested 100% at TA = +25NC. Limits over the operating range are guaranteed by design and characterization. Note 2: All voltages are referenced to GND. Note 3: Test is performed on unmounted/unsoldered ports. Note 4: The voltage is trimmed and verified with 16x averaging. Note 5: This current is always present. Note 6: The IC enters sleep mode after SCL < VIL and SDA < VIL for longer than 2.5s. Note 7: Timing must be fast enough to prevent the IC from entering sleep mode due to bus low for period > tSLEEP. Note 8: fSCL must meet the minimum clock low time plus the rise/fall times. Note 9: The maximum tHD:DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal. Note 10: This device internally provides a hold time of at least 100ns for the SDA signal (referred to the VIH,MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 11: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instance. Note 12: CB is total capacitance of one bus line in pF. SDA tF tLOW tSU:DAT tR tSP tF tR tBUF tHD:STA SCL tHD:STA S tHD:DAT tSU:STA tSU:STO Sr P S Figure 1. I2C Bus Timing Diagram Maxim Integrated 3 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Typical Operating Characteristics (TA = +25NC, battery is Sanyo UF504553F, unless otherwise noted.) QUIESCENT CURRENT vs. SUPPLY VOLTAGE (ACTIVE MODE) VOLTAGE ADC ERROR vs. TEMPERATURE 25 20 TA = +25C 15 TA = -20C 10 MAX17058 toc02 TA = +70C VOLTAGE ADC ERROR (mV/CELL) 15 10 VCELL = 4.5V 5 0 -5 VCELL = 3.6V -10 VCELL = 2.5V -15 5 -20 0 2.5 3.0 3.5 -5 -20 4.5 4.0 VCELL (V) SOC ACCURACY TA = 0C REFERENCE SOC MODELGAUGE SOC REFERENCE SOC 40 55 70 MODELGAUGE ERROR MAX17058 toc04 10 100 75 5 75 5 50 0 50 0 25 -5 25 -5 -10 0 0 0 2 4 6 8 SOC (%) ERROR (%) SOC (%) 25 SOC ACCURACY TA = +20C ERROR MAX17058 toc03 100 10 TEMPERATURE (C) 10 10 ERROR (%) QUIESCENT CURRENT (A) 35 30 20 MAX17058 toc01 40 -10 0 -2 TIME (Hr) 2 4 6 8 10 TIME (Hr) MODELGAUGE SOC SOC (%) ERROR MAX17058 toc05 100 10 75 5 50 0 25 -5 0 ERROR (%) SOC ACCURACY TA = +40C REFERENCE SOC -10 0 2 4 6 8 10 TIME (Hr) Maxim Integrated 4 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Typical Operating Characteristics (continued) (TA = +25NC, battery is Sanyo UF504553F, unless otherwise noted.) MODELGAUGE SOC MAX17058 toc06 REFERENCE SOC MODELGAUGE SOC 75 5 75 5 50 0 50 0 25 -5 25 -5 -10 0 0 20 40 60 80 SOC (%) 100 0 2 4 NO ERROR ACCUMULATED AFTER 100 HOURS 10 MAX17058 toc09 VCELL 75 5 50 0 25 -5 0 -10 97 99 101 TIME (Hr) Maxim Integrated 103 105 OCV 0V 0V 0V 0A 95 10 8 BATTERY-INSERTION DEBOUNCE/ OCV ACQUISITION ERROR ERROR (%) MODELGAUGE SOC MAX17058 toc08 100 6 TIME (Hr) ZIGZAG PATTERN SOC ACCURACY (3/3) REFERENCE SOC 10 -10 0 100 TIME (Hr) SOC (%) ERROR MAX17058 toc07 10 ERROR (%) SOC (%) 100 ZIGZAG PATTERN SOC ACCURACY (2/3) ERROR ERROR (%) ZIGZAG PATTERN SOC ACCURACY (1/3) REFERENCE SOC DEBOUNCE BEGINS DEBOUNCE COMPLETED 4ms/div 5 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Pin/Bump Configurations TOP VIEW (PAD SIDE DOWN) TOP VIEW (BUMP SIDE DOWN) SCL QSTRT ALRT 8 7 6 5 MAX17058 MAX17059 + SDA CTG CELL VDD GND A1 A2 A3 A4 SDA SCL QSTRT ALRT B1 B2 B3 B4 MAX17058 MAX17059 EP + 1 2 3 4 CTG CELL VDD GND WLP TDFN Pin/Bump Description PIN/BUMP NAME FUNCTION TDFN WLP 1 A1 CTG Connect to GND 1 A2 CELL Connect to Positive Battery Terminal. MAX17058: Not connected internally. MAX17059: Voltage-sense input. 3 A3 VDD Power-Supply Input. Bypass with 0.1FF to GND. MAX17058: Voltage-sense input. Connect to a positive battery terminal. MAX17059: Connect to a regulated power-supply voltage. 4 A4 GND Ground. Connect to a negative battery terminal. 5 B4 ALRT Open-Drain, Active-Low Alert Output. Optionally connect to the interrupt input of the system microcontroller. 6 B3 QSTRT 7 B2 SCL I2C Clock Input. SCL has an internal pulldown (IPD) for sensing disconnection. 8 B1 SDA Open-Drain I2C Data Input/Output. SDA has an internal pulldown (IPD) for sensing disconnection. -- -- EP Maxim Integrated Quick-Start Input. Resets state-of-charge calculation. Connect to GND if not used. Exposed Pad (TDFN Only). Connect to GND. 6 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs ModelGauge Theory of Operation The MAX17058/MAX17059 ICs simulate the internal, nonlinear dynamics of a Li+ battery to determine its state of charge (SOC). The sophisticated battery model considers impedance and the slow rate of chemical reactions in the battery (Figure 2). The ModelGauge algorithm performs best with a custom model, obtained by characterizing the battery at multiple discharge currents and temperatures to precisely model it. Contact Maxim if you need a custom model. At poweron reset (POR), the ICs have a preloaded ROM model that performs well for some batteries. Fuel-Gauge Performance In coulomb counter-based fuel gauges, SOC drifts because offset error in the current-sense ADC measurement accumulates over time. Instantaneous error can be very small, but never precisely zero. Error accumulates over time in such systems (typically 0.5%-2% per day) and requires periodic corrections. Some algorithms correct drift using occasional events, and until such an event occurs the algorithm's error is boundless: * Reaching predefined SOC levels near full or empty * Measuring the relaxed battery voltage after a long period of inactivity * Completing a full charge/discharge cycle The ModelGauge algorithm requires no correction events because it uses only voltage, which is stable over time. As the SOC accuracy without full/empty/relax shows the algorithm remains accurate despite the absence of any of the above events; it neither drifts nor accumulates error over time. To correctly measure performance of a fuel gauge as experienced by end-users, exercise the battery dynamically; accuracy cannot be fully determined from only simple cycles. Battery Voltage and State-of-Charge The open-circuit voltage (OCV) of a Li+ battery uniquely determines its SOC; one SOC can have only one value of OCV. In contrast, a given VCELL can occur at many different values of OCV because VCELL is a function of time, OCV, load, temperature, age, and impedance, etc.; one value of OCV can have many values of VCELL. Therefore, one SOC can have many values of VCELL, so VCELL cannot uniquely determine SOC. Figure 3 shows that VCELL = 3.81V occurs at 2%, 50%, and 72% SOC. Even the use of sophisticated tables to consider both voltage and load results in significant error due to the load transients typically experienced in a system. During charging or discharging, and for approximately 30min after, VCELL and OCV differ substantially, and VCELL has been affected by the preceding hours of battery activity. ModelGauge uses voltage comprehensively by using voltage measured over a long period of time. VDD VOLTAGE REFERENCE CELL GND IC GROUND ALRT 3.6V 3.4V 3.81V = 50% 80% QSTRT SOC ADC (VCELL) 3.8V 3.81V = 72% 3.81V = 2% 100% STATE MACHINE (SOC) 4.0V 3.81V TIME BASE (32kHz) BIAS 4.2V VCELL MAX17058 MAX17059 60% VCELL Detailed Description 3.2V SOC 40% 20% I2C INTERFACE SDA SCL 0% 0 1 2 3 4 5 6 7 8 TIME (Hr) Figure 2. Block Diagram Maxim Integrated Figure 3. Instantaneous Voltage Does Not Translate Directly to SOC 7 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Temperature Compensation For best performance, the host microcontroller must measure battery temperature periodically, and compensate the RCOMP ModelGauge parameter accordingly, at least once per minute. Each custom model defines constants RCOMP0 (default is 0x97), TempCoUp (default is -0.5), and TempCoDown (default is -5.0). To calculate the new value of CONFIG.RCOMP: // T is battery temperature (degrees Celsius) if (T > 20) { RCOMP = RCOMP0 + (T - 20) x TempCoUp; } else { RCOMP = RCMOP0 + (T - 20) x TempCoDown; } 60 C/3 LOAD CAPACITY LOST (%) 50 40 30 20 10 C/10 LOAD 0 3.0 3.1 3.2 3.3 3.4 3.5 TARGET EMPTY VOLTAGE (V) Figure 4. Increasing Empty Voltage Reduces Battery Capacity Impact of Empty-Voltage Selection Most applications have a minimum operating voltage below which the system immediately powers off (empty voltage). When characterizing the battery to create a custom model, choose empty voltage carefully. As shown in Figure 4, capacity unavailable to the system increases at an accelerating rate as empty voltage increases. To ensure a controlled shutdown, consider including operating margin into the fuel gauge based on some low threshold of SOC, for example, shutting down at 3% or 5%. This utilizes the battery more effectively than adding error margin to empty voltage. Battery Insertion When the battery is first inserted into the system, the fuel-gauge IC has no previous knowledge about the battery's SOC. Assuming that the battery is relaxed, the IC translates its first VCELL measurement into the best initial estimate of SOC. Initial error caused by the battery not being in a relaxed state diminishes over time, regardless of loading following this initial conversion. While the SOC estimated by the coulomb counter diverges, the ModelGauge SOC converges, correcting error automatically as illustrated in Figure 5; initial error has no longlasting impact. Battery-Insertion Debounce Any time the IC powers on or resets (see the VRESET Register (0x18) section), it estimates that OCV is the maximum of 16 VCELL samples (1ms each, full 12-bit resolution). OCV is ready 17ms after battery insertion, and SOC is ready 175ms after that. LONGER BATTERY RELAXATION IMPROVES INITIAL ACCURACY MODELGAUGE HEALS ERROR AUTOMATICALLY OVER TIME 45% UNRELAXED ERROR -10mV -5% VOLTAGE ERROR -20mV 0.1 1 0% 10 100 -10% 1000 RELAXATION TIME BEFORE INSERTION (MINUTES) 30% SOC 0% 0mV SOC SOC ERROR SOC ERROR (%) INITIAL VOLTAGE ERROR (mV) RELAXED ERROR REFERENCE SOC RELAXED SOC -5% 15% UNRELAXED SOC -10% 0 20 0% 40 60 80 TIME AFTER INSERTION (MINUTES) Figure 5. ModelGauge Heals Error Automatically Maxim Integrated 8 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Battery-Swap Detection If VCELL falls below VRST then returns above VRST, the IC quick-starts. This handles the battery swap; the SOC of the previous battery doesn not affect that of the new one. See the Quick-Start and VRESET Register (0x18) sections. Figure 7 illustrates a waveform that could corrupt the initial SOC. If the disturbance is severe, quick-start after the inrush current has stopped and voltage has settled, but before the system is fully powered. If issued too soon or too late, a quick-start causes SOC error. Quick-Start Large inrush current might reduce VCELL longer than the initial sampling period. Issue a quick-start so that VCELL is nearest OCV during the 17ms following the command. If the IC generates an erroneous initial SOC, the battery insertion and system power-up waveforms must be examined to determine if a quick-start is necessary, as well as the best time to execute the command. The IC samples the maximum VCELL during the first 17ms (see the Battery Insertion section). Unless VCELL is fully relaxed, even the best sampled voltage can appear greater or less than OCV. Therefore, quick-start must be used cautiously. Most systems should not use quick-start because the ICs handle most startup problems transparently, such as intermittent battery-terminal connection during insertion. If battery voltage stabilizes faster than 17ms, as illustrated in Figure 6, then do not use quick-start. The quick-start command restarts fuel-gauge calculations in the same manner as initial power-up of the IC. If the system power-up sequence is so noisy that the initial estimate of SOC has unacceptable error, the system microcontroller might be able to reduce the error by using quick-start. A quick-start is initiated by a rising edge on the QSTRT pin, or by writing 1 to the quick-start bit on the MODE register. If the IC remains powered by a charger when the cell is removed, then it continues to measure the charge voltage even though the cell is not present. When the cell is reinserted, quick-start before the charger affects VCELL. Power-On Reset (POR) POR includes a quick-start, so only use it for when a quick-start is safe (see the Quick-Start section). This command restores all registers to their default values. After this command, reload the custom model. See the CMD Register (0xFE) section. Alert Interrupt The ICs can interrupt a system microcontroller when SOC becomes low. See the CONFIG Register (0x0C) and STATUS Register (0x1A) sections. When the alert is triggered, the IC asserts the ALRT pin logic-low and sets CONFIG.ALRT = 1. The ALRT pin remains logic-low until the system writes CONFIG.ALRT = 0 to clear the alert. The alert function is enabled by default and can occur immediately upon power-up. Entering sleep mode does not clear the ALRT bit or the ALRT pin. VCELL STEADY SYSTEM LOAD BEGINS VCELL STEADY SYSTEM LOAD BEGINS VCELL HAS FULLY RELAXED 17ms TIME INITIAL SAMPLE DEBOUNCE WINDOW Figure 6. Insertion Waveform Not Requiring Quick-Start Command Maxim Integrated BEST TIME TO QUICK-START VCELL HAS FULLY RELAXED 17ms INITIAL SAMPLE DEBOUNCE WINDOW TIME QUICK-START DURING THIS TIME SPAN Figure 7. Insertion Waveform Requiring Quick-Start Command 9 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Sleep Mode VCELL Register (0x02) In sleep mode, the IC halts all operations, reducing current consumption (below 1FA). After exiting sleep mode, the IC continues normal operation. In sleep mode, the IC does not detect self-discharge. If the battery changes state while the IC sleeps, the IC cannot detect it, causing SOC error. Wake up the IC before charging or discharging. To enter sleep mode, either: * Hold SDA and SCL logic-low for a period of tSLEEP. A rising edge on SDA or SCL wakes up the IC. * Write CONFIG.SLEEP = 1. To wake up the IC, write CONFIG.SLEEP = 0. Other communication does not wake up the IC. POR wakes up the IC. The MAX17058 measures VCELL between the VDD and GND pins. The MAX17059 measures VCELL between the CELL and GND pins. The register value is the average of four ADC conversions. The value updates every 250ms in active mode. Register Summary The MODE register allows the system processor to send special commands to the IC (see Figure 8). SOC Register (0x04) The ModelGauge algorithm calculates relative SOC, automatically adapting to variation in battery size. The upper byte least-significant bit has units of 1%. The first update is available approximately 1s after POR. Subsequent updates occur at variable intervals depending on application conditions. MODE Register (0x06) All registers must be written and read as 16-bit words; 8-bit writes cause no effect. Any bits marked X (don't care) or read only must be written with the rest of the register, but the value written is ignored by the IC. The values read from don't care bits are undefined. Calculate the register's value by multiplying the 16-bit word by the register's LSb value, as shown in Table 1. * Quick-Start estimates SOC assuming OCV is equal to immediate VCELL. Use with caution; see the QuickStart section. Table 1. Register Summary ADDRESS REGISTER NAME 16-BIT LSb 0x02 VCELL 78.125 FV/cell READ/WRITE DEFAULT ADC measurement of VCELL. Battery state of charge. 0x04 SOC 1%/256 0x06 MODE 0x08 DESCRIPTION R -- R -- -- Initiates quick-start and enables sleep mode. W 0x0000 VERSION -- IC production version. R 0x001_ 0x0C CONFIG -- Compensation to optimize performance, sleep mode, alert indicators, and configuration. R/W 0x971C 0x18 VRESET -- Configures VCELL threshold below which the IC resets itself. R/W 0x96__ 0x01__ 0x1A STATUS -- Low SOC alert and reset indicators. R/W 0x40 to 0x7F TABLE -- Configures the battery parameters. W -- 0xFE CMD -- Sends POR command. R/W 0xFFFF MSB--ADDRESS 0x06 X QuickStart X X MSb X X LSB--ADDRESS 0x07 X X X LSb MSb X X X X X X X LSb Figure 8. MODE Register Format Maxim Integrated 10 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs 31%, 00010b 30%, 11111b 1%). the POR value of ATHD is 0x1C or 4%. The alert occurs only on a falling edge past this threshold. VERSION Register (0x08) The value of this read-only register indicates the production version of the IC (0x001_). CONFIG Register (0x0C) See Figure 9. * RCOMP compensates the model for different lithium chemistries. The system must adjust RCOMP periodically (see the Temperature Compensation section). The POR value of RCOMP is 0x97. * SLEEP forces the IC in or out of sleep mode. Writing 1 forces the IC to enter sleep mode, and 0 forces the IC to exit. The POR value of SLEEP is 0. Use with caution (see the Sleep Mode section). * * VRESET Register (0x18) See Figure 10. * VRESET[7:1] adjusts a fast analog comparator and a slower digital ADC threshold to detect battery removal and reinsertion. Set between 2.28V and 3.48V, 40mV to 80mV below the application's empty voltage according to the desired reset threshold for your application. If the comparator is enabled, the IC resets 1ms after VCELL rises above the threshold. Otherwise, the IC resets 250ms after the VCELL register rises above the threshold. ALRT (alert status bit) is set by the IC when SOC becomes low. When this bit is set, the ALRT pin asserts low. Clear to deassert the ALRT pin. The POR value is 0 (see the Alert Interrupt section). See Figure 11. ATHD (empty alert threshold) sets the SOC threshold, where an interrupt is generated on the ALRT pin and can be programmed from 1% up to 32%. The value is (32 - ATHD)% (e.g., 00000b 32% 00001b U RI (reset indicator) is set when the device powers up. Any time this bit is set, the IC is not configured, so the custom model and any other configuration must be immediately reloaded and the bit should be cleared. STATUS Register (0x1A) MSB (RCOMP)--ADDRESS 0x0C LSB--ADDRESS 0x0D RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP 7 6 5 4 3 2 1 0 SLEEP MSb MSb LSb X ALRT ATHD LSb Figure 9. CONFIG Register Format MSB (VRESET)--ADDRESS 0x18 26 25 24 23 22 21 20 MSb LSB (ID)--ADDRESS 0x19 Dis ID7 LSb MSb ID6 ID5 ID4 ID3 ID2 ID1 ID0 LSb VRESET 20 Units: 40mV Figure 10. VRESET Register Format MSB--ADDRESS 0x1A X X X HD MSb X X LSB--ADDRESS 0x1B X RI X LSb MSb X X X X X X X LSb Figure 11. STATUS Register Format Maxim Integrated 11 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs TABLE Registers (0x40 to 0x7F) Contact Maxim for details on how to configure these registers. The default value is appropriate for some Li+ batteries. To unlock the TABLE registers, write 0x57 to address 0x3F, and 0x4A to address 0x3E. While the TABLE is unlocked, no ModelGauge registers are updated, so relock as soon as possible by writing 0x00 to address 0x3F, and 0x00 to address 0x3E. CMD Register (0xFE) Writing a value of 0x5400 to this register causes the device to completely reset as if power had been removed. Use with caution (see the Power-On Reset (POR) section). The reset occurs when the last bit has been clocked in. The IC does not respond with an I2C ACK after this command sequence. Application Examples The ICs have a variety of configurations, depending on the application. Table 2 shows the most common system configurations and the proper pin connections for each. In all cases, the system must provide pullup circuits for ALRT (if used), SDA, and SCL. Figure 12 shows an example application for a 1S cell pack. In this example, the ALRT pin is connected to the microcontroller's interrupt input so the MAX17058 indicates when the battery becomes low. The QSTRT pin is unused in this application and is connected to GND. Figure 13 shows a MAX17059 example application using a 2S cell pack. The MAX17059 is mounted on the system side and powered from a 3.3V supply generated by the system. The CELL pin is still connected directly to PACK+. Table 2. Possible Application Configurations SYSTEM CONFIGURATION IC VDD ALRT QSTRT 1S pack-side location MAX17058 Power directly from battery Leave unconnected Connect to GND 1S host-side location MAX17058 Power directly from battery Leave unconnected Connect to GND 1S host-side location, low-cell interrupt MAX17058 Power directly from battery Connect to system interrupt Connect to GND 1S host-side location, hardware quick-start MAX17058 Power directly from battery Leave unconnected Connect to rising-edge reset signal 2S pack-side location MAX17059 Power from +2.5V to +4.5V LDO in pack Leave unconnected Connect to GND 2S host-side location MAX17059 Power from +2.5V to +4.5V LDO or PMIC Leave unconnected Connect to GND 2S host-side location, low-cell interrupt MAX17059 Power from +2.5V to +4.5V LDO or PMIC Connect to system interrupt Connect to GND 2S host-side location, hardware quick-start MAX17059 Power from +2.5V to +4.5V LDO or PMIC Leave unconnected Connect to rising-edge reset signal 2.5V TO 4.5V OUTPUT FROM SYSTEM BATTERY PACK MAX17058 0.1F PROTECTION VDD ALRT CELL SDA CTG SCL GND SYSTEM P BATTERY PACK INTERRUPT I2C BUS MASTER 0.1F QSTRT PROTECTION NOTE: SYSTEM REQUIRED TO PROVIDE PULLUP CIRCUITS FOR ALRT, SDA, AND SCL. Figure 12. MAX17058 Application Circuit (1S Cell Pack) Maxim Integrated MAX17059 VDD ALRT CELL SDA CTG SCL GND QSTRT SYSTEM P INTERRUPT I2C BUS MASTER NOTE: SYSTEM REQUIRED TO PROVIDE PULLUP CIRCUITS FOR ALRT, SDA, AND SCL. Figure 13. MAX17059 Application Circuit (2S Cell Pack) 12 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs I2C Bus System The I2C bus system supports operation as a slave-only device in a single or multislave, and single or multimaster system. Slave devices can share the bus by uniquely setting the 7-bit slave address. The I2C interface consists of a serial-data line (SDA) and serialclock line (SCL). SDA and SCL provide bidirectional communication between the ICs slave device and a master device at speeds up to 400kHz. The ICs' SDA pin operates bidirectionally; that is, when the ICs receive data, SDA operates as an input, and when the ICs return data, SDA operates as an open-drain output, with the host system providing a resistive pullup. The ICs always operate as a slave device, receiving and transmitting data under the control of a master device. The master initiates all transactions on the bus and generates the SCL signal, as well as the START and STOP bits, which begin and end each transaction. Bit Transfer One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any change in SDA when SCL is high is interpreted as a START or STOP control signal. Bus Idle The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high when the bus is idle. The STOP condition is the proper method to return the bus to the idle state. START and STOP Conditions The master initiates transactions with a START condition (S) by forcing a high-to-low transition on SDA while SCL is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one transaction and begin another without returning the bus to the idle state. In multimaster systems, a Repeated START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities in which the SDA transitions when SCL is high. Maxim Integrated Acknowledge Bits Each byte of a data transfer is acknowledged with an acknowledge bit (A) or a no-acknowledge bit (N). Both the master and the MAX17058/MAX17059 slave generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL returns low. To generate a no-acknowledge (also called NAK), the receiver releases SDA before the rising edge of the acknowledgerelated clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication. Data Order A byte of data consists of 8 bits ordered most significant bit (MSb) first. The least significant bit (LSb) of each byte is followed by the acknowledge bit. The IC registers composed of multibyte values are ordered MSb first. The MSb of multibyte registers is stored on even datamemory addresses. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a slave address (SAddr) and the read/write (R/W) bit. When the bus is idle, the ICs continuously monitor for a START condition followed by its slave address. When the ICs receive a slave address that matches the value in the slave address register, they respond with an acknowledge bit during the clock period following the R/W bit. The 7-bit slave address is fixed to 6Ch (write)/6Dh (read): MAX17058 /MAX17059 SLAVE ADDRESS 0110110 Read/Write Bit The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0 selects a write transaction with the following bytes being written by the master to the slave. R/W = 1 selects a read transaction with the following bytes being read from the slave by the master (Table 3). 13 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Table 3. I2C Protocol Key KEY DESCRIPTION S KEY DESCRIPTION START bit Sr Repeated START SAddr Slave address (7 bit) W R/W bit = 0 MAddr Memory address byte P STOP bit Data Data byte written by master Data Data byte returned by slave A Acknowledge bit--master A Acknowledge bit--slave N No acknowledge--master N No acknowledge bit--slave Bus Timing The ICs are compatible with any bus timing up to 400kHz. No special configuration is required to operate at any speed. I2C Command Protocols The command protocols involve several transaction formats. The simplest format consists of the master writing the START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the ICs. More complex formats, such as the Write Data and Read Data, read data and execute device-specific operations. All bytes in each command format require the slave or host to return an acknowledge bit before continuing with the next byte. Table 3 shows the key that applies to the transaction formats. Basic Transaction Formats Write: S. SAddr W. A. MAddr. A. Data0. A. Data1. A. P A write transaction transfers 2 or more data bytes to the ICs. The data transfer begins at the memory address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the transaction, except for the acknowledge cycles: Read: S. SAddr W. A. MAddr. A. Sr. SAddr R. A. Data0. A. Data1. N. P Write Portion Read Portion A read transaction transfers 2 or more bytes from the ICs. Read transactions are composed of two parts, a write portion followed by a read portion, and are therefore inherently longer than a write transaction. The write portion communicates the starting point for the Maxim Integrated read operation. The read portion follows immediately, beginning with a Repeated START, slave address with R/W set to a 1. Control of SDA is assumed by the ICs, beginning with the slave address acknowledge cycle. Control of the SDA signal is retained by the ICs throughout the transaction, except for the acknowledge cycles. The master indicates the end of a read transaction by responding to the last byte it requires with a no acknowledge. This signals the ICs that control of SDA is to remain with the master following the acknowledge clock. Write Data Protocol The write data protocol is used to write to register to the ICs starting at memory address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1, and DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by sending a STOP or Repeated START after receiving the last acknowledge bit: S. SAddr W. A. MAddr. A. Data0. A. Data1. A... DataN. A. P The MSB of the data to be stored at address MAddr can be written immediately after the MAddr byte is acknowledged. Because the address is automatically incremented after the LSB of each byte is received by the ICs, the MSB of the data at address MAddr + 1 can be written immediately after the acknowledgment of the data at address MAddr. If the bus master continues an autoincremented write transaction beyond address 4Fh, the ICs ignore the data. A valid write must include both register bytes. Data is also ignored on writes to readonly addresses. Incomplete bytes and bytes that are not acknowledged by the ICs are not written to memory. 14 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Read Data Protocol The read data protocol is used to read to register from the ICs starting at the memory address specified by MAddr. Both register bytes must be read in the same transaction for the register data to be valid. Data0 represents the data byte in memory location MAddr, Data1 represents the data from MAddr + 1, and DataN represents the last byte read by the master: S. SAddr W. A. MAddr. A. Sr. SAddr R. A. Data0. A. Data1. A... DataN. N. P Data is returned beginning with the MSB of the data in MAddr. Because the address is automatically incremented after the LSB of each byte is returned, the MSB of the data at address MAddr + 1 is available to the host immediately after the acknowledgment of the data at address MAddr. If the bus master continues to read beyond address FFh, the ICs output data values of FFh. Addresses labeled Reserved in the memory map return undefined data. The bus master terminates the read transaction at any byte boundary by issuing a no acknowledge followed by a STOP or Repeated START. Ordering Information TEMP RANGE PIN-PACKAGE MAX17058G+ PART -40NC to +85NC 8 TDFN-EP* 1-Cell ModelGauge IC DESCRIPTION MAX17058G+T10 -40NC to +85NC 8 TDFN-EP* 1-Cell ModelGauge IC MAX17058X+ -40NC to +85NC 8 WLP 1-Cell ModelGauge IC MAX17058X+T10 -40NC to +85NC 8 WLP 1-Cell ModelGauge IC MAX17059G+ -40NC to +85NC 8 TDFN-EP* 2-Cell ModelGauge IC MAX17059G+T10 -40NC to +85NC 8 TDFN-EP* 2-Cell ModelGauge IC MAX17059X+ -40NC to +85NC 8 WLP 2-Cell ModelGauge IC MAX17059X+T10 -40NC to +85NC 8 WLP 2-Cell ModelGauge IC +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel. Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 WLP W80B1+1 21-0555 Refer to Application Note 1891 8 TDFN-EP T822+3 21-0168 90-0065 Maxim Integrated 15 MAX17058/MAX17059 1-Cell /2-Cell Li+ ModelGauge ICs Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 2/12 Initial release 1 4/12 Corrected byte-order errors 10, 11 -- 2 6/12 Updated Absolute Maximum Ratings section; corrected memory address for CMD 2, 9, 12 3 8/12 Corrected formula for RCOMP and TempCo 4 6/13 Corrected conditions for entering sleep mode and Absolute Maximum voltage ratings, and removed all mentions of EnSleep 5 8/13 Corrected the device version number 8 2, 10 10 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2013 Maxim Integrated Products, Inc. 16 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.