DM54LS471/DM74LS471 National Semiconductor DM54/74LS471 (256 x 8) 2048-Bit TTL PROM General Description These Schottky memories are organized in the popular 256 words by & bits configuration. Memory enable inputs are provided to control the output states. When the device is enabled, the outputs represent the contents of the selected word, When disabled, the 8 outputs go to the OFF or high impedance state. PROMs are shipped from the factory with lows in all loca- tions. A high may be programmed into any selected location by following the programming instructions. Features @ Advanced titanium-tungsten (Ti-W) fuses w Schottky-clamped for high speed Address access down to60 ns max Enable access30 ns max Enable recovery30 ns max m@ PNP inputs for reduced input loading m All DC and AC parameters guaranteed over tempera- ture Low voltage TRI-SAFE programming @ TRI-STATE outputs Block Diagram 2048-BIT ARRAY 32 x 64 MEMORY MATRIX xz be S| me Pd rp} BUF Ry BUF Fe BUF F- @ BUF F"} BUF F) BUF F] BUF P=) BUF ENABLE | T I | I I | I GATE a7 o6 as a4 a3 a2 a1 a0 TL/D/9190-1 Pin Names A0-A7 Addresses Gi-G2 Output Enables GND Ground Q0-Q7 Outputs Voc Power Supply 3-26 Connection Diagrams Dual-In-Line Package / Aoj1 20FVer Ali72 19}Aa7 A243 18PA6 As4 17,;A5 A4a5 16;62 Qo46 15}Gi Qi-47 14-07 Q248 13-06 03-19 12}a5 GND4 10 1104 TL/D/9190-2 Top View Order Number DM54/74LS471J or DM74LS471N See NS Package Number J20A or N20A Ordering Information Plastic Leaded Chip Carrier (PLCC) yo 222s | 3 2 1 20 19 AS 14 18B AG Ams 17) A5 00-16 16 G2 Qi17 15F Gi 02 +48 14]; 07 9 10 11 12 13 rr? go yo a +t DO 0 Sozaodgdg o TL/D/9190-3. Top View Order Number DM74LS471V See NS Package Number V20A Commercial Temp Range (0C to + 70C) Parameter/Order Number Max Access Time (ns) DM74LS471N 60 DM74LS471J 60 DM74LS471V 60 Military Temp Range ( 55C to + 125C) Parameter/Order Number Max Access Time (ns) DM54LS471J 70 3-27 L2PS12NG/iZPS1PSING DM54LS471/DM74LS471 Absolute Maximum Ratings (note 1) Operating Conditions If Military/Aerospace specified devices are required, Min Max Units please contact the National Semiconductor Sales Supply Voltage (Vcc) Ottice/Distributors for availability and specifications. Military 4.50 5.50 V Supply Voltage (Note 2) 0.5V to +7.0V Commercial 4.75 5.25 v input Voltage (Note 2) 1.2V to +5.5V Aen Temperature (Ta) 55+ 105 0 Output Voltage (Note 2) -0.5V to +5.5V Commercial 0 170 Storage Temperature 65C to + 150C Logical 0 Input Voltage 0 0.8 V Lead Temp. (Soldering, 10 seconds) 300C Logical 1 Input Voltage 290 55 V ESD to be determined Note 1: Absolute maximum ratings are those values beyond which the de- vice may be permanently damaged. They do not maan that the device may be operated at these values. Note 2: These limits do not apply during programming ratings, refer to the programming instructions. DC Electrical Characteristics (Note 1) Symbol Parameter Conditions DMS4L$471 DM74L$471 Units Min | Typ Max | Min | Typ Max lie Input Load Current Voc = Max, Vin = 0.45V 80 | 250 80 | 250 BA lH Input Leakage Current Voc = Max, Vin = 2.7V 25 25 pA Voc = Max, Vin = 5.5V 1.0 1.0 mA VoL Low Level Output Voltage | Voc = Min, lol = 16mA 0.35 0.50 0.35 | 0.45 V VIL Low Level Input Voltage 0.80 0.80 Vv Vin High Level Input Voltage 2.0 2.0 Vv Vc Input Clamp Voltage Voc = Min, iw = 18mA 0.8 | 1.2 -0.8 | -1.2 Vv C Input Capacitance Voc = 5.0V, Vin = 2.0V Ta = 25C, 1 MHz 4.0 4.0 | pF Co Output Capacitance Voc = 5.0V, Vo = 2.0V 60 60 E Ta = 25C, 1 MHz, Outputs Off P loc Power Supply Current Voc = Max, Inputs Grounded 76 100 75 400 mA All Outputs Open los Short Circuit Vo = OV, Vec = Max _ _ _ _ Output Current (Note 2) 20 70 20 70 mA loz Output Leakage Voc = Max, Vo = 0.45V to 2.4V +50 +50 pA (TRI-STATE) Chip Disabled 50 50 aA Von Output Voltage High lon = 2.0mA 2.4 3.2 Vv lon = 6.5 mA 2.4 3.2 Vv Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Voc = 5.0v and Ta = 25C. Note 2: During log measurement, only one output at a time should be grounded. Permanent damage may otherwise result. AC Electrical Characteristics with standard Load and Operating Conditions Symbol JEDEC Symbol Parameter DMS4LS471 OM74LS471 Units Min Typ Max Min Typ Max TAA TAVQV Address Access Time 45 70 40 60 ns TEA TEVQV Enable Access Time 15 35 15 30 ns TER TEXQX Enable Recovery Time 16 35 16 30 ns T2X TEVQX Output Enable Time 15 35 15 30 ns TXZ TEXQZ Output Disable Time 15 35 15 30 ns 3-28 Functional Description TESTABILITY The Schottky PROM die includes extra rows and columns of fusable links for testing the programmability of each chip. These test fuses are placed at the worst-case chip locations to provide the highest possible confidence in the program- ming tests in the final product. A ROM pattern is also per- manently fixed in the additional circuitry and coded to pro- vide a parity check of input address levels. These and other test circuits are used to test for correct operation of the row and column-select circuits and functionality of input and en- able gates. All test circuits are available at both wafer and assembled device levels to allow 100% functional and para- metric testing at every stage of the test flow. RELIABILITY As with all National products, the Ti-'W PROMs are subject- ed to an on-going reliability evaluation by the Reliability As- surance Department. These evaluations employ accelerat- d life tests, including dynamic high-temperature operating life, temperature-humidity life, temperature cycling, and ther- mal shock. To date, nearly 7.4 million Schottky Ti-W PROM device hours have been logged, with samples in Epoxy B molded DIP (N-package), PLCC (V-package) and CERDIP (J-package). Device performance in all package configura- tions is excellent. TITANIUM-TUNGSTEN FUSES Nationals Programmable Read-Only Memories (PROMs) feature titanium-tungsten (Ti-W) fuse links designed to pro- gram efficiently with only 10.5V applied. The high perform- ance and reliability of these PROMs are the result of fabrica- tion by a Schottky bipolar process, of which the titanium- tungsten metallization is an integral part, and the use of an on-chip programming circuit. A major advantage of the titanium-tungsten fuse technology is the low programming voltage of the fuse links. At 10.5V, this virtually eliminates the need for guard-ring devices and wide spacings required for other fuse technologies. Care is taken, however, to minimize voltage drops across the die and to reduce parasitics. The device is designed te ensure that worst-case fuse operating current is low enough for reliable long-term operation. The Darlington programming circuit is liberally designed to insure adequate power density for blowing the fuse links. The complete circuit design is optimized to provide high performance over the entire oper- ating ranges of Voc and temperature. 3-29 LZpS1PZING/12S 1SING