DC1763A-D - Linear Technology

219210f

LTC2192

LTC2191/LTC2190

APPLICATIONS

n Communications

n Cellular Base Stations

n Software-Deﬁned Radios

n Portable Medical Imaging

n Multi-Channel Data Acquisition

n Nondestructive Testing

TYPICAL APPLICATION

DESCRIPTION

16-Bit, 65Msps/40Msps/

25Msps Low Power

Dual ADCs

The LTC

2192/LTC2191/LTC2190 are 2-channel, simul-

taneous sampling 16-bit A/D converters designed for

digitizing high frequency, wide dynamic range signals. They

are perfect for demanding communications applications

with AC performance that includes 77dB SNR and 90dB

spurious free dynamic range (SFDR). Ultralow jitter of

0.07psRMS allows undersampling of IF frequencies with

excellent noise performance.

DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)

and no missing codes over temperature. The transition

noise is 3.3LSBRMS.

To minimize the number of data lines the digital outputs

are serial LVDS. Each channel outputs one bit, two bits or

four bits at a time. The LVDS drivers have optional internal

termination and adjustable output levels to ensure clean

signal integrity.

The ENC+ and ENC– inputs may be driven differentially or

single ended with a sine wave, PECL, LVDS, TTL or CMOS

inputs. An internal clock duty cycle stabilizer allows high

performance at full speed for a wide range of clock duty

cycles.

FEATURES

n 2-Channel Simultaneous Sampling ADC

n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel

n 77dB SNR

n 90dB SFDR

n Low Power: 198mW/146mW/104mW Total

n 99mW/73mW/52mW per Channel

n Single 1.8V Supply

n Selectable Input Ranges: 1VP-P to 2VP-P

n 550MHz Full-Power Bandwidth S/H

n Shutdown and Nap Modes

n Serial SPI Port for Conﬁguration

n 52-Pin (7mm × 8mm) QFN Package

2-Tone FFT, fIN = 70MHz and 69MHz

16-BIT

ADC CORE

CH1

ANALOG

INPUT

CH2

ANALOG

INPUT

ENCODE

INPUT

S/H

16-BIT

ADC CORE

OUT1A

OUT1B

OUT1C

OUT1D

OUT2A

OUT2B

OUT2C

OUT2D

DATA CLOCK OUT

FRAME

S/H DATA

SERIALIZER

PLL

OGND

219210 TA01a

SERIALIZED

LVDS

OUTPUTS

GND

VDD OVDD

1.8V1.8V

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

219210 G07

LTC2192

LTC2191/LTC2190

219210f

Supply Voltages

VDD, OVDD ................................................ –0.3V to 2V

Analog Input Voltage

AIN+, AIN–, PAR/SER, SENSE

(Note 3) ....................................–0.3V to (VDD + 0.2V)

Digital Input Voltage

ENC+, ENC–, CS, SDI, SCK (Note 4) ...... –0.3V to 3.9V

SDO (Note 4) ............................................ –0.3V to 3.9V

Digital Output Voltage ................–0.3V to (OVDD + 0.3V)

Operating Temperature Range

LTC2192C, LTC2191C, LTC2190C............. 0°C to 70°C

LTC2192I, LTC2191I, LTC2190I ............ –40°C to 85°C

Storage Temperature Range ................... –65°C to 150°C

(Notes 1, 2)

1615 17 18 19

TOP VIEW

GND

UKG PACKAGE

52-LEAD (7mm × 8mm) PLASTIC QFN

20 21 22 23 24 25 26

5152 50 49 48 47 46 45 44 43 42 41

1VCM1

GND

AIN1+

AIN1–

GND

REFH

REFL

REFH

REFL

PAR/SER

AIN2+

AIN2–

GND

VCM2

OUT1C+

OUT1C–

OUT1D+

OUT1D–

DCO+

DCO–

OVDD

OGND

FR+

FR–

OUT2A+

OUT2A–

OUT2B+

OUT2B–

VDD

SENSE

GND

VREF

GND

SDO

GND

OUT1A+

OUT1A–

OUT1B+

OUT1B–

VDD

ENC+

ENC–

SCK

SDI

GND

OUT2D–

OUT2D+

OUT2C–

OUT2C+

TJMAX = 150°C, θJA = 29°C/W

EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2192CUKG#PBF LTC2192CUKG#TRPBF LTC2192UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2192IUKG#PBF LTC2192IUKG#TRPBF LTC2192UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

LTC2191CUKG#PBF LTC2191CUKG#TRPBF LTC2191UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2191IUKG#PBF LTC2191IUKG#TRPBF LTC2191UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

LTC2190CUKG#PBF LTC2190CUKG#TRPBF LTC2190UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2190IUKG#PBF LTC2190IUKG#TRPBF LTC2190UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

219210f

LTC2192

LTC2191/LTC2190

CONVERTER CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

PARAMETER CONDITIONS

LTC2192 LTC2191 LTC2190

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Resolution (No Missing Codes) l16 16 16 Bits

Integral Linearity Error Differential Analog Input

(Note 6)

l–6 ±2 6 –6 ±2 6 –6 ±2 6 LSB

Differential Linearity Error Differential Analog Input l–0.9 ±0.5 0.9 –0.9 ±0.5 0.9 –0.9 ±0.5 0.9 LSB

Offset Error (Note 7) l–7 ±1.5 7 –7 ±1.5 7 –7 ±1.5 7 mV

Gain Error Internal Reference

External Reference

–1.7

±1.5

–0.4

0.9

–1.7

±1.5

–0.4

0.9

–1.7

±1.5

–0.4

0.9

%FS

Offset Drift ±10 ±10 ±10 µV/°C

Full-Scale Drift Internal Reference

External Reference

±30

±10

±30

±10

±30

±10

ppm/°C

Gain Matching ±0.3 ±0.3 ±0.3 %FS

Offset Matching ±1.5 ±1.5 ±1.5 mV

Transition Noise 3.3 3.3 3.2 LSBRMS

ANALOG INPUT

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P

VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l0.7 VCM 1.25 V

VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V

IINCM Analog Input Common Mode Current Per Pin, 65Msps

Per Pin, 40Msps

Per Pin, 25Msps

104

µA

IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN– < VDD l–1 1 µA

IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA

IIN3 SENSE Input Leakage Current 0.625V < SENSE < 1.3V l–6 6 µA

tAP Sample-and-Hold Acquisition Delay Time 0 ns

tJITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode

Differential Encode

0.07

0.09

psRMS

CMRR Analog Input Common Mode Rejection Ratio 80 dB

BW–3B Full-Power Bandwidth Figure 6 Test Circuit 550 MHz

LTC2192

LTC2191/LTC2190

219210f

DYNAMIC ACCURACY

The l denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2192 LTC2191 LTC2190

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

SNR Signal-to-Noise Ratio 5MHz Input

30MHz Input

70MHz Input

140MHz Input

75.3

76.9

76.8

76.3

75.2

76.9

76.8

76.7

76.2

75.6

77.1

76.9

76.4

dBFS

SFDR Spurious Free Dynamic Range

2nd Harmonic

5MHz Input

30MHz Input

70MHz Input

140MHz Input

dBFS

Spurious Free Dynamic Range

3rd Harmonic

5MHz Input

30MHz Input

70MHz Input

140MHz Input

dBFS

Spurious Free Dynamic Range

4th Harmonic or Higher

5MHz Input

30MHz Input

70MHz Input

140MHz Input

dBFS

S/(N+D) Signal-to-Noise Plus

Distortion Ratio

5MHz Input

30MHz Input

70MHz Input

140MHz Input

74.8

76.8

76.7

76.4

76.3

74.8

76.7

76.6

76.3

75.2

76.9

76.8

76.5

76.4

dBFS

Crosstalk 10MHz Input –110 –110 –110 dBc

INTERNAL REFERENCE CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full

operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V

VCM Output Temperature Drift ±25 ppm/°C

VCM Output Resistance –600µA < IOUT < 1mA 4 Ω

VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V

VREF Output Temperature Drift ±25 ppm/°C

VREF Output Resistance –400µA < IOUT < 1mA 7 Ω

VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V

DIGITAL INPUTS AND OUTPUTS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ENCODE INPUTS (ENC+, ENC–)

Differential Encode Mode (ENC– Not Tied to GND)

VID Differential Input Voltage (Note 8) l0.2 V

VICM Common Mode Input Voltage Internally Set

Externally Set (Note 8)

1.1

1.2

1.6

VIN Input Voltage Range ENC+, ENC– to GND (Note 8) l0.2 3.6 V

RIN Input Resistance See Figure 10 10 kΩ

CIN Input Capacitance (Note 8) 3.5 pF

219210f

LTC2192

LTC2191/LTC2190

DIGITAL INPUTS AND OUTPUTS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Single-Ended Encode Mode (ENC– Tied to GND)

VIH High Level Input Voltage VDD =1.8V l1.2 V

VIL Low Level Input Voltage VDD =1.8V l0.6 V

VIN Input Voltage Range ENC+ to GND l0 3.6 V

RIN Input Resistance See Figure 11 30 kΩ

CIN Input Capacitance (Note 8) 3.5 pF

DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)

VIH High Level Input Voltage VDD =1.8V l1.3 V

VIL Low Level Input Voltage VDD =1.8V l0.6 V

IIN Input Current VIN = 0V to 3.6V l–10 10 µA

CIN Input Capacitance (Note 8) 3 pF

SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)

ROL Logic Low Output Resistance to GND VDD =1.8V, SDO = 0V 200 Ω

IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA

COUT Output Capacitance (Note 8) 3 pF

DIGITAL DATA OUTPUTS

VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.375

RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω

POWER REQUIREMENTS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 9)

SYMBOL PARAMETER CONDITIONS

LTC2192 LTC2191 LTC2190

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

OVDD Output Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

IVDD Analog Supply Current Sine Wave Input l99 109 72 80 49 56 mA

IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

4-Lane Mode, 1.75mA Mode

4-Lane Mode, 3.5mA Mode

10.2

17.6

13.6

24.7

21.1

39.6

9.2

16.6

12.8

23.9

20.3

38.8

8.7

16.1

12.3

23.4

19.9

38.4

PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

4-Lane Mode, 1.75mA Mode

4-Lane Mode, 3.5mA Mode

198

211

203

223

217

250

227

251

242

281

146

159

152

172

166

199

173

197

189

229

104

118

111

131

124

158

130

153

146

186

PSLEEP Sleep Mode Power 1 1 1 mW

PNAP Nap Mode Power 50 50 50 mW

PDIFFCLK Power Increase with Diffential Encode Mode Enabled

(No Increase for Sleep Mode)

20 20 20 mW

LTC2192

LTC2191/LTC2190

219210f

TIMING CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2192 LTC2191 LTC2190

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

fSSampling Frequency (Notes 10, 11) l5 65 5 40 5 25 MHz

tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

7.69

100

11.88

12.5

100

tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

7.69

100

11.88

12.5

100

tAP Sample-and-Hold

Acquistion Delay Time

0 0 0 ns

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output)

tSER Serial Data Bit Period 4-Lane Output Mode

2-Lane Output Mode

1-Lane Output Mode

1/(4 • fS)

1/(8 • fS)

1/(16 • fS)

Sec

tFRAME FR to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER Sec

tDATA Data to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER Sec

tPD Propagation Delay (Note 8) l0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER Sec

trOutput Rise Time Data, DCO, FR, 20% to 80% 0.17 ns

tfOutput Fall Time Data, DCO, FR, 20% to 80% 0.17 ns

DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P

Pipeline Latency 7 Cycles

SPI Port Timing (Note 8)

tSCK SCK Period Write Mode

Readback Mode,

CSDO = 20pF, RPULLUP = 2k

250

tSCS-to-SCK Setup Time l5 ns

tHSCK-to-CS Setup Time l5 ns

tDS SDI Setup Time l5 ns

tDH SDI Hold Time l5 ns

tDO SCK Falling to SDO

Valid

Readback Mode,

CSDO = 20pF, RPULLUP = 2k

l125 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above VDD

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2192), 40MHz

(LTC2191), or 25MHz (LTC2190), 2-lane output mode, differential

ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive,

unless otherwise noted.

Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a

best ﬁt straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5LSB when

the output code ﬂickers between 0000 0000 0000 0000 and 1111 1111

1111 1111 in 2’s complement output mode.

Note 8: Guaranteed by design, not subject to test.

Note 9: VDD = OVDD=1.8V, fSAMPLE = 65MHz (LTC2192),

40MHz (LTC2191), or 25MHz (LTC2190), 2-lane output mode,

ENC+ = single-ended 1.8V square wave, ENC– = 0V, input range = 2VP-P

with differential drive, unless otherwise noted. The supply current and

power dissipation speciﬁcations are totals for the entire IC, not per

channel.

Note 10: Recommended operating conditions.

Note 11: The maximum sampling frequency depends on the speed grade

of the part and also which serialization mode is used. The maximum serial

data rate is 1000Mbps, so tSER must be greater than or equal to 1ns.

219210f

LTC2192

LTC2191/LTC2190

TIMING DIAGRAMS

4-Lane Output Mode

ANALOG

INPUT

ENC–

tENCH

tAP

N+1

ENC+

DCO–

FR–

OUT#A–

D15 D13 D11 D9 D15 D13 D11 D9 D15

OUT#A+

OUT#B–

D14 D12 D10 D8 D14 D12 D10 D8 D14

OUT#B+

OUT#C–

D7 D5 D3 D1 D7 D5 D3 D1 D7

OUT#C+

OUT#D–

D6 D4 D2 D0 D6 D4 D2 D0 D6

OUT#D+

SAMPLE N–7 SAMPLE N–6 SAMPLE N–5

219210 TD01

DCO+

FR+

tPD

tENCL

tDATA

tFRAME

tSER

2-Lane Output Mode

D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11

D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10

ANALOG

INPUT

ENC–

tENCH

tAP N+1

ENC+

DCO–

FR+

OUT#A–

OUT#A+

OUT#B–

OUT#B+

DCO+

FR–

tENCL

tSER

tDATA

tFRAME

tPD tSER

SAMPLE N–5

219210 TD02

SAMPLE N–6SAMPLE N–7

OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED

LTC2192

LTC2191/LTC2190

219210f

TIMING DIAGRAMS

1-Lane Output Mode

D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

N+1

D15 D14 D13 D12

ANALOG

INPUT

ENC–tENCH

tAP

ENC+

DCO–

FR+

OUT#A–

OUT#A+

DCO+

FR–

tENCL

tFRAME tDATA tSER

tSER

tPD

tSER

SAMPLE N–7 SAMPLE N–6 SAMPLE N–5

219210 TD03

OUT#B+, OUT#B–, OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED

tStDS

A5 A4 A3 A2 A1 A0 XX

D7 D6 D5 D4 D3 D2 D1 D0

XX XX XX XX XX XX XX

SCK

SDI R/W

SDO HIGH IMPEDANCE

SPI Port Timing (Readback Mode)

SPI Port Timing (Write Mode)

tDH

tDO

tSCK tH

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

219210 TD04

SCK

SDI R/W

SDO HIGH IMPEDANCE

219210f

LTC2192

LTC2191/LTC2190

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2192: 64k Point FFT,

fIN = 30MHz, –1dBFS, 65Msps

LTC2192: 64k Point FFT,

fIN = 70MHz, –1dBFS, 65Msps

LTC2192: 64k Point FFT,

fIN = 140MHz, –1dBFS, 65Msps

LTC2192: 64k Point 2-Tone FFT,

fIN = 69MHz, 70MHz, –7dBFS,

65Msps LTC2192: Shorted Input Histogram

LTC2192: SNR vs Input Frequency,

–1dBFS, 65Msps, 2V Range

LTC2192: Integral

Nonlinearity (INL)

LTC2192: Differential

Nonlinearity (DNL)

LTC2192: 64k Point FFT,

fIN = 5MHz, –1dBFS, 65Msps

OUTPUT CODE

–4.0

–3.0

–2.0

–1.0

INL ERROR (LSB)

1.0

4.0

3.0

2.0

16384 32768 49152 65536

219210 G01

OUTPUT CODE

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

219210 G02

016384 32768 49152 65536

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G03

010 20 30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G04

010 20 30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G05

010 20 30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G06

010 20 30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

219210 G07

OUTPUT CODE

32831

1000

3000

2000

COUNT

4000

5000

10000

9000

8000

7000

6000

32837 32843 32849 32855

219210 G08

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300

219210 G09

SINGLE-ENDED

ENCODE

DIFFERENTIAL

ENCODE

LTC2192

LTC2191/LTC2190

219210f

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2192: IVDD vs Sample Rate,

5MHz, –1dBFS Sine Wave on

Each Channel

LTC2192: IOVDD vs Sample Rate,

5MHz, –1dBFS Sine Wave on

Each Input

LTC2192: SNR vs SENSE,

fIN = 5MHz, –1dBFS

LTC2192: 2nd, 3rd Harmonic vs

Input Frequency, –1dBFS, 65Msps,

2V Range

LTC2192: SFDR vs Input Level,

fIN = 70MHz, 65Msps, 2V Range

LTC2191: Integral

Nonlinearity (INL)

LTC2191: Differential

Nonlinearity (DNL)

LTC2191: 64k Point FFT,

fIN = 5MHz, –1dBFS, 40Msps

LTC2192: 2nd, 3rd Harmonic vs

Input Frequency, –1dBFS, 65Msps,

1V Range

0 50 100 150 200 250 300

INPUT FREQUENCY (MHz)

100

2ND AND 3RD HARMONIC (dBFS)

219210 G10

2ND

3RD

0 50 100 150 200 250 300

INPUT FREQUENCY (MHz)

100

2ND AND 3RD HARMONIC (dBFS)

219210 G11

2ND

3RD

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

130

120

110

–70 –60 –50 –40 –30 –20 –10 0

219210 G12

dBFS

dBc

SAMPLE RATE (Msps)

VDD

(mA)

100

110

10 20 30 40

219210 G13

50 60

SAMPLE RATE (Msps)

OVDD

(mA)

20 40

219210 G14

4 LANE, 3.5mA

2 LANE, 3.5mA

4 LANE, 1.75mA

1 LANE, 3.5mA

2 LANE, 1.75mA

1 LANE, 1.75mA

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

219210 G15

OUTPUT CODE

–4.0

–3.0

–2.0

–1.0

INL ERROR (LSB)

1.0

4.0

3.0

2.0

16384 32768 49152 65536

219210 G16

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

219210 G17

OUTPUT CODE

016384 32768 49152 65536

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

105 15 20

219210 G18

219210f

LTC2192

LTC2191/LTC2190

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2191: 64k Point FFT,

fIN = 30MHz, –1dBFS, 40Msps

LTC2191: 64k Point FFT,

fIN = 70MHz, –1dBFS, 40Msps

LTC2191: 64k Point FFT,

fIN = 140MHz, –1dBFS, 40Msps

LTC2191: Shorted Input Histogram

LTC2191: SNR vs Input Frequency,

–1dBFS, 40Msps, 2V Range

LTC2191: SFDR vs Input Level,

fIN = 70MHz, 40Msps, 2V Range

LTC2191: 64k Point 2-Tone FFT,

fIN = 69MHz, 70MHz, –7dBFS,

40Msps

LTC2191: 2nd, 3rd Harmonic vs

Input Frequency, –1dBFS, 40Msps,

2V Range

LTC2191: 2nd, 3rd Harmonic vs

Input Frequency, –1dBFS, 40Msps,

1V Range

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G19

0 105 15 20

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G20

0 105 15 20

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G21

0 105 15 20

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G22

0 105 15 20

OUTPUT CODE

32823

1000

3000

2000

COUNT

4000

5000

10000

9000

8000

7000

6000

32829 32835 32841 32847

219210 G23

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300

219210 G24

SINGLE-ENDED

ENCODE

DIFFERENTIAL

ENCODE

0 50 100 150 200 250 300

INPUT FREQUENCY (MHz)

100

2ND AND 3RD HARMONIC (dBFS)

219210 G25

2ND

3RD

0 50 100 150 200 250 300

INPUT FREQUENCY (MHz)

100

2ND AND 3RD HARMONIC (dBFS)

219210 G26

2ND

3RD

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

130

120

110

–70 –60 –50 –40 –30 –20 –10 0

219210 G27

dBFS

dBc

LTC2192

LTC2191/LTC2190

219210f

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2191: IVDD vs Sample Rate,

5MHz, –1dBFS Sine Wave Input

on Each Channel

LTC2191: IOVDD vs Sample Rate,

5MHz, –1dBFS Sine Wave on

Each Input

LTC2191: SNR vs SENSE,

fIN = 5MHz, –1dBFS

LTC2190: Integral

Nonlinearity (INL)

LTC2190: Differential

Nonlinearity (DNL)

LTC2190: 64k Point FFT,

fIN = 5MHz, –1dBFS, 25Msps

LTC2190: 64k Point FFT,

fIN = 30MHz, –1dBFS, 25Msps

LTC2190: 64k Point FFT,

fIN = 70MHz, –1dBFS, 25Msps LTC2190: 64k Point FFT,

fIN = 140MHz, –1dBFS, 25Msps

SAMPLE RATE (Msps)

IVDD (mA)

10 20 30 40

219210 G28

SAMPLE RATE (Msps)

IOVDD (mA)

219210 G29

510 20 30

4 LANE, 3.5mA

2 LANE, 3.5mA

4 LANE, 1.75mA

1 LANE, 3.5mA

2 LANE, 1.75mA

1 LANE, 1.75mA

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

219210 G30

OUTPUT CODE

–4.0

–3.0

–2.0

–1.0

INL ERROR (LSB)

1.0

4.0

3.0

2.0

16384 32768 49152 65536

219210 G31

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

219210 G32

OUTPUT CODE

016384 32768 49152 65536

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

105

219210 G33

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G34

0 105

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G35

0 105

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G36

0 105

219210f

LTC2192

LTC2191/LTC2190

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2190: 64k Point, 2-Tone FFT,

fIN = 69MHz, 70MHz, –7dBFS,

25Msps LTC2190: Shorted Input Histogram

LTC2190: SNR vs Input Frequency,

–1dBFS, 25Msps, 2V Range

LTC2190: 2nd, 3rd Harmonic vs

Input Frequency, –1dBFS, 25Msps,

2V Range

LTC2190: SFDR vs Input Level,

fIN = 70MHz, 25Msps, 2V Range

LTC2190: 2nd, 3rd Harmonic vs

Input Frequency, –1dBFS, 25Msps,

1V Range

LTC2190: IVDD vs Sample Rate,

5MHz, –1dBFS Sine Wave Input on

Each Channel

LTC2190: IOVDD vs Sample Rate,

5MHz, –1dBFS Sine Wave on Each

Input

LTC2190: SNR vs SENSE,

fIN = 5MHz, –1dBFS

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

219210 G37

0 105

OUTPUT CODE

32836

1000

3000

2000

COUNT

4000

5000

10000

9000

8000

7000

6000

32842 32848 32854 32860

219210 G38

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300

219210 G39

SINGLE-ENDED

ENCODE

DIFFERENTIAL

ENCODE

0 50 100 150 200 250 300

INPUT FREQUENCY (MHz)

100

2ND AND 3RD HARMONIC (dBFS)

219210 G40

2ND

3RD

0 50 100 150 200 250 300

INPUT FREQUENCY (MHz)

100

2ND AND 3RD HARMONIC (dBFS)

219210 G41

2ND

3RD

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

130

120

110

–70 –60 –50 –40 –30 –20 –10 0

219210 G42

dBFS

dBc

SAMPLE RATE (Msps)

VDD

(mA)

219210 G43

35 510 15 25

SAMPLE RATE (Msps)

0VDD

(mA)

219210 G44

15 510 15 25

4 LANE, 3.5mA

2 LANE, 3.5mA

4 LANE, 1.75mA

1 LANE, 3.5mA

2 LANE, 1.75mA

1 LANE, 1.75mA

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

219210 G45

LTC2192

LTC2191/LTC2190

219210f

PIN FUNCTIONS

VCM1 (Pin 1): Common Mode Bias Output, Nominally Equal

to VDD/2. VCM1 should be used to bias the common mode

of the analog inputs of channel 1. Bypass to ground with

a 0.1µF ceramic capacitor.

GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 53):

ADC Power Ground. The exposed pad must be soldered

to the PCB ground.

AIN1+ (Pin 3): Channel 1 Positive Differential Analog

Input.

AIN1– (Pin 4): Channel 1 Negative Differential Analog

Input.

REFH (Pins 6, 8): ADC High Reference. See the Reference

section in the Applications Information for recommended

bypassing circuits for REFH and REFL.

REFL (Pins 7, 9): ADC Low Reference. See the Reference

section in the Applications Information for recommended

bypassing circuits for REFH and REFL.

PAR/SER (Pin 10): Programming Mode Selection Pin.

Connect to ground to enable the serial programming mode.

CS, SCK, SDI, SDO become a serial interface that control

the A/D operating modes. Connect to VDD to enable the

parallel programming mode where CS, SCK, SDI, SDO

become parallel logic inputs that control a reduced set of

the A/D operating modes. PAR/SER should be connected

directly to ground or the VDD of the part and not be driven

by a logic signal.

AIN2+ (Pin 11): Channel 2 Positive Differential Analog

Input.

AIN2– (Pin 12): Channel 2 Negative Differential Analog

Input.

VCM2 (Pin 14): Common Mode Bias Output, Nominally

Equal to VDD/2. VCM2 should be used to bias the common

mode of the analog inputs of channel 2. Bypass to ground

with a 0.1µF ceramic capacitor.

VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V

to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.

Adjacent pins can share a bypass capacitor.

ENC+ (Pin 17): Encode Input. Conversion starts on the

rising edge.

ENC– (Pin 18): Encode Complement Input. Conversion

starts on the falling edge. Tie to GND for single-ended

encode mode.

CS (Pin 19): In serial programming mode, (PAR/SER =

0V), CS is the serial interface chip select input. When

CS is low, SCK is enabled for shifting data on SDI into

the mode control registers. In the parallel programming

mode (PAR/SER = VDD), CS along with SCK selects 1-,

2- or 4-lane output mode (see Table 3). CS can be driven

with 1.8V to 3.3V logic.

SCK (Pin 20): In serial programming mode, (PAR/SER =

0V), SCK is the serial interface clock input. In the parallel

programming mode (PAR/SER = VDD), SCK along with CS

selects 1-, 2- or 4-lane output mode (see Table 3). SCK

can be driven with 1.8V to 3.3V logic.

SDI (Pin 21): In Serial Programming Mode, (PAR/SER =

0V), SDI is the Serial Interface Data Input. Data on SDI

is clocked into the mode control registers on the rising

edge of SCK. In the parallel programming pode (PAR/SER

= VDD), SDI can be used to power down the part. SDI can

be driven with 1.8V to 3.3V logic.

OGND (Pin 33): Output Driver Ground. This pin must be

shorted to the ground plane by a very low inductance path.

Use multiple vias close to the pin.

OVDD (Pin 34): Output Driver Supply. Bypass to ground

with a 0.1µF ceramic capacitor.

SDO (Pin 46): In serial programming mode, (PAR/SER

= 0V), SDO is the optional serial interface data output.

Data on SDO is read back from the mode control regis-

ters and can be latched on the falling edge of SCK. SDO

is an open-drain NMOS output that requires an external

2k pull-up resistor to 1.8V to 3.3V. If read back from the

mode control registers is not needed, the pull-up resistor

is not necessary and SDO can be left unconnected. In the

parallel programming mode (PAR/SER = VDD), SDO selects

3.5mA or 1.75mA LVDS output currents. When used as an

input, SDO can be driven with 1.8V to 3.3V logic through

a 1k series resistor.

219210f

LTC2192

LTC2191/LTC2190

VREF (Pin 48): Reference Voltage Output. Bypass to ground

with a 2.2µF ceramic capacitor. The reference output is

nominally 1.25V.

SENSE (Pin 50): Reference Programming Pin. Connecting

SENSE to VDD selects the internal reference and a ±1V input

range. Connecting SENSE to ground selects the internal

reference and a ±0.5V input range. An external reference

between 0.625V and 1.3V applied to SENSE selects an

input range of ±0.8 • VSENSE.

LVDS Outputs

The following pins are differential LVDS outputs. The

output current level is programmable. There is an optional

internal 100Ω termination resistor between the pins of

each LVDS output pair.

PIN FUNCTIONS

OUT2D–/OUT2D+, OUT2C–/OUT2C+, OUT2B–/OUT2B+,

OUT2A–/OUT2A+ (Pins 23/24, 25/26, 27/28, 29/30): Serial

Data Outputs for Channel 2. In 1-lane output mode only

OUT2A–/OUT2A+ are used. In 2-Lane output mode only

OUT2A–/OUT2A+ and OUT2B–/OUT2B+ are used.

FR–/FR+ (Pins 31/32): Frame Start Outputs.

DCO–/DCO+ (Pins 35/36): Data Clock Outputs.

OUT1D–/OUT1D+, OUT1C–/OUT1C+, OUT1B–/OUT1B+,

OUT1A–/OUT1A+ (Pins 37/38, 39/40, 41/42, 43/44): Serial

Data Outputs for Channel 1. In 1-lane output mode only

OUT1A–/OUT1A+ are used. In 2-lane output mode only

OUT1A–/OUT1A+ and OUT1B–/OUT1B+ are used.

LTC2192

LTC2191/LTC2190

219210f

FUNCTIONAL BLOCK DIAGRAM

DIFF REF

AMP

REF BUF

2.2µF

0.1µF 0.1µF

REFH REFL

RANGE

SELECT

1.25V

REFERENCE

REFH REFL VCM1 VCM2

VDD/2

SDO

219210 F01

S/H

SENSE

VREF

2.2µF

MODE

CONTROL

REGISTERS

SCKPAR/SER SDI

16-BIT

ADC CORE

CH2

ANALOG

INPUT

CH1

ANALOG

INPUT

S/H 16-BIT

ADC CORE

OUT1A

OUT1B

OUT1C

OUT1D

OUT2A

OUT2B

OUT2C

OUT2D

DATA CLOCK OUT

FRAME

DATA

SERIALIZER

OGND

OVDD

ENC–

VDD

ENC+1.8V1.8V

PLL

Figure 1. Functional Block Diagram

219210f

LTC2192

LTC2191/LTC2190

APPLICATIONS INFORMATION

CONVERTER OPERATION

The LTC2192/LTC2191/LTC2190 are low power, 2-channel,

16-bit, 65/40/25Msps A/D converters that are powered

by a single 1.8V supply. The analog inputs should be

driven differentially. The encode input can be driven dif-

ferentially or single ended for lower power consumption.

To minimize the number of data lines the digital outputs

are serial LVDS. Each channel outputs one bit at a time

(1-lane mode), two bits at a time (2-lane mode) or four

bits at a time (4-lane mode). Many additional features can

be chosen by programming the mode control registers

through a serial SPI port.

ANALOG INPUT

The analog inputs are differential CMOS sample-and-

hold circuits (Figure 2). The inputs should be driven

differentially around a common mode voltage set by the

VCM1 or VCM2 output pins, which are nominally VDD/2.

For the 2V input range, the inputs should swing from

VCM – 0.5V to VCM + 0.5V. There should be 180° phase

difference between the inputs.

The two channels are simultaneously sampled by a shared

encode circuit (Figure 2).

CSAMPLE

5pF

RON

15Ω

RON

15Ω

VDD

LTC2192

AIN+

219210 F02

CSAMPLE

5pF

VDD

AIN–

ENC–

ENC+

1.2V

10k

1.2V

10k

CPARASITIC

1.8pF

CPARASITIC

1.8pF

10Ω

10Ω

Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels Is Shown

Single-Ended Input

For applications less sensitive to harmonic distortion, the

AIN+ input can be driven singled ended with a 1VP-P signal

centered around VCM. The AIN– input should be connected

to VCM and the VCM bypass capacitor should be increased

to 2.2µF. With a singled-ended input the harmonic distortion

and INL will degrade, but the noise and DNL will remain

unchanged.

INPUT DRIVE CIRCUITS

Input Filtering

If possible, there should be an RC lowpass ﬁlter right at

the analog inputs. This lowpass ﬁlter isolates the drive

circuitry from the A/D sample-and-hold switching, and

also limits wideband noise from the drive circuitry. Figure 3

shows an example of an input RC ﬁlter. The RC component

values should be chosen based on the application’s input

frequency.

Transformer Coupled Circuits

Figure 3 shows the analog input being driven by an RF

transformer with a center-tapped secondary. The center

LTC2192

LTC2191/LTC2190

219210f

APPLICATIONS INFORMATION

25Ω

25Ω 25Ω

25Ω

50Ω

0.1µF

AIN+

AIN–

12pF

0.1µF

VCM

LTC2192

ANALOG

INPUT

0.1µF T1

1:1

T1: MA/COM MABAES0060

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

219210 F03

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

25Ω

50Ω

12Ω

0.1µF

AIN+

AIN–

8.2pF

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1 T2

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1TL

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

219210 F04

LTC2192

Figure 4. Recommended Front-End Circuit for Input Frequencies

from 5MHz to 150MHz

25Ω

50Ω

0.1µF

AIN+

AIN–

1.8pF

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1TL

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

219210 F05

LTC2192

Figure 5. Recommended Front-End Circuit for Input Frequencies

from 150MHz to 250MHz

25Ω

50Ω

0.1µF

4.7nH

AIN+

AIN–

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

219210 F06

LTC2192

Figure 6. Recommended Front-End Circuit for Input Frequencies

Above 250MHz

25Ω

200Ω

0.1µF AIN+

AIN–

0.1µF

12pF

VCM

LTC2192

219210 F07

–

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

0.1µF

Figure 7. Front-End Circuit Using a High Speed

Differential Ampliﬁer

tap is biased with VCM, setting the A/D input at its optimal

DC level. At higher input frequencies a transmission line

balun transformer (Figures 4 to 6) has better balance,

resulting in lower A/D distortion.

Ampliﬁer Circuits

Figure 7 shows the analog input being driven by a high

speed differential ampliﬁer. The output of the ampliﬁer is AC

coupled to the A/D so the ampliﬁer’s output common mode

voltage can be optimally set to minimize distortion.

At very high frequencies an RF gain block will often have

lower distortion than a differential ampliﬁer. If the gain

block is single ended, then a transformer circuit (Figures 4

to 6) should convert the signal to differential before driv-

ing the A/D.

219210f

LTC2192

LTC2191/LTC2190

APPLICATIONS INFORMATION

Reference

The LTC2192/LTC2191/LTC2190 have an internal 1.25V

voltage reference. For a 2V input range using the internal

reference, connect SENSE to VDD. For a 1V input range

using the internal reference, connect SENSE to ground.

For a 2V input range with an external reference, apply a

1.25V reference voltage to SENSE (Figure 9).

The input range can be adjusted by applying a voltage to

SENSE that is between 0.625V and 1.30V. The input range

will then be 1.6 • VSENSE.

The VREF, REFH and REFL pins should be bypassed as

shown in Figure 8. A low inductance 2.2µF interdigitated

capacitor is recommended for the bypass between REFH

and REFL. This type of capacitor is available at a low cost

from multiple suppliers.

Alternatively, C1 can be replaced by a standard 2.2µF

capacitor between REFH and REFL. The capacitors should

be as close to the pins as possible (not on the back side

of the circuit board).

Figure 8c and 8d show the recommended circuit board

layout for the REFH/REFL bypass capacitors. Note that in

Figure 8c, every pin of the interdigitated capacitor (C1)

is connected since the pins are not internally connected

in some vendors’ capacitors. In Figure 8d the REFH and

REFL pins are connected by short jumpers in an internal

layer. To minimize the inductance of these jumpers they

can be placed in a small hole in the GND plane on the

second board layer.

Figure 8a. Reference Circuit

SENSE

1.25V

EXTERNAL

REFERENCE

2.2µF

1µF

VREF

219210 F09

LTC2192

Figure 9. Using an External 1.25V Reference

VREF

REFH

SENSE

TIE TO VDD FOR 2V RANGE;

TIE TO GND FOR 1V RANGE;

RANGE = 1.6 • VSENSE FOR

0.625V < VSENSE < 1.300V

1.25V

REFL

INTERNAL ADC

HIGH REFERENCE

BUFFER

219210 F08a

LTC2192

5Ω

0.8x

DIFF AMP

INTERNAL ADC

LOW REFERENCE

C1: 2.2µF LOW INDUCTANCE

INTERDIGITATED CAPACITOR

TDK CLLE1AX7S0G225M

MURATA LLA219C70G225M

AVX W2L14Z225M

OR EQUIVALENT

1.25V BANDGAP

REFERENCE

0.625V

RANGE

DETECT

AND

CONTROL

2.2µF

0.1µF

–

REFH

REFL

219210 F08b

LTC2192

CAPACITORS ARE 0402 PACKAGE SIZE

0.1µF

2.2µF

0.1µF

Figure 8b. Alternative REFH/REFL Bypass Circuit

Figure 8c. Recommended Layout for the REFH/REFL Bypass

Circuit in Figure 8a

Figure 8d. Recommended Layout for the REFH/REFL Bypass

Circuit in Figure 8b

219210 F08c

219210 F08d

LTC2192

LTC2191/LTC2190

219210f

Encode Input

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12, 13). The

encode inputs are internally biased to 1.2V through 10k

equivalent resistance. The encode inputs can be taken above

VDD (up to 3.6V), and the common mode range is from 1.1V

to 1.6V. In the differential encode mode, ENC– should stay

at least 200mV above ground to avoid falsely triggering the

single-ended encode mode. For good jitter performance

ENC+ should have fast rise and fall times.

The single-ended encode mode should be used with

CMOS encode inputs. To select this mode, ENC– is con-

nected to ground and ENC+ is driven with a square wave

APPLICATIONS INFORMATION

encode input. ENC+ can be taken above VDD (up to 3.6V)

so 1.8V to 3.3V CMOS logic levels can be used. The ENC+

threshold is 0.9V. For good jitter performance ENC+ should

have fast rise and fall times. If the encode signal is turned

off or drops below approximately 500kHz, the A/D enters

nap mode.

Figure 12. Sinusoidal Encode Drive

ENC+

ENC–

PECL OR

LVDS

CLOCK

0.1µF

219210 F13

LTC2192

Figure 13. PECL or LVDS Encode Drive

50Ω

100Ω

0.1µF

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

LTC2192

219210 F12

ENC–

ENC+

0.1µF

VDD

LTC2192

219210 F10

ENC–

ENC+

15k

VDD

DIFFERENTIAL

COMPARATOR

30k

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

30k

ENC+

ENC–

219210 F11

1.8V TO 3.3V

LTC2192

CMOS LOGIC

BUFFER

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

Clock PLL and Duty Cycle Stabilizer

The encode clock is multiplied by an internal phase-locked

loop (PLL) to generate the serial digital output data. If the

encode signal changes frequency or is turned off, the PLL

requires 25µs to lock onto the input clock.

A clock duty cycle stabilizer circuit allows the duty cycle

of the applied encode signal to vary from 30% to 70%.

In the serial programming mode it is possible to disable

the duty cycle stabilizer, but this is not recommended. In

the parallel programming mode the duty cycle stabilizer

is always enabled.

219210f

LTC2192

LTC2191/LTC2190

APPLICATIONS INFORMATION

DIGITAL OUTPUTS

The digital outputs of the LTC2192/LTC2191/LTC2190 are

serialized LVDS signals. Each channel outputs one bit at

a time (1-lane mode), two bits at a time (2-lane mode) or

four bits at a time (4-lane mode). Please refer to the Tim-

ing Diagrams for details. In 4-lane mode the clock duty

cycle stabilizer must be enabled.

The output data should be latched on the rising and falling

edges of the data clock out (DCO). A data frame output

(FR) can be used to determine when the data from a new

conversion result begins.

The maximum serial data rate for the data outputs is 1Gbps,

so the maximum sample rate of the ADC will depend on

the serialization mode as well as the speed grade of the

ADC (See Table 1). The minimum sample rate for all se-

rialization modes is 5Msps.

By default the outputs are standard LVDS levels: 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100Ω differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

The outputs are powered by OVDD and OGND which are

isolated from the A/D core power and ground.

Table 1. Maximum Sampling Frequency for All Serialization

Modes. Note That These Limits are for the LTC2192. The

Sampling Frequency for the Slower Speed Grades Cannot

Exceed 40MHz (LTC2191) or 25MHz (LTC2190)

SERIALIZATION

MODE

MAXIMUM

SAMPLING

FREQUENCY,

fS (MHz)

DCO

FREQUENCY

SERIAL

DATA RATE

4-Lane 65 2 • fSfS4 • fS

2-Lane 65 4 • fSfS8 • fS

1-Lane 62.5 8 • fSfS16 • fS

Programmable LVDS Output Current

In LVDS mode, the default output driver current is 3.5mA.

This current can be adjusted by control register A2 in the

serial programming mode. Available current levels are

1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

In the parallel programming mode the SDO pin can select

either 3.5mA or 1.75mA.

Optional LVDS Driver Internal Termination

In most cases using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100Ω termination resistor can

be enabled by serially programming mode control register

A2. The internal termination helps absorb any reﬂections

caused by imperfect termination at the receiver. When

the internal termination is enabled, the output driver

current is doubled to maintain the same output voltage

swing. Internal termination can only be selected in serial

programming mode.

DATA FORMAT

Table 2 shows the relationship between the analog input

voltage and the digital data output bits. By default the

output data format is offset binary. The 2’s complement

format can be selected by serially programming mode

control register A1.

Table 2. Output Codes vs Input Voltage

AIN+-AIN–

(2V RANGE)

D15-D0

(OFFSET BINARY)

D15-D0

(2’ s COMPLEMENT)

>1.000000V

+0.999970V

+0.999939V

1111 1111 1111 1111

1111 1111 1111 1110

0111 1111 1111 1111

0111 1111 1111 1110

+0.000030V

+0.000000V

–0.000030V

–0.000061V

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

0111 1111 1111 1110

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

–0.999939V

–1.000000V

<–1.000000V

0000 0000 0000 0001

0000 0000 0000 0000

1000 0000 0000 0001

1000 0000 0000 0000

Digital Output Randomizer

Interference from the A/D digital outputs is sometimes

unavoidable. Digital interference may be from capacitive or

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off-chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

LTC2192

LTC2191/LTC2190

219210f

The digital output is randomized by applying an exclusive

OR logic operation between the LSB and all other data

output bits. To decode, the reverse operation is applied—an

exclusive OR operation is applied between the LSB and all

other bits. The FR and DCO outputs are not affected. The

output randomizer is enabled by serially programming

mode control register A1.

Digital Output Test Pattern

To allow in-circuit testing of the digital interface to the

A/D, there is a test mode that forces the A/D data outputs

(D15-D0) of both channels to known values. The digital

output test patterns are enabled by serially programming

mode control registers A2, A3 and A4. When enabled,

the test patterns override all other formatting modes: 2’s

complement and randomizer.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A2. The current drive for all

digital outputs including DCO and FR are disabled to save

power or enable in-circuit testing. When disabled the com-

mon mode of each output pair becomes high impedance,

but the differential impedance may remain low.

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire device is powered down,

resulting in 1mW power consumption. Sleep mode is

enabled by mode control register A1 (serial program-

ming mode), or by SDI (parallel programming mode).

The amount of time required to recover from sleep mode

depends on the size of the bypass capacitors on VREF

REFH and REFL. For the suggested values in Figure 8, the

A/D will stabilize after 2ms.

In nap mode any combination of A/D channels can be

powered down while the internal reference circuits and the

PLL stay active, allowing faster wake up than from sleep

mode. Recovering from nap mode requires at least 100

clock cycles. If the application demands very accurate DC

settling then an additional 50µs should be allowed so the

on-chip references can settle from the slight temperature

shift caused by the change in supply current as the A/D

leaves nap mode. Nap mode is enabled by mode control

DEVICE PROGRAMMING MODES

The operating modes of the LTC2192/LTC2191/LTC2190

can be programmed by either a parallel interface or a

simple serial interface. The serial interface has more ﬂex-

ibility and can program all available modes. The parallel

interface is more limited and can only program some of

the more commonly used modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to VDD. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to VDD or ground, or driven by 1.8V, 2.5V or

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 3 shows the

modes set by CS, SCK, SDI and SDO.

Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)

PIN DESCRIPTION

CS/SCK 2-Lane/4-Lane/1-Lane Selection Bits

00 = 2-Lane Output Mode

01 = 4-Lane Output Mode

10 = 1-Lane Output Mode

11 = Not Used

SDI Power Down Control Bit

0 = Normal Operation

1 = Sleep Mode

SDO LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D mode control

registers. Data is written to a register with a 16-bit serial

word. Data can also be read back from a register to verify

its contents.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the ﬁrst 16 rising edges of

SCK. Any SCK rising edges after the ﬁrst 16 are ignored.

The data transfer ends when CS is taken high again.

APPLICATIONS INFORMATION

219210f

LTC2192

LTC2191/LTC2190

APPLICATIONS INFORMATION

The ﬁrst bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The ﬁnal eight bits are the register data (D7:D0).

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address bits

(A6:A0) will be read back on the SDO pin (see the Timing

Diagrams). During a read back command the register is

not updated and data on SDI is ignored.

The SDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and read back is not needed,

Table 4. Serial Programming Mode Register Map (PAR/SER = GND)

D7 D6 D5 D4 D3 D2 D1 D0

RESET X X X X X X X

Bit 7 RESET Software Reset Bit

0 = Not Used

1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in Sleep Mode.

This Bit is Automatically Set Back to Zero at the end of the SPI write command. The Reset register is write-only.

Data read back from the Reset register will be random.

Bits 6-0 Unused, Don’t Care Bits.

D7 D6 D5 D4 D3 D2 D1 D0

DCSOFF RAND TWOSCOMP SLEEP NAP_2 X X NAP_1

Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer On

1 = Clock Duty Cycle Stabilizer Off. This is not recommended.

Bit 6 RAND Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

Bit 5 TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

Bits 4, 3, 0 SLEEP:NAP_2:NAP_1 Sleep/Nap Mode Control Bits

000 = Normal Operation

0X1 = Channel 1 in Nap Mode

01X = Channel 2 in Nap Mode

1XX = Sleep Mode. Both Channels are Disabled.

Note: Any Combination of Channels Can Be Placed in Nap Mode

Bits 1, 2 Unused, Don’t Care Bits

then SDO can be left ﬂoating and no pull-up resistor is

needed.

Table 4 shows a map of the mode control registers.

Software Reset

If serial programming is used, the mode control registers

should be programmed as soon as possible after the power

supplies turn on and are stable. The ﬁrst serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset, bit D7 in the

reset register is written with a logic 1. After the reset SPI

write command is complete, bit D7 is automatically set

back to zero.

LTC2192

LTC2191/LTC2190

219210f

APPLICATIONS INFORMATION

D7 D6 D5 D4 D3 D2 D1 D0

ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTTEST OUTMODE1 OUTMODE0

Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 4 TERMON LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0

Bit 3 OUTOFF Output Disable Bit

0 = Digital Outputs are Enabled

1 = Digital Outputs are Disabled

Bit 2 OUTTEST Digital Output Test Pattern Control Bit

0 = Digital Output Test Pattern Off

1 = Digital Output Test Pattern On

Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits

00 = 2-Lane Output Mode

01 = 4-Lane Output Mode

10 = 1-Lane Output Mode

11 = Not Used

D7 D6 D5 D4 D3 D2 D1 D0

TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8

Bits 7-0 TP15:TP8 Test Pattern Data Bits (MSB)

TP15:TP8 Set the Test Pattern for Data Bit 15 (MSB) Through Data Bit 8.

D7 D6 D5 D4 D3 D2 D1 D0

TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0

Bits 7-0 TP7:TP0 Test Pattern Data Bits (LSB)

TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).

219210f

LTC2192

LTC2191/LTC2190

APPLICATIONS INFORMATION

GROUNDING AND BYPASSING

The LTC2192/LTC2191/LTC2190 require a printed circuit

board with a clean unbroken ground plane. A multilayer

board with an internal ground plane in the ﬁrst layer be-

neath the ADC is recommended. Layout for the printed

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass

capacitors must be located as close to the pins as possible.

Size 0402 ceramic capacitors are recommended. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

Of particular importance is the capacitor between REFH

and REFL. This capacitor should be on the same side of

the circuit board as the A/D, and as close to the device

as possible.

The analog inputs, encode signals, and digital outputs

should not be routed next to each other. Ground ﬁll and

grounded vias should be used as barriers to isolate these

signals from each other.

HEAT TRANSFER

Most of the heat generated by the LTC2192/LTC2191/

LTC2190 is transferred from the die through the bottom-

side exposed pad and package leads onto the printed circuit

board. For good electrical and thermal performance, the

exposed pad must be soldered to a large grounded pad

on the PC board. This pad should be connected to the

internal ground planes by an array of vias.

TYPICAL APPLICATIONS

LTC2192

VCM1

GND

AIN1+

AIN1–

GND

REFH

REFL

REFH

REFL

PAR/SER

AIN2+

AIN2–

GND

VCM2

OUT1C+

OUT1C–

OUT1D+

OUT1D–

DCO+

DCO–

OVDD

OGND

FR+

FR–

OUT2A+

OUT2A–

OUT2B+

OUT2B–

VDD

SENSE

GND

VREF

GND

SDO

GND

OUT1A+

OUT1A–

OUT1B+

OUT1B–

VDD

ENC+

ENC–

SCK

SDI

GND

OUT2D–

OUT2D+

OUT2C–

OUT2C+

–

CN1

C3 0.1µF

C29

0.1µF

2.2µF

C2 0.1µF

C16 0.1µF

219210 TA02

OVDD DIGITAL

OUTPUTS

C37

0.1µF

VDD

SENSE

SDO

VDD

ENCODE

INPUT SPI

PORT

PAR/SER

AIN1+

AIN1–

AIN2+

AIN2–

LTC2192

LTC2191/LTC2190

219210f

TYPICAL APPLICATIONS

Top Side

Inner Layer 3

Inner Layer 5

Inner Layer 2

Inner Layer 4

Bottom Side

219210f

LTC2192

LTC2191/LTC2190

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UKG Package

52-Lead Plastic QFN (7mm × 8mm)

(Reference LTC DWG # 05-08-1729 Rev Ø)

7.00 ± 0.10

(2 SIDES)

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45°C

CHAMFER

0.40 ± 0.10

5251

BOTTOM VIEW—EXPOSED PAD

TOP VIEW

SIDE VIEW

6.50 REF

(2 SIDES)

8.00 ± 0.10

(2 SIDES)

5.50 REF

(2 SIDES)

0.75 ± 0.05

R = 0.115

TYP

R = 0.10

TYP 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

6.45 ±0.10

5.41 ±0.10

0.00 – 0.05

(UKG52) QFN REV Ø 0306

5.50 REF

(2 SIDES)

5.41 ±0.05

6.45 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

6.10 ±0.05

7.50 ±0.05

6.50 REF

(2 SIDES) 7.10 ±0.05 8.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

LTC2192

LTC2191/LTC2190

219210f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2011

LT 0611 • PRINTED IN USA

TYPICAL APPLICATION

2-Tone FFT, fIN = 70MHz and 69MHz

16-BIT

ADC CORE

CH1

ANALOG

INPUT

CH2

ANALOG

INPUT

ENCODE

INPUT

S/H

16-BIT

ADC CORE

OUT1A

OUT1B

OUT1C

OUT1D

OUT2A

OUT2B

OUT2C

OUT2D

DATA CLOCK OUT

FRAME

S/H DATA

SERIALIZER

PLL

OGND

219210 TA01a

SERIALIZED

LVDS

OUTPUTS

GND

VDD OVDD

1.8V1.8V

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

219210 G07

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