Integrated
Circuit
Systems, Inc.
General Description Features
ICS9248-56
Block Diagram
Frequency Timing Generator for Pentium II Systems
9248-56 Rev E 12/27/00
Pin Configuration
28 pin SSOP and TSSOP
Pentium is a trademark on Intel Corporation.
• Generates the following system clocks:
- 2CPU(2.5V) up to 100MHz.
- 6 PCI(3.3V) @ 33.3MHz (Includes one free running).
- 1 REF clks (3.3V) at 14.318MHz.
- 1 Fixed clock at 48MHz
- 1 Fixed clock at 48 or 24MHz
• Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
• Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
• Efficient Power management scheme through stop clocks
and power down modes.
• Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
• 28 pin 209mil SSOP and 173mil TSSOP
The ICS9248-56 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-56 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
Power Groups
VDD, GND = PLL core
VDDREF, GNDREF = REF(0:1), X1, X2
VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4)
VDD48, GND48 = 48MHz, 48/24MHz
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248-56
Pin Descriptions
Pi n num ber Pi n nam e Type Descri pt i on
1 GNDREF P ower Ground for 14. 318 MHz referenc e cl ock outputs
2 X1 Input 14. 318 M Hz crystal i nput
3 X2 Output 14.318 M Hz cry stal output
4 PCICLK_F Output 3.3 V free running P CI c lock output, will not be st opped by t he P CI_STOP#
5,6, 9,10, 11 P CICLK (1:5) Output 3.3 V P CI clock output s, generat i ng ti m ing requirem ents for Penti um II
7 GNDP CI P ower Ground for PCI cl ock outputs
8 V DDPCI P ower 3. 3 V power for the P CI cl ock outputs
12 V DD48 P ower 3. 3 V power for 48/24 MHz c locks
13 48 MHz Output 3.3 V 48 MHz cl ock output , fixed frequenc y c lock typical l y used with US B devi ces
14 TS#/48/24MHz Output 3. 3 V 48 or 24 MHz output and Tri -stat e opti on, active l ow = tri state m ode for t es ting,
act ive hi gh = normal operati on
15 GND48 Power Ground for 48/24 M Hz clocks
16 SEL 100/66# Input
control for the frequenc y of clocks at the CPU & PCICLK output pins. If logic "0" is
used t he 66.6 M Hz frequenc y i s sel ect ed. If Logi c " 1" i s used, the 100 MHz
frequency is sel ected. The P CI c l ock i s mul ti plexed to run at 33.3 M Hz for bot h
selected cases.
17 PD# Input Asynchronous active low i nput pin used to power down the device i nto a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latenc y of the power down will not be great er t han 3ms.
18 CPU_STOP# Input A synchronous active l ow input pi n used to stop the CPUCLK i n active l ow s tate, al l
other clock s wi ll conti nue to run. The CP UCLK will have a "Turnon " latenc y of at
l east 3 CP U cl ocks.
19 VDD P ower Isolated 3.3 V power for core
20 PCI-Stop# Input Synchronous acti ve low input used to stop the P CICLK in act ive l ow st ate. It wi l l not
effect P CICLK _F or any other out puts.
21 GND Power Isolated ground for core
22 GNDL P ower Ground for CPU cl ock outputs
23,24 CPUCLK (1:0) Output 2.5 V CPU c lock outputs
25 V DDL P ower 2. 5 V power for CPU c lock outputs
26 SPREAD# Output Power-on s pread spec trum enabl e opti on. A cti ve l ow = spread s pect rum cl ocki ng
enabl e. Active hi gh = spread spectrum cl ocking di s able.
27 REF0/SEL48# Output 3.3 V 14.318 MHz referenc e cl ock output and power-on 48/24 M Hz sel ect opti on.
A cti ve low = 48 MHz output at pi n 14. A ctive hi gh = 24 MHz output at pi n 14.
28 V DDREF P ower 3.3 V power for 14. 318 M Hz referenc e cl ock outputs.
3
ICS9248-56
Select Functions
(Functionality determined by TS# and SEL100/66# pin, see below)
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
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Power Management
ICS9248-56 Power Management Requirements
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry .
Board routing and signal loading may have a large impact on the initial clock distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only .
The REF will be stopped independant of these.
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4
ICS9248-56
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-56. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-56 internally . The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-56. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9248-56.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
5
ICS9248-56
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-56 prior to its control action of
powering down the clock synthesizer . Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3 ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
6
ICS9248-56
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability .
Electrical Characteristic s - Input/Supply/Common Output Parameters
TA =
0
- 7
0C
;
S
upp
l
y Vo
l
tage VDD = VDDL =
3
.
3
V +
/
-
5%
(
un
l
ess ot
h
erw
i
se state
d)
P
A
R
A
METER
S
YMB
O
L
CO
NDITI
O
N
S
MIN TYP M
A
X UNIT
S
Input High Voltage VIH 2V
DD+0.3 V
Input Low Voltage VIL VSS-0.3 0.8 V
Input High Current IIH VIN = VDD 0.1 5
µ
A
Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 2.0
µ
A
Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 -100
µ
A
Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz 60 180 mA
Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz 66 180 mA
Power Down I DD3.3PD CL = 0 pF; With input address t o Vdd or GND 70 600
µ
A
Supply Current
Input fr equency FiVDD = 3.3 V; 11 14.318 16 MHz
Input Capaci tance
CIN Logic Inputs 5 pF
CINX X1 & X2 pins 27 36 45 pF
Transition Time
Ttrans To 1st crossing of target Freq. 3 ms
Clk Stabilization
TSTAB From VDD = 3.3 V to 1% target Freq. 3 ms
Sk
ew
TCPU-PCI VT = 1.5 V; 1.5 2.4 4 ns
Guaranteed by design, not 100% tested i n producti on.
Electr ical Characteri st ics - Input/Supply/Common Output Parameter s
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz 16 72 mA
Supply Current IDD2.5OP100 CL = 0 pF; Select @ 100 MHz 23 100 mA
Skew1tCPU-PCI2 VT = 1.5 V; VTL = 1.25 V 1.5 3 4 ns
1Guaranteed by design, not 100% tested in production.
7
ICS9248-56
Electrical Characteristics - CPUCLK
TA =
0
- 7
0C
; VDD =
3
.
3
V +
/
-
5%
, VDDL =
2
.
5
V +
/
-
5%
;
C
L =
10
-
20
pF
(
un
l
ess ot
h
erw
i
se state
d)
PARAMETER
S
YMB
O
L
CO
NDITI
O
N
S
MIN TYP MAX UNIT
S
Output High Voltage VOH2B IOH = -12.0 mA 1.8 2.3 V
Output Low Voltag e VOL2B IOL = 12 mA 0.31 0.4 V
Output High Current IOH2B VOH = 1.7 V -27 mA
Output Low Current I OL2B VOL = 0.7 V 27 mA
Rise Time tr2B
VOL = 0.4 V, V OH = 2.0 V 0.4 1.15 1.6 ns
Fall Time tf2B
VOH = 2.0 V, V OL = 0.4 V 0.4 1.4 1.6 ns
Duty Cycle dt2B
VT = 1.25 V 44 48 55 %
Skew tsk2B
VT = 1.25 V 134 175 ps
tjcyc-cyc2B
VT = 1.25 V 186 250 ps
tj1s2B
VT = 1.25 V 52 150 ps
tjabs2B
VT = 1.25 V -250 150 +250 ps
Guarantee d by design, not 100% teste d in pr oduction.
Jitter
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH1 IOH = -18 mA 2.1 3.3 V
Output Low Voltage VOL1 IOL = 9.4 mA 0.1 0.4 V
Output High Current I OH1 VOH = 2.0 V -22 mA
Output Low Current IOL1 VOL = 0.8 V 16 57 mA
Rise Ti me1tr1 VOL = 0.4 V, VOH = 2.4 V 1.6 2 ns
Fall Time1tf1 VOH = 2.4 V, VOL = 0.4 V 1.8 2 ns
Duty Cycle1dt1 VT = 1.5 V 45 50 5 5 %
Skew1tsk1 VT = 1.5 V 222 500 ps
tjcyc-cyc
1
VT = 1.5 V 186 500 ps
t
j
1s1 VT = 1.5 V 52 150 ps
tjabs1 VT = 1.5 V 200 500 ps
1Guaranteed by design, not 100 % tested in production.
Jitter
8
ICS9248-56
Electrical Characteristics - REF/48MHz/24MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH5 IOH = -12 mA 2.6 3.1 V
Output Low Voltage VOL5 IOL = 9 mA 0.17 0.4 V
Output High Current IOH5 VOH = 2.0 V -44 -22 mA
Output Lo w Current IOL5 VOL = 0.8 V 16 42 mA
Rise Ti me1tr5 VOL = 0.4 V, VOH = 2.4 V 1.4 4 ns
Fall Time1tf5 VOH = 2.4 V, VOL = 0.4 V 1.1 4 ns
Duty Cycle1dt5 VT = 1.5 V 45 53 55 %
t
j
1
σ
5VT = 1.5 V, REF 185 250 ps
t
j
abs5 VT = 1.5 V, REF 385 800 ps
t
j
1
σ
5VT = 1.5 V, 48 MHz 169 250 ps
tjabs5 VT = 1.5 V, 48 MHz 469 800 ps
Jitter1
Jitter1
9
ICS9248-56
General Layout Precautions:
1) Use a ground plane on the top layer of the
PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
Capacitor V alues:
C1, C2 : Crystal load values determined by user
All unmarked capacitors are 0.01F ceramic
10
ICS9248-56
Ordering Information
ICS9248F-56
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = S tandard Device
Example:
ICS XXXXy F - PPP
MIN MAX MIN MAX
A - 2.00 - .079
A1 0.05 - .002 -
A2 1.65 1.85 .065 .073
b 0.22 0.38 .009 .015
c 0.09 0.25 .0035 .010
D
E 7.40 8.20 .291 .323
E1 5.00 5.60 .197 .220
e
L 0.55 0.95 .022 .037
N
α0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
28 9.90 10.50 .390 .413
MO-150 JEDEC
Doc.# 10-0033 6/1/00 Rev B
ND mm. D (inch)
SEE VARIATIONS
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS In Inches
COMMON DIMENSIONS
SEE VARIATIONS
0.65 BASIC 0.0256 BASIC
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
11
ICS9248-56
Ordering Information
ICS9248yG-56-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - PPP - T
4.40 mm. Body, 0.65 mm. pitch TSSOP
(173 mil) (0.0256 mil)
MIN MAX MIN MAX
A - 1.20 - .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.19 0.30 .007 .012
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e 0.65 BASIC 0.02 56 BASIC
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa - 0.10 - .004
VARIATIONS
MIN MAX MIN MAX
28 9.60 9.80 .378 .386
MO-153 JE DEC
Doc.# 10-0038
7/6/00 R ev B
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
CO MMO N DIMENSIONS In Inches
COMMON DIMENSIONS
SEE VARIATIONS
6.40 BASIC 0.2 5 2 BASIC
ND mm. D (inch)
SEE VARIATIONS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.