NCP43080AMTTWG - ON SEMICONDUCTOR

February, 2017 − Rev. 0 1Publication Order Number:

NCP43080/D

NCP43080

Synchronous Rectifier

Controller

The NCP43080 is a synchronous rectifier controller for switch

mode power supplies. The controller enables high efficiency designs

for flyback and quasi resonant flyback topologies.

Externally adjustable minimum off−time and on−time blanking

periods provides flexibility to drive various MOSFET package types

and PCB layout. A reliable and noise less operation of the S R system is

insured due to the Self Synchronization feature. The NCP43080 also

utilizes Kelvin connection of the driver to the MOSFET to achieve high

efficiency operation at full load and utilizes a light load detection

architecture to achieve high ef ficiency at light load.

The precise turn−off threshold, extremely low turn−off delay time

and high sink current capability of the driver allow the maximum

synchronous rectification MOSFET conduction time. The high

accuracy driver and 5 V gate clamp make it ideally suited for directly

driving GaN devices.

Features

•Self−Contained Control of Synchronous Rectifier in CCM, DCM and

QR for Flyback, Forward or LLC Applications

•Precise True Secondary Zero Current Detection

•Rugged Current Sense Pin (up to 150 V)

•Adjustable Minimum ON−Time

•Adjustable Minimum OFF-Time with Ringing Detection

•Adjustable Maximum ON−Time for CCM Controlling of Primary

QR Controller

•Improved Robust Self Synchronization Capability

•8 A / 4 A Peak Current Sink / Source Drive Capability

•Operating Voltage Range up to VCC = 35 V

•Automatic Light−load & Disable Mode

•Adaptive Gate Drive Clamp

•GaN Transistor Driving Capability (options A and C)

•Low Startup and Disable Current Consumption

•Maximum Operation Frequency up to 1 MHz

•SOIC-8 and DFN−8 (4x4) and WDFN8 (2x2) Packages

•These are Pb−Free Devices

Typical Applications

•Notebook Adapters

•High Power Density AC/DC Power Supplies (Cell Phone Chargers)

•LCD TVs

•All SMPS with High Efficiency Requirements

SOIC−8

D SUFFIX

CASE 751

MARKING

DIAGRAMS

43080x = Specific Device Code

x = A, B, C, D or Q

Fx = Specific Device Code

x = A or D

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G= Pb−Free Package

43080x

ALYW G

(Note: Microdot may be in either location)

43080x

ALYWG

DFN8

MN SUFFIX

CASE 488AF

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See detailed ordering and shipping information on page 33 o

this data sheet.

ORDERING INFORMATION

FxMG

WDFN8

MT SUFFIX

CASE 511AT

NCP43080

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Figure 1. Typical Application Example − LLC Converter with Optional LLD

OK1

RTN

MIN_TON

MIN_TOFF

MIN_TON

MIN_TOFF

Figure 2. Typical Application Example − DCM, CCM or QR Flyback Converter with optional LLD

Vbulk

FLYBACK

CONTROL

CIRCUITRY

+Vout

GND

OK1

C1 C2

TR1

R5 R6

VCC

DRV

FB CS

NCP43080

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Figure 3. Typical Application Example − Primary Side Flyback Converter with optional LLD

Vbulk

FLYBACK

SIDE

CONTROLLER

+Vout

GND

C1 C2

C10

TR1

R9 R10

R11

PRIMARY

VCC

DRV

COMP CS

ZCD

Figure 4. Typical Application Example − QR Converter − Capability to Force Primary into CCM Under Heavy

Loads utilizing MAX−TON

Vbulk

CONTROL

CIRCUITRY

+Vout

GND

OK1

R10

TR1

TR2

NCP43080Q

R11

R12

R13

R14

R15

R16

R17

R18

R19

C2 C8 C9

VCC

DRV

FB CSZCD

NCP43080

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PIN FUNCTION DESCRIPTION

ver. A, B, C, D ver. Q Pin Name Description

1 1 VCC Supply voltage pin

2 2 MIN_TOFF Adjust the minimum off time period by connecting resistor to ground.

3 3 MIN_TON Adjust the minimum on time period by connecting resistor to ground.

4 4 LLD This input modulates the driver clamp level and/or turns the driver off during light load

conditions.

5 − NC Leave this pin opened or tie it to ground.

6 6 CS Current sense pin detects if the current flows through the SR MOSFET and/or its body

diode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin can

decrease the turn off threshold if needed.

7 7 GND Ground connection for the SR MOSFET driver, VCC decoupling capacitor and for mini-

mum on and off time adjust resistors and LLD input.

GND pin should be wired directly to the SR MOSFET source terminal/soldering point

using Kelvin connection. DFN8 exposed flag should be connected to GND

8 8 DRV Driver output for the SR MOSFET

− 5 MAX_TON Adjust the maximum on time period by connecting resistor to ground.

Figure 5. Internal Circuit Architecture − NCP43080A, B, C, D

Minimum ON time

generator

MIN_TON

detection

100μA

MIN_TOFF

CS_ON

CS_OFF

DRV

VCC

GND

VCC managment

UVLO

DRV Out

DRIVER

VDD

CS_RESET

LLD

Disable detection

V DRV clamp

modulation

V_DRV

control

ADJ ELAPSED

Minimum OFF

time generator

ADJ

RESET

ELAPSED

Control logic

DISABLE

NCP43080

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Minimum ON time

generator

MIN_TON

detection

100mA

MIN_TOFF

MAX_TON

CS_ON

CS_OFF

DRV

VCC

GND

VCC managment

UVLO

DRV Out

DRIVER

VDD

CS_RESET

LLD

Disable detection

V DRV clamp

modulation

V_DRV

control

ADJ

ELAPSED

Minimum OFF

time generator

ADJ

RESET

ELAPSED

Control logic

DISABLE

ELAPSED

Maximum ON time

generator EN

ADJ

Figure 6. Internal Circuit Architecture − NCP43080Q (CCM QR) with MAX_TON

NCP43080

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ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage VCC −0.3 to 37.0 V

MIN_TON, MIN_TOFF, MAX_TON, LLD Input Voltage VMIN_TON,

VMIN_TOFF,

VMAX_TON, VLLD

−0.3 to VCC V

Driver Output Voltage VDRV −0.3 to 17.0 V

Current Sense Input Voltage VCS −4 to 150 V

Current Sense Dynamic Input Voltage (tPW = 200 ns) VCS_DYN −10 to 150 V

MIN_TON, MIN_TOFF, MAX_TON, LLD Input Current IMIN_TON, IMIN_TOFF,

IMAX_TON, ILLD −10 to 10 mA

Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8 RqJ−A_SOIC8 160 °C/W

Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, DFN8 RqJ−A_DFN8 80 °C/W

Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, WDFN8 RqJ−A_WDFN8 160 °C/W

Maximum Junction Temperature TJMAX 150 °C

Storage Temperature TSTG −60 to 150 °C

ESD Capability, Human Body Model, Except Pin 6, per JESD22−A114E ESDHBM 2000 V

ESD Capability, Human Body Model, Pin 6, per JESD22−A114E ESDHBM 1000 V

ESD Capability, Machine Model, per JESD22−A115−A ESDMM 200 V

ESD Capability, Charged Device Model, Except Pin 6, per JESD22−C101F ESDCDM 750 V

ESD Capability, Charged Device Model, Pin 6, per JESD22−C101F ESDCDM 250 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. This device meets latch−up tests defined by JEDEC Standard JESD78D Class I.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Maximum Operating Input Voltage VCC 35 V

Operating Junction Temperature TJ−40 125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS

−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VLLD = 0 V; VCS = −1 to +4 V; fCS = 100 kHz, DCCS =

50%, unless otherwise noted. Typical values are at TJ = +25°C

Parameter Test Conditions Symbol Min Typ Max Unit

SUPPLY SECTION

VCC UVLO (ver. B & C) VCC rising VCCON 8.3 8.8 9.3 V

VCC falling VCCOFF 7.3 7.8 8.3

VCC UVLO Hysteresis (ver. B & C) VCCHYS 1.0 V

VCC UVLO (ver. A, D & Q) VCC rising VCCON 4.20 4.45 4.80 V

VCC falling VCCOFF 3.70 3.95 4.20

VCC UVLO Hysteresis

(ver. A, D & Q) VCCHYS 0.5 V

Start−up Delay VCC rising from 0 to VCCON + 1 V @ tr = 10 mstSTART_DEL 75 125 ms

NCP43080

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ELECTRICAL CHARACTERISTICS

−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VLLD = 0 V; VCS = −1 to +4 V; fCS = 100 kHz, DCCS =

50%, unless otherwise noted. Typical values are at TJ = +25°C

Parameter UnitMaxTypMinSymbolTest Conditions

SUPPLY SECTION

Current Consumption,

RMIN_TON = RMIN_TOFF = 0 kWCDRV = 0 nF, fSW = 500 kHz A, C ICC 3.0 4.0 5.6 mA

B, D, Q 3.5 4.5 6.0

CDRV = 1 nF, fSW = 500 kHz A, C 4.5 6.0 7.5

B, D, Q 7.7 9.0 10.7

CDRV = 10 nF, fSW = 500 kHz A, C 20 25 30

B, D, Q 40 50 60

Current Consumption No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF

= 0 kWICC 1.0 2.0 2.5 mA

Current Consumption below UVLO No switching, VCC = VCCOFF – 0.1 V, VCS = 0 V ICC_UVLO 75 125 mA

Current Consumption in Disable

Mode VLLD = VCC − 0.1 V, VCS = 0 V ICC_DIS 30 55 75 mA

DRIVER OUTPUT

Output Voltage Rise−Time CDRV = 10 nF, 10% to 90% VDRVMAX tr40 55 ns

Output Voltage Fall−Time CDRV = 10 nF, 90% to 10% VDRVMAX tf20 35 ns

Driver Source Resistance RDRV_SOURCE 1.2 W

Driver Sink Resistance RDRV_SINK 0.5 W

Output Peak Source Current IDRV_SOURCE 4 A

Output Peak Sink Current IDRV_SINK 8 A

Maximum Driver Output Voltage VCC = 35 V, CDRV > 1 nF, VLLD = 0 V,

(ver. B, D and Q) VDRVMAX 9.0 9.5 10.5 V

VCC = 35 V, CDRV > 1 nF, VLLD = 0 V, (ver. A, C) 4.3 4.7 5.5

Minimum Driver Output Voltage VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. B) VDRVMIN 7.2 7.8 8.5 V

VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. C) 4.2 4.7 5.3

VCC = VCCOFF + 200 mV, VLLD = 0 V 3.6 4.0 4.4

Minimum Driver Output Voltage VLLD = VCC − VLLDREC V VDRVLLDMIN 0.0 0.4 1.2 V

CS INPUT

Total Propagation Delay From CS

to DRV Output On VCS goes down from 4 to −1 V, tf_CS = 5 ns tPD_ON 35 60 ns

Total Propagation Delay From CS

to DRV Output Off VCS goes up from −1 to 4 V, tr_CS = 5 ns tPD_OFF 12 23 ns

CS Bias Current VCS = −20 mV ICS −105 −100 −95 mA

Turn On CS Threshold Voltage VTH_CS_ON −120 −75 −40 mV

Turn Off CS Threshold Voltage Guaranteed by Design VTH_CS_OFF −1 0 mV

Turn Off Timer Reset Threshold

Voltage VTH_CS_RESET 0.4 0.5 0.6 V

CS Leakage Current VCS = 150 V ICS_LEAKAGE 0.4 mA

MINIMUM tON and tOFF ADJUST

Minimum tON time RMIN_TON = 0 WtON_MIN 25 56 75 ns

Minimum tOFF time RMIN_TOFF = 0 WtOFF_MIN 160 245 290 ns

Minimum tON time RMIN_TON = 10 kWtON_MIN 0.92 1.00 1.08 ms

Minimum tOFF time RMIN_TOFF = 10 kWtOFF_MIN 0.92 1.00 1.08 ms

Minimum tON time RMIN_TON = 50 kWtON_MIN 4.62 5.00 5.38 ms

Minimum tOFF time RMIN_TOFF = 50 kWtOFF_MIN 4.62 5.00 5.38 ms

NCP43080

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ELECTRICAL CHARACTERISTICS

−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VLLD = 0 V; VCS = −1 to +4 V; fCS = 100 kHz, DCCS =

50%, unless otherwise noted. Typical values are at TJ = +25°C

Parameter UnitMaxTypMinSymbolTest Conditions

MAXIMUM tON ADJUST

Maximum tON Time VMAX_TON = 3 V tON_MAX 4.3 4.8 5.3 ms

Maximum tON Time VMAX_TON = 0.3 V tON_MAX 41 48 55 ms

Maximum tON Output Current VMAX_TON = 0.3 V, VCS = 0 V IMAX_TON −105 −100 −95 mA

LLD INPUT

Disable Threshold VLLD_DIS = VCC − VLLD VLLD_DIS 0.8 0.9 1.0 V

Recovery Threshold VLLD_REC = VCC − VLLD VLLD_REC 0.9 1.0 1.1 V

Disable Hysteresis VLLD_DISH 0.1 V

Disable Time Hysteresis Disable to Normal, Normal to Disable tLLD_DISH 45 ms

Disable Recovery Time tLLD_DIS_REC 6.0 12.5 16.0 ms

Low Pass Filter Frequency fLPLLD 6 10 13 kHz

Driver Voltage Clamp Threshold VDRV = VDRVMAX, VLLDMAX = VCC − VLLD VLLDMAX 2.0 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

TYPICAL CHARACTERISTICS

Figure 7. VCCON and VCCOFF Levels,

ver. A, D, Q Figure 8. VCCON and VCCOFF Levels,

ver. B, C

TJ (°C) TJ (°C)

100806040200−20−40

3.7

3.8

3.9

4.1

4.2

4.4

4.6

4.7

100806040200−20−40

7.3

7.5

7.7

8.1

8.3

8.7

8.9

9.3

VCC (V)

120

4.0

4.3

4.5 VCCON

VCCOFF

VCCON

VCCOFF

120

7.9

8.5

9.1

NCP43080

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TYPICAL CHARACTERISTICS

Figure 9. Current Consumption, CDRV = 0 nF,

fCS = 500 kHz, ver. D Figure 10. Current Consumption, VCC =

VCCOFF − 0.1 V, VCS = 0 V, ver. D

VCC (V) TJ (°C)

3025 3520151050

1201006040200−20−40

100

120

Figure 11. Current Consumption, VCC = 12 V,

VCS = −1 to 4 V, fCS = 500 kHz, ver. A Figure 12. Current Consumption, VCC = 12 V,

VCS = −1 to 4 V, fCS = 500 kHz, ver. D

TJ (°C) TJ (°C)

100806040200−20−40

Figure 13. Current Consumption in Disable,

VCC = 12 V, VCS = 0 V, VLLD = VCC − 0.1 V

TJ (°C)

100806040200−20−40

ICC (mA)

ICC_UVLO (mA)

ICC (mA)

ICC_DIS (mA)

TJ = 85°CTJ = 55°CTJ = 125°C

TJ = 25°C

TJ = 0°C

TJ = −20°C

TJ = −40°C

120

CDRV = 0 nF

CDRV = 1 nF

CDRV = 10 nF

CDRV = 0 nF

CDRV = 1 nF

CDRV = 10 nF

120

NCP43080

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TYPICAL CHARACTERISTICS

Figure 14. CS Current, VCS = −20 mV Figure 15. CS Current, VCC = 12 V

TJ (°C) VCS (V)

100806040200−20−40

−110

−106

−104

−100

−98

−96

−94

−90

0.80.60.20−0.2−0.4−0.8−1.0

−1.4

−1.2

−1.0

−0.8

−0.6

−0.4

−0.2

Figure 16. Supply Current vs. CS Voltage,

VCC = 12 V Figure 17. CS Turn−on Threshold

VCS (V) TJ (°C)

3210−1−2−3−4

0.5

1.0

1.5

2.0

2.5

3.0

100806040200−20−40

−150

−130

−110

−90

−70

−50

−30

Figure 18. CS Turn−off Threshold Figure 19. CS Reset Threshold

TJ (°C) TJ (°C)

100806040200−20−40

−2.0

−1.5

−1.0

−0.5

0.5

1.0

0.40

0.45

0.50

0.55

0.60

ICS (mA)

ICC (mA)

VTH_CS_ON (mV)

VTH_CS_OFF (mV)

VTH_CS_RESET (V)

120

−92

−102

−108

−0.6 0.4 1.0

TJ = 125°C

TJ = 85°C

TJ = 55°C

TJ = 25°C

TJ = 0°C

TJ = −20°C

TJ = −40°C

TJ = 125°C

TJ = 85°C

TJ = 55°C

TJ = 25°C

TJ = 0°C

TJ = −20°C

TJ = −40°C

120

120 100806040200−20−40 120

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TYPICAL CHARACTERISTICS

Figure 20. CS Reset Threshold Figure 21. CS Leakage, VCS = 150 V

VCC (V)

302520 35151050

0.30

0.35

0.45

0.50

0.60

0.65

0.70

0.80

Figure 22. Propagation Delay from CS to DRV

Output On Figure 23. Propagation Delay from CS to DRV

Output Off

TJ (°C) TJ (°C)

100806040200−20−40

VTH_CS_RESET (V)tPD_ON (ns)

tPD_OFF (ns)

0.40

0.55

0.75

120

TJ (°C)

100 1206040200−20−40

120

140

180

200

ICS_LEAKAGE (nA)

100

160

Figure 24. Minimum On−time RMIN_TON = 0 WFigure 25. Minimum On−time RMIN_TON = 10 kW

TJ (°C) TJ (°C)

100806040200−20−40

0.92

0.94

0.96

0.98

1.00

1.04

1.06

1.08

tMIN_TON (ns)

tMIN_TON (ms)

120

1.02

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TYPICAL CHARACTERISTICS

Figure 26. Minimum On−time RMIN_TON = 50 kWFigure 27. Minimum Off−time RMIN_TOFF = 0 W

TJ (°C) TJ (°C)

100806040200−20−40

4.6

4.7

4.8

4.9

5.0

5.2

5.3

5.4

100806040200−20−40

190

200

220

230

240

260

270

290

Figure 28. Minimum Off−time RMIN_TOFF =

10 kW

Figure 29. Minimum Off−time RMIN_TOFF =

50 kW

TJ (°C) TJ (°C)

100806040200−20−40

0.92

0.94

0.96

1.00

1.02

1.04

1.06

1.08

100806040200−20−40

4.6

4.7

4.8

4.9

5.0

5.1

5.3

5.4

Figure 30. Minimum On−time RMIN_TON = 10 kWFigure 31. Minimum Off−time RMIN_TOFF =

10 kW

VCC (V) VCC (V)

302520 35151050

0.92

0.94

0.96

0.98

1.00

1.02

1.03

1.04

35302520151050

092

0.94

0.96

0.98

1.00

1.02

1.06

1.08

tMIN_TON (ms)

tMIN_TOFF (ns)

tMIN_TOFF (ms)

tMIN_TON (ms)

tMIN_TOFF (ms)

120

5.1

120

210

250

280

120

0.98

120

5.2

1.01

1.04

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TYPICAL CHARACTERISTICS

Figure 32. Driver and Output Voltage, ver. B, D

and Q Figure 33. Driver Output Voltage, ver. A and C

TJ (°C) TJ (°C)

100806040200−20−40

9.0

9.2

9.4

9.6

9.8

10.0

10.2

10.4

100806040200−20−40

4.3

4.5

4.7

4.9

5.1

5.3

5.5

Figure 34. Maximum On−time, ver. Q Figure 35. Maximum On−time, VMAX_TON = 3 V,

ver. Q

VMAX_TON (V) TJ (°C)

3.02.52.01.51.00.50

100806040200−20−40

4.3

4.4

4.6

4.7

4.8

5.0

5.1

5.3

Figure 36. Maximum On−time, VMAX_TON =

0.3 V, ver. Q

TJ (°C)

100806040200−20−40

VDRV (V)

tMAX_TON (ms)

120

VCC = 12 V, CDRV = 0 nF

VCC = 12 V, CDRV = 1 nF

VCC = 12 V, CDRV = 10 nF

VCC = 35 V, CDRV = 0 nF

VCC = 35 V, CDRV = 1 nF

VCC = 35 V, CDRV = 10 nF

VCC = 12 V, CDRV = 0 nF

VCC = 12 V, CDRV = 1 nF

VCC = 12 V, CDRV = 10 nF

VCC = 35 V, CDRV = 0 nF

VCC = 35 V, CDRV = 1 nF

VCC = 35 V, CDRV = 10 nF

120

TJ = 125°C

TJ = 85°C

TJ = 55°C

TJ = 25°C

TJ = 0°C

TJ = −20°C

TJ = −40°C

120

4.5

4.9

5.2

120

NCP43080

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APPLICATION INFORMATION

General description

The NCP43080 is designed to operate either as a

standalone IC or as a companion IC to a primary side

controller to help achieve efficient synchronous

rectification in switch mode power supplies. This controller

features a high current gate driver along with high−speed

logic circuitry to provide appropriately timed drive signals

to a synchronous rectification MOSFET. With its novel

architecture, the NCP43080 has enough versatility to keep

the synchronous rectification system efficient under any

operating mode.

The NCP43080 works from an available voltage with

range from 4 V (A, D & Q options) or 8 V (B & C options)

to 35 V (typical). The wide VCC range allows direct

connection to the SMPS output voltage of most adapters

such as notebooks, cell phone chargers and LCD TV

adapters.

Precise turn-off threshold of the current sense comparator

together with an accurate offset current source allows the

user to adjust for any required turn-off current threshold of

the SR MOSFET switch using a single resistor. Compared

to other SR controllers that provide turn-off thresholds in t h e

range of − 1 0 m V t o −5 m V , the NCP43080 offers a turn-off

threshold of 0 mV. When using a low RDS(on) SR (1 mW)

MOSFET our competition, with a −10 mV turn of f, will turn

off with 10 A still flowing through the SR FET, while our

0 mV turn off turns off the FET at 0 A; significantly

reducing the turn-off current threshold and improving

efficiency. Many of the competitor parts maintain a drain

source voltage across the MOSFET causing the SR

MOSFET to operate in the linear region to reduce turn−off

time. Thanks to the 8 A sink current of the NCP43080

significantly reduces turn off time allowing for a minimal

drain source voltage to be utilized and efficiency

maximized.

To overcome false triggering issues after turn-on and

turn−off events, the NCP43080 provides adjustable

minimum on-time and off-time blanking periods. Blanking

times can be adjusted independently of IC VCC using

external resistors connected to GND. If needed, blanking

periods can be modulated using additional components.

An extremely fast turn−off comparator, implemented on

the current sense pin, allows for NCP43080 implementation

in CCM applications without any additional components or

external triggering.

An output driver features capability to keep SR transistor

closed even when there is no supply voltage for NCP43080.

SR transistor drain voltage goes up and down during SMPS

operation and this is transferred through drain gate

capacitance to gate and may turn on transistor. NCP43080

uses this pulsing voltage at SR transistor gate (DRV pin) and

uses it internally to provide enough supply to activate

internal driver sink transistor. DRV voltage is pulled low

(not to zero) thanks to this feature and eliminate the risk of

turned on SR transistor before enough VCC is applied to

NCP43080.

Some IC versions include a MAX_TON circuit that helps

a quasi resonant (QR) controller to work in CCM mode

when a heavy load is present like in the example of a

printer’s motor starting up.

Finally, the NCP43080 features a special pin (LLD) that

can be used to reduce gate driver voltage clamp according

to application load conditions. This feature helps to reduce

issues with transition from disabled driver to full driver

output voltage and back. Disable state can be also activated

through this pin to decrease power consumption in no load

conditions. If the LLD feature is not wanted then the LLD

pin can be tied to GND.

Current Sense Input

Figure 37 shows the internal connection of the CS

circuitry on the current sense input. When the voltage on the

secondary winding of the SMPS reverses, the body diode o f

M1 starts to conduct current and the voltage of M1’s drain

drops approximately to −1 V. The CS pin sources current of

100 mA that creates a voltage drop on the RSHIFT_CS resistor

(resistor is optional, we recommend shorting this resistor).

Once the voltage on the CS pin is lower than VTH_CS_ON

threshold, M1 is turned−on. Because of parasitic

impedances, significant ringing can occur in the application.

To overcome false sudden turn−off due to mentioned

ringing, the minimum conduction time of the SR MOSFET

is activated. Minimum conduction time can be adjusted

using the RMIN_TON resistor.

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Figure 37. Current Sensing Circuitry Functionality

The SR MOSFET is turned-off as soon as the voltage on

the CS pin is higher than VTH_CS_OFF (typically −0.5 mV

minus any voltage dropped on the optional RSHIFT_CS). For

the same ringing reason, a minimum off-time timer is

asserted once the VCS goes above VTH_CS_RESET. The

minimum off-time can be externally adjusted using

RMIN_TOFF resistor. The minimum off−time generator can

be re−triggered by MIN_TOFF reset comparator if some

spurious ringing occurs on the CS input after SR MOSFET

turn−off event. This feature significantly simplifies SR

system implementation in flyback converters.

In an LLC converter the SR MOSFET M1 channel

conducts while secondary side current is decreasing (refer t o

Figure 38). Therefore the turn−off current depends on

MOSFET RDSON. The −0.5 mV threshold provides an

optimum switching period usage while keeping enough time

margin for the gate turn-off. The RSHIFT_CS resistor

provides the designer with the possibility to modify

(increase) the actual turn−on and turn−off secondary current

thresholds. To ensure proper switching, the min_tOFF timer

is reset, when the VDS of the MOSFET rings and falls down

past the VTH_CS_RESET. The minimum off−time needs to

expire before another drive pulse can be initiated. Minimum

off−time timer is started again when VDS rises above

VTH_CS_RESET.

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VDS =V

VTH_CS_RESET –(R

SHIFT_CS*ICS)

VTH_CS_OFF–(R

SHIFT_CS*ICS)

VTH_CS_ON–(R

SHIFT_CS*ICS)

VDRV

Min ON−time

Min OFF−time

Min tOFF timer was

stopped here because

of VCS<VTH_CS_RESET

tMIN_TON

tMIN_TOFF

ISEC

The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors

Turn−on delay Turn−off delay

Figure 38. CS Input Comparators Thresholds and Blanking Periods Timing in LLC

VDS =V

VTH_CS_RESET –(R

SHIFT_CS*ICS)

VTH_CS_OFF–(R

SHIFT_CS*ICS)

VTH_CS_ON–(R

SHIFT_CS*ICS)

VDRV

Min ON−time

Min OFF−time

tMIN_TON

tMIN_TOFF

ISEC

The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors

Turn−on delay Turn−off delay

Min tOFF timer was

stopped here because

of VCS<VTH_CS_RESET

Figure 39. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback

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If no RSHIFT_CS resistor is used, the turn-on, turn-off and

VTH_CS_RESET thresholds are fully given by the CS input

specification (please refer to electrical characteristics table).

The CS pin offset current causes a voltage drop that is equal

to:

VRSHIFT_CS +RSHIFT_CS *ICS (eq. 1)

Final turn−on and turn of f thresholds can be then calculated

as:

VCS_TURN_ON +VTH_CS_ON *ǒRSHIFT_CS *ICSǓ(eq. 2)

VCS_TURN_OFF +VTH_CS_OFF *ǒRSHIFT_CS *ICSǓ(eq. 3)

VCS_RESET +VTH_CS_RESET *ǒRSHIFT_CS *ICSǓ(eq. 4)

Note that RSHIFT_CS impact on turn-on and VTH_CS_RESET

thresholds is less critical than its effect on the turn−off

threshold.

It should be noted that when using a SR MOSFET in a

through hole package the parasitic inductance of the

MOSFET package leads (refer to Figure 40) causes a

turn−off current threshold increase. The current that flows

through the SR MOSFET experiences a high Di(t)/Dt that

induces an error voltage on the SR MOSFET leads due to

their parasitic inductance. This error voltage is proportional

to the derivative of the SR MOSFET current; and shifts the

CS input voltage to zero when significant current still flows

through the MOSFET channel. As a result, the SR MOSFET

is turned−off prematurely and the efficiency of the SMPS is

not optimized − refer to Figure 41 for a better understanding.

Figure 40. SR System Connection Including MOSFET and Layout Parasitic Inductances in LLC Application

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Figure 41. Waveforms From SR System Implemented in LLC Application and Using MOSFET in TO220 Package

With Long Leads − SR MOSFET channel Conduction Time is Reduced

Note that the efficiency impact caused by the error voltage

due to the parasitic inductance increases with lower

MOSFETs RDS(on) and/or higher operating frequency.

It is thus beneficial to minimize SR MOSFET package

leads length in order to maximize application efficiency. T h e

optimum solution for applications with high secondary

current Di/Dt and high operating frequency is to use

lead−less SR MOSFET i.e. SR MOSFET in SMT package.

The parasitic inductance of a SMT package is negligible

causing insignificant CS turn−off threshold shift and thus

minimum impact to efficiency (refer to Figure 42).

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Figure 42. Waveforms from SR System Implemented in LLC Application and Using MOSFET in SMT Package with

Minimized Parasitic Inductance − SR MOSFET Channel Conduction Time is Optimized

It can be deduced from the above paragraphs on the

induced error voltage and parameter tables that turn−off

threshold precision is quite critical. If we consider a SR

MOSFET with RDS(on) of 1 mW, the 1 mV error voltage on

the CS pin results in a 1 A turn-off current threshold

difference; thus the PCB layout is very critical when

implementing the SR system. Note that the CS turn-off

comparator is referred to the GND pin. Any parasitic

impedance (resistive or inductive − even on the magnitude

of mW and nH values) can cause a high error voltage that is

then evaluated by the CS comparator. Ideally the CS

turn−off comparator should detect voltage that is caused by

secondary current directly on the SR MOSFET channel

resistance. I n reality there will be small parasitic impedance

on the CS path due to the bonding wires, leads and soldering.

To assure the best efficiency results, a Kelvin connection of

the SR controller to the power circuitry should be

implemented. The GND pin should be connected to the SR

MOSFET source soldering point and current sense pin

should be connected to the SR MOSFET drain soldering

point − refer to Figure 40. Using a Kelvin connection will

avoid any impact of PCB layout parasitic elements on the SR

controller functionality; SR MOSFET parasitic elements

will still play a role in attaining an error voltage. Figure 44

and Figure 43 show examples of SR system layouts using

MOSFETs in TO220 and SMT packages. It is evident that

the MOSFET leads should be as short as possible to

minimize parasitic inductances when using packages with

leads (like TO220). Figure 43 shows how to layout design

with two SR MOSFETs in parallel. It has to be noted that it

is not easy task and designer has to paid lot of attention to do

symmetric Kelvin connection.

Figure 43. Recommended Layout When Using SR

MOSFET in SMT Package (2x SO8 FL)

Figure 44. Recommended Layout When Using SR

MOSFET in TO220 Package

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Figure 45. NCP43080 Operation after Start−Up Event

VDS = VCS

VTH_CS_RESET

VTH_CS_OFF

VTH_CS_ON

VCCON

Min OFF− time

VDRV

VCC

Min ON−time

tMIN_TOFF tMIN_TOFF

tMIN_TON

Not complete

tMIN_TOFF −

>IC

is not activated Complete

tMIN_TOFF

activates IC tMIN_TOFF is stopped

due to VDS drops

below VTH_CS_RESET

t1t2t3t4 t5t6t7 t8 t9 t10 t11t12

t13

t14

t15

Self Synchronization

Self synchronization feature during start−up can be seen

at Figure 45. Figure 45 shows how the minimum off−time

timer is reset when CS voltage is oscillating through

VTH_CS_RESET level. The NCP43080 starts operation at

time t1 (time t1 can be seen as a wake−up event from the

disable mode through LLD pin). Internal logic waits for one

complete minimum off−time period to expire before the

NCP43080 can activate the driver after a start−up or

wake−up event. The minimum off−time timer starts to run

at time t1, because VCS is higher than VTH_CS_RESET. The

timer is then reset, before its set minimum off−time period

expires, at time t2 thanks to CS voltage lower than

VTH_CS_RESET threshold. The aforementioned reset

situation can be seen again at time t3, t4, t5 and t6. A

complete minimum off−time period elapses between times

t7 and t8 allowing the IC to activate a driver output after time

t8.

Minimum tON and tOFF Adjustment

The NCP43080 offers an adjustable minimum on−time

and off−time blanking periods that ease the implementation

of a synchronous rectification system in any SMPS

topology. These timers avoid false triggering on the CS input

after the MOSFET is turned on or off.

The adjustment of minimum tON and tOFF periods are

done based on an internal timing capacitance and external

resistors connected to the GND pin − refer to Figure 46 for

a better understanding.

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Figure 46. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way)

Current through the MIN_TON adjust resistor can be

calculated as:

IR_MIN_TON +Vref

RTon_min (eq. 5)

If the internal current mirror creates the same current

through R MIN_TON as used the internal timing capacitor (Ct)

charging, then the minimum on−time duration can be

calculated using this equation.

MIN_TON +CtVref

IR_MIN_TON +CtVref

Vref

MIN_TON

+Ct@RMIN_TO

(eq. 6)

The internal capacitor size would be too large if

IR_MIN_TON was used. The internal current mirror uses a

proportional current, given by the internal current mirror

ratio. One can then calculate the MIN_TON and

MIN_TOFF blanking periods using below equations:

tMIN_TON +1.00 * 10−4 *RMIN_TON [ms] (eq. 7)

tMIN_TOFF +1.00 * 10−4 *RMIN_TOFF [ms] (eq. 8)

Note that the internal timing comparator delay affects the

accuracy of Equations 7 and 8 when MIN_TON/

MIN_TOFF times are selected near to their minimum

possible values. Please refer to Figures 47 and 48 for

measured minimum on and off time charts.

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Figure 47. MIN_TON Adjust Characteristics

Figure 48. MIN_TOFF Adjust Characteristics

RMIN_TON (kW)

906050403020100

tMIN_TON (ms)

100

8070

RMIN_TOFF (kW)

906050403020100

tMIN_TOFF (ms)

100

8070

The absolute minimum tON duration is internally clamped

to 55 ns and minimum tOFF duration to 245 ns in order to

prevent any potential issues with the MIN_TON and/or

MIN_TOFF pins being shorted to GND.

The NCP43080 features dedicated anti−ringing

protection system that is implemented with a MIN_TOFF

blank generator. The minimum off−time one−shot generator

is restarted in the case when the CS pin voltage crosses

VTH_CS_RESET threshold and MIN_TOFF period is active.

The total off-time blanking period is prolonged due to the

ringing in the application (refer to Figure 38).

Some applications may require adaptive minimum on and

off time blanking periods. With NCP43080 it is possible to

modulate blanking periods by using an external NPN

transistor − refer to Figure 49. The modulation signal can be

derived based on the load current, feedback regulator

voltage or other application parameter.

Figure 49. Possible Connection for MIN_TON and MIN_TOFF Modulation

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Maximum tON adjustment

The NCP43080Q offers an adjustable maximum on−time

(like the min_tON and min_tOFF settings shown above) that

can be very useful for QR controllers at high loads. Under

high load conditions the QR controller can operate in CCM

thanks to this feature. The NCP43080Q version has the

ability to turn−of f the D RV signal to the SR MOSFET before

the secondary side current reaches zero. The DRV signal

from the NCP43080Q can be fed to the primary side through

a pulse transformer (see Figure 4 for detail) to a transistor on

the primary side to emulate a ZCD event before an actual

ZCD event occurs. This feature helps to keep the minimum

switching frequency up so that there is better energy transfer

through the transformer (a smaller transformer core can be

used). Also another advantage is that the IC controls the SR

MOSFET and turns off from secondary side before the

primary side is turned on in CCM to ensure no cross

conduction. By controlling the SR MOSFET’s turn off

before the primary side turn off, producing a zero cross

conduction operation, this will improve efficiency.

The Internal connection of the MAX_TON feature is

shown in Figure 50. Figure 50 shows a method that allows

for a modification of the maximum on−time according to

output voltage. At a lower VOUT, caused by hard overload

or at startup, the maximum on−time should be longer than at

nominal voltage. Resistor RA can be used to modulate

maximum on−time according to VOUT or any other

parameter.

The operational waveforms at heavy load in QR type

SMPS are shown in Figure 51. After tMAX_TON time is

exceeded, the synchronous switch is turned off and the

secondary current is conducted by the diode. Information

about turned of f SR MOSFET is transferred by the DRV pin

through a sm a l l p u l s e t r a n s f o r m e r t o t h e p r im a r y s i d e w h e r e

it acts on the ZCD detection circuit to allow the primary

switch to be turned on. Secondary side current disappears

before the primary switch is turned on without a possibility

of cross current condition.

Figure 50. Internal Connection of the MAX_TON Generator, NCP43080Q

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VDS =V

VTH_CS_RESET –(R

SHIFT_CS*ICS)

VTH_CS_OFF–(R

SHIFT_CS*ICS)

VTH_CS_ON–(R

SHIFT_CS*ICS)

VDRV

Min ON−time

Min OFF−time

tMIN_TON

tMIN_TOFF

ISEC

The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors, tMAX_TON is adjustable by RMAX_TON

Turn−on delay Turn−off delay

Primary virtual ZCD

detection delay

Max ON−time tMAX_TON

Figure 51. Function of MAX_TON Generator in Heavy Load Condition

Adaptive Gate Driver Clamp and automatic Light Load

Turn−off

As synchronous rectification system significantly

improves efficiency in most of SMPS applications during

medium or full load conditions. However, as the load

reduces into light or no−load conditions the SR MOSFET

driving losses and SR controller consumption become more

critical. The NCP43080 offers two key features that help to

optimize application efficiency under light load and no load

conditions:

1st − The driver clamp voltage is modulated and follows

the output load condition. When the output load decreases

the driver clamp voltage decreases as well. Under heavy

load conditions the SR MOSFET’s gate needs to be driven

very hard to optimize the performance and reduce

conduction losses. During light load conditions it is not as

critical to drive the SR MOSFET’s channel into such a low

RDSON state. This adaptive gate clamp technique helps to

optimize efficiency during light load conditions especially

in LLC applications where the SR MOSFETs with high

input capacitance are used.

Driver voltage modulation improves the system behavior

when SR controller state is changed in and out of normal or

disable modes. Soft transient between drop at body diode

and drop at MOSFET’s RDS(on) only improves stability

during load transients.

2nd − In extremely low load conditions or no load

conditions the NCP43080 fully disables driver output and

reduces the internal power consumption when output load

drops below the level where skip−mode takes place.

Both features are controlled by voltage at LLD pin. The

LLD pin voltage characteristic is shown in Figure 52. Driver

voltage clamp is a linear function of the voltage difference

between the VCC and LLD pins from VLLD_REC point up to

VLLD_MAX. A disable mode is available, where the IC

current consumption is dramatically reduced, when the

difference of VCC − VLLD voltage drops below VLLD_DIS.

When the voltage difference between the VCC − VLLD pins

increase above VLLC_REC the disable mode ends and the IC

regains normal operation. It should be noted that there are

also some time delays to enter and exit from the disable

mode. Time waveforms are shown at Figure 53. There is a

time, t LLD_DISH, that the logic ignores changes from disable

mode to normal or reversely. There is also some time

tLLD_DIS_R that is needed after an exit from the disable mode

to assure proper internal block biasing before SR controller

starts work normally.

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VDRVCLAMP

VCC −VLLD

ICC

VDRVMAX

VLLD_MAX

VLLD_DIS VLLD_REC

Figure 52. LLD Voltage to Driver Clamp and Current Consumption Characteristic (DRV Unloaded)

Figure 53. LLD Pin Disable Behavior in Time Domain

ICC

VCC−VLLD

DISABLE MODE NORMAL

NORMAL

DISABLE MODE

tLLD_DISH tLLD_DISH tLLD_DISH tLLD_DISH

VLLD_DIS

VLLD_REC

tLLD_DIS_R tLLD_DIS_R

The two main SMPS applications that are using

synchronous rectification systems today are flyback and

LLC topologies. Different light load detection techniques

are used in NCP43080 controller to reflect differences in

operation of both mentioned applications.

Detail of the light load detection implementation

technique used in NCP43080 in flyback topologies is

displayed at Figure 54. Using a simple and cost effective

peak detector implemented with a diode D1, resistors R1

through R3 and capacitors C2 and C3, the load level can be

sensed. Output voltage of this detector on the LLD pin is

referenced to controller VCC with an internal differential

amplifier in NCP43080. The output of the differential

amplifier is then used in two places. First the output is used

in the driver block for gate drive clamp voltage adjustment.

Next, the output signal is evaluated by a no−load detection

comparator that activates IC disable mode in case the load

is disconnected from the application output.

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Figure 54. NCP43080 Light Load and No Load Detection Principle in Flyback Topologies

RTN

Vmodul

To DRV clamp

To disable

logic

VCC

LLD

GND

NCP43080

Operational waveforms related to the flyback LLD

circuitry are provided in Figure 55. The SR MOSFET drain

voltage drops to ~ 0 V when ISEC current is flowing. When

the SR MOSFET is conducting the capacitor C2 charges−up,

causing the difference between the LLD pin and VCC pin to

increase, and drop the LLD pin voltage. As the load

decreases the secondary side currents flows for a shorter a

shorter time. C2 has less time to accumulate charge and the

voltage on the C2 decreases, because it is discharged by R2

and R3. This smaller voltage on C2 will cause the LLD pin

voltage to increase towards VCC and the dif ference between

LLD and VCC will go to zero. The output voltage then

directly reduces DRV clamp voltage down from its

maximum level. The DRV is then fully disabled when IC

enters disable mode. The IC exits from disable mode when

difference between LLD voltage and VCC increases over

VLLD_REC. Resistors R2 and R3 are also used for voltage

level adjustment and with capacitor C3 form low pass filter

that filters relatively high speed ripple at C2. This low pass

filter also reduces speed of state change of the SR controller

from normal to disable mode or reversely. Time constant

should be higher than feedback loop time constant to keep

whole system stable.

Figure 55. NCP43080 Driver Clamp Modulation Waveforms in Flyback Application Entering into Light/No Load

Condition

ISEC

VC2

VDRV

VC3 VLLDMAX

VLLD_REC

VLLD_DIS VDRVMAX

IC enters

disable mode

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Figure 56. NCP43080 Driver Clamp Modulation Circuitry Transfer Characteristic in Flyback Application

IOUT

VCC−VLLD

VDRV IC enters

disable mode

VLLDMAX

VLLD_REC VLLD_DIS

VDRVMAX

The technique used for LLD detection in LLC is similar

to the LLD detection method used in a flyback with the exception the D1 and D2 OR−ing diodes are used to measure

the total duty cycle to see if it is operating in skip mode.

Figure 57. NCP43080 Light Load Detection in LLC Topology

RTN

Vmodul

To DRV clamp

To disable

logic

VCC

LLD

GND

Vmodul

To DRV clamp

To disable

logic

VCC

LLD

GND

NCP43080

The driver clamp modulation waveforms of NCP43080 in

LLC are provided in Figure 58. The driver clamp voltage

clips to its maximum level when LLC operates in normal

mode. When the LLC starts to operate in skip mode the

driver clamp voltage begins to decrease. The specific output

current level is determined by skip duty cycle and detection

circuit consists of R1, R2, R3, C2, C3 and diodes D1, D2.

The NCP43080 enters disable mode in low load condition,

when VCC−VLLD drops below VLLD_DIS (0.9 V). Disable

mode ends when this voltage increase above VLLD_REC

(1.0 V) Figure 59 shows how LLD voltage modulates the

driver output voltage clamp.

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VCS1

VCS2

VC2

VCC−VLLD

DRV clamp

Skip operationNormal operation

(VC3)

IC enters

disable mode

VDRVMAX

VLLDMAX

VLLD_REC VLLD_DIS

Figure 58. NCP43080 Driver Clamp Modulation Waveforms in LLC Application

VCC−VLLD

IOUT

DRV clamp

IC enters

disable mode

VLLDMAX

VLLD_REC VLLD_DIS

VDRVMAX

Figure 59. NCP43080 Driver Clamp Modulation Circuitry Characteristic in LLC Application

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There exist some LLC applications where behavior

described above is not the best choice. These applications

transfer significant portion of energy in a few first pulses in

skip burst. It is good to keep SR fully working during skip

mode to improve efficiency. There can be still saved some

energy using LLD function by activation disable mode

between skip bursts. Simplified schematic for this LLD

behavior is shown in Figure 60. Operation waveforms for

this option are provided in Figure 61. Capacitor C2 is

charged t o maximum voltage when LLC is switching. When

there is no switching in skip, capacitor C2 is discharged by

R2 and when LLD voltage referenced to VCC falls below

VLLD_DIS IC enters disable mode. Disable mode is ended

when LLC starts switching.

Figure 60. NCP43080 Light Load Detection in LLC Application − Other Option

RTN

Vmodul

To DRV clamp

To disable

logic

VCC

LLD

GND

Vmodul

To DRV clamp

To disable

logic

VCC

LLD

GND

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VCS1

VCS2

VC2

VCC−VLLD

DRV clamp

Skip operation

Normal operation

IC enters

disable mode

VDRVMAX

VLLDMAX

VLLD_REC

VLLD_DIS

Figure 61. NCP43080 Light Load Detection Behavior in LLC Application – Other Option

Power Dissipation Calculation

It is important to consider the power dissipation in the

MOSFET driver of a SR system. If no external gate resistor

is used and the internal gate resistance of the MOSFET is

very low, nearly all energy losses related to gate charge are

dissipated in the driver. Thus it is necessary to check the SR

driver power losses in the target application to avoid over

temperature and to optimize ef ficiency.

In SR systems the body diode of the SR MOSFET starts

conducting before SR MOSFET is turned−on, because there

is some delay from VTH_CS_ON detect to turn−on the driver .

On the other hand, the SR MOSFET turn off process always

starts before the drain to source voltage rises up

significantly. Therefore, the MOSFET switch always

operates under Zero Voltage Switching (ZVS) conditions

when in a synchronous rectification system.

The following steps show how to approximately calculate

the power dissipation and DIE temperature of the

NCP43080 controller. Note that real results can vary due to

the effects of the PCB layout on the thermal resistance.

Step 1 − MOSFET Gate−to Source Capacitance:

During ZVS operation the gate to drain capacitance does

not have a Miller effect like in hard switching systems

because the drain to source voltage does not change (or its

change is negligible).

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Figure 62. Typical MOSFET Capacitances

Dependency on VDS and VGS Voltages

Ciss +Cgs )Cgd

Crss +Cgd

Coss +Cds )Cgd

Therefore, the input capacitance of a MOSFET operating

in ZVS mode is given by the parallel combination of the gate

to source and gate to drain capacitances (i.e. Ciss capacitance

for given gate to source voltage). The total gate charge,

Qg_total, of most MOSFETs on the market is defined for hard

switching conditions. In order to accurately calculate the

driving losses in a SR system, it is necessary to determine the

gate charge of the MOSFET for operation specifically in a

ZVS system. Some manufacturers define this parameter as

Qg_ZVS. Unfortunately, most datasheets do not provide this

data. If the Ciss (or Qg_ZVS) parameter is not available then

it will need to be measured. Please note that the input

capacitance is not linear (as shown Figure 62) and it needs

to be characterized for a given gate voltage clamp level.

Step 2 − Gate Drive Losses Calculation:

Gate drive losses are affected by the gate driver clamp

voltage. Gate driver clamp voltage selection depends on the

type of MOSFET used (threshold voltage versus channel

resistance). The total power losses (driving loses and

conduction losses) should be considered when selecting the

gate driver clamp voltage. Most of today’s MOSFETs for SR

systems feature low RDS(on) for 5 V VGS voltage. The

NCP43080 offers both a 5 V gate clamp and a 10 V gate

clamp for those MOSFET that require higher gate to source

voltage.

The total driving loss can be calculated using the selected

gate driver clamp voltage and the input capacitance of the

MOSFET:

PDRV_total +VCC @VCLAMP @Cg_ZVS @fSW (eq. 9)

Where:

VCC is the NCP43080 supply voltage

VCLAMP is the driver clamp voltage

Cg_ZVS is the gate to source capacitance of the

MOSFET in ZVS mode

fsw is the switching frequency of the target

application

The total driving power loss won’t only be dissipated in

the IC, but also in external resistances like the external gate

resistor (if used) and the MOSFET internal gate resistance

(Figure 44). Because NCP43080 features a clamped driver,

it’s high side portion can be modeled as a regular driver

switch with equivalent resistance and a series voltage

source. The low side driver switch resistance does not drop

immediately at turn−off, thus it is necessary to use an

equivalent value (RDRV_SIN_EQ) for calculations. This

method simplifies power losses calculations and still

provides acceptable accuracy. Internal driver power

dissipation can then be calculated using Equation 10:

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Figure 63. Equivalent Schematic of Gate Drive Circuitry

PDRV_IC +1

2@Cg_ZVS @VCLAMP 2@fSW @ǒRDRV_SINK_EQ

RDRV_SINK_EQ )RG_EXT )Rg_intǓ)Cg_ZVS @VCLAMP @fSW @ǒVCC *VCLAMPǓ

2@Cg_ZVS @VCLAMP 2@fSW @ǒRDRV_SOURCE_EQ

RDRV_SOURCE_EQ )RG_EXT )Rg_intǓ

(eq. 10)

Where:

RDRV_SINK_EQ is the NCP43080x driver low side switch

equivalent resistance (0.5 W)

RDRV_SOURCE_EQ is the NCP43080x driver high side switch

equivalent resistance (1.2 W)

RG_EXT is the external gate resistor (if used)

Rg_int is the internal gate resistance of the

MOSFET

Step 3 − IC Consumption Calculation:

In this step, power dissipation related to the internal IC

consumption is calculated. This power loss is given by the

ICC current and the IC supply voltage. The ICC current

depends o n switching frequency and also on the selected m in

tON and tOFF periods because there is current flowing out

from the min tON and tOFF pins. The most accurate method

for calculating these losses is to measure the ICC current

when CDRV = 0 nF and the IC is switching at the target

frequency with given MIN_TON and MIN_TOFF adjust

resistors. IC consumption losses can be calculated as:

PCC +VCC @ICC (eq. 11)

Step 4 − IC Die Temperature Arise Calculation:

The die temperature can be calculated now that the total

internal power losses have been determined (driver losses

plus internal IC consumption losses). The package thermal

resistance is specified in the maximum ratings table for a

35 mm thin copper layer with no extra copper plates on any

pin (i.e. just 0.5 mm trace to each pin with standard soldering

points are used).

The DIE temperature is calculated as:

TDIE +ǒPDRV_IC )PCCǓ@RqJ−A )TA(eq. 12)

Where:

PDRV_IC is the IC driver internal power dissipation

PCC is the IC control internal power

dissipation

RqJA is the thermal resistance from junction to

ambient

TAis the ambient temperature

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PRODUCT OPTIONS

OPN Package UVLO [V] DRV clamp [V] Pin 5 function Usage

NCP43080ADR2G SOIC8 4.5 4.7 NC

LLC, CCM flyback, DCM flyback, forward,

QR, QR with primary side CCM control

NCP43080AMTTWG WDFN8 4.5 4.7 NC

NCP43080DDR2G SOIC8 4.5 9.5 NC

NCP43080DMNTWG DFN8 4.5 9.5 NC

NCP43080DMTTWG WDFN8 4.5 9.5 NC

NCP43080QDR2G SOIC8 4.5 9.5 MAX_TON QR with forced CCM from secondary side

ORDERING INFORMATION

Device Package Package marking Packing Shipping†

NCP43080ADR2G SOIC8 43080A SOIC−8

(Pb−Free) 2500 /Tape & Reel

NCP43080DDR2G 43080D

NCP43080QDR2G 43080Q

NCP43080AMTTWG WDFN8 FA WDFN−8

(Pb−Free) 3000 /Tape & Reel

NCP43080DMTTWG FD

NCP43080DMNTWG DFN8 43080D DFN−8

(Pb−Free) 4000 /Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCP43080

www.onsemi.com

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

SEATING

PLANE

X 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

AMIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024 1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NCP43080

www.onsemi.com

PACKAGE DIMENSIONS

DFN8 4x4

CASE 488AF

ISSUE C

ÉÉ

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. DETAILS A AND B SHOW OPTIONAL

CONSTRUCTIONS FOR TERMINALS.

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.25 0.35

D4.00 BSC

D2 1.91 2.21

E4.00 BSC

E2 2.09 2.39

e0.80 BSC

K0.20 −−−

L0.30 0.50

C0.15

2X TOP VIEW

SIDE VIEW

BOTTOM VIEW

ÇÇ

(A3) A1

SEATING

PLANE

C0.08

C0.10

8X L

NOTE 3

58 8X

0.10 C

0.05 C

PIN ONE

REFERENCE

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.63

2.21

2.39

0.80

PITCH

4.30

0.35

DETAIL A

OPTIONAL

CONSTRUCTIONS

ÉÉÉ

ÇÇÇ

ÇÇ

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTIONS

L1 −−− 0.15

DETAIL B

NOTE 4

DET AIL A

DIMENSIONS: MILLIMETERS

PACKAGE

OUTLINE

NCP43080

www.onsemi.com

PACKAGE DIMENSIONS

ÍÍÍ

SEATING

PLANE

0.10 C

WDFN8 2x2, 0.5P

CASE 511AT

ISSUE O

DIM

MIN MAX

MILLIMETERS

0.70 0.80

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

PIN ONE

REFERENCE

0.05 C

A0.10 C

NOTE 3

88X

0.05 C

2.00 BSC

0.50 BSC

0.40 0.60

--- 0.15

BOTTOM VIEW

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTIONS

DETAIL B

DET AIL A

L2 0.50 0.70

TOP VIEW

SIDE VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

2.30

0.50

0.78

DIMENSIONS: MILLIMETERS

0.30 PITCH

PACKAGE

OUTLINE

RECOMMENDED

0.88

e/2

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UBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

NCP43080/D

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