1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage: 4.5 V to 13.2 V
• 12Vpp analog signal capability
•R
ON 65 max. @ VDD=12 V, 25C
•RON 10 @ VDD=12 V, 25C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumptio n ISO-CMOS technology
Applications
• Key systems
• PBX systems
• Mobile radio
• Test equipment/instrumentation
• Analog/digital multiplexers
• Audio/Video switching
Description
The Zarlink MT8806 is fabricated in Zarlink’s ISO-
CMOS technology providing low power dissipation and
high reliability. The device contains a 8 x 4 array of
crosspoint switches along with a 5 to 32 line decoder
and latch circuits. Any one of the 32 switches can be
addressed by selecting the appropriate five address
bits. The selected switch can be turned on or off by
applying a logical one or zero to the DATA input. VSS is
the ground reference of the digital inputs. The range of
the analog signal is from VDD to VEE. Chip Select (CS)
allows the crosspoint array to be cascaded for matrix
expansion.
September 2011
Ordering Information
MT8806APR1 28 Pin PLCC* Tape & Reel
MT8 806 A P 1 28 Pin PLCC* Tubes
MT8806AE1 24 Pin PDIP* Tubes
* Pb free Matte Tin
-40C to +85C
MT8806
ISO-CMOS
8x4AnalogSwitchArray
Data Sheet
Figure 1 - Functional Block Diagram
5 to 32
Decoder Latches
8 x 4
Switch
Array
AX0
AX1
AY0
AY1
AY2
CS STROBE DATA RESET VDD VEE VSS
Xi I/O
(i=0-3)
Yi I/O (i=0-7)
11
3232
• • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • •
MT8806 Data Sheet
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Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Change Summary
Changes from the May 2005 issue to the September 2011 issue.
Page Item Change
1 Ordering Information Removed leaded packag es as per PCN notice.
Pin Description
Pin # Name Description
PDIP PLCC
1-3 1-3 Y2-Y0 Y2-Y0 Analog (Inputs/Outputs): these are connected to the Y2-Y0 columns of
the switch array.
46DATADATA (Input): a logic high input will turn on the selected switch and a logic low
will turn off the selected switch. Active High.
57 X0X0 Analog (Input/Output): this is connected to the X0 row of the switch array.
6 8 AX0 X0 Address Line (Input)
79 X1X1 Analog (Input/Output): this is connected to the X1 row of the switch array.
8 10 AX1 X1 Address Line (Input)
911 X2X2 Analog (Input/Output): this is connected to the X2 row of the switch array.
10 12 CS Chip Select (Input): this is used to select the device. Active High.
11 13 X3 X3 Analog (Input/Output): this is connected to the X3 row of the switch array.
12 14 VSS Digital Ground Reference
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
24
23
22
21
20
19
18
17
Y2
Y1
Y0
DATA
X0
AX0
X1
AX1
X2
CS
X3
VSS
VDD
Y3
Y4
Y5
Y6
Y7
RESET
STROBE
AY2
AY1
AY0
VEE
28 PIN PLCC
24 PIN PLASTIC DIP
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
Y5
Y6
Y7
RESET
STROBE
AY2
NC
NC
DATA
X0
AX0
X1
AX1
X2
AY1
3
2
1
28
27
26
12
13
14
15
16
17
18
Y0
Y1
Y2
VDD
Y3
Y4
CS
X3
VSS
VEE
AY0
NC
MT8806 Data Sheet
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Zarlink Semiconductor Inc.
Functional Description
The MT8806 is an analog switch matrix with an array size of 8 x 4. The switch array is arranged su ch that there are
8 columns by 4 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs.
The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high
degree of isolation when turned off. The control memory consists of a 32 bit write only RAM in which the bits are
selected by the address input s (AY0-AY2, AX0 & AX1). Data is presented to the memory o n the DATA input. Data is
asynchronously written into memory whenever both the CS (Chip Select) and the STROBE inputs are high and is
latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint
switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed
memory location are altered when data is written into memory. The remaining switches retain their previous states.
Any combination of X and Y inputs/output s can be interco nnected by est ablishing appropriate p atterns in the control
memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off
all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (VSS and VEE) are
provided for the MT8806 to enab le switching of nega tive ana lo g sign als. The ra nge for digital signals is from VDD to
VSS while the range for analog sig nals is from V DD to VEE. VSS and VEE pins can be tied together if a single voltage
reference is needed.
Address Decode
The five address input s alo ng with the STROBE and CS (Chip Select) input s are logically ANDe d to form an enable
signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To
write to a location, RESET must be low and CS must go high while the address and data are set up. Then the
STROBE input is set high and then low causing the data to be latc hed. The data can be changed while STROBE is
high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for correct data to be written to the latch.
13 15 VEE Negative Power Supply
14-16 16,17, 20 AY0-AY2 Y0 -Y2 Address Lines (Inputs)
17 21 STROBE STROBE (Input): enables fu nction selecte d by address and dat a. Ad dress must
be stable before STROBE goes hig h and DATA must be stable on the falling
edge of the STROBE. Active High.
18 22 RESET Master RESET (Input): this is used to turn off all switches regardless of the
condition of CS. Active High.
19-23 23-27 Y7-Y3 Y7-Y3 Analog (Inputs/Outputs): these are connected to the Y7-Y3 columns of
the switch array.
24 28 VDD Positive Power Supply
4, 5,
18, 19 NC No Connect
Pin Description
Pin # Name Description
PDIP PLCC
MT8806 Data Sheet
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Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
† DC Electrical Charac teristics are over recommended temperature range.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.
Parameter Symbol Min. Max. Units
1 Supply Voltage VDD
VSS -0.3
-0.3 15.0
VDD+0.3 V
V
2 Analog Input Voltage VINA -0.3 VDD+0.3 V
3 Digital Input Voltage VIN VSS-0.3 VDD+0.3 V
4 Current on any I/O Pin I 15 mA
5 Storage Temperature TS-65 +150 C
6 Package Power Dissipation PLASTIC DIP PD0.6 W
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1 Operating Temperature TO-40 25 85 C
2 Supply Voltage VDD
VSS 4.5
VEE 13.2
VDD-4.5 V
V
3 Analog Input Voltage VINA VEE VDD V
4 Digital Input Voltage VIN VSS VDD V
DC Electrical Characteristics†- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Quiescent Supply Current IDD 1 100 A All digital in puts at VIN=VSS or
VDD
0.4 1.5 mA All digital inputs at VIN=2.4 +
VSS; VSS =7.0V
5 15 mA All digital inputs at VIN=3.4V
2 Off-state Leakage Current
(See G.9 in Appendix) IOFF 1500 nA IVXi - VYjI = VDD - VEE
See Appendix, Fig. A.1
3 Input Logic “0” level VIL 0.8+VS
SVV
SS =7.5V; VEE=0V
4 Input Logic “1” level VIH 2.0+VSS VV
SS =6.5V; VEE=0V
5 Input Logic “1” level VIH 3.3 V
6 Input Leakage (digital pins) ILEAK 0.1 10 A All digital inputs at VIN = VSS
or VDD
MT8806 Data Sheet
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Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measureme nts are for Plastic D IPS only, cr osstalk values for PLCC packages are a pproximately 5 dB better.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offse t applied at the analog I/O pins.
Characteristics Sym. 25C70C85C Units Test Conditions
Typ. Max. Typ. Max. Typ. Max.
1 On-state VDD=12V
Resistance VDD=10V
VDD= 5V
(See G.1, G.2, G.3 in
Appendix)
RON 45
55
120
65
75
185
75
85
215
80
90
225
VSS=VEE=0V,VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
2 Difference in on-state
resistance between two
switches
(See G.4 in Appendix)
RON 510 10 10 VDD=12V, VSS=VEE=0,
VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
AC Electrical Characteristics† - Crosspoint Performance - Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Switch I/O Capacitance CS20 pF f=1 MHz
2 Feedthrough Capacitance CF0.2 pF f=1 MHz
3 Frequenc y Response
Channel “ON”
20LOG(VOUT/VXi)=-3dB
F3dB 45 MHz Switch is “ON”; VINA = 2Vpp
sinewave; RL = 1k
See Appendix, Fig. A.3
4 Total Harmonic Distortion
(See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; VINA = 2Vpp
sinewave f= 1kHz; RL=1k
5 Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
FDT -95 dB All Switches “OFF”; VINA=
2Vpp sinewave; f= 1kHz;
RL= 1k
See Appendix, Fig. A.4
6 Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
Xtalk -45 dB VINA=2Vpp sinewave
f= 10MHz; RL = 75
-90 dB VINA=2Vpp sinewave
f= 10kHz; RL = 600
-85 dB VINA=2Vpp sinewave
f= 10kHz; RL = 1k
-80 dB VINA=2Vpp sinewave
f= 1kHz; RL = 10k
Refer to Appendix , Fig. A .5
for test circuit.
7 Propagation delay through
switch tPS 30 ns RL=1k; CL=50pF
MT8806 Data Sheet
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Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5 ns.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Å Refer to Append ix, Fig. A.7 for test circuit.
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless
otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Control Input crosstalk to switch
(for CS, DATA, STROBE, Address) CXtalk 30 mVpp VIN=3V squarewave;
RIN=1k, RL=10k
See Appendix, Fig. A.6
2 Digital Input Capacitance CDI 10 pF f=1MHz
3 Switching Frequency FO20 MHz
4 Setup Time D ATA to STROBE tDS 10 ns RL= 1k, CL=50pF Å
5 Hold Time DATA to STRO BE tDH 10 ns RL= 1k, CL=50pF Å
6 Setup Time Address to STROBE tAS 10 ns RL= 1k, CL=50pF Å
7 Hold Time Add ress to STR O BE tAH 10 ns RL= 1k, CL=50pF Å
8 Setup Time CS to ST R O B E tCSS 10 ns RL= 1k, CL=50pF Å
9 Hold Time CS to ST R O B E tCSH 10 ns RL= 1k, CL=50pF Å
10 STROBE Pulse Width tSPW 20 ns RL= 1k, CL=50pF Å
11 RESET Pulse Width tRPW 40 ns RL= 1k, CL=50pF Å
12 STROBE to Switch Status Delay tS40 100 ns RL= 1k, CL=50pF Å
13 DATA to Switch Status Delay tD50 100 ns RL= 1k, CL=50pF Å
14 RESET to Switch Status Delay tR35 100 ns RL= 1k, CL=50pF Å
tCSS tCSH
tRPW
tSPW
tAS
tAH
tDH
tDtStRtR
tDS
50% 50%
50% 50%
50%50%50%
50% 50%
50% 50%
CS
RESET
STROBE
ADDRESS
DATA
SWITCH* ON
OFF
MT8806 Data Sheet
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Zarlink Semiconductor Inc.
Table 1 - Address Decode Truth Table
AX0 AX1 AY0 AY1 AY2 Connection
00000 X0-Y0
00100 X0-Y1
00010 X0-Y2
00110 X0-Y3
00001 X0-Y4
00101 X0-Y5
00011 X0-Y6
00111 X0-Y7
1
1
0
0
0
1
0
1
0
1
X1-Y0
X1-Y7
0
0
1
1
0
1
0
1
0
1
X2-Y0
X2-Y7
1
1
1
1
0
1
0
1
0
1
X3-Y0
X3-Y7
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certain ways or in combination with Zarlink, or non-Za rlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
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information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performan ce or su itability of any produ ct or servi ce. Inf ormatio n concerni ng po ssible meth ods of u se is p rovided a s a guide only and doe s not co nstitut e
any guarantee th at such methods of use will be satisfactory in a sp ecific piece of equip ment. It is the user ’s responsibili ty to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up t o date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or paramete rs. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user . All products and materials are sold and services provided subject to Zarlink’s conditions of sa le w hich are avai la ble on req ues t.
Purchase of Zarlink’s I2C components conveys a license un der the Philips I2C Patent rights to use thes e components in an I2C System, provided that the syste m
conforms to the I2C Standard Specification as defined by Philips.
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