1
Features
•Serial Peripheral Interface (SPI) Compatible
•Supports SPI Modes 0 (0,0) and 3 (1,1)
•2.1 MH z Clock Rate
•128-Byte Page Mode Only for Write Operations
•Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
•Block Write Protection
– Protect 1/4, 1/2, or Entire Array
•Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
•Self-Timed Write Cycle (5 ms Typical)
•High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >40 Years
– ESD Protection: >3000V
•20-Pin JEDEC SOIC and 8-Pin Leadless Array Packag e
Description
The AT25 P1024 prov ides 1,048 ,576 bits of serial electrical ly erasa ble progr ammabl e
read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device
is op timi zed fo r u se in m any indus trial and co mmer cial app lic ations whe re low power
and low vol tage ope ratio n are essenti al. The A T25P102 4 is av ailab le in space s avin g
20-pin JEDEC SOIC and 8-pin leadless array (LAP) packages.
Rev. 1082C–08/98
SPI Serial
EEPROMs
1M (131,072 x 8)
AT25P1024
Preliminary
Pin Configurations
Pin Name Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
NC No Connect
(continued)
20-Lead SOIC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CS
SO
NC
NC
NC
NC
NC
NC
WP
GND
VCC
HOLD
NC
NC
NC
NC
NC
NC
SCK
SI
8-Pin LAP
Bottom View
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
AT25P1024
2
The AT25P1024 is enabled through the Chip Select pin
(CS) and accessed via a 3-wire interface consisting of
Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (S CK). All pr ogramming cy cles are co mpletely s elf-
timed, and no separate ERASE cycle is required before
WRITE.
BLOCK WRITE protection is enabled by programming the
status register with top ¼, top ½ or entire array of write pro-
tection. Separate program enable and program disable
instructions are provided for additional data protection.
Hard w are d at a protect i on is pr ov id ed vi a th e W P pin to pro-
tect against inadv ertent write attempts to the s tatus regis-
ter. The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” ma y cause permanent d amage to th e
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of th is specification is not implie d. Ex pos ure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Bloc k Diagram
Absolute Maximum Ratings*
Operating Temperature..................................-55°C to +125°C
Storage Temperature .....................................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... -1.0V to +7.0V
Maximu m Op er at ing Voltage....... ...... ...... ..... ...... ..... ........6.25V
DC Output Current........................................................5.0 mA
131,072 x 8
AT25P1024
3
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. VIL and VIH max are reference only and are not tested.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacit anc e (CS , SCK, SI, WP, H OLD)6pFV
IN = 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,
TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 3.6 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open Read 2.0 5.0 mA
ICC2 Supply Current VCC = 5.0V at 2 MHz, SO = Open Write 4.0 7.0 mA
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 3.0 µA
ISB2 Standby Current VCC = 2.7V, CS = VCC 0.2 3.0 µA
ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 7.0 µA
IIL Input Leakage VIN = 0V to VCC -3.0 3.0 µA
IOL Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C-3.0 3.0
µ
A
V
IL(1) Input Low Voltage -0.6 VCC x 0.3 V
VIH(1) Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Volt age 4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V
VOH1 Output High Voltage IOH = -1.6 mA VCC - 0.8 V
VOL2 Output Low Volt age 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V
VOH2 Output High Voltage IOH = -100 µAV
CC - 0.2 V
AT25P1024
4
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter Voltage Min Max Units
fSCK SCK Clock Frequency 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
2.1
1.0
0.5 MHz
tRI Input Rise Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2µs
tFI Input Fall Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2µs
tWH SCK High Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
400
800 ns
tWL SCK Low Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
400
800 ns
tCS CS High Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
500
1000 ns
tCSS CS Setup Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
250
1000 ns
tCSH CS Hold Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
150
250
1000 ns
tSU Data In Setup Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
30
50
100 ns
tH Data In Hold Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50
100 ns
tHD Hold Setup Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
400 ns
tCD Hold Hold Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
300
400 ns
tVOutput Valid 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
200
400
800 ns
tHO Output Hold Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0ns
AT25P1024
5
Note: 1. This parameter is characterized and is not 100% tested.
tLZ Hold to Output Low Z 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
100
200
300 ns
tHZ Hold to Output High Z 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
200
300 ns
tDIS Output Disable Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
250
1000 ns
tWC Write Cycle Time 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
5
10
10 ms
Endurance(1) 5.0V, 25°C, Page Mode 4.5 - 5.5
2.7 - 5.5
1.8 - 3.6 100K Write
Cycles
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter Voltage Min Max Units
AT25P1024
6
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) i s always an
input, the AT25P1024 always operates as a slave.
TRANSMITTER/RECEIVER: The AT25P1024 has
separate pins designated for data transmission (SO) and
reception (S I).
MSB: The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE: After the device is selected with CS
going low, the fi rst byte wil l be receiv ed. This byte co ntains
the op-code that defines the operations to be performed.
INVALID OP-CODE: If an in vali d op-cod e is re ceive d, no
data will b e shift ed into t he AT25P 1024, an d the ser ial o ut-
put pin ( SO) wi ll rema in in a high imped ance s tate un til th e
falling edge of CS is detected again. This will reinitialize the
serial communication.
CHIP SELECT: The AT25P1024 is selected when the CS
pin is lo w. Wh en th e dev i ce is not selected, d ata wi ll not b e
accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is u sed in conj unct ion wi th th e CS
pin to select the AT25P1024. When the device is selected
and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device
without re settin g the seria l sequ ence. To paus e, the HOL D
pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The wr ite protect pin (WP ) will allow
normal read/write operatio ns when held high. When the
WP pin i s brough t low an d WPE N bit is “1”, al l write o pera-
tions to the status register are inhibited. WP going low
while CS is st ill low will inter rupt a write to the statu s regis-
ter. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the
status register. The WP pin function is blocked when the
WPEN bi t in the statu s register is “0”. This will a llow the
user to install the AT25P1024 in a system with the WP pin
tied to ground and still be able to write to the status regis-
ter. All WP pin functions are enabled when the WPEN bit is
set to “1”.
SPI Serial Interface
MASTER:
MICROCONTROLLER SLAVE:
AT25P1024
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (SPI CK)
SS0
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
AT25P1024
7
Functional Description
The AT25P1024 is designed to interface directly with the
synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.
The AT25P1024 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are trans-
ferred with the MS B first and st art with a high- to-low tra nsi-
tion.
WRITE ENABLE (WREN): The devic e wil l power u p in th e
write disable state when VCC is applied. All programming
instr ucti ons mus t t here fore be pre ced ed b y a Wr ite Enab le
instruction.
WRITE DISABLE (WRDI): To protect the device agains t
inadver ten t writes , the Write Disabl e instruction dis abl es all
programmi ng modes . The WRDI inst ructio n is indepe ndent
of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The REA DY/BUSY and Write Enable status of the devic e
can be determined by the RDSR instruction. Similarly, the
Block W rit e Pr otectio n bi ts i ndicate the exten t of prote ction
employed. These bits are set by using the WRSR i nstruc-
tion.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT2 5P1024 is divi ded into four array se gments.
Top quarter (1/4), top half ( 1/2), or all of the memory seg-
ments can be protected. Any of the data within any
select ed segment wil l therefore be READ on ly. The block
write protection le vels and corre sponding status register
control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that hav e the same pro perties and function s as the regular
memory cells (e.g. WREN, tWC, RDSR).
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is en a bl e d wh en t h e W P pin is low and the WPEN bit is
“1”. Hardware write protection is disabl ed when
either
the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
inclu ding the Bl ock Prot ect bits an d the WPE N bit, and th e
block- protec ted sec tions in the memory a rra y are dis able d.
Table 1. Instruction Set for the AT25P1024
Instruction
Name Instruction
Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Registe r
WRSR 0000 X001 Write Status Register
READ 0000 X011 R ead Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY) Bit 0 = 0 (RDY ) indicates the device is
READY. Bit 0 = 1 indicates the write cycl e is in
progress.
Bit 1 (WEN) Bit 1= 0 indicates the device
is not
WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0) See Table 4.
Bit 3 (BP1) See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
Table 4. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25P1024
000 None
1(1/4) 0 1 01800 - 01FFFF
2(1/2) 1 0 010000 - 01FFFF
3(All) 1 1 0000 - 01FFFF
AT25P1024
8
Writes are only allowed to sections of the memory which
are not block-protected.
Note: When the WPEN bit is hardware write protected, it can-
not be c hanged ba ck to “0”, as lon g as the W P pin is held
low.
READ SEQUENCE (READ): Reading the AT25P1024
via the SO (Serial Output) pin requires the following
sequence. After the CS line is pulled low to select a device,
the READ op-code is transmitted via the SI line followed by
the byte ad dress to be read (Refer to Table 6). U pon com-
pletion, any data on the SI lin e will be ignored. The data
(D7-D0) at the specified address is then shifted out onto
the SO line. If only one byte is to be read, the CS line
should be driven h igh afte r the da ta come s out. The READ
sequence can be continued since the byte address is auto-
matically incremented a nd data will continue to be shifte d
out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the
entire memory to be read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the
AT25P10 24, two separate instruction s must be executed.
First, the device must be write enabled via the Write
Enable (WREN) Instruction. Then a Write (WRITE) Instruc-
tion may be executed. Also, the address of the memory
location(s) to be programmed must be outsid e the pro-
tected address field l ocation selected by the Block Wr ite
Protectio n Level. During an internal write cyc le, all com-
mands will be ignored except the RDSR instruction.
A Wr ite Instr uction requires the fol lowing s equenc e. After
the CS line is pulled lo w to sel ect the dev ice, the W RITE
op-code i s transmitted via the SI line follo wed by the by te
addres s and the data (D7 -D0) to be program med (Refer to
Table 6). Pr ogram mi ng will s tart aft er the CS pin i s broug ht
high. (The LOW to High transition of the CS pin mu st oc cur
during t he SCK lo w time imm ediately after clocking i n the
D0 (LSB) data bit.
The READY/BU SY status of the devic e can be determ ined
by initiating a READ STA TUS REGISTER (RDSR) Instruc-
tion. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0
= 0, the WRITE cycle has ended. Only the READ STATUS
REGISTER instruction is enabled during the WRITE pro-
gramming cycle.
The A T25P1024 is capable of a 128-byte PAGE WRITE
operati on ONLY. Content of the page in the array wil l not
be guar anteed if l ess than 12 8 bytes of da ta is recei ved
(byte op erati on i s n ot supp or ted ). Afte r e ac h byte of data is
received, the seve n low order address bits are internally
incremented by one; the high order bits of the address will
remain constant. If more than 128 bytes of data are trans-
mitted, the ad dr es s cou nter wi ll roll ov er an d th e pr ev i ously
written data will be overwritten. The AT25P1024 is auto-
matically returned to the write disable state at the comple-
tion of a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the
device wil l i gno re the Wr it e in structi on and wil l return to th e
standby state, when CS is br ought high. A ne w CS falling
edge is required to re-initiate the serial communication.
Table 5. WPEN Operation
WPEN WP WEN Protected
Blocks Unprotected
Blocks Status
Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
Table 6. Address Key
Address AT25P1024
ANA16 - A0
Don’t Care Bits A23 - A17
AT25P1024
9
Timing Diagrams (for SPI Mode 0 (0, 0))
Synchronous Data Timing
WREN Timing
WRDI Timing
SO V
OH
V
OL
HI-Z HI-Z
t
V
VALID IN
SI V
IH
V
IL
t
H
t
SU
t
DIS
SCK V
IH
V
IL
t
WH
t
CSH
CS V
IH
V
IL
t
CSS
t
CS
t
WL
t
HO
AT25P1024
10
RDSR Timing
WRSR Timing
READ Timing
CS
SCK
01234567891011121314
SI INSTRUCTION
SO
76543210
DATA OUT
MSB
HIGH IMPEDANCE
CS
SI
SCK
HIGH IMPEDANCE
INSTRUCTION
3-BYTE ADDRESS
01234
4
5
5
6
6
7
7
8 9 10 11 28
23 22 21 3
... 21
321
0
0
29 30 31 32 33 34 35 36 37 38
SO
AT25P1024
11
WRITE Timing
HOLD Timing
CS
SCK
SI
SO
3-BYTE ADDRESS 1st BYTE DATA-IN 128th BYTE DATA-IN
INSTRUCTION
HIGH IMPEDANCE
0123456789101128
232221 3 10 654321072
29 30 31 32 33 34
1051
1052
1054
1053
1055
SO
SCK
HOLD
t
CD
t
HD
t
HZ
t
LZ
t
CD
t
HD
CS
AT25P1024
12
Ordering In formation
tWC (max)
(ms) ICC (max)
(µ
µµ
µA) ISB (max)
(µ
µµ
µA) fMAX
(kHz) Ordering Code Package Operation Range
5 7000 7.0 2100 AT25P1024C1-10CC
AT25P1024W1-10SC 8C1
20S Commercial
(0°C to 70°C)
7000 7.0 2100 AT25P1024C1-10CI
AT25P1024W1-10SI 8C1
20S Industrial
(-40°C to 85°C)
10 2000 3.0 1400 AT25P1024C1-10CC-2.7
AT25P1024W1-10SC-2.7 8C1
20S Commercial
(0°C to 70°C)
2000 3.0 1000 AT25P1024C1-10CI-2.7
AT25P1024W1-10SI-2.7 8C1
20S Industrial
(-40°C to 85°C)
10 1000 3.0 500 AT25P1024C1-10CC-1.8
AT25P1024W1-10SC-1.8 8C1
20S Commercial
(0°C to 70°C)
1000 3.0 500 AT25P1024C1-10CI-1.8
AT25P1024W1-10SI-1.8 8C1
20S Industrial
(-40°C to 85°C)
Package Type
8C1 8-Lead, 0.300" Wide, Leadless Array Package (LAP)
20S 20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
Blank Standard Device (4.5V to 5.5V)
-2.7 Low Voltage (2.7V to 5.5V)
-1.8 Low Voltage (1.8V to 3.6V)
AT25P1024
13
Packaging Information
5.15 (0.203)
4.85 (0.191)
8.15 (0.321)
7.85 (0.309) 0.42 (0.017)
0.34 (0.013)
1.30 (0.051)
1.00 (0.039)
1.27 (0.050) TYP 0.41 (0.016) TYP
0.64 (0.025) TYP
1
2
3
4
8
7
6
5
TOP VIEW SIDE
VIEW
BOTTOM VIEW
0.299 (7.60)
0.291 (7.39)
0.020 (0.508)
0.013 (0.330)
0.420 (10.7)
0.393 (9.98)
PIN 1
.050 (1.27) BSC
0.513 (13.0)
0.497 (12.6)
0.012 (0.305)
0.003 (0.076)
0.105 (2.67)
0.092 (2.34)
0
8REF
0.035 (0.889)
0.015 (0.381)
0.013 (0.330)
0.009 (0.229)
8C1, 8-Lead, 0.300" Wide, Leadless Array Pack age
(LAP)
Dimensions in Inches and (Millimeters)
20S, 20-Lead, 0.300" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
