AT25P1024
7
Functional Description
The AT25P1024 is designed to interface directly with the
synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.
The AT25P1024 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are trans-
ferred with the MS B first and st art with a high- to-low tra nsi-
tion.
WRITE ENABLE (WREN): The devic e wil l power u p in th e
write disable state when VCC is applied. All programming
instr ucti ons mus t t here fore be pre ced ed b y a Wr ite Enab le
instruction.
WRITE DISABLE (WRDI): To protect the device agains t
inadver ten t writes , the Write Disabl e instruction dis abl es all
programmi ng modes . The WRDI inst ructio n is indepe ndent
of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The REA DY/BUSY and Write Enable status of the devic e
can be determined by the RDSR instruction. Similarly, the
Block W rit e Pr otectio n bi ts i ndicate the exten t of prote ction
employed. These bits are set by using the WRSR i nstruc-
tion.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT2 5P1024 is divi ded into four array se gments.
Top quarter (1/4), top half ( 1/2), or all of the memory seg-
ments can be protected. Any of the data within any
select ed segment wil l therefore be READ on ly. The block
write protection le vels and corre sponding status register
control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that hav e the same pro perties and function s as the regular
memory cells (e.g. WREN, tWC, RDSR).
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is en a bl e d wh en t h e W P pin is low and the WPEN bit is
“1”. Hardware write protection is disabl ed when
either
the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
inclu ding the Bl ock Prot ect bits an d the WPE N bit, and th e
block- protec ted sec tions in the memory a rra y are dis able d.
Table 1. Instruction Set for the AT25P1024
Instruction
Name Instruction
Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Registe r
WRSR 0000 X001 Write Status Register
READ 0000 X011 R ead Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 3. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY) Bit 0 = 0 (RDY ) indicates the device is
READY. Bit 0 = 1 indicates the write cycl e is in
progress.
Bit 1 (WEN) Bit 1= 0 indicates the device
is not
WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0) See Table 4.
Bit 3 (BP1) See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
Table 4. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25P1024
000 None
1(1/4) 0 1 01800 - 01FFFF
2(1/2) 1 0 010000 - 01FFFF
3(All) 1 1 0000 - 01FFFF