PIC18F87J10-I/PT - Microchip Technology

PIC18F87J10 FAMILY

The PIC18F87J10 family parts you have received

conform functionally to the Device Data Sheet

(DS39663C), except for the anomalies described

below. Any Data Sheet Clarification issues related to

the PIC18F87J10 family will be reported in a separate

Data Sheet errata. Please check the Microchip web site

for any existing issues.

The following silicon errata apply only to

PIC18F87J10 family devices with these Device/

Revision IDs:

1. Module: ADC

When the A/D conversion clock is selected to be

either FOSC/64, FOSC/ 32 o r FOSC/16, th e GO/DONE

bit cannot be set for a second conversion without

first sele cting (temporari ly) the RC oscillator as the

A/D conversion clock. With the A/D conversion

clock settings of FOSC/2, FOSC/4 and FRC, the A/D

function s norm al ly.

Work around

For A/D conversion clock settings of FOSC/64,

FOSC/32 or FOSC/16, the following work around,

shown in Example 1, must be performed prior to

setting the GO/DONE bit for subsequent

conversions.

It is recommended that this code be inserted

immediately after the A/D result has been read

from the pre v ious conversion.

2. Module: ADC

When FOSC/8 is selected as the A/D conversion

clock, A/D conversion will not be performed.

Work around

None.

EXAMPLE 1:

Part Number Device ID Revision ID

PIC18F87 J1 0 01 0111 011 00011

PIC18F86J15 01 0111 010 00011

PIC18F86J10 01 0111 001 00011

PIC18F85J15 01 0111 000 00011

PIC18F85J10 01 0101 111 00011

PIC18F67J10 01 0101 101 00011

PIC18F66J15 01 0101 100 00011

PIC18F66J10 01 0101 011 00011

PIC18F65J15 01 0101 010 00011

PIC18F65J10 01 0101 001 00011

The Devic e IDs (DEVID1 an d DEVID2 ) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

MOVF ADCON2, W ;copy the value of ADCON2 to WREG

BSF ADCON2, ADCS0 ;temporarily select RC oscillator as clock

BSF ADCON2, ADCS1

MOVWF ADCON2 ;restore ADCON2 to original value

PIC18F87J10 Family Rev. A2 Silicon Errata

PIC18F87J10 FAMILY

3. Module: MSSP

In SPI mode, the Buffer Full bit (BF in SSPxSTAT

SSPxCON1) and the Receive Overflow Indicator

bit (SSPOV in SSPxCON1) are not reset upon

disabling the SPI module (by clearing the SSPEN

bit in SSPxCON1 register).

For example, if SSPxBUF is full (BF bit is set) and

the MSSP module is disabled, and then re-

enabled, the BF bit will remain set. In SPI Slave

mode, a subsequent write to SSPxBUF will result

in a write collision; or in SPI Slave mode, if a new

byte is receiv ed, a receive overflow will o ccur.

Work around

Ensure that if the buffer is full, SSPxBUF is read

(thus clearing the BF flag) before disabling the

MSSP module. Also, ensure that WCOL is clear

before disabling the MSSP module. If the module

was c onfigured in SPI Slave mode , ensure that th e

SSPOV bit is clear before disabling the module.

4. Module: MSSP

In its current implementation, the I2C™ Master

mode operates as follows:

a) The Baud Rate Generator for I2C in Master

mode is slower than the rates specified in

Table 17-3 of the Device Data Sheet.

For this revision of silicon, use the values

shown in Table 1 in place of those shown in

Table 17-3 of the Device Data Sheet. The

differences are shown in bold text.

b) Use the following formula in place of the

one shown in Register 17-4 (SSPCON1) of

the Device Data Sheet for bit description

SSPM3:SSPM0 = 1000.

SSPADD = INT(( FCY/FSCL) – (FCY/1.1 11 MHz)) – 1

Note: The I2C bus is a synchronous protocol, so

the accuracy of the bus frequency is not

critical.

Date Codes that pertain to this issue:

All engineering and production devices.

TABLE 1: I2C™ CLOCK RATE w/BRG

FOSC FCY FCY * 2 BRG Value FSCL

(2 Rollovers of BRG)

40 MHz 10 MHz 20 MHz 0Eh 400 kHz(1)

40 MHz 10 MHz 20 MHz 15h 312.5 kHz

40 MHz 10 MHz 20 MHz 59h 100 k Hz

16 MHz 4 MHz 8 MHz 05h 400 kHz(1)

16 MHz 4 MHz 8 MHz 08h 308 k Hz

16 MHz 4 MHz 8 MHz 23h 100 k Hz

4 MHz 1 MHz 2 MHz 01h 333 kHz(1)

4 MHz 1 MHz 2 MHz 08h 100 k Hz

4 MHz 1 MHz 2 MHz 00h 1 MHz(1)

Note 1: The I2C™ inte rface do es not co nform to the 400 kH z I2C sp ecifi cation ( which ap plies to r ates greater th an

100 kHz) in all details, but may be used with care where higher rates are required by the application.

PIC18F87J10 FAMILY

5. Module: MSSP

After an I2C transfer is initiated, the SSPxBUF

additional writes are blocked. The data transfer may

be corrupted if SSPxBUF is written during this tim e.

The WCOL bit is set any time an SSPxBUF write

occurs during a transfer.

Work around

Avoid writing SSPxBUF until the data transfer is

complete, indicated by the setting of the SSP1IF

bit (PIR1<3>).

V erify the WCOL bit (SSPxCON1<7>) is clear after

writing SSPxBUF to ensure any potential transfer

in progress is not corrupted.

Date Codes that pertain to this issue:

All engineering and production devices.

6. Module: MSSP (SPI Mode)

When the SPI is using Timer2/2 as the clock

source, a shorter than expected SCKx pulse may

occur on the first bit of the transmitted/received

data (Figure 1).

FIGURE 1: SCKx PULSE VARIATION

USING TIMER2/2

Work around

To avoid p rodu cing t he sho rt puls e, turn o ff Timer2

and clear the TMR2 register, load the SSPxBUF

with the d ata to tran smit and the n turn T imer2 back

on. Refer to Example 2 for sample code.

EXAMPLE 2: A VOIDING THE INITIAL

SHORT SCK1 PULSE

(FOR MSSP1)

Date Codes that pertain to this issue:

All engineering and production devices.

7. Module: MSSP

In SP I mode, the S DOx outpu t may chan ge after th e

inactive clock edge of the bit ‘0’ output. This may

affect some SPI components that read data over

300 ns after the inactive edge of SCKx.

Work around

None

Date Codes that pertain to this issue:

All engineering and production devices.

SDOx

SCKx

Write SSPxBUF

bit 7 =

bit 6 =

bit 5 =

. . . .

LOOP BTFSS SSP1STAT, BF ;Data received?

;(Xmit complete?)

BRA LOOP ;No

MOVF SSP1BUF, W ;W = SSPBUF

MOVWF RXDATA ;Save in user RAM

MOVF TXDATA, W ;W = TXDATA

BCF T2CON, TMR2ON ;Timer2 off

CLRF TMR2 ;Clear Timer2

MOVWF SSP1BUF ;Xmit New data

BSF T2CON, TMR2ON ;Timer2 on

PIC18F87J10 FAMILY

8. Module: MSSP

It has been observed that following a Power-on

Reset, I2C modes may not initialize properly by

just co nfi guri ng t he SC L x a nd SDAx pi ns as e ith er

input s or ou tput s. This has on ly been seen i n a few

unique sy stem enviro nm ent s .

A test of a statistically significant sample of pre-

production systems, across the voltage and

current range of the application’s power supply,

should indicate if a system is susceptible to this

issue.

Work around

Before configuring the module for I2C operation:

1. Configure the SC L x an d SDAx pin s as output s

by clearing their corresponding TRIS bits.

2. Force SCLx and SDAx low by clearing the

corresponding LAT bits.

3. While keeping the LAT bits clear, configure

SCLx and SDAx as inpu ts by setting their TRIS

bits.

Once this is done, use the SSPxCON1 and

SSPxCON2 registers to configure the proper I2C

mode as before.

Date Codes that pertain to this issue:

All engineering and production devices.

9. Module: MSSP

When the MSSP peripherals are configured for

SPI mode, the Buf fer Ful l bit, BF (SSPxSTAT<0>),

should not be polled i n software to determine whe n

the transfer is complete .

Work around

Copy the SSPxSTAT register into a variable and

perform the bit test on the variable. In Example 3,

SSP1STAT is copied into the working register

where the bit test is performed.

EXAMPLE 3: MS SP1

A second option is to poll th e Master Sy nchron ous

Serial Port Interrupt Flag bit, SSP1IF (PIR1<3>).

This bit can be polled an d will set when the transfer

is complete.

Date Codes that pertain to this issue:

All engineering and production devices.

10. Module: A/D

The A/D offset is greater than the specified limit in

Table 26-26 of the Device Data Sheet. The

updated conditions and limits are shown in bold

text in Table 2.

Work around

Three work arounds exist.

1. Configure th e A/D to u se the VREF+ a nd VREF-

pins for th e volta ge referenc es. This is do ne by

setting the VCFG<1:0> bits (ADCON1<5:4>).

2. Perform a conversion on a known voltage

reference voltage and adjus t the A/D result in

software.

3. Increase system clock speed to 40 MHz and

adjust A/D sett ings acc ordingl y. Higher s ystem

clock frequencies decrease offset error.

Date Codes that pertain to this issue:

All engineering and production devices.

TABLE 2: A/D CONVERTER CHARACTERISTICS: PIC18F87J10 FAMILY (INDUSTRIAL)

loop_MSB:

MOVF SSP1STAT, W

BTFSS WREG, BF

BRA loop_MSB

Param

No. Symbol Characteristic Min Typ Max Units Conditions

A06A EOFF Offset Error — — < ±5.0 LSb VREF = VREF+ and VREF-

A06 EOFF Offset Error — — <±5.0 LSb VREF = VSS and VDD

PIC18F87J10 FAMILY

11. Module: EUSART

In rare situations, one or more extra zero bytes

have been observed in a pa cket transmitted by the

module operating in Asynchronous mode. The

actual data is not lost or corrupt ed; only unwante d

(extra) zero bytes are observed in the packet.

This situation has only been observed when the

content s of the transmit buffer , TXREGx, are trans-

ferred to the TSR durin g the transmi ssion of a Sto p

bit. For this to occur, three things must happen in

the sa me inst ruction cycle:

• TXREGx is written to;

• the baud rate counter overflows (at the end of

the bit period); and

• a Stop bit is being transmitted (shifted out of

TSR).

Work around

If possible, do not use the module’s double-buffer

capability. Instead, load the TXREGx register

when the TRMT bit (TXSTAx<1>) is set, indicating

the TSR is empty.

If double-buffering is used and back-to-back

transmission is performed, then load TXREGx

immediately after TXxIF is set, or wait 1-bit time

after TXxIF is set. Both solutions prevent writing

TXREGx while a Stop bit is transmitted. Note that

TXxIF is set at the beginning of the Stop bit

transmission.

If transmission is intermittent, then do the

following:

• Wait for the TRMT bit to be set before

loading TXR EGx .

• Alternatively, use a free timer resource to

time the baud period. Set up the timer to

overflow at the end of S top bit, then st art the

timer when you load the TXREGx. Do not

load the TXREGx when timer is about to

overflow.

Date Codes that pertain to this issue:

All engineering and production devices.

12. Module: EUSART

In 9-Bit Async hro no us Fu ll-Duplex R ec eive mod e,

the receiv ed data may be corrupted i f the TX9D bit

(TXSTAx<0 >) is not modified imme diately after th e

RCIDL bit (BAUDCONx<6>) is set.

Work around

Write to TX9D only when a reception is not in

progress (RCIDL = 1). Since there is no interrupt

associated with RCIDL, it must be polled in software

to determine when TX9D can be updated.

Date Codes that pertain to this issue:

All engineering and production devices.

13. Module: EUSART

After the last r eceived byte h as been re ad from the

EUSART receive buffer, RCREGx, the value is no

longer valid for subsequent read operations.

Work around

The RCREGx register should only b e read once for

each byte received . After each byte is received from

the EUSART, store the byte into a use r variab le. To

determine when a byte is available to read from

RCREGx, poll the RCIDL bit (BAUDC ONx<6>) for

a low-to-high transition, or use the EUSART

Receive Interrupt Flag, RC1IF (PIR1<5>).

Date Codes that pertain to this issue:

All engineering and production devices.

14. Module: EUSART

With the auto-wake-up option enabled by setting

the WUE bit (BAUDCONx<1>), the RC1IF

(PIR1<5>) bit will become set on a high-to-low

transiti on on the RXx pin. While the WUE bit is se t,

reading the receive buffer, RCREGx, will not clear

the RCxIF i nterrup t flag. Therefo re, the first oppor-

tunity to automatically clear RCxIF by reading

RCREGx will happen only after WUE bit is cleared.

Work around

There are two worka rounds available:

1. Poll the WUE bit and read RCREGx after the

WUE bit is automatically clea red.

Date Codes that pertain to this issue:

All engineering and production devices.

Note: RCxIF can only be cleared by reading

RCREGx

PIC18F87J10 FAMILY

15. Module: Timer1

In 16-Bit Asynchronous Counter mode (with or

without use of the Timer1 oscillator), the TMR1H

and TM R3H b uff ers do not u pdate when TM RxL i s

read.

This issue only affects reading the TMRxH regis-

ters. The timers increment and set the interrupt

flags as ex pe cte d. The time r regis ters can als o be

written as expected.

Work around

1. Use 8-bit mode by clearing the RD16 bit

(T1CON<7>).

2. Use the internal clock synchronization option

by cl earing t he T1SYNC bit (T1CON<2>).

Date Codes that pertain to this issue:

All engineering and production devices.

16. Module: CPU

The device current consumption is not reduced

significantly when the device enters IDLE mode.

The device does stop execution and peripherals

continue to run as expected.

Work around

None

Date Codes that pertain to this issue:

All engineering and production devices.

17. Module: External Memory Bus

The A<19:1 6> EMB addre ss lines and Read/ Wr ite

control pins (OE, WRH and WRL) are released to

their respective inactive states at the same time

violati ng timing c ondition m entioned in Figure 26.5

and Figure 26.6 in the data sheet. This may result

in peripheral device on the bus detecting an

address change when Write/Read is initiated. The

bus capacitance and signal delay on the address

and control lines can affect the probability of

invalid detection.

Work around

Two workarounds are available

1. Use a la tch base d on the falling e dge of ALE to

hold the A <19:16> signals.

2. Or, add a de lay c ir c ui t t o e xte nd t he va l id ti me

for A<19:16> signals to ensure the address is

valid until Read/Write signals go inactive.

18. Module: External Memory Bus

For PIC18F8XXX devices, the Stack Pointer may

incorrec tly incre ment duri ng a ta ble read o peration

if the ext ernal mem ory bus wait sta tes are ena bled

(i.e., Configuration bit, WAIT, is clear

(CONFIG3L<7> = 0) and WAIT bits

(MEMCON<5:4>) are not equal to ‘11’).

Work around

If using the external memory bus and performing

TBLRD operations with a non-zero wait state

(CONFIG3L<7> = 0 and WAIT<1:0>

(MEMCON<5:4>) are not equal to ‘11’), disable

interrupts by clearing the GIE/GIEH (INTCON<7>)

and PEIE/GIEL (INTCON<6>) bits prior to executing

any TBLRD operation.

19. Module: Core (Program Memory Space)

Writes to program memory address 300000h, that

are not blocked, can cause the program memory

at different locations to be corrupted.

Work around

Do not write to address 300000h. If you wish to

modify the contents of the Configuration registers,

then mod ify the Configuration W ords located at the

end of the user m emory (7FF4h for PIC 18FX5J10

device s and 3FF4h for PIC18F X4J10 devices) an d

issue a Reset command. This will reload the

Configuration registers with the new configuration

setting.

PIC18F87J10 FAMILY

REVISION HISTORY

Rev A Document (8/2005)

First revision of this document. Includes silicon issues

1 (ADC), 2 (ADC), and 3 (MSSP).

Rev B Document (5/2006)

Added silicon issues 4-9 (MSSP), 10 (A/D), 11-

14 (EUS ART), 15 (Timer1), 16 (CPU), 17 (External

Memory Bus), 18, (External Memory Bus), and 19

(Core Program Memory Space).

PIC18F87J10 FAMILY

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for your convenien ce

and may be supers eded by updat es . It is y our resp o ns i bil it y to

ensure that your application meets with your specifications.

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02/16/06