HA4P5002-5Z - Intersil Corporation

®HA-5002

110MHz, High Slew Rate, High Output

Current Buffer

The HA-5002 is a monolithic, wideband, high slew rate, high

output current, buffer amplifier.

Utilizing the advantages of the Intersil D.I. technologies, the

HA-5002 current buffer offers 1300V/µs slew rate with

110MHz of bandwidth. The ±200mA output current capability

is enhanced by a 3Ω output impedance.

The monolithic HA-5002 will replace the hybrid LH0002 with

corresponding performance increases. These chara cteristics

range from the 3000kΩ input impedance to the increased

output v olta ge swing. Mo nolith ic desig n technolo gies hav e

allow ed a more precise b uff er to be de v eloped w ith more than

an order of magnitude smaller gain error.

The HA-5002 will provide many present hybrid users with a

higher degree of reliability and at the same time increase

overall circuit performance.

For the military grade product, refer to the HA-5002/883

datasheet.

Features

• Voltage Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.995

• High Input Impedance . . . . . . . . . . . . . . . . . . . . . .3000kΩ

• Low Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . 3Ω

• Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . 1300V/µs

• Very Wide Bandwidth. . . . . . . . . . . . . . . . . . . . . . 110MHz

• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±200mA

• Pulsed Output Current . . . . . . . . . . . . . . . . . . . . . . 400mA

• Monolithic Construction

•Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Line Driver

• Data Acquistion

• 110MHz Buffer

• Radara Cable Driver

• High Power Current Booster

• High Power Current Source

• Sample and Holds

• Video Products

Ordering Information

PART NUMBER PART MARKING TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

HA2-5002-2 HA2-5002-2 -55 to 125 8 Pin Metal Can T8.C

HA2-5002-5 HA2-5002-5 0 to 75 8 Pin Metal Can T8.C

HA3-5002-5 HA3-5002-5 0 to 75 8 Ld PDIP E8.3

HA3-5002-5Z (Note) HA3-5002-5Z 0 to 75 8 Ld PDIP* (Pb-free) E8.3

HA4P5002-5 HA4P5002-5 0 to 75 20 Ld PLCC N20.35

HA4P5002-5Z (Note) HA4P5002-5Z 0 to 75 20 Ld PLCC (Pb-free) N20.35

HA9P5002-5 50025 0 to 75 8 Ld SOIC M8.15

HA9P5002-5Z (Note) 50025Z 0 to 75 8 Ld SOIC (Pb-free) M8.15

HA9P5002-9 50029 -40 to 85 8 Ld SOIC M8.15

HA9P5002-9Z (Note) 50029Z -40 to 85 8 Ld SOIC (Pb-free) M8.15

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

March 8, 2006 FN2921.11Data Sheet

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN2921.11

March 8, 2006

Pinouts HA-5002 (PDIP, SOIC)

TOP VIEW HA-5002 (PLCC)

TOP VIEW HA-5002 (METAL CAN)

TOP VIEW

NOTE: Case Voltage = Floating

OUT

V2+

V1-

V1+

V2-

193 2 201

910 11 12 13

V2-

V1-

V2+

V1+

OUT

V2-V2+

OUT

V1+

V1-

HA-5002

3FN2921.11

March 8, 2006

Absolute Maximum Ratings Thermal Info rmation

Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V1+ to V1-

Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . ±200mA

Output Current (50ms On, 1s Off) . . . . . . . . . . . . . . . . . . . . ±400mA

Operating Conditions

Temperature Range

HA-5002-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C

HA-5002-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C

HA-5002-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W)

PDIP Package*. . . . . . . . . . . . . . . . . . . 92 N/A

Metal Can Package . . . . . . . . . . . . . . . 155 67

PLCC Package. . . . . . . . . . . . . . . . . . . 74 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 157 N/A

Max Junction Temperature (Hermetic Packages, Note 1). . . . . . 175°C

Max Junction Temperature (Plastic Packages, Note 1) . . . . . . . . 150°C

Max Storage Temperature Range . . . . . . . . . . . . . . -65°C to 150°C

Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300°C

(PLCC and SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing

applications.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Maximum po wer dissipation, in cluding load con ditions, must be designed t o maintain the ma ximum junction temper ature below 175°C for the

can packages, and below 150°C for the plastic packages.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified

PARAMETER TEST

CONDITIONS TEMP

(°C)

HA-5002-2 HA-5002-5, -9

UNITSMIN TYP MAX MIN TYP MAX

INPUT CHARACTERISTICS

Offset Voltage 25 - 5 20 - 5 20 mV

Full - 10 30 - 10 30 mV

Average Offset Voltage Drift Full - 30 - - 30 - µV/°C

Bias Current 25 - 2 7 - 2 7 µA

Full - 3.4 10 - 2.4 10 µA

Input Resistance Full 1.5 3 - 1.5 3 - MΩ

Input Noise Voltage 10Hz-1MHz 25 - 18 - - 18 - µVP-P

TRANSFER CHARACTERISTICS

Voltage Gain

(VOUT = ±10V) RL = 50Ω25 - 0.900 - - 0.900 - V/V

RL = 100Ω25 - 0.971 - - 0.971 - V/V

RL = 1kΩ25 - 0.995 - - 0.995 - V/V

RL = 1kΩ Full 0.980 - - 0.980 - - V/V

-3dB Bandwidth VIN = 1VP-P 25 - 110 - - 110 - MHz

AC Current Gain 25 - 40 - - 40 - A/mA

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 100Ω25 ±10 ±10.7 - ±10 ±11.2 - V

RL = 1kΩ, VS = ±15V Full ±10 ±13.5 - ±10 ±13.9 - V

RL = 1kΩ, VS = ±12V Full ±10 ±10.5 - ±10 ±10.5 - V

Output Current VIN = ±10V, RL = 40Ω25 - 220 - - 220 - mA

Output Resistance Full - 3 10 - 3 10 Ω

Harmonic Distortion VIN = 1VRMS, f = 10kHz 25 - <0.005 - - <0.005 - %

TRANSIENT RESPONSE

Full Power Bandwidth (Note 3) 25 - 20.7 - - 2 0.7 - MHz

Rise Time 25 - 3.6 - - 3.6 - ns

Propagation Delay 25 - 2 - - 2 - ns

Overshoot 25 - 30 - - 30 - %

Slew Rate 25 1.0 1.3 - 1.0 1.3 - V/ns

Settling Time To 0.1% 25 - 50 - - 50 - ns

HA-5002

4FN2921.11

March 8, 2006

Differential Gain RL = 500Ω25 - 0.06 - - 0.06 - %

Differential Phase RL = 500Ω25 - 0.22 - - 0.22 - Degrees

POWER REQUIREMENTS

Supply Current 25 - 8.3 - - 8.3 - mA

Full--10--10mA

Power Supply Rejection Ratio AV = 10V Full 54 64 - 54 64 - dB

NOTE:

3. .

Electrical Specifications VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified (Continued)

PARAMETER TEST

CONDITIONS TEMP

(°C)

HA-5002-2 HA-5002-5, -9

UNITSMIN TYP MAX MIN TYP MAX

FPBW Slew Rate

2πVPEAK

--------------------------- ;V

P=10V=

Test Circuit and Waveforms

FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE

SMALL SIGNAL WAVEFORMS SMALL SIGNAL WAVEFORMS

OUTIN

-15V

+15VV2+

V1+

V2-V1-

VOUT

VIN

RS = 50Ω, RL = 100Ω

VOUT

VIN

RS = 50Ω, RL = 1kΩ

HA-5002

5FN2921.11

March 8, 2006

Schematic Diagram

Application Information

Layout Considerations

The wide bandwidth of the HA-5002 necessi tates that high

frequency circuit layout procedures be followed. Failure to

follow these guidelines can result in marginal performance.

Probably the most crucial of the RF/video layout rules is the

use of a ground plane. A ground plane provides isolation and

minimizes distributed circuit capacitance and inductance

which will degrade high frequency performance.

Other considerations are proper power supply bypassing

and keeping the input and output conne ctions as short as

possible which minimizes distributed capacitance and

reduces board space.

Power Supply Decoupling

For optimal device performance, it is recommended that the

positive and negative power supplies be bypassed with

capacitors to ground. Ceramic capacitors ranging in value

from 0.01 to 0.1µF will minimize high frequency variations in

supply voltage, while low frequency bypassing requires

LARGE SIGNAL WAVEFORMS LARGE SIGNAL WAVEFORMS

Test Circuit and Waveforms (Continued)

VOUT

VIN

RS = 50Ω, RL = 100Ω

VOUT

VIN

RS = 50Ω, RL = 1kΩ

R10

Q25

Q10

Q11

Q15 Q23

Q21

Q22

Q24

Q27

Q26

Q20 Q18

R4R1

Q7Q4

R12

Q16 Q14 Q13

R2RN3

R11

Q12

RN1

Q19

RN2

V1-

V2-

OUT

V2+

V1+

Q17

HA-5002

6FN2921.11

March 8, 2006

larger valued capacitors since the impedance of the

capacitor is dependent on frequency.

It is also recommended that the bypass capacitors be

connected close to the HA-5002 (preferably directly to the

supply pins).

Operation at Reduced Supply Levels

The HA-5002 can operate at supply voltage le vels as low as

±5V and lower. Output swing is directly affected as well as

slight reductions in slew rate and bandwidth.

Short Circuit Protection

The output current can be limited b y using the f ollo wing circuit:

Capacitive Loading

The HA-5002 will drive large capacitive loads without oscillation

but peak current limits should not be exceeded. F ollo wing the

f ormula I = Cdv/dt implies that the slew rate or the capacitiv e

load must be controlled to keep peak current below the

maximum or use the current limiting approach as shown. The

HA-5002 can become unstable with small capacitive loads

(50pF) if certain precautions are not taken. Stability is

enhanced by any one of the follo wing: a source resistance in

series with the input of 50Ω to 1kΩ; increasing capacitive load

to 150pF or greater; decreasing CLOAD to 20pF or less; adding

an output resistor of 10Ω to 50Ω; or adding feedbac k

capacitance of 50pF or greater . Adding source resistance

generally yields the best results.

OUT

V+

RLIM

V1-V2-

V2+

V1+

V-

IOUTMAX = 200mA

(CONTINUOUS)

RLIM V+

IOUTMAX

--------------------------V-

IOUTMAX

--------------------------

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

25 45 65 85 105 125

TEMPERAT URE (°C)

MAXIMUM POWER DISSIPATION (W)

SOIC

PDIP PLCC

QUIESCENT PO WER DISSIPATION

AT ±15V SUPPLIES

Where: TJMAX = Maximum Junction Temperature of the

Device

TA = Ambient

θJC = Junction to Case Thermal Resistance

θCS = Case to Heat Sink Thermal Resistance

θSA = Heat Sink to Ambient Thermal Resistance

Graph is based on:

PDMAX TJMAX TA

–

θJC θCS θSA

--------------------------------------------=

PDMAX TJMAX TA

–

θJA

--------------------------------

FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE

CAN

HA-5002

7FN2921.11

March 8, 2006

Typical Application

FIGURE 3. COAXIAL CABLE DRIVER - 50Ω SYSTEM

RL 50Ω

RG -58

50Ω

V1-V

-12V

V1+V

+12V

VIN

VOUT

VIN

Typical Performance Curves

FIGURE 4. GAIN/PHASE vs FREQUENCY (RL = 1kΩ) FIGURE 5. GAIN/PHASE vs FREQUENCY (RL = 50Ω)

FIGURE 6. VOLTAGE GAIN vs TEMPERATURE (RL = 100Ω) FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (RL = 1kΩ)

-3

-18

PHASE

FREQUENCY (MHz)

VOLTAGE GAIN (dB)

VS = ±15V, RS = 50Ω

GAIN

-6

-9

-12

-15

0°

45°

90°

135°

180°

PHASE SHIFT

1 10 100

-3

-18

PHASE

1 10 100

FREQUENCY (MHz)

VOLTAGE GAIN (dB)

VS = ±15V, RS = 50Ω

GAIN

-6

-9

-12

-15

0°

45°

90°

135°

180°

PHASE SHIFT

TEMPERATURE (°C)

0.994

0.992

0.990

0.988

0.986

0.984

0.982

0.980

0.978

0.976

0.974 0 20406080100120-20-40-60

VOLTAG E GAIN (V/V)

VOUT = -10V TO +10V

VS = ±15V

TEMPERAT URE (°C)

0.998

0.997

0.996

0.995

0.994

0.993

0.992

0.991 0 20 40 60 80 100 120-20-40-60

VOLTAGE GAIN (V/V)

VOUT = 0 TO -10V

VOUT = 0 TO +10V

VS = ±15V

HA-5002

8FN2921.11

March 8, 2006

FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE FIGURE 9. BIAS CURRENT vs TEMPERATURE

FIGURE 10. MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE FIGURE 11. SUPPLY CURRENT vs TEMPERATURE

FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 13. INPUT/OUTPUT IMPEDANCE vs FREQUENCY

Typical Performance Curves (Continued)

TEMPERATURE (°C)

020406080100120-20-40-60

OFFSET VOLTAGE (mV)

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

VS = ±15V

TEMPERATURE (°C)

0 20 40 60 80 100 120-20-40-60

BIAS CURRENT (µA)

7VS = ±15V

TEMPERAT URE (°C)

020406080100120-20-40-60

OUTPUT VOLTAGE (V)

+VOUT

VS = ±15V, RLOAD = 100Ω

-VOUT

TEMPERATURE (°C)

0 20 40 60 80 100 120-20-40-60

SUPPLY CURRENT (mA)

VS = ±15V, IOUT = 0mA

0 2 4 6 8 1012141618

SUPPLY CURRENT (mA)

SUPPLY VOLTAGE (±V)

-55°C

125°C, 25°C

IOUT = 0mA

100K

10K

1000

100

ZOUT

100K 1M 10M 100M

FREQUENCY (Hz)

ZIN

IMPEDANCE (Ω)

VS = ±15V

HA-5002

9FN2921.11

March 8, 2006

Die Characteristics

SUBSTRATE PO TENTIAL (POWERED UP):

V1-

TRANSISTOR COUNT:

PROCESS:

Bipolar Dielectric Isolation

FIGURE 14. VOUT MAXIMUM vs VSUPPLY FIGURE 15. PSRR vs FREQUENCY

FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE FIGURE 17. GAIN ERROR vs INPUT VOLTAGE

Typical Performance Curves (Continued)

15 12 8 5

TA = 25°C

VOUT MAX, VP-P AT 100kHz

TA = -55°C

TA = 125°C,

SUPPLY VOLTAGE (±V)

RLOAD = 100Ω

10K 100K 1M 10M

FREQUENCY (Hz)

PSRR (dB)

0100M

SLEW RATE (V/µs)

1500

1400

1300

1200

1100

1000

900 6 8 10 12 14 16 18

SUPPLY VOLTAGE (±V)

TA = 25°C

VS = ±15V

RL = 600

RL = 1K

150

100

VOUT - VIN (mV)

0246810

INPUT VOLTAGE (VOLTS)

-10-8-6-4-2

-50

-100

-150

RL = 100

HA-5002

10 FN2921.11

March 8, 2006

Metallization Mask Layout HA-5002

V1-IN

OUT

V2+

V1+ (ALT) V1- (ALT)

V2-

V1+

HA-5002

11 FN2921.11

March 8, 2006

HA-5002

Dual-In-Line Plastic Pac kages (PDIP)

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

B1 Be

-A-

0.010 (0.25) C AMBS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between

English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated

in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru-

sions. Mold flash or protrusions shall not exceed 0.010 inch

(0.25mm).

6. E and are measured with the leads constrained to be per-

pendicular to datum .

7. eB and eC are measured at the lead tips with the leads uncon-

strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.

Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,

E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch

(0.76 - 1.14mm).

eA-C-

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.355 0.400 9.01 10.16 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA0.300 BSC 7.62 BSC 6

eB- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N8 89

Rev. 0 12/93

12 FN2921.11

March 8, 2006

Metal Can Pac k ages (Can)

NOTES:

1. (All leads) Øb applies between L1 and L2. Øb1 applies between

L2 and 0.500 from the reference plane. Diameter is uncontrolled

in L1 and beyond 0.500 from the reference plane.

2. Measured from maximum diameter of the product.

3. α is the basic spacing from the centerline of the tab to terminal 1

and β is the basic spacing of each lead or lead position (N -1

places) from α, looking at the bottom of the package.

4. N is the maximum number of terminal positions.

5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

6. Controlling dimension: INCH.

Øb

ØD2

Øek1

Øb1

B ASE AND

SEATING PLANE

ØD ØD1

REFERENCE PLANE

Øb2

Øb1

BASE METAL LEAD FINISH

SECTION A-A

T8.C MIL-STD-1835 MACY1-X8 (A1)

8 LEAD METAL CAN PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.165 0.185 4.19 4.70 -

Øb 0.016 0.019 0.41 0.48 1

Øb1 0.016 0.021 0.41 0.53 1

Øb2 0.016 0.024 0.41 0.61 -

ØD 0.335 0.375 8.51 9.40 -

ØD1 0.305 0.335 7.75 8.51 -

ØD2 0.110 0.160 2.79 4.06 -

e 0.200 BSC 5.08 BSC -

e1 0.100 BSC 2.54 BSC -

F - 0.040 - 1.02 -

k 0.027 0.034 0.69 0.86 -

k1 0.027 0.045 0.69 1.14 2

L 0.500 0.750 12.70 19.05 1

L1 - 0.050 - 1.27 1

L2 0.250 - 6.35 - 1

Q 0.010 0.045 0.25 1.14 -

α45o BSC 45o BSC 3

β45o BSC 45o BSC 3

N8 84

Rev. 0 5/18/94

HA-5002

13 FN2921.11

March 8, 2006

HA-5002

Plastic Leaded Chip Carrier Packages (PLCC)

ASEATING

PLANE

0.020 (0.51)

MIN

VIEW “A”

D2/E2

0.025 (0.64)

0.045 (1.14) R

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

EE1

0.042 (1.07)

0.048 (1.22)

PIN (1) IDENTIFIER

0.020 (0.51) MAX

3 PLCS 0.026 (0.66)

0.032 (0.81)

0.045 (1.14)

MIN

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)

MIN

VIEW “A” TYP.

0.004 (0.10) C

-C-

D2/E2

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1

and E1 include mold mismatch and are measured at the extreme

material condition at the body parting line.

4. To be measured at seating plane contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

-C-

N20.35 (JEDEC MS-018AA I SSU E A)

20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.385 0.395 9.78 10.03 -

D1 0.350 0.356 8.89 9.04 3

D2 0.141 0.169 3.59 4.29 4, 5

E 0.385 0.395 9.78 10.03 -

E1 0.350 0.356 8.89 9.04 3

E2 0.141 0.169 3.59 4.29 4, 5

N20 206

Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN2921.11

March 8, 2006

HA-5002

Small Outline Plastic Packages (SOIC)

INDEX

AREA

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05