{ SGS-THOMSON JF MICROELECTRONICS ST5090 LOW VOLTAGE 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END FEATURES: Complete CODEC and FILTER systemincluding: a 14 BIT LINEAR ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS. a 8 BIT COMPANDED ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS A-LAW OR n-LAW. a TRANSMIT AND RECEIVE BAND-PASS FILTERS a ACTIVE ANTIALIAS NOISE FILTER. Phone Features: a THREE SWITCHABLE MICROPHONE AM- PLIFIER INPUTS. GAIN PROGRAMMABLE: 20 dB PREAMP. (+MUTE), 0. . 22.5 dB AM- PLIFIER, 1.5 dB STEPS. a EARPIECE AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: . . 30 dB, 2 dB STEPS. a EXTERNAL AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: . . 30 dB, 2 dB STEPS. a TRANSIENT SUPRESSION SIGNAL DURING POWER ON AND DURING AMPLIFIER SWITCHING. a INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. ATTENUATION PROGRAMMABLE: 16 dB RANGE, 1 dB STEP. ROUTING POSSI- BLE TO BOTH OUTPUTS. a INTERNAL RING OR TONE GENERATCR IN- CLUDING DTMF TONES, SINEWAVE OR SQUAREWAVE WAVEFORMS. ATTENU- ATION PROGRAMMABLE: 27dB RANGE, 3dB STEP. THREE FREQUENCY RANGES: a) 3.9Hz... . 996Hz, 3.9Hz STEP b) 7.8Hz.... 1992Hz, 7.8Hz STEP c) 15.6Hz.... 3984Hz, 15.6Hz STEP = PROGRAMMABLE PULSE WIDTH MODU- LATED BUZZER DRIVER OUTPUT. General Features: a SINGLE 3.3V +10% OR 5V +10% SUPPLY SELECTABLE. a EXTENDED TEMPERATURE RANGE OPERA- TION (*) -40C to 85C. 1.5 kW STANDBY POWER (TYP. AT 3V). 21 mW OPERATING POWER (TYP. AT 3V). CMOS COMPATIBLE DIGITAL INTERFACES. PROGRAMMABLE PCM AND CONTROL IN- TERFACE MIGROWIRE COMPATIBLE. February 1996 5028 TQFP44(10x10x1.4) ORDERING NUMBERS: Package Dim. Cond. STS5090AD $028 Tube ST5090ADTR $628 Tape&Reel ST5090TQFP TQFP44 =| 10x10x1.4 | Tray 8x20 STS5090TQFPTR | TQFP44 =| 10x10x1.4 | Tape&Reel APPLICATIONS: a GSM DIGITAL CELLULAR TELEPHONES. a CT2 DIGITAL CORDLESS TELEPHONES. a DECT DIGITAL CORDLESS TELEPHONES. a BATTERY GPERATED AUDIO FRONT-ENDS FOR DSPs. (*) Functionality guaranteed in the range 40C 10 +85C; Timing and Electrical Specifications are guaranteed in the range 30C to +85C. GENERAL DESCRIPTION ST5090 is a high performance low power combined PCM CODEG/FILTER device tailored to implement the audio front-end functions required by the next generation low voltage/low power consumption digital terminals. ST5090 offers a number of programmable func- tions accessed through a serial control channelthat easily interfaces to any classical microcontroller. The PCM interface supports both non-delayed (nor- mal and reverse) and delayed frame synchroniza- tion modes. 5715090 can be configurated either as a 14-bit lin- ear or as an 8-bit companded PCM cocer. Additionally to the CODEC/FILTER function, 575090 includes a Tone/Ring/DTMF generator, a sidetone generation, and a buzzer driver output. $1T5090 fulfills and exceeds D3/D4 and CCITT rec- ommendations and ETSI requirements for digital handsetterminals. Main applications include digital mobile phones, as cellular and cordless phones, or any battery pow- ered equipment that requires audio codecs operat- ing at low single supply voltages 1/29ST5090 PIN CONNECTIONS (Top view) a = + i <= t co 6 8 8 6 os 8 8 EF a B 2 2 > > 2 = = = Go = = COI CIC CI CI CI CI Co 35 34 \ Lf nec. Tt O 33 [] ict Nc. CO 1 28 [TD Mica4 L ] Voca CO 2 27 [TZ Mic3- ver- [J 2 sz [] nc Voce CO 3 26 [ID onpa vers [] 8 at [] mica. N.c. Cy 4 25 TT) Mict+ NC. 0 4 30 1 MIce- Vey 5 24 MIC1- re. TL) vu [J 5 za [] ne Ve, CO 6 23 TT) mice+ TOFP44 v, C7 $028 2 FD mice vis [] 8 2s [] No Lr- - Vv. CO] 8 21 [1D Lo ne. []7 a |] ne GNDP CI] 9 20 [1D McLK cnop [] 8 26 [] Lo D 10 19 FS r CO rT) ne. [2 26 |] McL ccLK Cy 11 18 [TD GND DR [ 10 24 | FS cs- Cj 12 17 [ED 2B, cl CO 13 16 [1D co ne [Ju 2a [] Nec BZ 14 15 V cy HI) Vcc \ 12 13 14 15 1 17 #18 #19 20 21 2 / DeaTLos4 a 5 og , Gb M 89 9 KF A Gg S DeaTLogs BLOCK DIAGRAM MIG3- MIG PREAMP MIC AMP 20dB O->225 Mice + MUTE + 5d5 STEP + Mict- PREFILTER & DE TRANSMIT ge] BANDPASS 1 PCMADC ax micas ) FILTER REGISTER MIG1+ BANDPASS 7 RECEIVE MIC3+ VS & TE eS FILTER PCM DAC RECISTER r OF VFr- O- -30dB. 4 2dB STEP TONE, RING EN VFr+ ~, & DTMF co RTE GENER. CONTROL INTERFACE cl 5 = & FILTER -WIRE os VLr- ei] TONE AMP CGCLK a] fg ae8 LOOK GENERATOR MOLK VLre tf & SYNCHRONIZER FS EXTA OUTPUT. INTERFACE LATCH Lo d SIDETCNE AMP a BUZZER 12 > ST BSB se | DRIVER / =| =| =| LEVEL ADJUST ~ ~ is (PWM) Des Tar GNDP GNDA GND CCGA VCC CCP 2/29 SGS-THOMSON ky MICROELECTRONICS$ST5090 PIN FUNCTIONS (S028) Pin | Name Description 1 N.C. Not Connected. 2 Vecca | Positive power supply input for the analog section. +5V +10% of 3.3V 110% selectable. Voc and Vcca must be directly connected together. 3 Veccp | Positive power supply input for the power section. 5V +10% or 3.3V +10% selectable Vccp and Vcc must be connected together. 4 N.C. Not Connected. 5,6 Vers, Ver_| Receive analog earpiece amplifier complementary outputs. These outputs can drive directly earpiece transductor. The signal at this output can be the sum of: - Receive Speech signal from Dr, - Internal Tone Generator, - Sidetone signal. 7,8 Vir, Vir-| Receive analog extra amplifier complementary outputs. The signal at these outputs can be the sum of: - Receive Speech signal from Dr, - Internal Tone generator, - Sidetone signal. 9 GNDP | Power ground. Vr and VL, driver are referenced to this pin. GNDP and GND must be connected together close to the device. 10 Dr Receive data input: Data is shifted in during the assigned Received timeslots In delayed and non- delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK, while in non-delayed reverse frame synchr. mode voice data byte is shifted in at the MCLK frequency on the rising edges of MCLK. 11 CCLK | Control Clock input: This clock shifts serial control information into Cl and out from CO when the CS- inputis low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 12 CS- | Chip Select input: When this pin is low, control information is written into and out from the ST5090 via Cl and CO pins. 13 Cl Control data Input: Serial Control information is shifted into the ST5090 on this pin when CS- is low on the rising edges of CCLK. 14 BZ Pulse width modulated buzzer driver output. 15 Vcc Positive power supply input for the digital section. +5V +10% or 3.3V+10% selectable. 16 co Control data Output: Serial contrel/status information is shifted out from the ST5090 on this pin when CS- is low on the falling edges of CCLK. 17 Dx Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots. Elsewhere Dx output is in the high impedance state. In delayed and non-delayed normal frame synchr. modes, voice data byte is shifted out from TRISTATE output Dx at the MCLK on the rising edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted out on the falling edge of MCLK. 18 GND_| Ground: All digital signals are referenced to this pin. 19 FS Frame Sync input: This signal is a 8kKHz clock which defines the start of the transmit and receive frames. Any ofthree formats may be used forthis signal: non delayed normal mode, delayed mode, and non delayed reverse made. 20 MCLK | Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CRO. MCLK is used also to shift-in and out data. 21 LO A logic 1 written into DO (CR1) appears at LO pinas a logic 0 A logic 0 written into DO (CR1) appears at LO pin as a logic 1. 22 MIC2- | Second negative high impedance input to transmit pre-amplifier for microphone connection. 23 MIC2+ | Second Positive high impedance input to transmit pre-amplifier for microphone connection. 24 MIC1- | Negative high impedance input to transmit pre-amplifier for microphone connection. 25 MICG1+ | Positive high impedance input to transmit pre-amplifier for microphone connection. 26 GNDA | Analog Ground: All analog signals are referenced to this pin. GND and GNDA must be connected together close to the device. 27 MIC3-_| Third negative high impedance output to transmit preamplitier for microphone connection. 28 MIG3+ | Third positive high impedance output to transmit preamplifier for microphone connection. {7 SGS-THOMSON 3/28 'T7 isicroeLeciRoNicsST5090 PIN FUNCTIONS (TQFP44) Pin | Name Description j NLC. Not Connected. 2,3 Vers, VFr_| Receive anakbg earpiece amplifier complementary outputs. These outputs can drive directly earpiece transductor. The signal at this cutout can be the summ of: - Receive Speech signal from Dr, - Internal Tone Generator, - Sidetone signal. 4 N.C. Not Connected. 5,6 Vis, Vir_-]| Receive analg extra amplifier complementary outputs. The signal at these outputs can be the sum of: - Receive Speech signal from DR, - Internal Tone generator, - Sidetone signal. Z NLC. Not Connected. 8 GNDP | Power ground. Vr, and Vir driver are referenced to this pin. GNDP and GND must be connected together close to the device. 9 N.C. Not Connected. 10 Dr Receive data input: Data is shifted in during the assigned Received time slots In delayed and non- delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK, while in non-delayed reverse frame sinchr. mode voice data byte is shifted in at the MCLK frequency on the rising edges of MCLK. 11,12,13| NG. Not Connected. 14 CCLK | Control Clock input: This clock shifts serial control information into Cl and out from CO when the C&- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 15 CS- | Chip Select input: When this pin is low, control information is written into and out from the ST5090 via Cl and CO pins. 16 Cl Control data Input: Serial Control information is shifted into the ST5090 on this pin when C&- is low on the rising edges of CCLK. 17 BZ Pulse width modulated buzzer driver output. 18 Veco Positive power supply input for the digital section. +5V+10% or 3.3V +10% selectable. 19 co Control data Output: Serial control/status information is shifted out fromthe ST5090 on this pin when CS- is low on the falling edges of CCLK. 20 Dx Transmit Data ouput: Data is shifted outon this pin during the assigned transmit time slots. Elsewhere Dx output is inthe high impendance state. In delayed and non-delayed normal frame synchr. modes, voice data byte is shifted outfrom TRISTATE output Dx atthe MCLK onthe rising edge of MCLK, while innondelayed reverse frame synchr mode voice data byte is shifted out onthe falling edae of MCLK. 21 GND_| Ground: All digital signals are referenced to this pin. 22.23 NLC. Not Connected. 24 FS Frame Sync input: This signal is a 8kKHz clock which defines the start of the transmit and receive frames. Either of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. 25 MCLK | Master Clock Input: This signal is used bythe switched capacitor filters and the encoder/decoder sequencing logic. Values must be 512 KHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CRO. MCLK is used also to shift-in and out data. 26 LO A logic 1 written into DO (CR1) appears at LO pinas a logic 0 A logic 0 written into DO (CR1) appears at LO pin as a logic 1. 27,28.29| NC. Not Connected. 30 MIC2-_ | Second negative high impedance input to transmit preamplifier for microphone connection. 31 MIG2+__| Second Positive high impedance input to transmit pre-amplitier for microphone connection. 32 N.C. Not Connected. 33 MIC1-_ | Negative high impedance input to transmit pre-amplifier for microphone connection, 34 MIC1+4 | Positive high impedance input to transmit pre-amplifier for microphone connection. 35 N.C. Not Connected. 36 GNDA | Analog Ground: Allanalog signals are referenced to this pin. GND and GNDA must be connected together close to the device. 37 MIC3-_ | Third negative high impedance output to transmit preamplifier for microphone connection. 38 MICG3+4 | Third positive high impedance output to transmit preamplifier for microphone connection. 39,40 NLC. Not Connected. 41 Veca_ | Positive power supply input for the analog section. +5V +10% of 3.3V 110% selectable. Voc and Voca must be directly connected together. 42 Vocp | Positive power supply input for the power section. 5V +10% orf 3.3V +10% selectable Vocp and Vcc must be connected together. 43.44 N.C. Not Connected. 4/29 A397 Sicsostsomanes$ST5090 FUNCTIONAL DESCRIPTION IDEVICE OPERATION L1 Power on initialization: When power is first applied, power on reset cir- cuitry initializes ST5090 and puts it into the power down state. Gain Control Registers for the various programmable gain amplifiers and programmable switches are initialized as indicated in the Gontrol Register description section. All CODEC functions are disabled. The desired selection for all programmable func- tions may be intialized prior to a power up com- mand using the MIGROWIRE control channel. 12 Power up/down control: Following power-on initialization, power up and power down control may be accomplished by writ- ing any of the control instructions listed in Table 1 into ST5090 with P bit set to 0 tor power up or 1 for power down. Normally, it is recommended that all programma- ble functions be initially programmed while the device is powered down. Power state control can then be included with the last programming in- struction or in a separate single byte instruction. Any of the programmable registers may also be moditied while ST5090 is powered up or down by setting "P bit as indicated. When power up or down control is entered as a single byte instruc- tion, bit 1 must be set toa O. When a power up command is given, all de-acti- vated circuits are activated, but output Dx will re- main in the high impedance state until the second Fs pulse after power up. 13 Power down state: Following a pericd of activity, power down state may be reentered by writing a power down in- struction. Control Registers remain in their current state and can be changed by MICROWIRE control inter- face. In addition to the power down instruction, detec- tion of loss MCLK (no transition detected) auto- matically enters the device in "reset power down state with Dx outputin the high impedance state. 14 Transmit section: Transmit analog interface is designed in two stages to enable gains up to 42.5 dB to be real- ized. Stage 1 is a low noise differential amplifier providing 20 dB gain. A microphone may be ca- pacitevely connected to MIC1+, MIC1- inputs, while the MIG2+ MIG2- and MIC3+ MIC3- inputs may be used to capacitively connect a second mi- crophone or a third microphone respectively or an auxiliary audio circuit. MIG1 or MIG2 or MC3 or transmit mute is selected with bits 6 and 7 of reg- ister GR4. In the mute case, the analog transmit signal is grounded and the sidetone path is also disabled. Following the first stage is a programmable gain amplifier which provides from 0 to 22.5 dB of ad- ditional gain in 1.5dB step. The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the internal O dBm voltage is 0.49 Vrms (overload level is 0.7 Vrms). Second stage amplifier gain can be pro- grammed with bits 4 to 7 of CR5. An active RC pretilter then precedes the 8th order band pass switched capacitor filter. A/D converter can be either a 14-bit linear (bit GCM =0 in register CRO) or can have a compressing characteristics (bit CM =1 in register CRO) according to CCITT A or MU255 ceding laws. A precision on chip volt- age reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an in- ternal autozero circuit. Each encode cycle begins immediatly at the be- ginning of the selected Transmittime slot. The to- tal signal delay referenced to the start of the time slot is approximatively 195 js (due to the transmit filter) plus 125 ws (due to encoding delay), which totals 320 pts. Voice data is shifted out on Dx dur- ing the selected time slot on the transmit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de- layed reverse mode. 15 Receive section: Voice Data is shifted into the decoders Receive voice data Register via the Dr pin during the se- lected time slot on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MGLK in non-delayed reverse mode. The decoder consists of either a 14-bit linear or an expanding DAC with A or MU255 law decod- ing characteristic. Following the Decoder is a 3400 Hz 8th order band-pass switched capacitor filter with integral Sin X/X correction for the 8 KHz sample and hold. 0 cdBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A tran- scient suppressing circuitry ensure interference noise suppression at power up. The analog speech signal output can be routed either to earpiece (VFR, VFR- outputs) or to an ex- tra analog output (Vir+, Vir- outputs) by setting bits OE and SE (1 and 0 of GR4). Total signal delay is approximatively 190 us (filter plus decoding delay) plus 62.5 us (1/2 frame) which gives approximatively 252 us. Differential outputs Vrrs,VerR- are intended to di- rectly drive an earpiece. Preceding the outputs is a programmable attenuation amplifier, which must Ey SGS-THOMSON 5/28 MICROELECTRONICSST5090 be set by writing to bits 4 to 7 in register CR6. At- tenuations in the range 0 to -30 cB relative to the maximum level in 2 dB step can be programmed. The input of this programmable amplitier is the sum of several signals which can be selected by writing to register CR4_: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5 Vers and Ver- outputs are capable of driving output power level up to 66mW into differentially con- nected load impedance of 30 . Piezoceramic re- ceivers up to 50nF can also be driven. Differential outputs Vir+,Vir- are intended to di- rectly drive an extra output. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range 0 to -30 dB rela- tive to the maximum level in 2.0 dB step can be programmed. The input of this programmable am- plifier can be the sum of signals which can be se- lected by writing to register CR4: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5. Vir+ and Vir. outputs are capable of driving output power level up to 66mW into ditlerentially con- nected load impedance of 30 9. Piezoceramic re- ceivers up to 50nF can also be driven. BUZZER OUTPUT: Single ended output BZ is intended te drive a buzzer, via an external BUT, with a squarewave pulse width modulated (PWM)} signal the fre- quency of which is stored into register CR8. For some applications it is also possible to ampli- tude modulate this PWM signal with a square- wave signal having a frequency stored in register CRY. Maximum load for BZ is 5kQ and 50pF. 16 Digital Interface (Fig. 1) Fs Frame Sync input determines the beginning of frame. It may have any duration trem a single cy- cle of MCLK to a squarewave. Three different re- lationships may be established between the Frame Sync input and the first time slot of frame by setting bits BDM1 and DMO in register CR1. 6/29 yy SGs:THOMsoN Non delayed data mode is similar to long frame timing on ST5080A: first time slot begins nomi- nally coincident with the rising edge of Fs. Alter- native is to use delayed data mode, which is simi- lar to short frame sync timing on ST5080A, in which Fs input must be high at least a half cycle of MCLK earlier the frame beginning. In the case of companded code only (bit GM = 1 in register CRO) a time slot assignment circuit on chip may be used with all timing modes, allowing connec- tion to one of the two B1 and B2 voice data chan- nels. Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles follow- ing immediately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles follow- ing immediately time slot B1. In Format 2, time slot B1 is identical to Format 1. Time slot B2 appears two bit slots after time slot Bi. This two bits space is left available for inser- tion of the D channel data. Data format is selected by bit FF (2) in register GRO. Time slot B1 or B2 is selected by bit TS (1) in Control Register CR1. Bit EN (2) in contrel register GR1 enables or dis- ables the voice data transfer on Dx and Dr as appropriate. During the assigned time slot, Dx output shifts data out from the voice data register on the rising edges of MCLK in the case of de- layed and non-delayed normal modes or on the falling edges of MCLK in the case of non-delayed reverse mode. Serial voice data is shitted into Dr input during the same time slot on the falling edges of MCLK in the case of delayed and non- delayed normal modes or on the rising edges of MCLK in the case of non-delayed reverse moce. Dx is in the high impedance Tristate condition when in the non selected time slots. 17 Control Interface: Control information or data is written inte or read- back from ST5090 via the serial control port con- sisting of control clack CCLK, serial data input Cl and output CO, and Chip Select input, CS-. All contral instructions require 2 bytes as listed in Ta- ble 1, with the exception of a single byte power- up/down command. To shift control data into ST5090, CCLK must be pulsed high 8 times while CS- is low. Data on Cl input is shifted into the serial input register on the rising edge of each GCLK pulse. After all data is shitted in, the content of the input shift register is decoded, and may indicate that a 2nd byte of contrel data will follow. This second byte may either be defined by a second byte-wide CS- pulse or may follow the first contiguously, i.e. it is not mandatory for CS- to return high in between the first and second control bytes. At the end of the 2nd control byte, data is loaded into the ap- MICROELECTRONICS$ST5090 Figure 1: Digital! Interface Format (*) FORMAT 1 Fs (delayed timing) MCLK (non delayed timing) MCLK (non delayed timing) BR | Bi | B2 | x | x x DX _ Bi | B2 | J FORMAT 2 Fe (delayed timing) BR | B1 B2 DeaTLors (*) Significant Only For Companded C cde. propriate programmable register. CS- must return high at the end of the 2nd byte. To read-back status information from ST5090, the first byte of the appropriate instruction is strobed in during the first CS- pulse, as defined in Table 1. GS- must be set low for a further 8 CCGLK cy- cles, during which data is shifted out of the CO pin on the falling edges of GCLK. When G&- is high, CO pin is in the high imped- ance Tri-state, enabling CO pins of several de- vices to be multiplexed together. Thus, to summarise, 2 byte READ and WRITE in- structions may use either two 8-bit wide CS- pulses or a single 16 bit wide CS- pulse. 18 Control channel access to PCM interface: It is possible to access the B channel previously iy SGS-THOMSON MICROELECTRONICS selected in Register CR1 in the case of com- panded code only. A byte written into Control Register CR3 will be automatically transmitted from Dx output in the following frame in place of the transmit PCM data. A byte written into Control Register CR2 will be automatically sent through the receive path to the Receive amplitiers. In order to implement a continuous data flow from the Control MICROWIRE interface to a B chan- nel, it is necessary to send the control byte on each PCM frame. A current byte received on Dr input can be read in the register GR2. In order to implement a con- tinuous data flow from a B channel to MI- CROWIRE interface, it is necessary to read regis- ter CR2 at each PCM frame. 7/29ST5090 TI PROGRAMMABLE FUNCTIONS For both formats of Digital Interface, programma- ble functions are configured by writing to a num- verification. Byte one is always register address, while byte two is Data. Table 1 lists the register set and their respective ber of registers using a 2-byte write cycle. adresses. Most of these registers can also be read-back for Table 1: Programmable Register Intructions Function Address byte Data byte 4 Single byte Power up/down none Write CRO see CRO TABLE 2 Read-back CRO see CRO Write CR1 see CR1 TABLE 3 Read-back CR1 see CRI Write Data to receive path see CR2 TABLE 4 Read data from Dr see CR2 Write Data to Dy see CR3 TABLE 5 71|/6 1,5 3/2 1 0 P|X|xX]xX |X ]xX]oO} xX P|O/0]}/0/9;]0]1 |X P|o;/o]}/0/9;}1]1 |X P|O/O0}0]/1;])0]1|xX P|o{/o]}o;{;1]}1]1 |x P|O/O/}1/9]0]1 |x P|}|o/;/o;}1]/o0;1]1 |X P|}/o;/o]}1]/1/])0]1 |X Write CR4 P|o{i1]0{]60]01]1 | X |seeCR4 TABLES Read-back CR4 P{|o{]/i1 {o]0 1,1 1 | X [see CR4 Write CRS P|o]i1]o0j]1]01]1 | X |see CRS TABLE 7 Read-back CR5S P|o]|4 Oo] 1 1 1 | X |see CRS Write CR6 P|oj{i1{]1{0}]01]1 | X |see CRG TABLE 8 Read-back CR6 P|o]|4 1}, 0] 14 1 | X |see CRE Write CR7 P|oj]1]1 {140 %471=| X |see CR? TABLE 9 Read-back CR7 P|o|4 1]14 1 1 | X |see CR7 Write CR8 P|1 {0 }]0{6]0]1 | X |see CR8 TABLE 10 Read-back CR8& P{|i{/o ;];o]0]1 1 | X |see CR8 Write CR9 P|1{]0O}0O]1]01]1 | X |see CRO TABLE 11 Read-back CR9 P {4 o/| 0] 1 1 1 | X |see CRS Write CR10 P|1{0O}1{60}]01]1 | X {see CR10 TABLE 12 Read-back CR10 P| Oo; i ]o]1 1 | X {see CR1O Write CR11 P|1{]oO} 1 {1 )041 =| X {see CR11 TABLE 13 Read-back CR11 P| i{o}]i1{14)141 =| X [see CRI11 Write Test Register CR14 P|1]{i4]1]0;}]07 1 =| X {reserved bit 7 of the address byte and data byte is always the first bit clocked into or out from: Cl and CO pins when MICROWIRE serial NOTE 1: port is enabled. X =raserved: writed NOTE 2: *P* bit is Power up/down Control bit. P = 1 Means Power Down. Bit 1 indicates, if set, the presence of a sacond byte. NOTE 3: Bit 2 is write/read selectbit. NOTE 4: Registers C R12, CR13, and CR15 are not accessible. 8/29 A397 Sicsostsomanes$ST5090 Table 2: Control Register CRO Functions 4 CM MA FF B7 DL Function -=- 900 6 FO 0 1 0 1 MCLK = 512 kHz MCLK = 1.536 MHz MCLK = 2.048 MHz MCLK = 2.560 MHz Linear code Companded code -=--43o0C -+o+-o Linear Code Companded Code * 2-complement sign and magnitude 2-complement 1-complement MU-law: CCITT D3-D4 * MlU-law: Bare Coding A-law including even bit inversion A-law: Bare Coding a4 B1 and B2 consecutive B1 and B2 separated * a & bits time-slot 7 bits time-slot (1 ( * (1 (i bee ee fe as Normal operation Digital Loop-back Table 3: Control Register GR1 Functions state at power on initialization significant in companced mode only 7 4 DN1 DMO BO MR MX EN TS SV Function --30 -0a = delayed data timing non-delayed normal data timing non-delayed reverse data timing LO latch set to 1 LO latch set to 0 Dr connected to rec. path CR2 connected to rec. path a4 Trans path connected to Dx CR8 connected to Dx voice data transfer disable voice data transfer enable as B1 channel selected Be channel selected a4 3.3V power supply 5.0V power supply state at power on initialization significant in companded mode only iy SGS-THOMSON 9/29 MICROELECTRONICSST5090 Table 4: Control Register CR2 Functions 7 6 5 4 3 2 1 0 Function d7 | d | d5 | d4 | d3 | d2 | di do msb Isb | Data sent to Receive path or Data received from Dr input (1) (1) Significant in companded mode only. Table 5: Control Registers GR3 Functions 7 6 5 4 3 2 1 0 Function d7 | d&6 | d5 | d4 | d3 | d2/ di do msb Isb | Dy data transmitted (1) (1) Significant in companded mode only Table 6: Control Register CR4 Functions 7 6 5 4 3 2 1 0 Function VS | TE | SI | OE1 | OE2| RATE SE 0 0 Transmit input muted 0 1 MIC1 Selected 1 0 MIC2 Selected 1 1 MIC3 Selected 0 Internal sidetone disabled 1 Internal sidetone enabled 0 0 Receive output muted 0 1 VFr output selected 1 0 VLr output selected 1 1 NOT ALLOWED 0 Ring / Tone to Ver or Vir disabled 1 Ring/ Tone to Vr, or VL, enabled x 0 | Receive Signal to Ver or Vir disabled 1 | Receive Signal to Vrr or VLr enabled * state at power on initialization x: rasarved: write 0 10/29 SGS-THOMSON ky MICROELECTRONICSTable 7: Control Register CR5 Functions $ST5090 7|/6/|5 [4 3/21] 0 Function Transmit amplifier Sidetone amplifier 0 0 0 0 0 dB gain * 0 0 0 1 1.5 dB gain - - - - in 1.5 dB step 1 1 1 1 22.5 dB gain 0 0 0 0 |-12.5dB gain * 0 0 0 1 |-13.5 dB gain - - - - in 1 dB step 1 1 1 1 |-27.5 dB gain * state at power on initialization Table 8: Control Register CR6 Functions 7/6 {5/4 1/3 /]2 {410 i ifi Function Earpiece ampifier - [EARA] Extra amplifier [EXTA] 0 0 0 0 0 dB gain * 0 0 0 1 -2 dB gain - - - - in2 dB step 1 1 1 1 -30 dB gain 0 0 0 0 |OdBgain * 0 0 0 1 |-2dB gain - - - - in 2 dB step 1 1 1 1 |-30dB gain *: state at power on initialization Table 9: Control Register CR7 Functions 7/6[5 1/4 {3 ]2{1 | 0 Function Tone gain F1 F2 | SN | DE Attenuation #1 Vpp f2 Von 0 0 0 0 OdB * 1.6(2) 1.26(2) 0 0 0 1 -3dB 0 0 1 0 -6dB 0 0) 1 1 -9dB 0 1 0 0 -12 dB 0 1 0 1 -15 dB 0 1 1 0 -18 dB 0 1 1 1 -21 dB 1 x x 0 -24 dB 1 x x 1 -27 dB 0.066 0.053 0 0 f1 andf2 muted * 0 1 f2 selected 1 0 f1 selected 1 1 f1 and f2 in summed mode 0 Squarewave signal selected * 1 Sinewave signal selected 0 |Normal operation * 1 |Tone /Ring Generator connected to Transmit path *: state at power on initialization (2): value provided iff or {2 is selacied alone. if 11 and f2 are selectedin the summed meda, f1=0.89 Vpp while f2=0.7 Vop. Xx reserved: write 0 iy 11/29 MICROELECTRONICSST5090 Table 10: Control Register CR8 Functions 7 6 5 4 3 2 1 0 Function f17 | f16 | f15 | f14 | f13 | f12 | f11 | 10 msb Isb | Binary equivalent of the decimal number used to calculate f1 Table 11: Control Register GR9 Functions 7 6 5 4 3 2 1 0 . Function f27 | f26 | f25 | f24 | f23 | f22 | f21 | f20 msb Isb | Binary equivalent of the decimal number used to calculate f2 Table 12: Control Register CR10 Functions 7 6 5 4 3 2 1 QO Function DFT | HFT Xx x x Xx X Xx 0 0 | (*) Standard Frequency Tone Range 0 1 | Halved Frequency Tone Range 1 0 |Doubled Frequency Tone Range 1 1 | Forbidden (*) Default values inserted into the Register at Power On. X reserved, write 0. Table 13: Control Register CR11 Functions 7 6 5 4 3 2 1 0 Function BE | BI | B25 | B24 | BZ3 | BZ2 | B21 | BZO 0 Buzzer output disabled (set to 0) * 1 Buzzer output enabled 0 Duty Cycle is intended as the relative width of logic 1 * 1 Duty cycle is intended as the relative width of logic 0 msb Isb | Binary equivalent of the decimal number used to calculate the duty cycle. * state at power on initialization Vers (7 SGS-THOMSON 77 wicnoeuscrromes$ST5090 CONTROL REGISTER CRO First byte of a READ or a WRITE instruction to Control Register GRO is as shown in TABLE 1. Second byte is as shown in TABLE 2. Master Clock Frequency Selection A master clock must be provided to ST5090 for operation of filter and coding/decoding functions. MCLK frequency can be either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz. Bit Fi (7) and FO (6) must be set during initializa- tion to select the correct internal divider. Default value is 512 KHz. Any clock different from the default one must be selected prior a Power-Up instruction. Coding Law Selection Bits MA (4) and IA (3) permit selection of Mu-255 law or A law coding with or without even bit inver- sion if companded code (bit GM = 1) is selected. Bits MA({4) and IA(3) permit selection of 2-com- plement, 1-complement or sign and magnitude it linear code (bit CM = 0) is selected. Coding Selection Bit CM (5) permits selection either of linear coding (14-bit) or companded coding (8-bit}. Default value is linear coding. Digital Interface format (1) Bit FF(2) = 0 selects digital interface in Format 1 where B1 and B2 channel are consecutive. FF=1 selects Format 2 where B1 and B2 channel are separated by two bits. (See digital interface for- mat section.) 56+8 selection (1) Bit 'B7 (1) selects capability for ST5090 to take into account only the seven most significant bits of the PCM data byte selected. When 'B7 is set, the LSB bit on Dr is ignored and LSB bit on Dx is high impedance. This function al- lows connection of an external "in band data generator directly connected on the Digital Inter- face. (1) Significant in companded mode only Digital loopback Digital loopback mode is entered by setting DL bit(0) equal 1. In Digital Loopback mode, data written into Re- ceive PCM Data Register from the selected re- ceived time-slot is read-back from that Register in the selected transmit time-slot on Dx. No PGM decoding or encoding takes place in this mode. Transmit and Receive amplifier stages are muted. CONTROL REGISTER CR1 First byte of a READ or a WRITE instruction to Control Register CR1 is as shown in TABLE 1. Second byte is as shown in TABLE 3. Digital Interface Timing Bit DM1(7) = 0 selects digital interface in delayed timing mode, while DM1 = 1 and DMO =0 selects nen-delayed normal data timing mode, and DM1 = 1 and DMO = 1 selects non-delayed reverse data timing mode. Default is delayed data timing. Latch output control Bit DO controls directly logical status of latch out- put LO: ie, a ZERO written in bit DO puts the output LO at logical 1, while a ONE written in bit DO sets the output LO to zero. Microwire access to B channel on receive path (1) Bit MR (4) selects access from MICROWIRE Register CR2 to Receive path. When bit MR is set high, cata written to register GR2 is decoded each frame, sent to the receive path and cata in- put at Dr is ignored. In the other direction, current PCM data input re- ceived at Dr can be read from register CR2 each frame. Microwire access to B channel on transmit path (1) Bit MX (3) selects access from MICROWIRE write only Register GR3 to Dx output. When bit MX is set high, data written to CR3 is output at Dy every frame and the output of PGM encoder is ignored. Mu 255 law True A law even bit A law without even bit inversion inversion msb Isb | msb Isb | msb Isb Vin = + fullscale 1/;0/0;/0/G0;/O0;0;0;7/0;/1;0;17)/0}/171} 0); 7}, 7] 717) 1]) 7] 7] 7141 Vin =0V 1y)1 > ayy ryt yr ya papa poy a; oyA yay 7A; iy oy ay; ay;oyayajyoa ~ O11; i {1771p i prt yr yoy it p;oy; 7} aoyt yoy; 1t;oy;o;}o;o;o;}a);o)}o Vin = - full scale O1;O;O;/0;/0;/0]7/0)/0/0;/07/1)/0)/171)/0;/1)/0)/0/74]), 1) 7) 7) 7) 141 MSB is always the first PCM bit shifted in or out of: ST5090. 13/29 SGS-THOMSON hy MICROELECTRONICSST5090 Transmit/Receive enabling/disabling Bit EN (2) enables or disables voice data trans- fer on Dx and Dr pins. When cisabled, PCM data fram DR is net decoded and PGM time-slots are high impedance on Dx. Default value is disabled. B-channel selection (1) Bit TS(1} permits selection between B1 or B2 channels. Default value is B1 channel. Supply Voltage selection Bit SV (0) permits selection of the power supply ot the ST5090. Default value is 3.3V. CONTROL REGISTER CR2 (1) Data sent to receive path or data received from Dr input. Refer to bit MR{4) in Contrel Register GR1 paragraph. CONTROL REGISTER CR3 (1) Dx data transmitted. Refer to bit MX(3) in "Control Register CR1 paragraph. CONTROL REGISTER CR4 First byte of a READ or a WRITE instruction to Control Register CR4 is as shown in TABLE 1. Second byte is as shown in TABLE6. Transmit Input Selection MIC1 or MIC2 or MIG3 or transmit mute can be selected with bits 6 and 7 (Vs and TE). Transmit gain can be adjusted within a 22.5 dB range in 1.5 dB step with Register CR5. Sidetone Selection Bit SI (5) enables or disables Sidetone circuitry. When enabled, sidetone gain can be adjusted with Register (CR5). When Transmit path is dis- abled, sidetone circuit is also disabled. Output Driver Selection Bits OE1(4) and OE2(3) provide the selection among the earpiece output or the extra amplifier output or both outputs muted. OE1 = 1 and OE2 = 1 is not allowed. Ring/Tone signal selection Bit RTE (2) provide select capability to connect on-chip Ring/Tone generator either to an extra amplifier input or to earpiece amplifier input. (1) Significant in companded mode only 14/29 iy SGS-THOMSON PCM receive data selection Bits SE (0) provide select capability to connect received speech signal either to an extra amplifier input or to earpiece amplifier input. CONTROL REGISTER CRS5 First byte of a READ or a WRITE instuction to Control Register CR5 is as shown in TABLE 1. Second byte is as shown in TABLE 7. Transmit gain selection Transmit amplifier can be programmed for a gain from OcB to 22.5dB in 1.5dB step with bits 4 to 7. 0 dBmO level at the output of the transmit ampli- tier (A reference point) is 0.492 Vrms (overload voltage is 0.707 Vrms). Sidetone attenuation selection Transmit signal picked up after the switched ca- pacitor low pass filter may be fed back inte both Receive amplifiers. Attenuation of the signal at the output of the sidetone attenuator can be programmed trom 12.5dB to -27.5dB relative to reference paint A in 1 dB step with bits 0 to 3. CONTROL REGISTER CR6 First byte of a READ or a WRITE instruction to Control Register GR6 is as shown in TABLE 1. Second byte is as shown in TABLE 8. Earpiece amplifier gain selection: Earpiece Receive gain can be programmed in 2 dB step from O cB to -30 dB relative to the maxi- mum with bits 4 to 7. 0 dBmO voltage at the output of the amplifier on pins Ver+ and Verr- is then 1.965 Vrms when 0dB gain is selected down to 61.85 Vrms when -30dB gain is selected. Extra amplifier gain selection: Extra Receive amplifier gain can be programmed in 2 dB step from 0 dB to -30 GB relative to the maximum with bits 0 te 3. 0 dBmO voltage on the output of the amplifier on pins Vire+ and Vir- 1.965 Vrms when 0 dB gain is selected down to 61.85 mVrms when -30 dB gain is selected. CONTROL REGISTER CR7: First byte of a READ or a WRITE instruction to Control Register CR7 is as shown in TABLE 1. Second byte is as shown in TABLE 9. MICROELECTRONICS$ST5090 Tone/Ring amplifier gain selection Output level of Ring/Tone generator, before at- tenuation by programmable attenuator is 1.6 Vpk- pk when {1 generator is selected alone or summed with the f2 generator and 1.26 Vpk-pk when {2 generator is selected alone. Selected output level can be attenuated down to -27 dB by programmable attenutator by setting bits 4 to 7. Frequency mode selection Bits Fi (3) and 'F2 (2) permit selection of f1 and/or f2 frequency generator according to TA- BLE g. When f1 (or f2) is selected, output of the Ring/Tone is a squarewave (or a sinewave) signal at the frequency selected in the CR8 (or CR9) Register. When fi and f? are selected in summed mode, output of the Ring/Tene generator is a_ signal where f1 and f2 frequency are summed. In order to meet DTMF specifications, 12 output level is attenuated by 2cB relative to the f1 output level. Frequency temporization must be controlled by the microcontroller. Waveform selection Bit SN (1) selects waveform of the output of the Ring/Tone generator. Sinewave or squarewave signal can be selected. DTMF selection Bit DE (0) permits connection of Ring/Tone/DTMF generator on the Transmit Data path instead of the Transmit Amplitier output. Earpiece or extra receive output feed-back may be provided by sidetone circuitry by setting bit SI or directly by setting bit RTE in Register CR4. Loudspeaker feed-back may be provided directly by setting bit RTLin Register CR4. CONTROL REGISTERS CR8 AND CR9 First byte of a READ or a WRITE instruction to Control Register CR8 or GRY is as shown in TA- BLE 1. Second byte is respectively as shown in TABLE 10 and 11. If "standard frequency tone range is selected, Tone or Ring signal frequency value is defined by the formula: f1 = CR8/0.128 Hz and f2 = CR9/0.128 Hz where GR8 and GR9 are decimal equivalents of the binary values of the CR8 and GR9 registers hy SGS-THOMSON respectively. Thus, any frequency between 7.8 Hz and 1992 Hz may be selected in 7.8 Hz step. If "halved frequency tone rangeis selected, Tone or Ring signal frequency value is defined by the formula: t1 =CR8/ 0.256 Hz and t2 =CR9/ 0.256 Hz This any frequency between 3.9Hz and 996Hz may be selected in 3.9Hz step. If doubled frequency tone rangeis selected, Tone or Ring signal frequency value is defined by the formula: f1 =CR8/ 0.064 Hz and f2 =CR9/ 0.064 Hz Thus any frequency between 15.6Hz and 3984Hz may be selected in 15.6Hz step. TABLE 12 gives examples for the main frequen- cies usual for Tone or Ring generation. CONTROL REGISTER CR10 Bit DFT(1) and HFT{0) permits the selection among "standard frequency tone range (i.e. from 7.8Hz to 1992Hz in 7.8Hz step), "halved fre- quency tone range (i.e. from 3.9Hz to 996Hz in 3.9Hz step), and doubled frequency tone range (i.e. from 15.6Hz to 3984Hz in 15.6Hz step) ac- cording to the values described in CONTROL REGISTER CR8 and CR9. CONTROL REGISTER CR11 Bit BE(7) permits connection of a f1 squarewave PWM Ring signal, amplitude modulated or not by a 12 squarewave signal, to buzzer driver output BZ. Bits BZ5 to BZO define the duty cycle of the PWM squarewave, according to the following for- mula: Duty Cycle = GR11(5 = 0) x 0.78125% where GR11(5 = 0) is the decimal equivalent of the binary value BZ5+ BZ0. When BE = 1, if bits F1 = 1 and F2 = 0 in regis- ter CR7, a f1 PWM ring signal is present at the buzzer output, while if bits Fi = 1 and F2 = 1 in register CR? the f1 PWM ring signal is also am- plitude modulated by a f2 squarewave tre- quency. Bit BI (6) allows to chose the logic level at which the duty cycle is reterred: BI = 0 means that duty cycle is intended as the relative width of the logici, while BI = 1 means that duty cycle is intended as the relative width of the logic O. When BE = 0 (or during power down) BZ = 0 if Bl=OorBZ=1 if Bl=1. 15/29 MICROELECTRONICSST5090 Table 12: Examples of Usual Frequency Selection (Standard frequency tone range) Description f1 value (decimal) | Theoretic value (Hz) | Typical value (Hz) Error % Tone 250 Hz 32 250 250 .00 Tone 330 Hz 42 330 328.2 .56 Tone 425 Hz 54 425 421.9 .73 Tone 440 Hz 56 440 437.5 .56 Tone 800 Hz 102 800 796.5 .39 Tone 1330 Hz 170 1330 1328.1 .14 DTMF 697 Hz 8&9 697 695.3 .24 DTMF 770 Hz 99 770 773.4 +.44 DTMF 852 Hz 109 852 851.6 .05 DTMF 941 Hz 120 941 937.5 .37 DTMF 1209 Hz 155 1209 1210.9 +.16 DTMF 1336 Hz 171 1336 1335.9 .01 DTMF 1477 Hz 189 1477 1476.6 00 DTMF 1633 Hz 209 1633 1632.8 .O0 SOL 50 392 390.6 -.30 LA 56 440 437.5 .56 Sl 63 494 492.2 .34 DO 67 523.25 523.5 +.04 RE 75 587.33 586.0 .23 MI flat 80 622.25 625.0 +.45 Ml 84 659.25 656.3 45 FA 89 698.5 695.3 .45 FA sharp 95 740 742.2 +.30 SOL 100 784 781.3 .34 SOL sharp 106 830.6 828.2 .29 LA 113 880 882.9 +.33 Sl 126 987.8 984.4 .34 DO 134 1046.5 1046.9 +.04 RE 150 1174.66 1171.9 .283 Ml 169 1318.5 1320.4 +.14 16/28 Ky 8Gs:THomson MICROELECTRONICSTIMING DIAGRAM Non Delayed Data Timing Mode (Normal) (*) $ST5090 1AM FM WMH oe he Hi - el uy Wl ( | it i m MOLK, [XG 1 ? 3 4 i fs 6 7 16 17 i i } { I fod i 1 acim i i i i M i iste tHMF coed tl pe oro Pe Po y rr Yt : FS ia h ! : Ai "W~-----+4 nn p~--- | | I ! i gl ere i HiDMz tOMD ij t bgt he Ht | Dx _4/ 1 rs] x 4 x 3 y a yy 7 16 : i 1SDM | tHMD . XENI YE Delayed Data Timing Mode (*) 1AM iFM WMH int eld bial il il t i | ! Ny MCLK ow 44 2 3 eX fs\_ fe} {7 16 17 wt el i ii id bi i i i WML {SFM ItHMF! | | eer | i | ' j ; | i | FS | i | | Ni ! ! i ! \{OMZ \ tOMD - : j>4 i { ee i i Dx ____f 1 2 'g 4 $ & ? 16 { J i : ; 1 i {SDM | 1HMD $$ 1 1 DR x 1 x 2 xX 3 K 4 Xx 5 X & X 7 x 16 x J 1 (*) In the case of companded code the timing is applied to 8 bitsinstead of 16 bits (see STS080Adata sheet) hy SGS-THOMSON 17/29 MICROELECTRONICSST5090 TIMING DIAGRAM (continued) Non Delayed Reverse Data Timing Mode (*) tWwiMIM iRM {FM a o tWwML, (*) In tha case of companded code the timing is applied to8 bitsinstead cf 16 bits. Serial Control Timing (MICROWIRE MODE) tRC tFE twCH tSDC tHeD ZoGccooonoe AQOOARS se 18/29 $GS-THOMSON ky MICROELECTRONICS$ST5090 ABSOLUTE MAXIMUM RATINGS Parameter Value Vcc to GND 7 Vo at MIC (Veco = 5.5 Veco +1 to GND -1 Current at Ver and Vir 100 Current at any digital output 50 Voltage at digital cc = 5.5V); limited at + 50mA Veco + 1to GND -1 Storage t re - 65 to+ 150 Lead Te re solde 10s + 260 TIMING SPECIFICATIONS (unless otherwise specified, Voc = 3.3V + 10%0r 5V+ 10%, Ta =30C to 85C ; typical characteristics are specified Vcc = 3.3V, Ta = 25 C; all signals are referenced to GND, see Note 5 for timing definitions) NOTICE: All timing specifications can be changed. MASTER CLOCK TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit fictk Frequency of MCLK Selection of frequency is 512 kHz programmable (see table 2) 1.536 MHz 2.048 MHz 2.560 MHz twmH Period of MCLK high Measured from Vin to Vin 80 ns two Period of MCLK low Measured from Vit to Vit 80 ns tam Rise Time of MCLK Measured from Vi_ to Vin 30 ns tem Fall Time of MCLK Measured from Vin to ViL 30 ns PCM INTERFACE TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit tHMe Hold Time MCLK low to FS low 0 ns tsem Setup Time, FS high to MCLK 30 ns low tomp Delay Time, MCLK highto data Load = 100 pf 100 ns valid tonz Delay Time, MCLK low to DX 10 100 ns disabled tprFb Delay Time, FS highto data valid) Load = 100 pf ; 100 ns Applies only if FS rises later than MCLK rising edge in Non Delayed Made only tspM Setup Time, Dr valid to MCLK 20 ns receive edge tump Hold Time, MCLK low to Dr 10 ns invalid tHMFR Hold Time MCLK High to FS low 30 ns tseMR Setup Time, FS high to MCLK High 30 ns tompR Delay Time, MCLK low to data valid| Load = 100pF 100 ns tomzR Delay Time, MCLK High to DX 10 100 ns disabled tHMDR Hold Time, MCLK High to Dr 20 ns invalid 19/29 7 SGS-THOMSON MICROELECTRONICSST5090 SERIAL CONTROL PORT TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit focLk Frequency of CCLK 2.048 MHz tweu Period of CCLK high Measured from Vin to Vin 160 ns tweL Period of CCLK low Measured from Vit to ViL 160 ns tac Rise Time of CCLK Measured from Vii to Vin 50 ns tec Fall Time of CCLK Measured from Vjyq to VIL 50 ns tucs Hold Time, CCLK high to CS low 10 ns tssc Setup Time, CSlow to CCLK high 50 ns tspc Setup Time, Cl valid to CCLK high 50 ns tucp Hold Time, CCLK high to Cl invalid 50 ns tpcpb Delay Time, CCLK low ta CO Load = 100 pF 80 ns data valid tosp Delay Time, CSow to CO data 50 ns valid topz Delay Time CS-high or 8th CCLK 10 80 ns low to CO high impedance whichever comes first tusc Hold Time, 8th CCLK high to 100 ns CS high tscs Setup Time, CS high to CCLK high 100 ns Note 5: A signal is valid if itis above Vit or below Vit and invalid ifit is between Vit and Vin. For the purpoas of this specification the following conditions apply: a) All input signal are defined as: ViL = 0.2Vocc, ViH = 0.8Vcc, tk < 10ns, tr < 10ns. b) Delay times are measured from the inputs signal valid tothe output signal valid. c) Setup times ara measured from the data input valid to the clock input invalid. d) Hold times are measured from the clock signal valid to the data input invalid. ELECTRICAL CHARACTERISTICS (unless otherwise specitied, Vec = 3.3V + 10% or 5V +10%, Ta = 30C 10 85C ; typical characteristic are specified at Vec = 3.3V, Ta =25C ; all signals are referenced to GND) DIGITAL INTERFACES Symbol Parameter Test Condition Min. Typ. Max. Unit VIL Input Low Voltage All digital inputs DC 0.3Vcc Vv AC 0.2Vcc Vv Vin Input High Voltage All digital inputs DC | 0.7Vcc Vv AC | 0.8Vcc V VoL Output Low Voltage All digital outputs, IL = 104A 0.1 Vv All digital outputs, IL = 2mA 0.4 Vv Vou Output High Voltage All digital cutouts, IL = 10A Voc-0.1 Vv Alldigital outputs, IL =2mA Voc-0.4 Vv lit Inout Low Current Any digital input, -10 10 pA GND < Vin < ViL iH Input High Current Any digital input, -10 10 pA Vin < Vin < Voc loz Output Current in High Dy and CO -10 10 pA impedance (Tri-state) A.C. TESTING INPUT, OUTPUT WAVEFORM INTPUT/GUTPUT nsvec AC Testing: inputs are driven at 0.8Vcc for , O.ANOG OWNCG a logic "1"and0.2VCC for a logic "0 . > TEST POINTS Timing measurements are made at 0.7Vcc nove asvec oavec for a logic 1and 0.3Vcc fora logic 0. 20/29 437 Sironsemones$ST5090 ANALOG INTERFACES Symbol Parameter Test Condition Min. Typ. Max. Unit Imic Input Leakage GND < Vic < Vcc -100 +100 LA Ric Inout Resistance GND < Vaic < Vcc 50 kQ River Load Resistance (*) Vers. to Ver- 30 2 C.ver Load Capacitance (*) From Vers to Ver- 50 nF Rovero Output Resistance Steady zero PCM code applied 1.0 Qo te DR; |=+1mA Vosvrro Differential offset: Alternating + zero PCM code -100 +100 mv Voltage at Vers, Ver applied to DR maximum receive gain; Ri = 1002 Rivir Load Resistance (*) Vig to Vir- 30 0 Civtr Load Capacitance (*) from Virs to Vir 50 nF Rotvro Output Resistance Steady zero PCM code applied 1 2 to DR; 14 1mA Vosviro Differential offset Voltage at Alternating + zero PCM code 100 +100 mV Vir, Vir applied to DR maximum receive gain: R_ = 500 (*) See application note for Ve, and V_, connections. POWER DISSIPATION Symbol Parameter Test Condition Min. Typ. Max. Unit leco Power down Current at 3.3V+10% | CCLK,Cl =0.1V; CS = Vec-0.1V 0.5 5 LA leco Power down Current at 5V +10% | CCLK,Cl = 0.1V;CS = Vec-0.1V 1 10 pA lect Power Up Current at 3.3 410% | View, Vir. and Ver, Vrr not 7 10 mA loaded lect Power Up Current at 5V+ 10% Vir, Vir and Vers, Ver- not 8 12 mA loaded TRANSMISSION CHARACTERISTICS (unless otherwise specified, Voc = 3.3V 4 10% or 5V 410%, TA = -30C to 85C; typical characteristics are specified at Voc = 3.3V, TA = 25C, MIC1/2/3 = odBm0, Dr = 6dBm0 PCM code, f = 1015.625 Hz; all signal are referenced to GND) AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Transmit path - Absolute levels at MIC1 / MIC2/ MIC3 Parameter Test Condition Min. Typ. Max. Unit 0 dBm level Transmit Amps connected for 49.26 mVRMs 20dB gain Overload level 70.71 mVRMs 0 dBm0 level Transmit Amps connected for 3.694 mVRMs 42 5dB gain Overload level 5.302 mVams 21/29 7 SGS-THOMSON MICROELECTRENICSST5090 TRANSMISSION CHARACTERISTICS (continued) AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Receive path - Absolute levels at Vrr (Differentially measured) Parameter Test Condition Min. Typ. Max. Unit 0 dBMO level Receive Amp programmed for 1.965 VaRMs OdB gain 0 dBMO level Receive Amp programmed for 61.85 mVams - 30dB attenuation AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Receive path - Absolute levels at Vir (Differentially measured) Parameter Test Condition Min. Typ. Max. Unit 0 dBMO level Receive Amp programmed for 1.965 Vams OdB gain 0 dBMO level Receive Amp programmed for 61.85 mVRms - 300B gain AMPLITUDE RESPONSE Transmit path Symbol Parameter Test Condition Min. Typ. Max. Unit Gxa Transmit Gain Absolute Transmit Gain Programmed for | -0.5 0.5 dB Accuracy maximum. Measure deviation of Digital PCM Gode from ideal OdBmo PCM code at Dy GxaG Transmit Gain Variation with Measure Transmit Gain over -0.5 05 dB programmed gain the range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GXA, i.e. Gaxg = G actua - G prog. > Gxa Gxat Transmit Gain Variation with Measured relative to Gxa. -0.1 0.1 dB temperature min. gain < Gy < Max. gain Gxav Transmit Gain Variation with Measured relative to Gxa -0.1 0.1 dB supply Gx = Maximum gain Gxar Transmit Gain Variation with Relative to 1015,625 Hz, frequency multitone test technique used. min. gain < Gx < Max. gain f = 60 Hz -30 dB f = 100 Hz -20 dB f = 200 Hz -6 dB f = 300 Hz -1.5 0.5 dB f = 400 Hz te 3000 Hz -0.5 05 dB f = 3400 Hz -1.5 0.0 dB f = 4000 Hz -14 dB f = 4600 Hz (*) -35 dB f = 8000 Hz (*) -47 dB Gxat Transmit Gain Variation with Sinusoidal Test method. signal level Reference Level = -10 dBm0 Vuic = -40 dBm0 to +3 dBmo -0.5 05 dB Vuic = -50 dBm to -40 dBmo -0.5 05 dB Vic =-55 dBm0 to -50 dBm0 -1.2 1.2 dB (*) The limit at frequencies between 4600Hz and 8000Hz lies on a straightline connecting the two frequencies on a linear (dB) scale versus log (Hz) scale. 22/29 437 Sironsemones$ST5090 AMPLITUDE RESPONSE Receive path Symbol Parameter Test Condition Min. Typ. Max. Unit Grae Receive Gain Absolute Accuracy | Receive gain programmed for -0.5 0.5 dB maximum Apply -6 dBmo PCM code to Dr Measure Ver. Grav Receive Gain Absolute Accuracy | Receive gain programmed for -0.5 0.5 dB maximum Apply -6 dBmo PCM code to Dr Measure Vir. GRAGE Receive Gain Variation with Measure Vrr Gain over the -0.5 0.5 dB programmed gain range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GRAE, Le. Grace =G actua- G prog. - Grae GRaAGL Receive Gain Variation with Measure VL, Gain over the -0.5 0.5 dB programmed gain range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GRAL, ie. Grace =G actual- G prog. - GRAL Grat Receive Gain Variation with Measured relative to GRA. (VLr -0.1 0.1 dB temperature and VFr) min. gain < GR < Max. gain Grav Receive Gain Variation with Measured relative to GRA. (Vir -0.1 0.1 dB Supply and Ver) Gr = Maximum Gain GRaF Receive Gain Variation with Relative to 1015,625 Hz, frequency (VLrand Ver) multitone test technique used. min. gain < Gr < Max. gain f = 60Hz -20 dB f = 100Hz -12 dB f = 200 Hz -2 dB f = 300 Hz -1.5 0.5 dB f = 400 Hz te 3000 Hz -0.5 05 dB f = 3400 Hz -1.5 0.0 dB f = 4000 Hz -14 dB Gra. & Receive Gain Variation with Sinusoidal Test Method signal level (Ver) Reference Level = -10 dBm0 Dr = -40 dBm to -3 dBmo -0.5 0.5 dB Dr = -50 dBm0 to -40 dBmd -0.5 0.5 dB Dr = -55 dBm to-50 dBmd -1.2 1.2 dB GraL L Receive Gain Variation with Sinusoidal Test Method signal level (Vi) Reference Level = 10 dBm0 Dr = -40 dBmO to -3 dBmo -0.5 05 dB Dr = -50 dBm0 to -40 dBmd -0,5 0.5 dB Dr = -55 dBm0 to -50 dBmd -1.2 1.2 dB G7 385:THomson ow MICROELECTRONICSST5090 ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol Parameter Test Condition Min. Typ. Max. Unit DXA Tx Delay, Absolute f = 1600 Hz 320 us DXR Tx Delay, Relative f = 500 - 600 Hz 290 ps f = 600 - 800 Hz 180 ls f = 800 - 1000 Hz 50 pis f= 1000 - 1600 Hz 20 pis f = 1600 - 2600 Hz 55 ps f = 2600 - 2800 Hz 80 us f = 2800 - 3000 Hz 180 Ls DRA Rx Delay, Absolute f = 1600 Hz 280 ps DRR Rx Delay, Relative f = 500 - 600 Hz 200 ps f = 600 - 800 Hz 110 ps f = 800 - 1000 Hz 50 pis f= 1000 - 1600 Hz 20 ls f= 1600 - 2600 Hz 65 pis f = 2600 - 2800 Hz 100 ps f = 2800 - 3000 Hz 220 ws NOISE Symbol Parameter Test Condition Min. Typ. Max. Unit NXP Tx Noise, P weighted (up to Vuic = OV, DE = 0 -75 -70 | dBm0p 35dB) NRP Rx Noise, A weighted Receive PCM code = Positive Zero 120 150 | pVrms (max. gain) $l=0 and RIE =0 (*) NRS Noise, Single Frequency MIC = OV, Loop-around -50 dBmo measurament fromf = 9 Hz to 100 kHz PPSRx PSRR, Tx MIG = OV, Voc = 3.3 Voc + 50 MVims; 30 60 dB f = OHz to 50KHz PPSRp PSRR, Rx PCM Code equals Positive Zero, Voc = 3.3 VDC +50 mrms, f =0Hz - 4 kHz 30 70 dB f = 4kKHz - 50 kHz 30 70 dB S08 Spurious Out-Band signal at DR input set to -6 dBm0 PCM the output code 300 - 3400 Hz Input PCM Code applied at DR 4600 Hz - 5600 Hz -40 dB 5600 Hz - 7600 Hz -50 dB 7600 Hz - 8400 Hz -50 dB (*) A Weighted 24/29 iy SGS-THOMSON MICROELECTRONICS$ST5090 DISTORTION Symbol Parameter Test Condition Min. Typ. | Max. | Unit Stpx Signal to Total Distortion Sinusoidal Test Method # (") (up to 35dB gain) (measured using linear 300 to 3400 weighting) Level = 0 dBmO 56] 56 65 dB Typical values are measured with | Level =-6 dBmO 50 | 50 64 dB 30.5dB gain Level = -10 dBmd 48] 48 61 dB Level = -20 dBmd 43] 43 52 dB Level = -30 dBmd 38|37.5| 42 dB Level = -40 dBmod 29/285) 31 dB Level = -45 dBmd 24| 23 26 dB Level = -55 dBm 15] 13 16 dB Spex Single Frequency Distortion 0 dBm0 input signal -80 -56 dB transmit STpRE Signal to Total Distortion (VFr) Sinusoidal Test Method (*) ( up to 20cB attenuation) (measured using linear 300 to 3400 weighting) Level = -6 dBmo 50 64 dB Typical values are measured with | Level =-10 dBm0 48 62 dB 20dB attenuation. Level = -20 dBmd 43 53 dB Level = -30 dBmd 38 43 dB Level = -40 dBmd 29 33 dB Level = -45 dBmd 24 28 dB Level = -55 dBmd 15 18 dB Sper Single Frequency Distortion -6 dBm0 input signal -80 -50 dB receive (Ver) STDRL Signal to Total Distortion (VLr) Sinusoidal Test Method (") (up to 20dB attenuation) (measured using linear 300 to 3400 weighting) Level = -6 dBmo 50 64 dB Typical values are measured with | Level =-10 dBm0 48 62 dB 20dB attenuation Level = -20 dBmd 43 53 dB Level = -30 dBmd 38 43 dB Level = -40 dBmdo 29 33 dB Level =-45 dBmd 24 28 dB Level = -55 dBmd 15 18 dB Spr Single Frequency Distortion -6 dBm0 input signal -80 -50 dB receive (Vir) IMD Intermodulation Loop-around measurement -75 -46 dB Voltage at MIC = -10 dBmo te -27 dBm, 2 Frequencies in the range 300 - 3400 Hz (*) The limit curve shall be determined by straight lines joining successive coordinates given in the table. (#) Lower limits used during the automatic testing to avoid unrealistic yield loss due to +2dB imprecision of time-limiteadnoise measurements. CROSSTALK Symbol Parameter Test Condition Min. Typ. Max Unit CTwr Transmit to Receive Transmit Level = 0 dBmo, -100 -65 dB f = 300 - 3400 Hz DR = Quiet PCM Code Ctrx Receive to Transmit Receive Level = -6 dBm0, -80 -65 dB f = 300 - 3400 Hz MIC =0V 25/29 7 SGS-THOMSON MICROELECTRONICSST5090 APPLICATIONS Application Note for Microphone Connections DIFFERENTIAL NODE SINGLE ENDED NODE MIXED MODE (REVERSIBLE) @.47UF oe nici- @.47uUF @.47uUF yj nicz: CH nic2- @.47UF @.47uUF nica J nici- 6.47uUF @.47uUF fF nic2+ CH nic2- @,47UF @.47UF nici: ntci- G.47uF g.47uUF } ntc2: CH nice- G.47uUF ST5090 ST5090 ST5090 we we we 4 4 4 HSPISTSEGGA- 82 Application Note for Vrr and Vir Connections DYNAMIC RECEIVERS CERAMIC RECEIVERS DYNAMIC/CERAMIC RECEIVERS (329) (50nF) (REVERSIBLE) R 1 | VFr+ | VEr+ | VFr+ VEr- ) VFr- ) VFr- ST5090 ST5090 ST5090 R R > Vine iT Vure | Vire | VLr- ) VLr- ) VLr- DESTLO7BA R must be greater than 300 For higher capacitive transducers, lower R values can be used. used. To minimize noise sources, all ground connec- POWER SUPPLIES While pins of ST5090 device are well protected against electrical misuse, it is recommended that the standard CMOS practise of applying GND be- fore any other connections are made should al- ways be followed. In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be 26/29 iy SGS-THOMSON tions to each device should meet at a common point as close as possible to the GND pin in order to prevent the interaction of ground return cur- rents flowing through a commen bus impedance. A power supply decoupling capacitor of 0.1 pF should be connected from this common point to Vec as close as possible to the device pins. MICROELECTRONICS$ST5090 TQFP44 (10 x 10) PACKAGE MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.60 0.063 Al 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 0.30 0.37 0.45 0.012 0.014 0.018 Cc 0.09 0.20 0.004 0.008 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L 0.45 0.60 0.75 0.018 0.024 0.030 | 1.00 0.039 K 0(min.), 3.5(typ.}, 7(max.} A2 0.1 0rnm Oo O04 Seating Plane CL. 27/29 f SGS-THOMSON T/ iwcRoeLectRemesST5090 $028 PACKAGE AND MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 2.65 0.104 al 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 cl 45 (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 $s 8 (max.) L + cl al Tee < Uf tN _4 LAll et | TF] | |s oonnonoononoon _ | DOCUUUUDUUUUUOD 28/29 iy SGS-THOMSON MICROELECTRONICS$ST5090 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility tor the consequences of use of such information nor for any infringement of patents or other rights cf third parties which may result from its use. No licanse is granted by implication or otharwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in lita support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 29/29 f SGS-THOMSON T/ iwcRoeLectRemes