Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
M56693FP/GP
MITSUBISHI <CONTROL / DRIVER IC>
DESCRIPTION
The M56693 is a semiconductor integrated circuit that has a built-
in, 32-bit shift register and a latch of CMOS structure with serial
input and serial/parallel output, and a 32-bit totem-pole-type
parallel output driver of high pressure proof DMOS structure.
Employed are BI-CMOS and high pressure proof DMOS
processing technology.
FEATURES
●Serial input–serial/parallel output
●Cascade connections possible through serial output
●Latch circuit included for each stage
●Driver supply voltage: VH=120V
●Operating temperature: -20 – 75°C
APPLICATION
Vacuum Fluorescent Display ANODE DRIVER
FUNCTION
The M56693 comprises a 32-bit D type flip-flop with a 32 latches
connected to its output.
In accordance with truth table 1, inputting data to SIN and clock
pulse to CLK allows SIN signal to be put into the internal shift
register when the clock changes from “H” to “L”, and
simultaneously shift register data to be shifted sequentially.
Serial output SOUT is used by connecting to the next stage
M56693 SIN when more than one M56693 is used to expand bits
in the series.
In accordance with truth table 2, parallel output allows the latch to
pass data through if LAT input is turned to “H”, and data to be
retained if LAT is turned to “L”. Driver output HVOn allows data
from the latch to be output if BLK input is turned to “L”, and “L” to
be output if BLK input is turned to “H”, irrespective of data from the
latch.
PIN CONFIGURATION
(
TOP VIEW
)
SIN
SOUT
HVO 1
HVO 2
HVO 3
HVO 4
HVO 5
HVO 6
HVO 7
HVO 8
HVO 9
HVO10
HVO11
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
VH
VDD
N.C
LGND
CLK
LAT
VH
BLK
PGND
HVO22
HVO21
HVO20
HVO19
HVO18
HVO17
HVO16
HVO15
HVO14
HVO13
HVO12
PGND
HVO32
HVO31
HVO30
HVO29
HVO28
HVO27
HVO26
HVO25
HVO24
HVO23
Outline 44P6N-A (FP)
M56693FP
N.C: no connection
Outline 48P6D-A (GP)
HVO19
HVO12
HVO13
N.C
46
47
37
38
39
40
41
42
43
44
45
22
21
20
19
18
17
16
15
14
13
23
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
35
34
HVO14
HVO15
HVO16
HVO17
HVO18
HVO20
HVO21
HVO22
12
24
N.C
HVO32
HVO31
HVO30
HVO29
HVO28
HVO27
HVO26
HVO25
HVO24
HVO23
N.C
36
48
HVO 5
HVO 6
N.C
HVO 7
HVO 8
HVO 9
HVO10
HVO11
N.C
HVO 3
HVO 4
HVO 2
PGND
VDD
PGND
LGND
CLK
BLK
SOUT
VH
SIN
HVO
1
LAT
VH
M56693GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
M56693FP/GP
MITSUBISHI <CONTROL / DRIVER IC>
BLOCK DIAGRAM (Note : Pin No. in paretheses are of M56693GP)
Output
protect
circuit
8
7
9
6
Q
T
D
Q
LD
Q
T
D
Q
LD
Q
T
D
Q
LD
Q
T
D
Q
LD
Q
T
D
Q
LD
Q
T
D
Q
LD
2
42 4341
14
13
12
BLK
LAT
SIN
CLK
SOUT
4N.C
10
1
44
11
VH
PGND
5
VDD
LGND
HVO32HVO31HVO30HVO 3HVO 2HVO 1
3
(12) (13) (14) (46) (47) (48)
(4)
(8)
(7)
(9)
(6)
(2)(10)
(1)(11)
(5)
(3)
(18)(24)(25)
(37)(38)
Truth table 2. Latch and driver sections
HVOnDn LAT BLK
X
H
L
X
Dn=nth bit DFF retention data
HVOn=nth bit driver output
L=“L” level
H=“H” level
X=“L” level or “H” level
Truth table 1. Shift register section
CLK
↓
H or L
Shift register operation
DATA is shifted.
No changes.
TRUTH TABLE
X
H
H
L
H
L
L
L
Output all “L”
H
L
Latch’s data output.
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
M56693FP/GP
MITSUBISHI <CONTROL / DRIVER IC>
HVO1 – 32 Output driver (push-pull)
FunctionPin name
PIN FUNCTION DESCRIPTION
VDD
LGND
VH
PGND
CLK
SIN
SOUT
LAT
BLK
Serial data output
Latch input. When the LATCH is set to “H”, the data in the shift resister will enter the each latch circuit.
When the LATCH input is set to “L”, the data will be held.
Enable input for output control. When the BLK input is set to “L”, data in the latch circuit will appear at outputs.
When the BLK input is set to “H”, all outputs will be set to “L”.
Logic stage supply voltage
Logic stage ground
Output stage supply voltage
Output stage ground
Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be
shifted in order by High to Low change of the clock.
Serial data input
Logic inputs voltage
Outputs voltage
Power dissipation range
Storage temperature range
Logic outputs voltage
Logic stage supply voltage
Output stage supply voltage
VI
VHVO
Tstg
-0.3 – 120
VO-0.3 – VDD+0.3
VDD -0.3 – 7
VH
Pd
-0.3 – VDD+0.3
-0.3 – VH
-55 – 150
940
High supply voltage output pin
Symbol Ratings UnitParameter Conditions
ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)
V
V
V
V
V
°C
mW
Ta ≤ 25°C
Data output
3.1
High supply voltage output pin
V
-2
-100
SIN, LAT, CLK
BLK
VTH
VTL Output protect operating voltage
IHVOH “H” output current
VOH
VOL Logic output voltage
VHVOH Driver output voltage
VHVOL
IHSupply current 2
Operating temperature
Supply voltage
Supply voltage
Topr 10 – 110
VDD 4.5 – 5.5
VH-20 – 75
Symbol Ratings UnitParameter Conditions
RECOMMENDED OPERATING CONDITIONS
V
V
°C
Limits
Min. Typ. Max.
Symbol Test conditions Unit
Parameter
ELECTRICAL CHARACTERISTICS (VDD=5V, VH=110V and Ta=25°C, unless otherwise noted)
IDD
IHVOL
Supply current 1
“L” input current
“L” output current
IOH = -0.1mA
100
4.5
1
0
2
0
-20
106
4.95
3.4
2
50
4
2
mA
mA
V
V
IIH
IIL
“H” input current
No load
Output all “L”, no load
IHVOH = -0.5mA
IHVOL = 0.5mA
VIH=5V Input pin
IOL = 0.1mA
High supply voltage output pin
VIL = 0V
02
µA
0.7
0.04
-1
1
0.4
µA
µA
V
mA
mA
-3
3
µA
Output all “H”, no load
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
M56693FP/GP
MITSUBISHI <CONTROL / DRIVER IC>
RO = 220KΩ
CO = 50pF
Driver output propagation time
tPLH(SO) Logic output propagation time
Limits
Min. Typ. Max.
Symbol Test conditions UnitParameter
SWITCHING CHARACTERISTICS (VDD=5V, VH=110V and Ta=25°C, unless otherwise noted)
fCLK
tPHL(SO)
tPHL(OUT)
trout
tfout
Clock frequency
Driver output rise and fall time
Duty = 45 – 55% 120
100
0.16
1.3
0.35
8
300
300
MHz
ns
ns
tPLH(OUT)
CL = 15pF
1µs
CO RO
TEST CIRCUIT
PG DUT CL
50Ω
SOUT
HVOn
VHVDDinput
(1) Pulse generator characteristics
tr≤20ns tf≤20ns
(2) Capacitance CL includes connection
floating capacitance and probe input
capacitance.
: RO=220KΩ
: CO=50pF
2
1
2.5
2
µs
µs
µs
TIMING WAVEFORM
SOUT
HVOn
SIN
BLK
CLK
1/fmax
th
tsu
tfso trso
trOUT tfOUT
tPLH(OUT)
50% 50%
50%
50% 50%
50%
tPHL(SO)
50% 50%
50%
tPHL(OUT)
90%
10%
90%
50% 10%
tPLH(SO)
90%
10%
90%
10%
50%
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
M56693FP/GP
MITSUBISHI <CONTROL / DRIVER IC>
Note
Output current IOH (mA)
10
9
8
7
6
5
4
3
2
1
1
14
16
24
32
13–
0
Duty cycle vs Permissible
output current 1 8–
9
16
24
32
Output current IOH (mA)
20 60 80 100
40
20 10060 8040
TYPICAL CHARACTERISTICS
Thermal derating
Temperature Ta (°C)
Power dissipation Pd (W)
1.0
0.94
0.5
0100755025
0
Driver output VON–IOH
0
2
4
6
8
10
0246810
“H” output voltage VON (V)
“H” output current IOH(mA)
Ta=-20°C
Ta=+25°C
Ta=+75°C
Duty cycle vs Permissible
output current
Duty cycle (%)Duty cycle (%)
Note •
•
•
•
Ta=25°C
Repeated frequency >100Hz
Figure in the circle represents the number of
concurrently operating output circuits.
Current value denotes a numerical value per circuit.
Note •
•
•
•
Ta=75°C
Repeated frequency >100Hz
Figure in the circle represents the number of
concurrently operating output circuits.
Current value denotes a numerical value per circuit.
1.
2.
3.
VDD=5V and VH=110V, unless otherwise noted
Thermal derating characteristics represent those of an individual IC unit.
Allowable duty cycle output current characteristics represent that when a standard
substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)
0
10
9
8
7
6
5
4
3
2
1
00