®
Integrated Circuits Group
LH28F64BNHG-PBSL60
Synchronus Dual Work Flash Memory
64M (4M × 16)
(Model No.: LHF64N08)
Spec No.: FM02X010
Issue Date: October 24, 2002
PRELIMINARY PRODUCT SPECIFICATIONS
LHF64N08
• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,
full or in part, of this material is prohibited without the express written permission of the company.
• When using the products covered herein, please observe the conditions written herein and the precautions outlined in
the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly
adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the
product s c overed herein for the equipme nt l is te d in Paragraph (2) , eve n for the following app licati on areas, be sure
to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph
(3).
• Office electronics
• Instrumentation and measuring equipment
• Machine tools
• Audiovisual equipment
• Home appliance
• Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high
reliability, should first contact a sales representative of the company and then accept responsibility for
incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring
reliability and safety of the equipment and the overall system.
• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
• Mainframe c omputers
• Traffic control systems
• Gas leak detectors and automatic cutoff devices
• Rescue and security equipment
• Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely high performance
in term s o f fun ctiona lity, reliability, or a ccurac y.
• Aerospace equipment
• Communications equipment for trunk lines
• Control equipment for the nuclear power industry
• Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales
representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 0.1 1
sharp
LHF64N08 1
PAGE
0.75mm pitch 56-Ball CSP Pinout............................. 3
Pin Descriptions.......................................................... 4
Simultaneous Op er ati on Mod es
Allowed with Four Planes.................................. 6
Memory Map.............................................................. 7
Ident if ier Codes and OTP Address
for Read Operation............................................. 8
Identifier Codes and OTP Address for
Read Operation on Partition Configuration........ 8
OTP Block Address Map for OTP Program............... 9
Bus Operation........................................................... 10
Command Definitions ..... ........ .................................. 11
Functions of Block Lock and Block Lock-Down..... 13
Block Locking State Transitions upon
Command Write................................................ 13
Block Locking State Transitions upon
WP# Transition......................... ........ ................ 14
Status Register Definition......................................... 15
Extende d Stat us Regi st er Defini tion ................. ....... 16
Read Configuration Register Definition................... 17
PAGE
Frequency Configuration Settings............................ 18
Frequency Configuration.......................................... 18
Output Configuration................................................ 19
Read Sequence and Burst Length ............................. 19
Partit ion Config ura tion Regi st er Defini tion.............. 20
Partition Configuration ............................................. 20
1 Electrical Specifications......................................... 21
1.1 Absolute Maximum Ratings ........................... 21
1.2 Operating Conditions...................................... 21
1.2.1 Capacitance.............................................. 22
1.2.2 AC Input/Output Test Conditions............ 22
1.2.3 DC Characteristics ................................... 23
1.2.4 AC Characteristics
- Read-Only Operations......................... 25
1.2.5 AC Characteristics
- Wr ite Operations ................................. 33
1.2.6 Reset Operations...................................... 35
1.2.7 Block Erase, Advanced Factory
Program, (Page Buffer) Program
and OTP Program Performance............. 36
CONTENTS
Rev. 0.1 1
sharp
LHF64N08 2
LH28F640BNHG-PBSL60
64Mbit (4Mbit×16)
Synchronous Dual Work Flash MEMORY
64M density with 16Bit I/O Interface
High Performance Reads
• 60/20ns 8-Word Page Mode
• 52MHz Synchronous Burst Mode
Configurative 4-Plane Dual Work
• Flexible Partit ioning
• Read operations during Block Erase or (Page Buffer)
Program
• Status Register for Each Partition
Low Power Operation
• 1.7V Read and Write Operations
• VCCQ for Input/Output Power Supply Isolation
• Automatic Po wer Sav ing s Mode Reduces ICCR
in Static Mode
Enhanced Code + Data Storage
• 5µs Typical Erase/Program Suspends
OTP (One Time Program) Block
• 4-Word Factory-Programmed Area
• 4-Word User-Programmab l e Area
High Performance Program with Page Buffer
• 16-Word Page Buffer
• 5µs/Wor d (Typ.) at 12V VPP
Operating Temperature -40°C to +85°C
Advanced Factory Programming Mode
• 3.5µs/Word (Typ.)
Flexible Blocking Architecture
• Eight 4K-word Parameter Blocks
• One-hundred and twenty-seven 32K-word
Main Blocks
• Bottom Parameter Location
Enhanced Data Protection Features
• Individual Block Lock and Block Lock-Down with
Zero-Latency
• All blocks are locked at power-up or device reset.
• Absolute Protection with VPP≤VPPLK
• Block Erase, Advanced Factory Program,
(Page Buffer) Wor d Pr ogr am Loc kou t duri ng
Power Transitions
Automated Erase/Program Algorithms
• 1.8V Low-Power 22µs/ Word (Typ.)
Programming
• 12V No Glue Logic 9µs/Word (Typ.)
Production Programming and 0.5s Erase (Typ.)
Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
0.75mm pitch 56-Ball CSP
ETOXTM* Flash Technology
Not designed or rated as radiation hardened
CMOS Process (P-type silicon substrate)
The product, which is 4-Plane Synchronous Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low
power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can
operate at VCC=1.7V-1.95V and VPP=0.9V-1.95V or 11.7V-12.3V. Its low voltage operation capability greatly extends
battery life for portable applications.
The product provides high performance asynchronous page mode and synchronous burst mode. It allows code execution
directly from Flash, thus eliminating time consuming wait states. Furthermore, its newly configurative partitioning
architecture allows flexible dual work operation.
The memory array block architecture utilizes Enhanced Data Protection features and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as an unique number.
* ETOX is a trademark of Intel Corporation.
Rev. 0.1 1
sharp
LHF64N08 3
A
11
A
12
A
9
A
8
GND
A
20
V
CC
CLK
RST#
VPP
A
18
A
17
A
5
A
6
A
4
H
G
F
E
D
C
B
A
A
3
A
13
A
15
A
14
A
10
A
21
WAIT
ADV#
A16
DQ12
WE#
A
19
WP#
NC
A
7
A
2A
1
V
CCQ
GND
DQ14
DQ15
DQ6DQ13
DQ4DQ11
DQ10
DQ2
DQ1DQ9
DQ0CE#
A
0
OE#
DQ7
12
3
4
56
7
GND
DQ5
VCC
DQ3
V
CCQ
DQ8
GND
0.75mm pitch
56-BALL CSP
PINOUT
11mm x 8mm
TOP VIEW
Figure 1. 0.75mm pitch 56-Ball CSP Pinout
Rev. 0.1 1
sharp
LHF64N08 4
Table 1. Pin Descriptions
Symbol Type Name and Function
A0-A21 INPUT ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21
DQ0-DQ15 INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code and read/partition configuration register code reads. Data pins float to
high-impedance (High Z) when the chip or outputs are deselected. Data is internally
latched during an erase or program cycle.
CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to
standby levels.
CLK INPUT
CLOCK: Synchronizes the memory to the system bus operating frequency in
synchronous burst mode. The first rising (or falling if RCR.6 is "0") edge latches the
address when ADV# is VIL or upon a rising ADV# edge. This is used only for
synchronous burst mode.
ADV# INPUT ADDRESS VALID: Addresses are input to the memory when ADV# is low (VIL).
Addresses are latched on ADV#’s rising edge during read and write operations.
RST# INPUT
RESET: When low (VIL), RST# resets internal automation and inhibits write operations
which provides data protection. RST#-high (VIH) enables normal operation. After
power-up or reset mode, the device is automatically set to asynchronous read array
mode. RST# must be low during power-up/down.
OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WP# INPUT WRITE PROTECT: When WP# is VIL, locked-down blocks cannot be unlocked. Erase
or prog ram oper at ion can be execute d to the blocks w hic h ar e not locked a nd no t l o ck ed-
down. When WP# is VIH, lock-down is disabled.
WAIT OUTPUT
WAIT: Indicates data valid in synchronous burst modes. The read configuration register
bit 10 (RCR.10, WT) determines its polarity. With CE# at VIL, WAIT’s active output is
VOL or V OH. WAIT is High-Z if CE# is VIH. WAIT is not gated by OE#. WAIT is used
only for synchronous burst mode.
VPP INPUT
MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin.
With VPP≤VPPLK, block erase, advanced factory program, (page buffer) program or
OTP program cannot be executed and should not be attempted.
Applying 12V±0.3V to VPP provides fast erasing or fast programming mode. In this
mode, VPP is power supply pin. Applying 12V±0.3V to VPP during erase/program can
only be done for a maximum of 1,000 cycles on each block. VPP may be connected to
12V±0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits
may reduce block cycling capability or cause permanent damage.
Rev. 0.1 1
sharp
LHF64N08 5
VCC SUPPLY DEVICE POWER SUPPLY (1.7V-1.95V): With VCC≤VLKO, all write attempts to the
flash memory are inhibited. Device operations at invalid VCC voltage (see DC
Characteristics) produce spurious results and should not be attempted.
VCCQ SUPPLY INPUT/OUTPUT POWER SUPPLY (1.7V-1.95V): Power supply for all input/output
pins.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
Table 1. Pin Descriptions
Symbol Type Name and Function
Rev. 0.1 1
(Continued)
sharp
LHF64N08 6
NOTES:
1. "X" denotes the operation available.
2. Configurative Partition Dual Work Restrictions:
Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each
partition. Only one partition can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
It is not possible to do burst reads that cross partition boundaries.
Table 2. Simultaneous Operation Modes Allowed with Four Planes(1, 2)
IF ONE
PARTIT ION IS:
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
Read
Array Read
ID/OTP
Read
Status Read
Query Word
Program
Page
Buffer
Program
OTP
Program Block
Erase
Advanced
Factory
Program
Program
Suspend
Block
Erase
Suspend
Read ArrayXXXX X X X X X
Read ID/OTPXXXX X X X X X
Read StatusXXXX X X X X X X X
Read QueryXXXX X X X X X
Word ProgramXXXX X
Page Buffer
Progra m XXXX X
OTP Program X
Block EraseXXXX
Advanced
Factory
Program X
Program
Suspend XXXX X
Block Erase
Suspend XXXX X X X
Rev. 0.1 1
sharp
LHF64N08 7
6
5
4
3
2
1
0
74K-WORD 007000H - 007FFFH
4K-WORD 006000H - 006FFFH
4K-WORD 005000H - 005FFFH
4K-WORD 004000H - 004FFFH
4K-WORD
003000H - 003FFFH
4K-WORD
002000H - 002FFFH
4K-WORD
001000H - 001FFFH
4K-WORD
000000H - 000FFFH
PLANE2 (UNIFORM PLANE)
92
93
94
95
64
65
72
73
74
75
32K-WORD
278000H - 27FFFFH
32K-WORD
270000H - 277FFFH
32K-WORD
268000H - 26FFFFH
32K-WORD
260000H - 267FFFH
32K-WORD
258000H - 25FFFFH
32K-WORD
250000H - 257FFFH
32K-WORD
248000H - 24FFFFH
32K-WORD
240000H - 247FFFH
32K-WORD
238000H - 23FFFFH
32K-WORD
230000H - 237FFFH
32K-WORD
228000H - 22FFFFH
32K-WORD
220000H - 227FFFH
32K-WORD
218000H - 21FFFFH
32K-WORD 210000H - 217FFFH
32K-WORD 208000H - 20FFFFH
32K-WORD 200000H - 207FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
76
78
79
80
81
82
83
77
84
85
66
68
69
70
71
67
86
88
89
90
91
87
PLANE1 (UNIFORM PLANE)
BLOCK NUMBER ADDRESS RANGE
62
63
32
33
34
35
42
43
44
45
32K-WORD
178000H - 17FFFFH
32K-WORD
170000H - 177FFFH
32K-WORD
168000H - 16FFFFH
32K-WORD
160000H - 167FFFH
32K-WORD
158000H - 15FFFFH
32K-WORD
150000H - 157FFFH
32K-WORD
148000H - 14FFFFH
32K-WORD
140000H - 147FFFH
32K-WORD
138000H - 13FFFFH
32K-WORD
130000H - 137FFFH
32K-WORD
128000H - 12FFFFH
32K-WORD
120000H - 127FFFH
32K-WORD
118000H - 11FFFFH
32K-WORD 110000H - 117FFFH
32K-WORD 108000H - 10FFFFH
32K-WORD 100000H - 107FFFH
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
46
48
49
50
51
52
53
47
54
55
36
38
39
40
41
37
56
58
59
60
61
57
12
13
14
15
32K-WORD
078000H - 07FFFFH
32K-WORD
070000H - 077FFFH
32K-WORD
068000H - 06FFFFH
32K-WORD
060000H - 067FFFH
32K-WORD
058000H - 05FFFFH
32K-WORD
050000H - 057FFFH
32K-WORD
PLANE0 (PARAMETER PLANE)
048000H - 04FFFFH
32K-WORD
040000H - 047FFFH
32K-WORD
038000H - 03FFFFH
32K-WORD
030000H - 037FFFH
32K-WORD
028000H - 02FFFFH
32K-WORD
020000H - 027FFFH
32K-WORD
018000H - 01FFFFH
32K-WORD 010000H - 017FFFH
32K-WORD 008000H - 00FFFFH
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
16
18
19
20
21
22
23
17
24
25
8
9
10
11
26
28
29
30
31
27
127
128
129
130
131
132
133
32K-WORD
PLANE3 (UNIFORM PLANE)
3F8000H - 3FFFFFH
122
123
124
102
103
104
105
32K-WORD
378000H - 37FFFFH
32K-WORD
370000H - 377FFFH
32K-WORD
368000H - 36FFFFH
32K-WORD
360000H - 367FFFH
32K-WORD
358000H - 35FFFFH
32K-WORD
350000H - 357FFFH
32K-WORD
348000H - 34FFFFH
32K-WORD
340000H - 347FFFH
32K-WORD
338000H - 33FFFFH
32K-WORD
330000H - 337FFFH
32K-WORD
328000H - 32FFFFH
32K-WORD
320000H - 327FFFH
32K-WORD
318000H - 31FFFFH
32K-WORD 310000H - 317FFFH
32K-WORD 308000H - 30FFFFH
32K-WORD 300000H - 307FFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
106
108
109
110
111
112
113
107
114
115
96
98
99
100
101
97
116
118
119
120
121
117
125
126
134
BLOCK NUMBER ADDRESS RANGE
Figure 2. Memory Map (Bottom Parameter)
Rev. 0.1 1
sharp
LHF64N08 8
NOTES:
1. The address A21-A16 are shown in below table for reading the manufacturer code, device code,
device configuration code and OTP data.
2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address).
3. Block Address = The beginning location of a block address within the partition to which
the Read Identifier Codes/OTP command (90H) has been written.
DQ15-DQ2 are reserved for future implementation.
4. RCRC=Read Configuration Register Code.
5. PCRC=Partition Configuration Register Code.
6. OTP-LK=OTP Block Lock configuration.
7. OTP=OTP Block data.
NOTES:
1. The address to read the identifier codes or OTP data is dependent on the partition which is selected
when writing the Read Identifier Codes/OTP command (90H).
2. Refer to Table 15 for the partition configuration register.
Table 3. Identifier Codes and OTP Address for Read Operation
Code Address
[A15-A0]Data
[DQ15-DQ0]Notes
Manufact ur er Code Manufac tur er Code 0000H 00B0H 1
Device Code Bottom Parameter Device Code 0001H 00BBH 1, 2
Block Lock Configuration
Code Block is Unlocked
Block
Address
+ 2
DQ0 = 0 3
Block is Locked DQ0 = 1 3
Block is not Locked-Down DQ1 = 0 3
Block is Locked-Down DQ1 = 1 3
Device Configuration Code Read Configuration Register 0005H RCRC 1, 4
Partition Configuration Register 0006H PCRC 1, 5
OTP OTP Lock 0080H OTP-LK 1, 6
OTP 0081-0088H OTP 1, 7
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) (64M-bit device)
Partition Configuration Register (2) Address (64M-bit device)
PCR.10 PCR.9 PCR.8 [A21-A16]
00000H
0 0 1 00H or 10H
0 1 0 00H or 20H
1 0 0 00H or 30H
0 1 1 00H or 10H or 20H
1 1 0 00H or 20H or 30H
1 0 1 00H or 10H or 30H
1 1 1 00H or 10H or 20H or 30H
Rev. 0.1 1
sharp
LHF64N08 9
Customer Programmable Area Lock Bit (DQ
1
)
Factory Programmed Area Lock Bit (DQ
0
)
Customer Programmable Area
Factory Programmed Area
Reserved for Future Implementation
000080H
000081H
000084H
000085H
000088H
[A
21
-A
0
]
(DQ
15
-DQ
2)
Figure 3. OTP Block Address Map for OTP Program
(The area outside 80H~88H cannot be used.)
Rev. 0.1 1
sharp
LHF64N08 10
NOTES:
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but cannot be altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK
and VPPH1/2 voltages.
3. RST# at GND±0.2V ensures the lowest power consumption.
4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when
VPP=VPPH1/2 and VCC=1.7V-1.95V.
Command writes involving advanced factory program are reliably executed when VPP=VPPH2 and VCC=1.7V-1.95V.
5. Refer to Table 6 for valid DIN during a write operation.
6. Never hold OE# low and WE# low at the same timing.
7. Refer to Appendix of LH28F640BN series for more information about query code.
8. WAIT indicates data valid in synchronous burst modes. WAIT is used only for synchronous burst mode.
Ta ble 5. Bus Operation(1, 2)
Mode Notes RST# CE# OE# WE# ADV# WP# Address VPP DQ0-15 WAIT
Read Arra;y 6 VIH VIL VIL VIH VIL XXX
DOUT See
NOTE 8
Output Disa ble VIH VIL VIH VIH XXXXHigh ZV
IL or VIH
Standby VIH VIH XXXX X XHigh ZHigh Z
Reset 3 VIL XXXXX X XHigh ZHigh Z
Re ad I den tifier
Codes/OTP 6VIH VIL VIL VIH VIL XSee
T able 3 and
Table 4 XSee
T able 3 and
Table 4 VIL or VIH
Read Query 6,7 VIH VIL VIL VIH VIL XSee
Appendix XSee
Appendix VIL or VIH
Write 4,5,6 VIH VIL VIH VIL VIL XXXD
IN VIL or VIH
Rev. 0.1 1
sharp
LHF64N08 11
NOTES:
1. Bus operations are defined in Table 5.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
bus cycle.
X=Any valid ad dress withi n the device .
PA=Address within the selected partition.
IA=Identifier codes address (See Table 3 and Table 4).
QA=Query codes address. Refer to Appendix of LH28F640BN series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
RCRC=Read configuration register code presented on the addresses A0-A15.
PCRC=Partition configuration register code presented on the address A0-A15.
3. ID=Data read from identifi er codes. (See Table 3 and Tabl e 4).
QD=Data read from query database. Refer to Appendix of LH28F640BN series for details.
SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever
goes high first) during command write cycles.
OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first)
during command write cycles.
N- 1=N is the numbe r of the words to be loa ded into a page bu ffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, read configuration register code, partition configuration register code and the data within OTP block
(See Table 3 and Table 4).
The Read Query command is available for reading CFI (Common Flash Interface) information.
Table 6. Command Definitions(11)
Command Bus
Cycles
Req’d Notes First Bus Cycle Second Bus Cycle
Oper(1) Addr(2) Data Oper(1) Addr(2) Data(3)
Read Array 1 Write PA FFH
Read Identifier Codes/OTP ≥ 2 4 Write PA 90H Read IA or OA ID or OD
Read Query ≥ 24WritePA 98HReadQA QD
Read Status Register 2 Write PA 70H Read PA SRD
Clear Statu s Register 1 Write PA 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Advanced Factory Program 2 5,9 Write X 30H Write X D0H
Program 25,6WriteWA40H or
10H Write WA WD
Page Buffer Program ≥ 4 5,7 Wr ite WA E8H Write WA N-1
Block Erase and (Page Buffer)
Program Suspend 18,9WritePA B0H
Block Erase and (Page Buffer)
Program Resume 18,9WritePA D0H
Set Bloc k Lock Bit 2 Write B A 60H Write BA 01H
Clear Block Lock Bit 2 10 Write BA 60H Write BA D0H
Set Block Lock-down Bit 2 Write B A 60H Write BA 2FH
OTP Program 2 9 Write OA C0H Write OA OD
Set Read Configuration Register 2 Write RCRC 60H Write RCRC 03H
Set Partition Configuration Register
2 Write PCRC 60H Write PCRC 04H
Rev. 0.1 1
sharp
LHF64N08 12
5. Block erase, advanced factory program or (page buffer) program cannot be executed when the selected block is locked.
Unlocked block can be erased or programmed when RST# is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any
valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of
LH28F640BN series for details.
8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Advanced factory program and OTP program operations can not be suspended. The OTP Program command can not be
accepted while the block erase operation is being suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is VIL. When
WP# is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 0.1 1
sharp
LHF64N08 13
NOTES:
1. DQ0=1: a block is locked; DQ0=0: a block is unlocked.
DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, advanced factory
prog ram and (page buffer) program ope ratio ns.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,
[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.
4. When WP# is driven to V
IL in [110] state, the state changes to [011] and the blocks are
automatically locked.
5. OTP (One Time Program) block has the lock function which is different from those described
above.
NOTES:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit
command and "Set Lock-down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the
corresponding block is locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that WP# is not changed and fixed VIL or VIH.
Table 7. Functions of Block Lock(5) and Block Lock-Down
Current State Erase/Program Allowed (2)
State WP# DQ1(1) DQ0(1) State Name
[000] 0 0 0 Unlocked Yes
[001](3) 0 0 1 Locked No
[011] 0 1 1 Locked-down No
[100] 1 0 0 Unlocked Yes
[101](3) 1 0 1 Locked No
[110](4) 1 1 0 Lock-down Disable Yes
[111] 1 1 1 Lock-down Disable No
Table 8. Block Locking State Transitions upon Command Write(4)
Current State Result after Lock Command Written (Next State)
State WP# DQ1DQ0Set Lock(1) Clear Lock(1) Set Lock-down(1)
[000] 0 0 0 [ 001] No Change [011](2)
[001] 0 0 1 No Change(3) [000] [011]
[011] 0 1 1 No Change No Change No Change
[100] 1 0 0 [ 101] No Change [111](2)
[101] 1 0 1 No Change [100] [111]
[110] 1 1 0 [111] No Change [111](2)
[111] 1 1 1 No Change [110] No Change
Rev. 0.1 1
sharp
LHF64N08 14
NOTES:
1. "WP#=0→1" means that WP# is driven to VIH and "WP#=1→0" means that WP# is driven to
VIL.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When WP# is driven to V
IL in [110] state, the state changes to [011] and the blocks are
automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in
previous, current and next state.
Table 9. Block Locking State Transitions upon WP# Transition(4)
Previo us State Current State Result after WP# Transition (Next State)
State WP# DQ1DQ0WP#=0→1(1) WP#=1→0(1)
- [000] 0 0 0 [100] -
- [001] 0 0 1 [101] -
[110](2) [011] 011 [110] -
Other th an [110](2) [111] -
- [100] 1 0 0 - [000]
- [101] 1 0 1 - [001]
- [110] 110 - [011](3)
- [111] 1 1 1 - [011]
Rev. 0.1 1
sharp
LHF64N08 15
Table 10. Status Register Definition
RRRRRRRR
15 14 13 12 11 10 9 8
WSMS BESS BES PBPAFPOPS VPPS PBPSS DPS PPES
76543210
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE STATUS (BES)
1 = Error in Block Erase
0 = Successful Block Erase
SR.4 = (PAGE BUFFER) PROGRAM,
ADVANCED FACTORY PROGRAM AND
OTP PROGRAM STATUS (PBPAFPOPS)
1 = Error in (Page Buffe r) P rog ram,
Advanced Factory Program or OTP Program
0 = Successful (Page Buffer) Program,
Advanced Factory Program or OTP Program
SR.3 = VPP STATUS (VPPS)
1 = VPP LOW Detect, Operation Abort
0 = VPP OK
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
STATUS (PBPSS)
1 = (Pa ge Buffe r) Program S usp end ed
0 = (Page Buffer) Program in Prog ress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.0 = PARTITION PROGRAM AND ERASE STATUS
(PPES)
1 = Another Partition is busy.
AFP: Program or Verify busy.
0 = Depending on status of SR.7.
The addressed partition is busy or no partition is
busy.
AFP: Program or Verify done, AFP ready.
NOTES:
Status Register indicates the status of the partition, not WSM (Write
State Ma chi ne). Even i f th e SR. 7 is "1 ", t he WSM may be occupi ed
by the other partition when the device is set to 2, 3 or 4 partitions
configuration.
Check SR.7 to determine block erase, advanced factory program,
(page buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1" s after a block er ase , advanced factory
program, (page buffer) program, set/clear block lock bit, set block
lock-down bit, set read configuration register, set partition
configuration register a ttempt, an improper c ommand se quence was
entered.
SR.3 does not provide a continuous indication of VPP level. The
WSM interrogates and indicates the VPP level only after Block
Erase, Advanced Factory Program, (Page Buffer) Program or OTP
Program command sequences. SR.3 is not guaranteed to report
accurate feedbac k when VPP≠VPPH1, VPPH2 or VPPLK.
SR.1 does not provide a continuous indication of block lock bit. The
WSM interrogates the block lock bit only after Block Erase,
Advanced Factory Program, (Page Buffer) Program or OTP
Program command sequences. It informs the system, depending on
the attempted operation, if the block lock bit is set. Reading the
block lock configuration codes after writing the Read Identifier
Codes/OTP command indicates block lock bit status.
SR.15 - SR.8 are reserved fo r future use and should be masked out
when polling the status register.
If SR.7="0" and SR.0="0", the address ed partition is busy and other
partition is not busy. In AFP Mode, it indicates that the device is
finished programming or verifying data or is ready for data.
If SR.7="0" and SR.0="1", another partition is busy (the addressed
partition is not busy). In AFP Mode, it indicates that the device is
programming or verifying data.
If SR.7="1" and SR.0="0", no partition is busy. In AFP Mode, it
indicates that the device has exited AFP mode.
SR.7="1" and SR.0="1" will not occur.
Rev. 0.1 1
sharp
LHF64N08 16
Table 11. Extended Status Register Definition
RRRRRRRR
15 14 13 12 11 10 9 8
SMSRRRRRRR
76543210
XSR.15-8 =
RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
XSR.6-0 =
RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted.
If XSR.7 i s "0 ", the com mand i s n ot accept ed and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and
should be masked out when polling the extended status
register.
Rev. 0.1 1
sharp
LHF64N08 17
Table 12. Read Configuration Register Definition
RM R FC2 FC1 FC0 WT DOC WC
15 14 13 12 11 10 9 8
BS CC R R BW BL2 BL1 BL0
76543210
RCR.15 = READ MODE (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
RCR.13-11 = FREQUENCY CONFIGURATION (FC2-0)
000 = Code 0 reserved for future use
001 = Code 1 reserved for future use
010 = Code 2
01 1 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6 reserved for future use
111 = Code 7 reserved for future use (Default)
RCR.10 = WAIT SIGNAL POLARITY (WT)
0 = WAIT signal is active low
1 = WAIT signal is active high (Default)
RCR.9 = DATA OUTPUT CONFIGURATION (DOC)
0 = Hold Data for One Clock
1 = Hold Data for Two Clocks (Default)
RCR.8 = WAIT CONFIGURATION (WC)
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle Before Delay
(Default)
RCR.7 = BURST SEQUENCE (BS)
0 = Intel Burst Order
1 = Linear Burst Order (Default)
RCR.6 = CLOCK CONFIGURATION (CC)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
(Default)
RCR.5-4 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
RCR.3 = BURST WRAP (BW)
0 = Wrap Burst Reads within Burst Length set
by RCR.2-0
1 = No Wrap Burst Reads within Burst Length set
by RCR.2-0 (Default).
RCR.2-0 = BURST LENGTH (BL2-0)
001 = 4 Word Burst
010 = 8 Word Burst
011 = Re served for future use
111 = Continuous (Linear) Burst (Default)
NOTES:
Read configuration register affects the read operations from
main and parameter blocks. Read operations for status
register, query code, identifier codes, OTP block and device
configuration codes support single read cycles.
RCR.14, RCR.5 and RCR.4 bits are reserved for future use
and should be masked out when checking the read
configuration register.
Refer to Frequency Configuration in Table 13 and Figure 4
for information about the frequency configuration RCR.13-
11.
Undocumented combinations of bits RCR.13-11 are reserved
for future implementations and should not be used.
Data is not ready when WAIT is active.
Refer to Figure 5 for information about Data Output
configuration RCR.9.
Refer to Table 14 for information about Burst Wrap
configuration RCR.3.
In the asynchronous page mode, the burst length always
equals 8 words.
All the bits in the read configuration register are set to "1"
after power-up or device reset.
When the bit RCR.15 is set to "1", other bits are invalid.
Rev. 0.1 1
sharp
LHF64N08 18
CLK (C)
ADV# (V)
A20-0 (A)
DQ15-0 (D/Q)
Code 2
Code 3
Code 4
VALID
ADDRESS
VALID
OUTPUT VALID
OUTPUT VALID
OUTPUT VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT VALID
OUTPUT VALID
OUTPUT
Code 5
VALID
OUTPUT VALID
OUTPUT
DQ15-0 (D/Q)
DQ15-0 (D/Q)
DQ15-0 (D/Q)
A21-0 (A)
Table 13. Frequency Configuration Settings
Read Configuration Register Frequency
Configuration Code
Input Clock Frequency
(VCC=1.7V-1.95V)
RCR.13 RCR.12 RCR.11 60ns
010 2 ≤ 40MHz
011 3 ≤ 52MHz
100 4 ≤ 66MHz
101 5 TBD
Figure 4. Frequency Configuration
Rev. 0.1 1
sharp
LHF64N08 19
CLK (C)
1 CLK
DATA HOLD DQ15-0 (D/Q) VALID
OUTPUT VALID
OUTPUT
2 CLK
DATA HOLD DQ15-0 (D/Q) VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
NOTE:
1. The burst wrap bit (RCR.3) determines whether 4- or 8-word burst-accesses wrap within the burst-length boundary or
whether they cross word-length boundaries to perform linear accesses.
Table 14. Read Sequence and Burst Length
Starting
Address
[Decimal]
Burst
Wrap(1)
(RCR.3=)
Burst Addressing Sequence [Decimal]
4-Word Burst L eng th
(RCR.2-0=001) 8-Word Burs t Length
(RCR.2-0=010) Cotinuous Burst
(RCR.2-0=111)
Linear Intel Linear Intel Linear
0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6…
1 0 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7…
2 0 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8…
3 0 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9…
4 0 4-5-6-7 4-5-6-7 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10…
5 0 5-6-7-4 5-4-7-6 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11…
6 0 6-7-4-5 6-7-4-5 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12…
7 0 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13…
...
...
...
...
...
...
...
14 0 14-15-12-13 14-15-12-13 14-15-8-9-
10-11-12-13 14-15-12-13-
10-11-8-9 14-15-16-17-18-19-20…
15 0 15-12-13-14 15-14-13-12 15-8-9-10-
11-12-13-14 15-14-13-12-
11-10-9-8 15-16-17-18-19-20-21…
...
...
...
...
...
...
...
0 1 0-1-2-3 NA 0-1-2-3-4-5-6-7 NA 0-1-2-3-4-5-6…
1 1 1-2-3-4 NA 1-2-3-4-5-6-7-8 NA 1-2-3-4-5-6-7…
2 1 2-3-4-5 NA 2-3-4-5-6-7-8-9 NA 2-3-4-5-6-7-8…
3 1 3-4-5-6 NA 3-4-5-6-7-8-9-10 NA 3-4-5-6-7-8-9…
4 1 4-5-6-7 NA 4-5-6-7-8-9-10-11 NA 4-5-6-7-8-9-10…
5 1 5-6-7-8 NA 5-6-7-8-9-10-11-12 NA 5-6-7-8-9-10-11…
6 1 6-7-8-9 NA 6-7-8-9-
10-11-12-13 NA 6-7-8-9-10-11-12…
7 1 7-8-9-10 NA 7-8-9-10-
11-12-13-14 NA 7-8-9-10-11-12-13…
...
...
...
...
...
...
...
14 1 14-15-16-17 NA 14-15-16-17-
18-19-20-21 NA 14-15-16-17-18-19-20…
15 1 15-16-17-18 NA 15-16-17-18-
19-20-21-22 NA 15-16-17-18-19-20-21…
Figure 5. Data Output Configuration
Rev. 0.1 1
sharp
LHF64N08 20
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PARTITION2PARTITION3
PARTITION2
PARTITION2
PARTITION1
PARTITION2
000
001
010
100
011
110
101
111
PC2 PC1PC0 PARTITIONING FOR DUAL WORK PARTITIONING FOR DUAL WORK
PC2 PC1PC0
Table 15. Partition Configuration Register Definition
RRRRRPC2PC1PC0
15 14 13 12 11 10 9 8
RRRRRRRR
76543210
PCR.15-11 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
PCR.10-8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
(default in a bottom parameter device)
010 = Plane 0-1 and Plane2-3 are merged into one
partition respectively.
100 = Plane 0-2 are merged into one partition.
(default in a top parameter device)
011 = Plane 2-3 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
110 = Plane 0-1 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
101 = Plane 1-2 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
111 = There are four partitions in this configuration.
Each plane corresponds to each partition respec-
tively. Dual work operation is available between any
two partitions.
PCR.7-0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
NOTES:
After power-up or device reset, PCR10-8 (PC2-0) is set to
"001" in a bottom parameter device and "100" in a top
parameter device.
See Figure 6 for the detail on partition configuration.
PCR.15-11 and PCR.7-0 are reserved for future use and
should be masked out when checking the partition
configuration register.
Figure 6. Partition Configuration
Rev. 0.1 1
sharp
LHF64N08 21
1 Electric al Spec ificat ions
1.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Erase and Program...-40°C to +85°C(1)
Storage Temperature
During under Bias ............................... -40°C to +85°C
During non Bias................................ -65°C to +125°C
Voltage On Any Pin
(except VCC and VPP)..............-0.5V to VCC+0.5V (2)
VCC and VCCQ Supply Voltage........ -0.2V to +2.45V (2)
VPP Supply Voltage....................- 0.2V to +12.6V (2, 3, 4)
Output Short Circuit Current...........................100mA (5)
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
reco mme nded and ext ended exposur e beyond the
"Operating Conditions" may affect device
reliability.
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC vol tage is -0.5V on input/ out put pins and
-0.2V on VCC and VPP pins. During transitions, this
level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins is
VCC+0.5V which, during transitions, may overshoot to
VCC+2.0V for periods <20ns.
3. Maximum DC voltage on VPP may overshoot to
+13.0V for periods <20ns.
4. VPP erase/program voltage is normally 1.7V-1.95V.
Applying 11.7V-12.3V to VPP during erase/program
can be done for a maximum of 1,000 cycles on the
main blocks and 1,000 cycles on the parameter blocks.
VPP may be connected to 11.7V-12.3V for a total of 80
hours maximum.
5. Output shorted for no more than one second. No more
than one output shorted at a time.
1.2 Operating Conditions
NOTES:
1. See DC Characteristics tables for voltage range-specific specification.
2. Applying VPP=11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks
and 1,000 cycles on the parameter blocks. A permanent connection to VPP=11.7V-12.3V is not allowed and can cause
damage to the device.
Parameter Symbol Min. Typ. Max. Unit Notes
Operating Temperature TA-40 +25 +85 °C
VCC Supply Voltage VCC 1.7 1.8 1.95 V 1
I/O Supply Voltage VCCQ 1.7 1.8 1.95 V 1
VPP Voltage when Used as a Logic Control VPPH1 0.90 1.8 1.95 V 1
VPP Supply Voltage VPPH2 11.7 12 12.3 V 1, 2
Main Block Erase Cycling: VPP=VPPH1 100,000 Cycles
Parameter Block Erase Cycling: VPP=VPPH1 100,000 Cycles
Main Block Erase Cycling: VPP=VPPH2, 80 hrs. 1,000 Cycles
Parameter Block Erase Cycling: VPP=VPPH2, 80 hrs. 1,000 Cycles
Maximum VPP hours at VPPH2 80 Hours
Rev. 0.1 1
sharp
LHF64N08 22
TEST POINTSVCCQ/2 VCCQ/2INPUT
VCCQ
0.0
OUTPUT
AC test inputs are driven at VCCQ(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Worst case speed conditions are when VCC=VCC(min).
DEVICE
UNDER
TEST
RL=3.3k
CL
VCCQ(min)/2
OUT
CL Includes Jig
Capacitances.
1N914
Figure 7. Transient Input/Output Reference Waveform for VCC=1.7V-1.95V
Figure 8. Transient Equivalent Testing Load Circuit
Ta ble 16. Configuration Capacitance Loading Value
Test Configuration CL (pF)
VCC=1.7V-1.95V 50
1.2 .2 AC Inpu t/ O ut put Conditi ons
1.2.1 Capacitance(1) (TA=+25°C, f =1MHz)
NOTE:
1. Sampled, not 100% tested.
Parameter Symbol Condition Min. Typ. Max. Unit
Input Capacitance CIN VIN=0.0V 68pF
CE# Input Capacitance CCE VIN=0.0V 10 12 pF
Output Capacitanc e COUT VOUT=0.0V 10 12 pF
Rev. 0.1 1
sharp
LHF64N08 23
1.2.3 DC Characteristics
VCC=1.7V-1.95V
Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions
ILI Input Load Current 1 -1.0 +1.0 µAVCC=VCCMax.,
VCCQ=VCCQMax.,
VIN/VOUT=VCCQ or
GND
ILO Output Leakage Current 1 -1.0 +1.0 µA
ICCS VCC Standby Current 1420µA
VCC=VCCMax.,
CE#=RST#=
VCCQ±0.2V,
WP#, ADV#=
VCCQ or GND
ICCAS VCC Automatic Power Savings Curr ent 1,5 4 20 µA
VCC=VCCMax.,
CE#=GND±0.2V,
WP#, ADV#=
VCCQ or GND
ICCD VCC Reset Power-Down Current 1420µA RST#=GND±0.2V
ICCR
Average VCC Read
Current
Normal Mode 1,7 15 25 mA VCC=VCCMax.,
CE#=VIL,
OE#=VIH,
f=5MHz
Average VCC Read
Current
Page Mode 8 Word Read 1,7 5 10 mA
Average VCC Read
Current
Synchronous
CLK=40MHz
Burst Length=4 1,3,8 10 15 mA VCC=VCCMax.,
CE#=VIL,
OE#=VIH,
f=40MHz
Burst Length=8 1,3,8 10 15 mA
Burst Length=
Continuous 1,3,8 20 25 mA
Average VCC Read
Current
Synchronous
CLK=52MHz
Burst Length=4 1,3,8 15 20 mA VCC=VCCMax.,
CE#=VIL,
OE#=VIH,
f=52MHz
Burst Length=8 1,3,8 15 20 mA
Burst Length=
Continuous 1,3,8 25 30 mA
ICCW VCC (Page Buffer) Program,
Advanced Factory Program Current
1,6,8 20 60 mA VPP=VPPH1
1,6,8 10 20 mA VPP=VPPH2
ICCE VCC Block Erase Current 1,6,8 10 30 mA VPP=VPPH1
1,6,8 4 10 mA VPP=VPPH2
ICCWS
ICCES
VCC (Page Buffer) Program or
Block Erase Suspend Current 1,2,8 10 200 µACE#=VIH
IPPS
IPPR VPP Standby or Read Current 1,7,8 2 5 µAVPP≤VCC
IPPW VPP (Page Buffer) Program,
Advanced Factory Program Current
1,6,7,8 2 5 µAVPP=VPPH1
1,6,7,8 10 30 mA VPP=VPPH2
IPPE VPP Block Erase Current 1,6,7,8 2 5 µAVPP=VPPH1
1,6,7,8 5 15 mA VPP=VPPH2
Rev. 0.1 1
sharp
LHF64N08 24
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=1.8V and TA=+25°C
unless VCC is specif ied .
2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block
erase suspend mode, the device’s current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page
buffer) program suspend mode, the device’s current draw is the sum of ICCWS and ICCR.
3. The burst wrap bit (RCR.3) determines whether 4- or 8-word burst-accesses wrap within the burst-length boundary or
whether they cross word-length boundaries to perform linear accesses.
4. Block er ase , adva nced factor y pro gra m, (pag e buf f er ) pr ogr am and OTP pro gra m are inhibited when VPP≤VPPLK, and not
guaranteed in the range between VPPLK(max.) and VPPH1(min.), between VPPH1(max.) and VPPH2(min.) and above
VPPH2(max.).
5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (tAVQV) provide new data when addresses are changed.
6. Sampled, not 100% tested.
7. VPP is not used f or power s uppl y pin. With VPP≤VPPLK, block erase, advanced factory program, (page buffer) program
and OTP program cannot be executed and should not be attempted.
Applying 12V±0.3V to VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and
suppli es the memory c ell current for block erasing and ( page buffer) prog ramm i ng. Use sim i la r power s uppl y tr ac e widths
and layout considerations given to the VCC power bus.
Applying 12V±0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP
may be connected to 12V±0.3V for a total of 80 hours maximum.
8. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
IPPWS VPP (Page Buffer) Progr am
Suspend Current
1,7,8 2 5 µAVPP=VPPH1
1,7,8 10 200 µAVPP=VPPH2
IPPES VPP Block Erase Suspend Current 1,7,8 2 5 µAVPP=VPPH1
1,7,8 10 200 µAVPP=VPPH2
VIL Input Low Voltage 6 -0.4 0.4 V
VIH Input High Voltage 6 VCCQ
-0.4 VCCQ
+ 0.4 V
VOL Output Low Vo ltage 6 0.1 V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOL=100µA
VOH Output High Voltage 6 VCCQ
-0.1 V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOH=-100µA
VPPLK VPP Lockout during Normal
Operati ons 4,6,7 0.4 V
VPPH1 VPP during Block Erase, (Page Buffer)
Program or OTP Program Operations 7 0.9 1.8 1.95 V
VPPH2
VPP during Block Erase, Advanced
Factory Program, (Page Buffer)
Program or OTP Program Operations 7 11.7 12 12.3 V
VLKO VCC Lockout Voltage 1.0 V
VCC=1.7V-1.95V
Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions
DC Characteristics (Con tinu ed)
Rev. 0.1 1
sharp
LHF64N08 25
1.2.4 AC Ch aracteristi c s - Read-Onl y O perations(1)
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. Applies only to subsequent synchronous reads.
4. OE# may be delayed up to tELQV tGLQV aft er th e falling edge of CE# with out impact to tELQV.
VCC=1.7V-1.95V, TA=-40°C to +85°C
Symbol Parameter
Notes
Min. Max. Unit
tCLK CLK Period 19 ns
tCH (tCL)CLK High (Low) T i me 5 ns
tCHCL (tCLCH)CLK Fall (Rise) Time 3 ns
tAVCH Address Setup to CLK 9 ns
tVLCH ADV# Setup to CLK 10 ns
tELCH CE# Setup to CLK 9 ns
tCHQV CLK to Output Delay 14 ns
tCHQX Output Hold from CLK 3 ns
tCHAX Address Hold from CLK 10 ns
tCHTV CLK to WAIT Va lid 14 ns
tELTV CE# Low to WAIT Valid 14 ns
tEHTZ CE # Hi gh to WAIT Hig h Z 20 ns
tEHEL CE# High between Subsequent Synchronous Reads 3 15 ns
tAVVH Address Setup to ADV# 10 ns
tELVH CE# Setup to ADV# 10 ns
tAVAV Read Cycle Time 60 ns
tAVQV Ad dre ss to Ou tput Dela y 60 ns
tELQV CE# to Output Delay 4 60 ns
tVLQV ADV# to Output Delay 60 ns
tVLVH ADV# Pulse Width Low 10 ns
tVHVL ADV# Pulse Width High 10 ns
tVHAX Address Hold from ADV# 9 ns
tAPA Page Address Access Ti me 20 ns
tGLQV OE# to Output Delay 4 20 ns
tPHQV RST# High to Output Delay 150 ns
tEHQZ, tGHQZ CE# or OE# to Output in High Z, Whichever Occurs First 2 15 ns
tELQX CE# to Output in Low Z 2 0 ns
tGLQX OE# to Output in Low Z 2 0 ns
tOH Output H old from Firs t Oc curri ng A dd r ess, C E# or OE# ch ang e 2 0 ns
Rev. 0.1 1
sharp
LHF64N08 26
CLK (C)
tCLK
tCL
tCHCL
tCLCH tCH
tAVQV
tAVVH
tVLVH
tVHVL
tEHQZ
tGHQZ
tVHAX
tVLQV
tELQV
tPHQV
tELVH
tGLQV
tOH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
VIH
VIL
(P)
(D/Q)
(T)
(W)
(G)
(E)
(V)
(A)A20-0
DQ15-0
ADV#
CE#
OE#
WAIT
WE#
RST#
VALID
ADDRESS
VALID
OUTPUT
High Z
tELQX
tGLQX
High Z NOTE 1 High Z
tAVAV
NOTE:
1. WAIT shown active low.
A21-0 (A)
Figure 9. AC Waveform for CLK Input
Figure 10. AC Waveform for Single Asynchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 0.1 1
sharp
LHF64N08 27
VALID
ADDRESS
VALID
ADDRESS VALID
ADDRESS VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tAVQV
tVLVH
tVHVL
tVLQV
tELQV
tELVH
tVHAX
tEHQZ
tGHQZ
tOH
tAPA
tPHQV
High Z
tAVVH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
(P)
(D/Q)
(W)
(G)
(E)
(V)
(A)A20-3
VIH
VIL
(A)A2-0
DQ15-0
ADV#
CE#
OE#
WE#
(T)WAIT
RST#
VALID
ADDRESS
tGLQV
tELQX
tGLQX
VOH
VOL
High Z NOTE 1 High Z
tAVAV
NOTE:
1. WAIT shown active low.
A21-3 (A)
Figure 11. AC Waveform for Asynchronous 4-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 0.1 1
sharp
LHF64N08 28
Figure 12. AC Waveform for Asynchronous 8-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
VALID
ADDRESS
tAVQV
tVLVH
tVHVL
tVLQV
tELQV
tELVH
tVHAX
tEHQZ
tGHQZ
tOH
tAPA
tPHQV
tAVVH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
(P)
(D/Q)
(W)
(G)
(E)
(V)
(A)A20-3
(A)A2-0
DQ15-0
ADV#
CE#
OE#
WE#
(T)WAIT
RST#
tGLQV
tELQX
tGLQX
VOH
VOL
High Z NOTE 1 High Z
tAVAV
VIH
VIL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
High Z VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
NOTE:
1. WAIT shown active low.
A21-3 (A)
Rev. 0.1 1
sharp
LHF64N08 29
V
IH
V
IL
VALID
OUTPUT
VALID
ADDRESS
tAVVH
tAVCH tCHAX
tVHAX
tAVQV
tVLVH
tVLCH
tVLQV
tCHQV
tGHQZ
tEHQZ
tELVH
tELCH
tELQV
tOH
tCHQX
tVHVL
High Z
NOTE 1
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
(D/Q)
(W)
(G)
(E)
(V)
(A)A20-0
VIH
VIL
(C)CLK
DQ15-0
ADV#
CE#
OE#
WE#
tGLQV
tELQX
tGLQX
NOTE:
1. Depending upon the frequency configuration code in the read configuration register, insert clock cycles:
Frequency Configuration Code 2, insert two clock cycles
Frequency Configuration Code 3, insert three clock cycles
Frequency Configuration Code 4, insert four clock cycles
Frequency Configuration Code 5, insert five clock cycles
2. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
VOH
VOL
(T)WAIT High Z NOTE 2 High Z
tELTV tCHTV
tEHTZ
Figure 13. AC Waveform for Single Synchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
A21-0 (A)
Rev. 0.1 1
sharp
LHF64N08 30
V
IH
V
IL
VALID
ADDRESS
tAVVH
tAVCH tCHAX
tVHAX
tAVQV
tVLVH
tVLCH
tVLQV
tGHQZ
tEHQZ
tELVH
tELCH
tELQV
tOH
tCHQX tCHQV
tVHVL
High Z
NOTE 1
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
(D/Q)
(W)
(G)
(E)
(V)
(A)A20-0
VIH
VIL
(C)CLK
DQ15-0
ADV#
CE#
OE#
WE#
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tELQX
tGLQX
NOTE:
1. Depending upon the frequency configuration code in the read configuration register, insert clock cycles:
Frequency Configuration Code 2, insert two clock cycles
Frequency Configuration Code 3, insert three clock cycles
Frequency Configuration Code 4, insert four clock cycles
Frequency Configuration Code 5, insert five clock cycles
2. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
tGLQV
VOH
VOL
(T)WAIT High Z NOTE 2 High Z
tELTV tCHTV
tEHTZ
Figure 14. AC Waveform for Synchronous Burst Mode Read Operations
from Main Blocks or Parameter Blocks (4 Word Burst: RCR.2-0=001)
A21-0 (A)
Rev. 0.1 1
sharp
LHF64N08 31
VIH
VIL
VALID
ADDRESS
tAVVH
tAVCH tCHAX
tVH AX
tAVQV
tVLVH
tVLCH
tVLQV
tELVH
tELCH
tELQV
tVHVL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
(W)
(G)
(E)
(V)
(A)A20-0
VIH
VIL
(C)CLK
ADV#
CE#
OE#
WE#
NOTE:
1. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
VOH
VOL
(D/Q)
DQ15-0 High Z
VOH
VOL
(D/Q)
DQ15-0 High Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VOH
VOL
(D/Q)
DQ15-0 High Z
VOH
VOL
(T)WAIT High Z NOTE 1
tELTV
VOH
VOL
(T)WAIT High Z NOTE 1
tELTV tCHTV
VOH
VOL
(T)WAIT High Z NOTE 1
tELTV tCHTV
tCHTV
INVALID
OUTPUT INVALID
OUTPUT INVALID
OUTPUT INVALID
OUTPUT INVALID
OUTPUT INVALID
OUTPUT
tCHTV
tCHTV
tCHQV tCHQX
tELQX
tGLQX
tGL QV
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT INVALID
OUTPUT INVALID
OUTPUT
tCHQV tCHQX
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tCHQV tCHQX
4 Word Burst: RCR.2-0 = 001
8 Word Burst: RCR.2-0 = 010
Continuous Burst: RCR.2-0 = 111
Figure 15. AC Waveform for Synchronous Burst Mode Read Operations
from Main Blocks or Parameter Blocks (Frequency Configuration: RCR.13-11=010)
A21-0 (A)
Rev. 0.1 1
sharp
LHF64N08 32
VALID
OUTPUT INVALID
OUTPUT
NOTE 2
NOTE 1
VALID
OUTPUT
VALID
OUTPUT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
(D/Q)
(W)
(G)
(E)
(V)
(A)A20-0
VIH
VIL
(C)CLK
DQ15-0
ADV#
CE#
OE#
WE#
VOH
VOL
(T)WAIT
tCHTV tCHQX
tCHQV tCHQX
NOTES:
1. This delay occurs only in continuous burst mode or 4-, 8-word burst with no-wrap mode.
2. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
Figure 16. AC Waveform for an Output Delay when Continuous Burst Read
with Data Output Configurations Set to One Clock
A21-0 (A)
Rev. 0.1 1
sharp
LHF64N08 33
1.2.5 AC Characteristics - Write Operations(1), (2)
NOTES:
1. The timing characteristics for reading the status register during block erase, advanced factory program, (page buffer)
program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-
only operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Writ e pu lse widt h (t WP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.
5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
6. VPP should be held at VPP=VPPH1/2 until determination of block erase, (page buffer) program or OTP program success
(SR.1/3/4/5=0) and held at VPP=VPPH2 until determination of advanced factory program success (SR.0/1/3/4=0).
7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns.
8. Refer to Table 6 for valid address and data for block erase, advanced factory program, (page buffer) program, OTP
program or lock bit configuration.
VCC=1.7V-1.95V, TA=-40°C to +85°C
Symbol Parameter Notes Min. Max. Unit
tAVAV Write Cycle Time 60 ns
tPHWL (tPHEL)
RST# High Recovery to WE# (
CE#
) Going Low
3150 ns
tELWL (tWLEL)CE# (WE#) Setup to WE# (CE#) Going Low 0 ns
tWLWH (tELEH)WE# (CE#) Pulse Width 4 40 ns
tVLVH ADV# Pulse Width 10 ns
tDVWH (tDVEH)D ata Setup to WE# (C E#) Go ing High 8 40 ns
tAVWH (tAVEH)Address Setup to WE# (CE#) Going High 8 40 ns
tVLWH (tVLEH)ADV# Setup to WE# (CE#) Going High 40 ns
tAVVH Address Setup to ADV# Going High 10 ns
tWHEH (tEHWH)CE# (WE#) Hold from WE# (CE#) High 0 ns
tWHDX (tEHDX)D ata Hold from WE # (CE#) High 0 ns
tWHAX (tEHAX)A dd ress Hold from WE# (CE#) High 0 n s
tVHAX Address Hold from ADV# High 9 ns
tWHWL (tEHEL)WE# (CE#) Pulse Width High 5 20 ns
tSHWH (tSHEH)WP# High Setup to WE# (CE#) Going High 3 0 ns
tVVWH (tVVEH)V
PP Setup to WE# (CE#) Going High 3200 ns
tWHGL (tEHGL)Write Recovery before Read 30 ns
tQVSL WP# High Hold from Valid SRD 3, 6 0 ns
tQVVL VPP Hold from Va lid SRD 3, 6 0 ns
tWHR0 (tEHR0)WE# (CE#) High to SR.7 Going "0" 3, 7 tAVQV+
19 ns
Rev. 0.1 1
sharp
LHF64N08 34
VALID
ADDRESS VALID
ADDRESS VALID
ADDRESS
DATA IN DATA IN VALID
SRD
tAVVH
tVHVL
tVLVH
tVHAX tAVWH (tAVEH)
tVLWH (tVLEH)
tWHAX
(tEHAX)
tELWL (tWLEL)
tPHWL (tPHEL)
tWLWH
tWHWL (tEHEL)
tWHDX (tEHDX)tDVWH (tDVEH)
tSHWH (tSHEH)
tVVWH (tVVEH)
tWHQV1,2,3 (tEHQV1,2,3)
tQVSL
tQVVL
tWHEH (tEHWH)t
WHGL (tEHGL)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
(D/Q)
(W)
(G)
(E)
(V)
(A)
NOTE 1 NOTE 2 NOTE 3
NOTES 5, 6
NOTE 4
NOTE 6
NOTE 5
A20-0
DQ15-0
(V)
VPP
VIH
VPPH1,2
VPPLK
VIL
VIL
(P)
RST#
ADV#
CE#
OE#
WE#
VIH
VIL
(S)WP#
NOTES:
1. VCC power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, OE#, CE# and ADV# must be driven active, and WE# de-asserted.
(tELEH )
"1"
"0"
(R)SR.7
tWHR0 (tEHR0)
tAVAV
NOTES 5, 6
Figure 17. AC Waveform for Write Operations
A21-0 (A)
Rev. 0.1 1
sharp
LHF64N08 35
ABORT
COMPLETE
tPLPH
tPLPH
t2VPH
tPLRH tPHQV
tPHQV
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) RST# rising timing
RST#
RST#
VIL
VIH
VIL
VIH
VCC GND
VCC(min)
RST# VIL
VIH
SR.7="1"
VOH
VOL
(D/Q)
DQ15-0 VALID
OUTPUT
High Z
(P)
(P)
(P)
VOH
VOL
(D/Q)
DQ15-0 VALID
OUTPUT
High Z
VOH
VOL
(D/Q)
DQ15-0 VALID
OUTPUT
High Z
tPHQV
tVHQV
NOTES:
1. A reset time, tPHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC
Characteristics - Read-Only Operations for tPHQV.
2. tPLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, advanced factory program, (page buffer) program or OTP program operation is not
executi ng, the rese t w ill co mplete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and
also has been in stable there.
Reset AC Spec ific atio ns (VCC=1.7V-1.95V, TA=-40°C to +85°C)
Symbol Parameter Notes Min. Max. Unit
tPLPH RST# Low to Reset during Read
(RST# should be low durin g po we r-up.) 1, 2, 3 100 ns
tPLRH RST# Low to Reset during Erase or Program 1, 3, 4 20 µs
t2VPH VCC 1.7V to RST# High 1, 3, 5 100 ns
tVHQV VCC 1.7V to Output Delay 31ms
Figure 18 . AC Waveform for Rese t O perations
1.2.6 Reset Operations
Rev. 0.1 1
sharp
LHF64N08 36
1.2.7 Block Erase, Advanced Factory Program, (Page Buffer) Program and OTP Program
Performance(3)
NOTES:
1. Typical values measured at VCC=1.8V, VPP=1.8V or 12V, and TA=+25°C. Assumes corresponding lock bits
are not set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter
than tERES and its sequence is repeated, the block erase operation may not be finished.
6. AFP mode is allowed on ly w he n TA=+20°C t o +3 0°C.
7. In AFP mode, eight 4K-wor d parame te r b loc ks are pro grammed at a t ime. Specific at ion sho wn abo ve i s t he program t ime
per each 4K-word parameter block.
VCC=1.7V-1.95V, TA=-40°C to +85°C
Symbol Parameter Notes
PBP (Page
Buffer) is
Used, AFP
(Advanced
Factory
Program) is
Used or not
VPP=VPPH1
(In System) VPP=VPPH2
(In Manufacturing)
Unit
Min. Typ.(1)
Max.
(2)
Min. Typ.(1)
Max.
(2)
tWPB 4K-Word Parameter Block
Program Time
2 - 0.09 0.23 0.04 0.07 s
2 PBP 0.05 0.2 0.02 0.06 s
2, 6, 7 AFP - - 0.015 - s
tWMB 32K-Word Main Block
Program Time
2 - 0.72 1.8 0.31 0.6 s
2 PBP 0.34 1.4 0.17 0.5 s
2, 6 AFP - - 0.12 - s
tWHQV1/
tEHQV1 Word Program Time
2 - 22 150 9 130 µs
2 PBP 10 100 5 90 µs
2, 6 AFP - - 3.5 16 µs
tWHOV1/
tEHOV1 OTP Program Time 2 - 72 800 27 185 µs
tWHQV2/
tEHQV2
4K-Word Parameter Block
Erase Time 2 - 0.3 2.5 0.2 2.5 s
tWHQV3/
tEHQV3
32K-Word Main Block
Erase Time 2 - 0.6 4 0.5 4 s
tWHRH1/
tEHRH1
(Page Buffer) Program Suspend
Latency Time to Read 4- 510 510µs
tWHRH2/
tEHRH2
Bloc k Erase Suspend
Latency Time to Read 4- 520 520µs
tERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command 5 - 500 500 µs
tARES
Latency Time for AFP Set-Up 2, 6 AFP - - - 5 µs
Lat enc y for AFP Veri fy Transitio n 2, 6 A FP - - 2 .7 5 .6 µs
Latency for AFP Verify 2, 6 AFP - - 1.7 130 µs
Rev. 0.1 1
sharp
Rev. 1.10
i
A-1 RECOMMENDED OPERATING CO NDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
t2VPH
GND
VCC(min)
RST#
VIL
VIH
(P)
tPHQV
VPP *1
GND
VCCWH1/2
(V)
CE#
VIL
VIH
(E)
WE#
VIL
VIH
(W)
OE#
VIL
VIH
(G)
WP#
VIL
VIH
(S)
VOH
VOL
(D/Q)
DATA High Z Valid
Output
tVR
tFtELQV
tFtGLQV
(A)ADDRESS Valid
(RP#)
(VCCW)
tRor tF
Address
VIL
VIH
tAVQV tRor tF
tR
tR
*1 To prevent the unwanted writes, system designers should consider the design, which applies VPP (VCCW)
to 0V during read operations and VPPH1/2 (VCCWH1/2) during write or erase operations.
(VPPH1/2)
See the application note AP-007-SW-E for details.
VCC
VCCQ
ADV#
VIL
VIH
(V)
tFtVLQV tR
sharp
Rev. 1.10
ii
A-1.1.1 Rise a nd Fall Time
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 0.5 30000 µs/V
tRInput Sig nal R ise Time 1, 2 1 µs/V
tFInput Signal Fall Time 1, 2 1 µs/V
sharp
Rev. 1.10
iii
A-1.2 Glitch Noises
Do n ot in put the glitc h noises whic h a re below VIH (M in .) or abov e VIL ( M ax.) on add ress, dat a, reset , and cont rol s ign al s,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
(a) Acceptable Glitch Noises
Input Signal
VIH (Min.)
Input Signal
VIH (Min.)
Input Signal
VIL (Max.)
Input Signal
VIL (Max.)
(b)
NOT
Acceptable Glitch Noises
sharp
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Document No. Document Name
AP-001-SD-E Flash Memory Family Software Drivers
AP-006-PT-E Data Protection Method of SHARP Flash Memory
AP-007-SW-E RP#, VPP Electr ic P otential S wit chi ng Circuit
sharp
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
NORTH AMERICA EUROPE JAPAN
SHARP Microelectronics of the Americas
5700 NW Pacific Rim Blvd.
Camas, WA 98607, U.S.A.
Phone: (1) 360-834-2500
Fax: (1) 360-834-8903
Fast Info: (1) 800-833-9437
www.sharpsma.com
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Division of Sharp Electronics (Europe) GmbH
Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
Fax: (49) 40-2376-2232
www.sharpsme.com
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Electronic Components & Devices
22-22 Nagaike-cho, Abeno-Ku
Osaka 545-8522, Japan
Phone: (81) 6-6621-1221
Fax: (81) 6117-725300/6117-725301
www.sharp-world.com
TAIWAN SINGAPORE KOREA
SHARP Electronic Components
(Taiwan) Corporation
8F-A, No. 16, Sec. 4, Nanking E. Rd.
Taipei, Taiwan, Republic of China
Phone: (886) 2-2577-7341
Fax: (886) 2-2577-7326/2-2577-7328
SHARP Electronics (Singapore) PTE., Ltd.
438A, Alexandra Road, #05-01/02
Alexandra Technopark,
Singapore 119967
Phone: (65) 271-3566
Fax: (65) 271-3855
SHARP Electronic Components
(Korea) Corporation
RM 501 Geosung B/D, 541
Dohwa-dong, Mapo-ku
Seoul 121-701, Korea
Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
CHINA HONG KONG
SHARP Microelectronics of China
(Shanghai) Co., Ltd.
28 Xin Jin Qiao Road King Tower 16F
Pudong Shanghai, 201206 P.R. China
Phone: (86) 21-5854-7710/21-5834-6056
Fax: (86) 21-5854-4340/21-5834-6057
Head Office:
No. 360, Bashen Road,
Xin Development Bldg. 22
Waigaoqiao Free Trade Zone Shanghai
200131 P.R. China
Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
Shenzhen Representative Office:
Room 13B1, Tower C,
Electronics Science & Technology Building
Shen Nan Zhong Road
Shenzhen, P.R. China
Phone: (86) 755-3273731
Fax: (86) 755-3273735
