700 MHz to 2700 MHz Rx Mixer with Integrated
IF DGA, Fractional-N PLL, and VCO
Data Sheet
ADRF6620
Rev. 0 Document Feedback
Information fur
nished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Integrated fractional-N phase-locked loop (PLL)
RF input frequency range: 700 MHz to 2700 MHz
Internal local oscillator (LO) frequency range: 350 MHz to
2850 MHz
Input P1dB: 17 dBm
Output IP3: 45 dBm
Single-pole four-throw (SP4T) RF input switch
Digital step attenuator (DSA) range: 0 dB to 15 dB
Integrated RF tunable balun allowing single-ended 50 Ω input
Multicore integrated voltage controlled oscillator (VCO)
Digitally programmable variable gain amplifier (DGA)
−3 dB bandwidth: >600 MHz
Balanced 150 Ω IF output impedance
Programmable via 3-wire serial port interface (SPI)
Single 5 V supply
APPLICATIONS
Wireless receivers
Digital predistortion (DPD) receivers
FUNCTIONAL BLOCK DIAGRAM
LOCK_DET
VPTAT
LOIN–
VTUNE
LOIN+
÷1, ÷2,
÷4, ÷8
CHARGE
PUMPCP
N = INT +
REFIN
MUXOUT
RFIN0 IFOUT1–
MXOUT+
CS
SCLK
SDIO
MXOUT–
IFIN+
IFIN–
LOIN+
LOIN–
VTUNE
CP
SERIAL
PORT
INTERFACE LDO
VCO LDO
3.3V
IFOUT1+
IFOUT2–
IFOUT2+
LDO
2.5 V
RFSW0
RFSW1
RFIN1
RFIN2
RFIN3
÷2
÷8
÷4
÷2
×1
×2
+
PFD
FRAC
MOD
11489-001
DECL2
DECL4
DECL1
Figure 1.
GENERAL DESCRIPTION
The ADRF6620 is a highly integrated active mixer and synthesizer
that is ideally suited for wireless receiver subsystems. The feature
rich device consists of a high linearity broadband active mixer;
an integrated fractional-N PLL; low phase noise, multicore VCO;
and IF DGA. In addition, the ADRF6620 integrates a 4:1 RF
switch, an on-chip tunable RF balun, programmable RF attenuator,
and low dropout (LDO) regulators. This highly integrated device
fits within a small 7 mm × 7 mm footprint.
The high isolation 4:1 RF switch and on-chip tunable RF balun
enable the ADRF6620 to support four single-ended 50 Ω
terminated RF inputs. A programmable attenuator ensures
optimal RF input drive to the high linearity mixer core. The
integrated DSA has an attenuation range of 0 dB to 15 dB with
a step size of 1 dB.
The ADRF6620 offers two alternatives for generating the dif-
ferential LO input signal: externally, via a high frequency, low
phase noise LO signal, or internally, via the on-chip fractional-N
PLL synthesizer. The integrated synthesizer enables continuous
LO coverage from 350 MHz to 2850 MHz. The PLL reference
input can support a wide frequency range because the divide and
multiply blocks can be used to increase or decrease the reference
frequency to the desired value before it is passed to the phase
frequency detector (PFD).
The integrated high linearity DGA provides an additional gain
range from 3 dB to 15 dB in steps of 0.5 dB for maximum flexibility
in driving an analog-to-digital converter (ADC).
The ADRF6620 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 48-lead, RoHS-compliant,
7 mm × 7 mm LFCSP package with an exposed pad. Performance
is specified over the −40°C to +85°C temperature range.
ADRF6620 Data Sheet
Rev. 0 | Page 2 of 52
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
RF Input to IF DGA Output System Specifications ................. 3
Synthesizer/PLL Specifications ................................................... 4
RF Input to Mixer Output Specifications .................................. 6
IF DGA Specifications ................................................................. 7
Digital Logic Specifications ......................................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
RF Input to DGA Output System Performance ..................... 11
Phase-Locked Loop (PLL) ......................................................... 13
RF Input to Mixer Output Performance ................................. 17
IF DGA ........................................................................................ 20
Spurious Performance................................................................ 22
Theory of Operation ...................................................................... 24
RF Input Switches ....................................................................... 24
Tunable Balun ............................................................................. 25
RF Digital Step Attenuator (DSA) ............................................ 25
Active Mixer ................................................................................ 25
Digitally Programmable Variable Gain Amplifier (DGA) .... 25
LO Generation Block ................................................................. 26
Serial Port Interface (SPI) ......................................................... 27
Basic Connections ...................................................................... 28
RF Input Balun Insertion Loss Optimization ......................... 30
IP3 and Noise Figure Optimization ......................................... 31
Interstage Filtering Requirements ............................................ 35
IF DGA vs. Load ......................................................................... 38
ADC Interfacing ......................................................................... 39
Power Modes ............................................................................... 40
Layout .......................................................................................... 40
Register Map ................................................................................... 41
Register Address Descriptions ...................................................... 42
Register 0x00, Reset: 0x00000, Name: SOFT_RESET ........... 42
Register 0x01, Reset: 0x8B7F, Name: Enables ........................ 42
Register 0x02, Reset: 0x0058, Name: INT_DIV ..................... 43
Register 0x03, Reset: 0x0250, Name: FRAC_DIV ................. 43
Register 0x04, Reset: 0x0600, Name: MOD_DIV .................. 43
Register 0x20, Reset: 0x0C26, Name: CP_CTL ...................... 44
Register 0x21, Reset: 0x0003, Name: PFD_CTL .................... 45
Register 0x22, Reset: 0x000A, Name: FLO_CTL ................... 46
Register 0x23, Reset: 0x0000, Name: DGA_CTL................... 47
Register 0x30, Reset: 0x00000, Name: BALUN_CTL ............ 48
Register 0x31, Reset: 0x08EF, Name: MIXER_CTL .............. 48
Register 0x40, Reset: 0x0010, Name: PFD_CTL2 .................. 49
Register 0x42, Reset: 0x000E, Name: DITH_CTL1 ............... 50
Register 0x43, Reset: 0x0001, Name: DITH_CTL2 ............... 50
Outline Dimensions ....................................................................... 51
Ordering Guide .......................................................................... 51
REVISION HISTORY
7/13—Revision 0: Initial Version
Data Sheet ADRF6620
Rev. 0 | Page 3 of 52
SPECIFICATIONS
VCCx = 5 V, T A = 25°C, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
LO INPUT
Internal LO Frequency Range 350 2850 MHz
External LO Frequency Range LO_DIV_A = 00 350 3200 MHz
LO Input Level −6 0 +6 dBm
LO Input Impedance 50 Ω
RF INPUT
Input Frequency 700 2700 MHz
Input Return Loss 12 dB
Input Impedance
Ω
RF DIGITAL STEP AT TENUATOR
Attenuation Range Step size = 1 dB 0 15 dB
POWER SUPPLY 4.75 5.0 5.25 V
Power Consumption LO output buffer disabled
External LO + IF DGA enabled 1.3 W
Internal LO + IF DGA enabled 1.7 W
Only IF DGA enabled 0.6 W
Power-Down Current 6 mA
RF INPUT TO IF DGA OUTPUT SYSTEM SPECIFICATIONS
VCCx = 5 V, T A = 25°C, high-side LO injection, fIF = 200 MHz, internal LO frequency, IF DGA output load = 150 Ω, and 2 V p-p differential
output with third-order low-pass filter, unless otherwise noted. For mixer settings for maximum linearity, see Table 16. All losses from
input and output traces and baluns are de-embedded from results
Table 2. RF Switch + Balun + RF Attenuator + Mixer + IF DGA
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE AT fRF = 900 MHz fIF = 200 MHz
Voltage Conversion Gain 12 dB
Output P1dB 18 dBm
Output IP3 1 V p-p each output tone, 1 MHz tone spacing 43 dBm
Output IP2 1 V p-p each output tone, 1 MHz tone spacing 78 dBm
Noise Figure Noise figure optimized 16 dB
DYNAMIC PERFORMANCE AT
f
RF
=
1900 MHz
f
IF
= 200 MHz
Voltage Conversion Gain 11 dB
Output P1dB 18 dBm
Output IP3 1 V p-p each output tone, 1 MHz tone spacing 45 dBm
Output IP2 1 V p-p each output tone, 1 MHz tone spacing 75 dBm
Noise Figure Noise figure optimized 18.5 dB
DYNAMIC PERFORMANCE AT fRF = 2100 MHz fIF = 200 MHz dB
Voltage Conversion Gain 10.5 dBm
Output P1dB 18 dBm
Output IP3 1 V p-p each output tone, 1 MHz tone spacing 45 dBm
Output IP2 1 V p-p each output tone, 1 MHz tone spacing 66 dBm
Noise Figure Noise figure optimized 19 dB
DYNAMIC PERFORMANCE AT fRF = 2700 MHz fIF = 200 MHz
Voltage Conversion Gain 9 dB
Output P1dB 18 dBm
Output IP3 1 V p-p each output tone, 1 MHz tone spacing 44 dBm
Output IP2
1 V p-p each output tone, 1 MHz tone spacing
dBm
Noise Figure Noise figure optimized 21 dB
ADRF6620 Data Sheet
Rev. 0 | Page 4 of 52
SYNTHESIZER/PLL SPECIFICATIONS
VCCx = 5 V, T A = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, and loop filter bandwidth = 120 kHz, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
PLL REFERENCE
PLL Reference Frequency 12 464 MHz
PLL Reference Level For PLL lock condition −15 +4 +14 dBm
PFD FREQUENCY 24 58 MHz
INTERNAL VCO RANGE 2800 5700 MHz
OPEN-LOOP VCO PHASE NOISE VTUNE = 2 V, LO_DIV_A = 00
fVCO2 = 3.4 GHz 1 kHz offset −39 dBc/Hz
10 kHz offset −81 dBc/Hz
100 kHz offset −103 dBc/Hz
800 kHz offset −123 dBc/Hz
1 MHz offset −125 dBc/Hz
6 MHz offset −143 dBc/Hz
10 MHz offset −147 dBc/Hz
40 MHz offset −155 dBc/Hz
VCO sensitivity (KV) 88 MHz/V
fVCO1 = 4.6 GHz 1 kHz offset −39 dBc/Hz
10 kHz offset −74 dBc/Hz
100 kHz offset −101 dBc/Hz
800 kHz offset −123 dBc/Hz
1 MHz offset
−125
dBc/Hz
6 MHz offset −143 dBc/Hz
10 MHz offset −147 dBc/Hz
40 MHz offset −156 dBc/Hz
VCO sensitivity (KV) 89 MHz/V
fVCO0 = 5.5 GHz 1 kHz offset −39 dBc/Hz
10 kHz offset −69 dBc/Hz
100 kHz offset −99 dBc/Hz
800 kHz offset −121 dBc/Hz
1 MHz offset −124 dBc/Hz
6 MHz offset −142 dBc/Hz
10 MHz offset −146 dBc/Hz
40 MHz offset −155 dBc/Hz
VCO sensitivity (KV) 72 MHz/V
SYNTHESIZER SPECIFICATIONS
Measured at LO output, LO_DIV_A = 01
fLO = 1.710 GHz, fVCO2 = 3.420 GHz fREF = 153.6 MHz, fPFD = 38.4 MHz, 120 kHz loop filter
fPFD Spurs fPFD × 1 −83 dBc
fPFD × 2 −89 dBc
fPFD × 3 −90 dBc
fPFD × 4 −93 dBc
Closed-Loop Phase Noise 1 kHz offset −97 dBc/Hz
10 kHz offset −110 dBc/Hz
100 kHz offset −107 dBc/Hz
800 kHz offset −128 dBc/Hz
1 MHz offset −132 dBc/Hz
6 MHz offset −144 dBc/Hz
10 MHz offset −152 dBc/Hz
40 MHz offset −158 dBc/Hz
Integrated Phase Noise 10 kHz to 40 MHz integration bandwidth 0.21 ° rms
Figure of Merit (FOM)1 −222 dBc/Hz
Data Sheet ADRF6620
Rev. 0 | Page 5 of 52
Parameter Test Conditions/Comments Min Typ Max Unit
fLO = 2.305 GHz, fVCO1 = 4.610 GHz
fPFD Spurs fPFD × 1 −84 dBc
fPFD × 2 −87 dBc
fPFD × 3 −91 dBc
f
PFD
× 4
−92
dBc
Closed-Loop Phase Noise 1 kHz offset −93 dBc/Hz
10 kHz offset 105 dBc/Hz
100 kHz offset −103 dBc/Hz
800 kHz offset −116 dBc/Hz
1 MHz offset −130 dBc/Hz
6 MHz offset −144 dBc/Hz
10 MHz offset −152 dBc/Hz
40 MHz offset −156 dBc/Hz
Integrated Phase Noise 10 kHz to 40 MHz integration bandwidth 0.3 ° rms
Figure of Merit1 −222 dBc/Hz
fLO = 2.75 GHz, fVCO2 = 5.5 GHz
fPFD Spurs fPFD × 1 −82 dBc
fPFD × 2 −88 dBc
fPFD × 3 −93 dBc
fPFD × 4 −96 dBc
Closed-Loop Phase Noise 1 kHz offset −93 dBc/Hz
10 kHz offset
−101
dBc/Hz
100 kHz offset −99 dBc/Hz
800 kHz offset −122 dBc/Hz
1 MHz offset −128 dBc/Hz
6 MHz offset −144 dBc/Hz
10 MHz offset −151 dBc/Hz
40 MHz offset −154 dBc/Hz
Integrated Phase Noise 10 kHz to 40 MHz integration bandwidth 0.38 ° rms
Figure of Merit1 −222 dBc/Hz
1 Figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10 log 10(fPFD) – 20 log 10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 160 MHz
and fREF power = 4 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
ADRF6620 Data Sheet
Rev. 0 | Page 6 of 52
RF INPUT TO MIXER OUTPUT SPECIFICATIONS
VCCx = 5 V, TA = 25°C, high-side LO injection, fIF = 200 MHz, external LO frequency, and RF attenuation = 0 dB, unless otherwise noted.
Mixer settings configured for maximum linearity (see Table 16). All losses from input and output traces and baluns are de-embedded
from results.
Table 4. RF Switch + Balun + RF Attenuator + Mixer
Parameter Test Conditions/Comments Min Typ Max Unit
VOLTAGE GAIN Differential 255 Ω load −4 dB
MIXER OUTPUT IMPEDANCE Differential (see Figure 87) 255 Ω
DYNAMIC PERFORMANCE AT fRF= 900 MHz
Voltage Conversion Gain −2 dB
Input P1dB 17 dBm
Input IP3 −5 dBm each input tone, 1 MHz tone spacing 40 dBm
Input IP2 −5 dBm each input tone, 1 MHz tone spacing 65 dBm
Noise Figure 15 dB
LO to RF Leakage −70 dBm
RF to LO Leakage −60 dBc
LO to IF Leakage −32 dBm
RF to IF Leakage With respect to 0 dBm RF input power −45 dBc
Isolation1 Isolation between RFIN0 and RFIN3 −52 dBc
DYNAMIC PERFORMANCE AT fRF =1900 MHz
Voltage Conversion Gain −3 dB
Input P1dB 17 dBm
Input IP3 −5 dBm each input tone, 1 MHz tone spacing 40 dBm
Input IP2 −5 dBm each input tone, 1 MHz tone spacing 62 dBm
Noise Figure 17 dB
LO to RF Leakage −60 dBm
RF to LO Leakage −50 dBc
LO to IF Leakage −35 dBm
RF to IF Leakage With respect to 0 dBm RF input power −43 dBc
Isolation1 Isolation between RFIN0 and RFIN3 −47 dBc
DYNAMIC PERFORMANCE AT fRF = 2100 MHz
Voltage Conversion Gain −3.5 dB
Input P1dB 18 dBm
Input IP3 −5 dBm each input tone, 1 MHz tone spacing 40 dBm
Input IP2 −5 dBm each input tone, 1 MHz tone spacing 54.5 dBm
Noise Figure 18 dB
LO to RF Leakage −60 dBm
RF to LO Leakage −40 dBc
LO to IF Leakage −35 dBm
RF to IF Leakage With respect to 0 dBm RF input power −40 dBc
Isolation1 Isolation between RFIN0 and RFIN3 −45 dBc
DYNAMIC PERFORMANCE AT fRF = 2700 MHz
Voltage Conversion Gain −4.7 dB
Input P1dB 19 dBm
Input IP3 −5 dBm each input tone, 1 MHz tone spacing 40 dBm
Input IP2 −5 dBm each input tone, 1 MHz tone spacing 56 dBm
Noise Figure 21 dB
LO to RF Leakage −60 dBm
RF to LO Leakage −45 dBc
LO to IF Leakage −40 dBm
RF to IF Leakage With respect to 0 dBm RF input power −42 dBc
Isolation1 Isolation between RFIN0 and RFIN3 −41 dBc
1 Isolation between RF inputs. An input signal was applied to RFIN0 while RFIN1 to RFIN3 were terminated with 50 Ω. The IF signal amplitude was measured at the mixer
output. The internal switch was then configured for RFIN3, and the feedthrough was measured as a delta from the fundamental.
Data Sheet ADRF6620
Rev. 0 | Page 7 of 52
IF DGA SPECIFICATIONS
VCCx = 5 V, T A = 25°C, RS = RL = 150 Ω differential, fIF = 200 MHz, 2 V p-p differential output,unless otherwise noted. All losses from
input and output traces and baluns are de-embedded from results.
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
BANDWIDTH
−1 dB Bandwidth VOUT = 2 V p-p 500 MHz
−3 dB Bandwidth VOUT = 2 V p-p 700 MHz
SLEW RATE 5.5 V/ns
INPUT STAGE
Input P1dB At minimum gain 17 dBm
Input Impedance 150 Ω
Common-Mode Input Voltage 1.5 V
Common-Mode Rejection Ratio (CMRR) 50 dB
GAIN
Power/Voltage Gain, Step Size = 0.5 dB 3 15 dB
Gain Flatness 50 MHz < fC < 200 MHz 0.2 dB
Gain Conformance Error ±0.1 dB
Gain Temperature Sensitivity 0.008 dB/C
Gain Step Response 15 ns
OUTPUT STAGE
Output P1dB 18 dBm
Output Impedance See Figure 88 150 Ω
NOISE/HARMONIC PERFORMANCE at 200 MHz
Output IP3 1 V p-p each output tone, 1 MHz tone spacing 45 dBm
Output IP2 1 V p-p each output tone, 1 MHz tone spacing 63 dBm
HD2 VOUT = 2 V p-p −87 dBc
HD3 VOUT = 2 V p-p −84 dBc
Noise Figure 10 dB
ADRF6620 Data Sheet
Rev. 0 | Page 8 of 52
DIGITAL LOGIC SPECIFICATIONS
Table 6.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SERIAL PORT INTERFACE TIMING
Input Voltage High VIH 1.4 V
Input Voltage Low VIL 0.70 V
Output Voltage High VOH IOH = −100 µA 2.3 V
Output Voltage Low VOL IOL = +100 µA 0.2 V
Serial Clock Period tSCLK 38 ns
Setup Time Between Data and Rising Edge of SCLK tDS 8 ns
Hold Time Between Data and Rising Edge of SCLK tDH 8 ns
Setup Time Between Falling Edge of CS and SCLK tS 10 ns
Hold Time Between Rising Edge of CS and SCLK tH 10 ns
Minimum Period SCLK Can Be in Logic High State tHIGH 10 ns
Minimum Period SCLK Can Be in Logic Low State
t
LOW
10
ns
Maximum Time Delay Between Falling Edge of SCLK and Output
Data Valid for a Read Operation
tACCESS 231 ns
Maximum Time Delay Between CS Deactivation and SDIO Bus
Return to High Impedance
tZ 5 ns
Timing Diagram
t
S
t
DS
t
DH
t
HIGH
t
LOW
t
SCLK
t
H
DON' T CARE
DON' T CARE
A5 A4 A3 A2
A1 A0
D15 D14 D13 D3 D2 D1 D0
DON' T CARE
DON' T CARE
SCLK
SDIO R/W
t
Z
t
ACCESS
A6
11489-002
CS
Figure 2. Serial Port Interface Timing
Data Sheet ADRF6620
Rev. 0 | Page 9 of 52
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
VCCx −0.5 V to +5.5 V
RFSW0, RFSW1 −0.3 V to +3.6 V
RFIN0, RFIN1, RFIN2, RFIN3 20 dBm
LOIN−, LOIN+ 16 dBm
REFIN −0.3 V to +3.6 V
IFIN−, IFIN+ −1.2 V to +3.6 V
CS, SCLK, SDIO −0.3 V to +3.6 V
VTUNE −0.3 V to +3.6 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 8. Thermal Resistance
Package Type θJC Unit
48-Lead LFCSP 1.62 °C/W
ESD CAUTION
ADRF6620 Data Sheet
Rev. 0 | Page 10 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
VCC3
VCC4
IFIN–
IFIN+
GND
MXOUT+
MXOUT–
GND
LOOUT+
LOOUT–
GND
VCC5
48
47
46
45
44
43
42
41
40
39
38
37
GND
VTUNE
DECL4
LOIN+
LOIN–
MUXOUT
SDIO
SCLK
CS
RFSW1
RFSW0
DECL3
1
2
3
4
5
6
7
8
9
10
11
12
VCC1
DECL1
CP
GND
GND
REFIN
DECL2
IFOUT1+
IFOUT1–
IFOUT2+
IFOUT2–
VCC2
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND
PLANE WITH LOW THERMAL IMPE DANCE .
RFIN0
GND
GND
RFIN1
GND
GND
RFIN2
GND
GND
RFIN3
GND
35 GND36
34
33
32
31
30
29
28
27
26
25
TOP VIEW
(Not t o Scale)
PIN 1
INDICATOR
ADRF6620
11489-003
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions1
Pin No. Mnemonic Description
1, 12, 13, 14, 24 VCC1, VCC2, VCC3,
VCC4, VCC5
5 V Power Supplies. Decouple all power supply pins to ground, using 100 pF and 0.1 µF
capacitors. Place the decoupling capacitors near the pins.
2, 7, 37, 46 DECL1, DECL2,
DECL3, DECL4
Decouple all DECLx pins to ground, using 100 pF, 0.1 µF, and 10 µF capacitors. Place the
decoupling capacitors near the pins.
3 CP Synthesizer Charge Pump Output. Connect this pin to the VTUNE pin through the loop filter.
4, 5, 17, 20, 23, 25, 27,
28, 30, 31, 33, 34, 36, 48
GND Ground.
6 REFIN Synthesizer Reference Frequency Input.
8 to 11 IFOUT1+, IFOUT1−,
IFOUT2+, IFOUT2−
IF DGA Outputs. Connect the positive pins such that IFOUT1+ and IFOUT2+ are tied
together. Similarly, connect the negative pins such that IFOUT1− and IFOUT2− are tied
together. Refer to the Layout section for a recommended layout that minimizes parasitic
capacitance and optimizes performance.
15, 16 IFIN−, IFIN+ Differential IF DGA Inputs. AC couple the mixer outputs to the IF DGA inputs.
18, 19
MXOUT+, MXOUT−
Differential Mixer Outputs. AC couple the mixer outputs to the IF DGA inputs.
21, 22 LOOUT+, LOOUT− Differential LO Outputs. The differential output impedance is 50 Ω.
26, 29, 32, 35 RFIN3, RFIN2,
RFIN1, RFIN0
RF Inputs. These single-ended RF inputs have a 50 Ω input impedance and must be
ac-coupled.
38, 39 RFSW0, RFSW1 External Pin Control of RF Input Switches. For logic high, connect these pins to 2.5 V logic.
40 CS SPI Chip Select, Active Low. 3.3 V tolerant logic levels.
41
SCLK
SPI Clock. 3.3 V tolerant logic levels.
42 SDIO SPI Data Input or Output. 3.3 V tolerant logic levels.
43 MUXOUT Multiplexer Output. This output pin provides the PLL reference signal or the PLL lock
detect signal.
44, 45 LOIN−, LOIN+ Differential Local Oscillator Inputs. The differential input impedance is 50 Ω.
47 VTUNE VCO Tuning Voltage. Connect this pin to the CP pin through the loop filter.
49
EPAD
Exposed Pad. The exposed pad must be connected to a ground plane with low thermal
impedance.
1 For more connection information about these pins, see Table 14.
Data Sheet ADRF6620
Rev. 0 | Page 11 of 52
TYPICAL PERFORMANCE CHARACTERISTICS
RF INPUT TO DGA OUTPUT SYSTEM PERFORMANCE
VCCx = 5 V, T A = 25°C, RFDSA_SEL = 00 (0 dB), RFSW_SEL = 00 (RFIN0), BAL_CIN and BAL_COUT optimized for maximum gain;
MIXER_BIAS, MIXER_RDAC, and MIXER_CDAC optimized for highest linearity, DGA at maximum gain; third-order low-pass filter
between the mixer output and IF DGA input; high-side LO, internal LO frequency, IF frequency = 200 MHz, unless otherwise noted. All
losses from input and output traces and baluns are de-embedded from results.
5
6
7
8
9
10
11
12
13
14
15
600 1000 1400 1800 2200 2600 3000
GAIN (d B)
RF FREQ UE NC Y (MHz)
TA = –40° C
TA = +85°C
TA = +25°C
11489-004
Figure 4. Gain vs. RF Frequency; IF Frequency = 200 MHz
0
2
4
6
8
10
12
14
16
18
20
22
600 1000 1400 1800 2200 2600 3000
OP 1dB (d Bm)
RF FREQ UE NC Y (MHz)
T
A
= –40° C
T
A
= +85°C
T
A
= +25°C
11489-005
Figure 5. OP1dB vs. RF Frequency
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
50 100 150 200 250 300 350 400 450 500
GAIN (d B)
IF FREQUENCY (MHz)
RF FREQ UE NC Y = 900M Hz
RF FREQ UE NC Y = 2700M Hz
RF FREQ UE NC Y = 2100M Hz
RF FREQ UE NC Y = 1900M Hz
11489-007
Figure 6. Gain vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
IF FREQUENCY (MHz)
0
2
4
6
8
10
12
14
16
18
20
22
50 100 150 200 250 300 350 400 450 500
OP 1dB (d Bm)
RF FREQ UE NC Y = 900M Hz
RF FREQ UE NC Y = 1900M Hz
RF FREQ UE NC Y = 2100M Hz
RF FREQ UE NC Y = 2700M Hz
11489-008
Figure 7. OP1dB vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
ADRF6620 Data Sheet
Rev. 0 | Page 12 of 52
RF F RE QUENC Y (MHz)
5
15
25
35
45
55
65
75
85
95
600 1000 1400 1800 2200 2600 3000
OIP2 (dBm), OIP3 (dBm)
T
A
= –40° C T
A
= +85°C
T
A
= +25°C
OI P 2 ( dBm)
OI P 3 ( dBm)
11489-006
Figure 8. OIP2/OIP3 vs. RF Frequency; Measured on 1 V p-p on Each Tone
at DGA Output
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
50 100 150 200 250 300 350 400 450 500
GAIN (d B)
IF FREQUENCY (MHz)
LO FREQUENCY = 1100MHz
LO FREQUENCY = 2300MHz
LO FREQUENCY = 2100MHz
11489-110
Figure 9. Gain vs. IF Frequency; RF Sweep with Fixed LO;
IF and RF Roll-Off; Measured on 1 V p-p on Each Tone at DGA Output
5
15
25
35
45
55
65
75
85
95
012345678910 11 12 13 14 15
OIP2 (dBm), OIP3 (dBm)
RFDSA
RF FREQ UE NC Y = 900M Hz
RF FREQ UE NC Y = 1900M Hz
RF FREQ UE NC Y = 2100M Hz
RF FREQ UE NC Y = 2700M Hz
OIP2 (dBm)
OIP3 (dBm)
11489-111
Figure 10. OIP2/OIP3 vs. RFDSA; Measured on 1 V p-p on Each Tone at
DGA Output
IF FREQUENCY (MHz)
5
15
25
35
45
55
65
75
85
95
50 100 150 200 250 300 350 400 450 500
OIP2 (dBm), OIP3 (dBm)
RF FREQ UE NC Y = 900M Hz
RF FREQ UE NC Y = 1900M Hz
RF FREQ UE NC Y = 2100M Hz
RF FREQ UE NC Y = 2700M Hz
OIP3 (dBm)
OIP2 (dBm
)
11489-009
Figure 11. OIP2/OIP3 vs. IF Frequency; LO Sweep with Fixed RF,
IF Roll-Off; Measured on 1 V p-p on Each Tone at DGA Output
OIP3 (dBm)
OIP2 (dBm)
IF FREQUENCY (MHz)
5
15
25
35
45
55
65
75
85
95
50 100 150 200 250 300 350 400 450 500
OIP2 (dBm), OIP3 (dBm)
LO FREQUENCY = 1100MHz LO FREQUENCY = 2300MHz
LO FREQUENCY = 2100MHz
11489-112
Figure 12. OIP2/OIP3 vs. IF Frequency; RF Sweep with Fixed LO;
IF and RF Roll-Off; Measured on 1 V p-p on Each Tone at DGA Output
0
50
100
150
200
250
300
350
400
450
500
600 1000 1400 1800 2200 2600 3000
SUPPLY CURRENT (mA)
RF FREQ UE NC Y (MHz)
T
A
= –40° C
T
A
= +85°C
T
A
= +25°C
11489-113
Figure 13. Supply Current vs. RF Frequency
Data Sheet ADRF6620
Rev. 0 | Page 13 of 52
PHASE-LOCKED LOOP (PLL)
VCCx = 5 V, T A = 25°C, 120 kHz loop filter, fREF = 153.6 MHz, PLL reference amplitude = 4 dBm, fPFD = 38.4 MHz, measured at LO
output, unless otherwise noted.
–160
–150
–140
–130
–120
–
110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1k 10k 100k 1M 10M 100M
PHASE NOISE (d Bc/Hz)
OFFSET FREQUENCY (Hz)
11489-010
Figure 14. VCO2 Open-Loop VCO Phase Noise vs. Offset Frequency;
fVCO2 = 3.4 GHz, LO_DIV_A = 00, VTUNE = 2 V
–160
–150
–140
–130
–120
–
110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1k 10k 100k 1M 10M 100M
PHASE NOISE (d Bc/Hz)
OFFSET FREQUENCY (Hz)
11489-011
Figure 15. VCO1 Open-Loop Phase Noise vs. Offset Frequency;
fVCO1 = 4.6 GHz, LO_DIV_A = 00, VTUNE = 2 V
–160
–150
–140
–130
–120
–
110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1k 10k 100k 1M 10M 100M
PHASE NOISE (d Bc/Hz)
OFFSET FREQUENCY (Hz)
11489-012
Figure 16. VCO0 Open-Loop Phase Noise vs. Offset Frequency;
fVCO0 = 5.5 GHz, LO_DIV_A = 00, VTUNE = 2 V
1k 10k 100k 1M 10M 100M
OFFSET FREQUENCY (Hz)
–160
–155
–150
–145
–140
–135
–130
–125
–120
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
PHASE NOISE (d Bc/Hz)
LO_DIV_A = 00
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
11489-013
Figure 17. VCO2 Closed-Loop Phase Noise for Various LO_DIV_A Dividers vs.
Offset Frequency; fVCO2 = 3.4 GHz
1k 10k 100k 1M 10M 100M
OFFSET FREQUENCY (Hz)
–160
–155
–150
–145
–140
–135
–130
–125
–120
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
PHASE NOISE (d Bc/Hz)
LO_DIV_A = 00
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
11489-014
Figure 18. VCO1 Closed-Loop Phase Noise for Various LO_DIV_A Dividers vs.
Offset Frequency; fVCO1 = 4.6 GHz
1k 10k 100k 1M 10M 100M
OFFSET FREQUENCY (Hz)
–160
–155
–150
–145
–140
–135
–130
–125
–120
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
PHASE NOISE (d Bc/Hz)
LO_DIV_A = 00
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
11489-015
Figure 19. VCO0 Closed-Loop Phase Noise for Various LO_DIV_A Dividers vs.
Offset Frequency; fVCO0 = 5.532 GHz
ADRF6620 Data Sheet
Rev. 0 | Page 14 of 52
230
225
220
215
210
205
200
1400 1600 1800 2000 2200 2400 2600 2800
FOM (dBc/Hz/Hz)
LO FREQUENCY (MHz)
11489-016
TA = –40° C
TA = +25°C
TA = +85°C
Figure 20. PLL Figure of Merit (FOM) vs. LO Frequency
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PHASE NOISE (dBc/Hz)
VCO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C 1kHz OF FSE T
10kHz OFF S E T
100kHz OFF S E T
800kHz OFF S E T
6MHz OFFSET
11489-017
2579 2979 3379 3779 4179 4579 4979 5379 5779
Figure 21. Open-Loop Phase Noise vs. VCO Frequency;
LO_DIV_A = 00
11489-018
–160
–155
–150
–95
–145
–140
–135
–130
–125
–120
–115
–110
–105
–100
–90
–85
PHASE NOISE (dBc/Hz)
LO FREQUENCY (MHz)
1384 1584 1784 1984 2184 2384 2584 2784
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C 1kHz O FF S E T
50kHz OFF S E T
400kHz OFF S E T
1MHz OFFSET
10MHz OFFSET
–165
Figure 22. 120 kHz Bandwidth Loop Phase Noise, LO_DIV_A = 01;
Offset = 1 kHz, 50 kHz, 400 kHz, 1 MHz, and 10 MHz
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
2800 3200 3600 4000 4400 4800 5200 5600
V
TUNE
(V)
VCO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
11489-019
Figure 23. VTUNE vs. VCO Frequency
–160
–155
–150
–145
–140
–135
–130
–125
–120
–
115
–
110
–105
–100
2579 2979 3379 3779 4179 4579 4979 5379 5779
PHASE NOISE (dBc/Hz)
VCO FREQUENCY (MHz)
TA = –40° C
TA = +25°C
TA = +85°C
1MHz OFFSET
10MHz OFFSET
40MHz OFFSET
11489-020
Figure 24. Open-Loop Phase Noise vs. VCO Frequency;
LO_DIV_A = 00
LO FREQUENCY (MHz)
–165
–160
–155
–150
–145
–140
–135
–130
–125
–120
–115
–110
–105
–100
–95
–90
–85
1384 1584 1784 1984 2184 2384 2584 2784
PHASE NOISE (d Bc/Hz)
TA = –40° C
TA = +25°C
TA = +85°C
100kHz O FFS E T
800kHz O FFS E T
6MHz OFFSET
40MHz OFF SET
11489-021
Figure 25. 120 kHz Bandwidth Loop Phase Noise, LO_DIV_A = 01;
Offset = 100 kHz, 800 kHz, 6 MHz, and 40 MHz
Data Sheet ADRF6620
Rev. 0 | Page 15 of 52
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2768 5568
INTEGRATED PHASE NOISE,
WITH S P UR ( ° rms)
VCO FREQ UE NC Y (MHz)
LO_DIV_A = 01
LO_DIV_A = 11
LO_DIV_A = 10
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
11489-126
3168 3568 3968 4368 4768 5168
Figure 26. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency;
LO_DIV_A = 01, 10, and 11, Including Spurs, for Various LO Divider Ratios
–110
–105
–100
–95
–90
–85
–80
–75
–70
2768 3168 3568 3968 4368 4768 5168 5568
VCO FREQUENCY (MHz)
REFERENCE SPURS (dBc), 1× PFD OFFSET
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
11489-028
Figure 27. fPFD Spurs vs. VCO Frequency;
1× PFD Offset; Measured at LO Output
–110
–105
–100
–95
–90
–85
–80
–75
–70
2768 3168 3568 3968 4368 4768 5168 5568
VCO FREQUENC Y (MHz)
REFERENCE SPURS (dBc), 3× PFD OFF SET
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
11489-029
Figure 28. fPFD Spurs vs. VCO Frequency;
3× PFD Offset; Measured at LO Output
2768 55683168 3568 3968 4368 4768 5168
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INTEGRATED PHASE NOISE,
WITHOUT S P UR ( ° rms)
VCO FREQ UE NC Y (MHz)
LO_DIV_A = 01
LO_DIV_A = 11
LO_DIV_A = 10
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
11489-128
Figure 29. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency;
LO_DIV_A = 01, 10, and 11, Excluding Spurs, for Various LO Divider Ratios
–110
–105
–100
–95
–90
–85
–80
–75
–70
2768 3168 3568 3968 4368 4768 5168 5568
VCO FREQ UE NC Y (MHz)
REFERENCE SPURS (dBc), 2× PFD OFF SET
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
11489-031
Figure 30. fPFD Spurs vs. VCO Frequency;
2× PFD Offset; Measured at LO Output
VCO FREQUENCY (MHz)
2768 3168 3568 3968 4368 4768 5168 5568
–120
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
REFERENCE SPURS (dBc), 4× PFD OFF SET
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
11489-032
Figure 31. fPFD Spurs vs. VCO Frequency;
4× PFD Offset; Measured at LO Output
ADRF6620 Data Sheet
Rev. 0 | Page 16 of 52
200
210
220
230
240
250
260
270
280
290
300
350 850 1350 1850 2350 2850
SUPPLY CURRENT (mA)
LO FREQUENCY (MHz)
LO_DRV_LVL = 00
LO_DRV_LVL = 01
LO_DRV_LVL = 10
LO_DRV_LVL = 11
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
11489-132
Figure 32. Supply Current vs. LO Frequency; LO_DRV_LVL = 00, 01, 10, and 11
RF FREQ UE NC Y (MHz)
–80
–70
–60
–50
–40
–30
–20
–10
0
600 1000 1400 1800 2200 2600 3000
RF TO LO FEEDTHROUGH (dBc)
11489-136
Figure 33. RF to LO Output Feedthrough, LO_DRV_LVL = 00
2818.2
2823.2
2828.2
2833.2
2838.2
2843.2
2848.2
2853.2
2858.2
2863.2
2868.2
025 50 75 100 125 150 175 200 225 250
LO FREQUENCY (MHz)
TIME (µs)
11489-137
Figure 34. LO Frequency Settling Time, Loop Filter Bandwidth = 120 kHz
–10
–8
–6
–4
–2
0
2
4
6
8
10
350 850 1350 1850 2350 2850
LO AMPLITUDE ( dBm)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
LO_DRV_LVL = 00
LO_DRV_LVL = 01
LO_DRV_LVL = 11
LO_DRV_LVL = 10
11489-135
Figure 35. LO Amplitude vs. LO Frequency; LO_DRV_LVL = 00, 01, 10, and 11
LO FREQUENCY (MHz)
–100
–98
–96
–94
–92
–90
–88
–86
–84
–82
–80
–78
–76
–74
–72
–70
1384 1584 1784 1984 2184 2384 2584 2784
REFERENCE SPURS (dBc), 1× PFD OFF SET
LO OUTPUT
DGA OUT P UT
11489-023
Figure 36. fPFD Spurs, LO_DIV_A = 01, 1× PFD Offset;
Measured on LO Output and DGA Output
Data Sheet ADRF6620
Rev. 0 | Page 17 of 52
RF INPUT TO MIXER OUTPUT PERFORMANCE
VCCx = 5 V, T A = 25°C, RL = 250 Ω, external LO, PLO = 0 dBm, RFDSA_SEL = 00 (0 dB), RFSW_SEL = 00 (RFIN0), BAL_CIN and
BAL_COUT optimized, MIXER_BIAS, MIXER_RDAC, and MIXER_CDAC optimized for highest linearity, DGA and LO output disabled,
unless otherwise noted. All losses from input and output traces and baluns are de-embedded from results.
–8
–7
–6
–5
–4
–3
–2
–1
0
600 1000 1400 1800 2200 2600 3000
GAIN (d B)
RF FREQ UE NC Y (MHz)
+85°C
+25°C
–40°C
11489-034
Figure 37. Mixer Gain vs. RF Frequency
0
2
4
6
8
10
12
14
16
18
20
22
600 1000 1400 1800 2200 2600 3000
IP 1dB (d Bm)
RF FREQ UE NC Y (MHz)
11489-035
TA = –40° C
TA = +25°C
TA = +85°C
Figure 38. Mixer IP1dB vs. RF Frequency
RF FREQ UE NC Y (MHz)
0
10
20
30
40
50
60
70
80
90
100
600 1000 1400 1800 2200 2600 3000
IIP2 (dBm), IIP3 (dBm)
IIP3 (dBm)
IIP2 (dBm)
11489-036
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
Figure 39. Mixer IIP2/IIP3 vs. RF Frequency; PIN = −5 dBm/Tone,
1 MHz Spacing
IF FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
0100 200 300 400 500 600 700 800 900 1000
GAIN (d B)
RF FREQ UE NC Y = 900M Hz
RF FREQ UE NC Y = 1900M Hz
RF FREQ UE NC Y = 2100M Hz
RF FREQ UE NC Y = 2700M Hz
11489-037
Figure 40. Mixer Gain vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
IF FREQUENCY (MHz)
0100 200 300 400 500 600 700 800 900 1000
0
2
4
6
8
10
12
14
16
18
20
22
IP 1dB (d Bm)
RF FREQ UE NC Y = 900M Hz
RF FREQ UE NC Y = 1900M Hz
RF FREQ UE NC Y = 2100M Hz
RF FREQ UE NC Y = 2700M Hz
11489-038
Figure 41. Mixer IP1dB vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
0
10
20
30
40
50
60
70
80
90
100
0100 200 300 400 500 600 700 800 900 1000
IIP2 (dBm), IIP3 (dBm)
IF FREQUENCY (MHz)
RF FREQ UE NC Y = 900M Hz
RF FREQ UE NC Y = 1900M Hz
RF FREQ UE NC Y = 2100M Hz
RF FREQ UE NC Y = 2700M Hz
IIP2 (dBm)
IIP3 (dBm)
11489-039
Figure 42. Mixer IIP2/IIP3 vs. IF Frequency; PIN = −5 dBm/Tone,
1 MHz Spacing, LO Sweep with Fixed RF, IF Roll-Off
ADRF6620 Data Sheet
Rev. 0 | Page 18 of 52
–8
–7
–6
–5
–4
–3
–2
–1
0
600 1000 1400 1800 2200 2600 3000
GAIN (d B)
RF FREQ UE NC Y (MHz)
RFSW_SEL = 00
RFSW_SEL = 01
RFSW_SEL = 10
RFSW_SEL = 11
11489-140
Figure 43. Mixer Gain vs. RF Frequency; RFSW_SEL = 00, 01, 10, and 11
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
600 1000 1400 1800 2200 2600 3000
ISOLATION (dBc)
RF FREQ UE NC Y (MHz)
ISOLATION RFSW_SEL = 00 TO 11
ISOLATION RFSW_SEL = 00 TO 01
ISOLATION RFSW_SEL = 00 TO 10
11489-142
Figure 44. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 00 Driven
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
600 1000 1400 1800 2200 2600 3000
ISOLATION (dBc)
RF FREQ UE NC Y (MHz)
ISOLATION RFSW_SEL = 01 TO 11
ISOLATION RFSW_SEL = 01 TO 00
ISOLATION RFSW_SEL = 01 TO 10
11489-141
Figure 45. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 01 Driven
RF FREQ UE NC Y (MHz)
0
10
20
30
40
50
60
70
80
90
100
600 1000 1400 1800 2200 2600 3000
IIP2 (dBm), IIP3 (dBm)
RFSW_SEL = 00
RFSW_SEL = 01
RFSW_SEL = 10
RFSW_SEL = 11 I IP2 ( dBm)
IIP3 (dBm)
11489-143
Figure 46. Mixer IIP2/IIP3 vs. RF Frequency; RFSW_SEL = 00, 01, 10, and 11
RF FREQ UE NC Y (MHz)
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
600 1000 1400 1800 2200 2600 3000
ISOLATION (dBc)
ISOLATION RFSW_SEL = 11 TO 11
ISOLATION RFSW_SEL = 11 TO 00
ISOLATION RFSW_SEL = 11 TO 01
11489-145
Figure 47. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 11 Driven
RF FREQ UE NC Y (MHz)
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
600 1000 1400 1800 2200 2600 3000
ISOLATION (dBc)
ISOLATION RFSW_SEL = 10 TO 11
ISOLATION RFSW_SEL = 10 TO 00
ISOLATION RFSW_SEL = 10 TO 01
11489-144
Figure 48. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 10 Driven
Data Sheet ADRF6620
Rev. 0 | Page 19 of 52
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
800 1200 1600 2000 2400 2800 3200
LO TO IF FEEDTHROUGH (dBm)
LO FREQUENCY (MHz)
11489-146
Figure 49. LO to IF Feedthrough at Mixer Output Without Filtering
800 1200 1600 2000 2400 2800 3200
RF F RE QUENC Y (MHz)
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
RF TO IF FEEDTHROUGH (dBc)
11489-147
Figure 50. RF to IF Feedthrough at Mixer Output Without Filtering;
Mixer Input Power = 0 dBm
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
350 600 850 1100 1350 1600 1850 2100 2350 2600 2850
LO TO RF FEE DTHRO UGH (dBm)
LO FREQUENCY (MHz)
EXTERNAL LO
INTERNAL LO
11489-148
Figure 51. LO to RF Feedthrough; PLO = 0 dBm
0
25
50
75
100
125
150
175
200
225
250
275
300
600 1000 1400 1800 2200 2600 3000
I
CC
(mA)
RF FREQ UE NC Y (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
INTERNAL LO
EXTERNAL LO
11489-149
Figure 52. ICC vs. RF Frequency; DGA and LO Output Disabled
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
600 1000 1400 1800 2200 2600
SSB NOISE FIG URE (dB)
RF FREQ UE NC Y (MHz)
OPTIMIZED FOR
HIGH LINEARITY
NOISE FIGURE
OPTIMIZED
11489-150
Figure 53. SSB Noise Figure vs. RF Frequency (see Table 16)
ADRF6620 Data Sheet
Rev. 0 | Page 20 of 52
IF DGA
VCCx = 5 V, T A = 25°C, RS = RL = 150 Ω, IF = 200 MHz, 2 V p-p differential output, unless otherwise noted. All losses from input and
output traces and baluns are de-embedded from results.
17
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
14
50 100 150 200 250 300 350 400 450 500
GAIN (d B)
IF F REQUENCY (MHz)
TA = –40° CTA = +25°CTA = +85°C
GAIN = 15d B
GAIN = 11d B
GAIN = 7d B
GAIN = 3d B
11489-151
Figure 54. DGA Gain vs. IF Frequency and Temperature
20
18
16
14
12
10
8
6
4
2
050 100 150 200 250 300 350 400 450 500
OP 1dB (d B)
IF F REQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
11489-152
Figure 55. DGA OP1dB vs. Frequency and Temperature; Maximum Gain
80
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
50 100 150 200 250 300 350 400 450 500
OIP2 (dBm), OIP3 (dBm)
IF F REQUENCY (MHz)
TA = –40° C
TA = +25°C
TA = +85°C
OIP2 (dBm)
OIP3 (dBm)
11489-153
Figure 56. DGA OIP2/OIP3 vs. IF Frequency and Temperature;
Maximum Gain
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
345678910 11 12 13 14 15
GAIN STEP ERRO R ( dB)
GAIN (d B)
GAIN (d B)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
11489-259
Figure 57. DGA Gain and Gain Step Error vs. Gain Setting and Temperature
20
18
16
14
12
10
8
6
4
2
0345678
910 11 12 13 14 15
OP1dB (dB)
GAI N ( dB)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
11489-155
Figure 58. DGA OP1dB vs. Gain Setting and Temperature
345678910 11 12 13 14 15
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
OIP2 (dBm), OIP3 (dBm)
GAI N ( dB)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
OI P 2 ( dBm)
OI P 3 ( dBm)
11489-156
Figure 59. DGA OIP2/OIP3 vs. Gain Setting and Temperature
Data Sheet ADRF6620
Rev. 0 | Page 21 of 52
50 500450400350300250200150100
–50
–70
–60
–80
–90
–100
–110
–120
–130
–140
–150
0
–20
–10
–30
–40
–50
–60
–70
–80
–90
–100
HD2 (d Bc)
HD3 (d Bc)
IF F REQUENCY (MHz)
TA = –40° C
TA = +25°C
TA = +85°C
11489-157
Figure 60. DGA HD2/HD3 vs. IF Frequency and Temperature; Maximum Gain
–7 –6 –5 –4 –3 –2 –1 012345678910
–50
–70
–60
–80
–90
–100
–110
–120
–130
–140
–150
0
–20
–10
–30
–40
–50
–60
–70
–80
–90
–100
HD2 (d Bc)
HD3 (d Bc)
P
OUT
(d Bm)
GAIN = 3d B
GAIN = 7d B
GAIN = 11d B
GAIN = 15d B
11489-158
Figure 61. DGA HD2/HD3 vs. Output Power (POUT) and Gain Setting
50 500450400350300250200150100
0
–20
–10
–30
–40
–50
–60
–70
–80
–90
–100
IM D2 ( dBc), IMD3 ( dBc)
IF F REQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
IM D2 ( dBc)
IM D3 ( dBc)
11489-159
Figure 62. DGA IMD2/IMD3 vs. IF Frequency and Temperature;
Maximum Gain
345678910 11 12 13 14 15
GAIN (d B)
–50
–70
–60
–80
–90
–100
–110
–120
–130
–140
–150
0
–20
–10
–30
–40
–50
–60
–70
–80
–90
–100
HD2 (d Bc)
HD3 (d Bc)
TA = –40° C
TA = +25°C
TA = +85°C
11489-160
Figure 63. DGA HD2/HD3 vs. Gain Setting and Temperature
–7 –6 –5 –4 –3 –5 –1 012345
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
OIP2 (dBm), OIP3 (dBm)
POUT (d Bm)
OIP2 (dBm)
OIP3 (dBm)
GAIN = 3d B
GAIN = 7d B
GAIN = 11d B
GAIN = 15d B
11489-161
Figure 64. DGA OIP2/OIP3 vs. Output Power (POUT) and Gain Setting
345678910 11 12 13 14 15
0
–20
–10
–30
–40
–50
–60
–70
–80
–90
–100
IM D2 ( dBc), IMD3 ( dBc)
GAIN (d B)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
IM D2 ( dBc)
IM D3 ( dBc)
11489-162
Figure 65. DGA IMD2/IMD3 vs. Gain Setting
ADRF6620 Data Sheet
Rev. 0 | Page 22 of 52
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products were measured in decibels
(dB) relative to the carrier (dBc) from the IF output power level. Data is shown for all spurious components greater than −115 dBc and
frequencies of less than 3 GHz.
915 MHz Performance
VCCx = 5 V, T A = 25°C, RF power = 0 dBm, internal LO, fRF = 914 MHz, fLO = 1114 MHz
M
0 1 2 3 4 5 6
N
0 −34 −35
1 −43 0 −52 −16
2 −72 −60 −72 −67 −74
3 −102 −73 −103 −78 <−115 −80
4 −102 <−115 <−115 <−115 <−115
5 <−115 −105 <−115 <−115 <−115
6 <−115 <−115 <−115 <−115
1910 MHz Performance
VCCx = 5 V, T A = 25°C, RF power = 0 dBm, internal LO, fRF = 1910 MHz, fLO = 2110 MHz.
M
0 1 2 3 4 5 6
N
0 −38.208
1
−40.462
−0.001
−50.9
2 −59.208 −69.655 −62.35
3 −106.741 −74.322 −106.429
4 <−115 <−115 <−115
5 <−115 <−115 −110.954
6 <−115 <−115
2140 MHz Performance
VCCx = 5 V, T A = 25°C, RF power = 0 dBm, internal LO, fRF = 2140 MHz, fLO = 2340 MHz.
M
0 1 2 3 4 5 6
N
0 −40
1 −36 0 −45
2 −58 −67 −59
3 <−115 −74 <−115
4 <−115 <−115 <−115
5 <−115 <−115 <−115
6 <−115 <−115
Data Sheet ADRF6620
Rev. 0 | Page 23 of 52
2700 MHz Performance
VCCx = 5 V, T A = 25°C, RF power = 0 dBm, internal LO, fRF = 2700 MHz, fLO = 2500 MHz.
M
0 1 2 3 4 5 6
N
0 −38.613
1 −40.126 −0.001 −43.84
2 −58.299 −67.06 −62.116
3 −73.603 <−115
4 <−115 <−115
5 <−115 <−115
6 <−115
ADRF6620 Data Sheet
Rev. 0 | Page 24 of 52
THEORY OF OPERATION
The ADRF6620 integrates the essential elements of a multi-
channel loopback receiver that is typically used in digital
predistortion systems. The main features of the ADRF6620
include a single-pole four throw (SP4T) RF input switch with
tunable balun, variable attenuation, a wideband active mixer,
and digitally programmable variable gain amplifier (DGA).
In addition, the ADRF6620 integrates a local oscillator (LO)
generation block consisting of a synthesizer and a multicore
voltage controlled oscillator (VCO) with an octave range and
low phase noise. The synthesizer uses a fractional-N phase-locked
loop (PLL) to enable continuous LO coverage from 350 MHz to
2850 MHz.
Putting all the building blocks of the ADRF6620 together,
the signal path through the device starts at the RF input, where
one of four single-ended RF inputs is selected by the input mux
and converted to a differential signal via a tunable balun. The
differential RF signal is attenuated to an optimal input level via
the digital step attenuator with 15 dB of attenuation range in steps
of 1 dB. The RF signal is then mixed via a Gilbert cell mixer with
the LO signal down to an IF frequency. The 255 Ω terminated
differential output of the mixer is brought off chip to a pair of
inductors and passed through an IF filter. The output of the IF
filter is ac-coupled off chip and fed to an on-chip digital attenuator
and IF DGA. The output of the IF DGA is then passed to an
off-chip analog-to-digital converter (ADC).
RF INPUT SWITCHES
The ADRF6620 integrates a SP4T switch where one of four RF
inputs is selected. The desired RF input can be selected using
either pin control or register writes via the SPI. Compared to the
serial write approach, pin control allows faster control over the
switch. When the RFSW0 pin (Pin 38) and the RFSW1 pin
(Pin 39) are used, the RF switches can switch at speeds of up to
100 ns. When serial port control is used, the switch time is 100 ns,
plus the latency of the SPI programming.
The RFSW_MUX bit (Register 0x23, Bit 11) selects whether the
RF input switch is controlled via the external pins or the SPI port.
By default at power-up, the device is configured for serial control.
Writing to the RFSW_SEL bits (Register 0x23, Bits[10:9]) allows
selection of one of the four RF inputs. Alternatively, by setting
the RFSW_MUX bit high, the RFSW0 and RFSW1 pins can be
used to select the RF input. Table 10 summarizes the different
control options for the RF inputs.
To maintain good channel-to-channel isolation, ensure that unused
RF inputs are properly terminated. The RFINx ports are internally
terminated with 50 Ω resistors and have a dc bias level of 2.5 V.
To avoid disrupting the dc level, the recommended termination
is a dc blocking capacitor to GND. Figure 66 shows the recom-
mended configuration when only RFIN0 is used, and the other
RF input ports are properly terminated.
RFIN0
RFIN1
RFIN2
RFIN3
0.1µF
0.1µF
0.1µF
50Ω
50Ω
50Ω
50Ω
11489-168
35
32
29
26
Figure 66. Terminating Unused RF Input Ports
Table 10. RF Input Selection Table
RFSW_MUX (Register Address 0x23[11])
SPI Control, RFSW_SEL
(Register Address 0x23[10:9]) Pin Control
Bit 11 Bit 10 Bit 9 RFSW1, Pin 39 RFSW0, Pin 38 RF Input
0 0 0 X1 X1 RFIN0
0 0 1 X1 X1 RFIN1
0
1
0
X
1
X
1
RFIN2
0 1 1 X1 X1 RFIN3
1 X1 X1 0 0 RFIN0
1 X1 X1 0 1 RFIN1
1 X1 X1 1 0 RFIN2
1 X1 X1 1 1 RFIN3
1 X = don’t care.
Data Sheet ADRF6620
Rev. 0 | Page 25 of 52
TUNABLE BALUN
The ADRF6620 integrates a programmable balun operating over
a frequency range from 700 MHz to 2700 MHz. The tunable
balun offers the benefit of ease of drivability from a single-ended
50 Ω RF input, and the single-ended-to-differential conversion
of the balun optimizes common-mode rejection.
11489-040
BAL_COUT
REG 0x30[ 7: 5]
BAL_CIN
REG 0x30[ 3: 1]
RFINx
Figure 67. Integrated Tunable Balun
The RF balun is tuned by switching parallel capacitances on the
primary and secondary sides by writing to Register 0x30. The
added capacitance, in parallel with the inductive windings of the
balun, changes the resonant frequency of the inductive capacitive
(LC) tank. Therefore, selecting the proper combination of BAL_
CIN (Register 0x30, Bits[3:1]) and BAL_COUT (Register 0x30,
Bits[7:5]) sets the desired frequency and minimizes the insertion
loss of the balun. Under most circumstances, the input and output
can be tuned together; however, sometimes for matching reasons,
it may be advantageous to tune them separately. See the RF Input
Balun Insertion Loss Optimization section for the recommended
BAL_CIN and BAL_COUT settings.
RF DIGITAL STEP ATTENUATOR (DSA)
The RF DSA follows the tunable balun. The attenuation range is
0 dB to 15 dB with a step size of 1 dB. DSA attenuation is set using
the RFDSA_SEL bits (Register 0x23, Bits[8:5]).
ACTIVE MIXER
The double balanced mixer uses high performance SiGe NPN
transistors. This mixer is based on the Gilbert cell design of four
cross-connected transistors.
The mixer output has a 255 Ω differential output resistance.
Bias the mixer outputs using either a pair of supply referenced
RF chokes or an output transformer with the center tap connected
to the positive supply.
DIGITALLY PROGRAMMABLE VARIABLE GAIN
AMPLIFIER (DGA)
The ADRF6620 integrates a differential IF DGA consisting of a
150 Ω digitally controlled passive attenuator followed by a highly
linear transconductance amplifier with feedback. The attenuation
range is 12 dB, and the transconductor amplifier has a fixed gain
of 15 dB. Therefore, at minimum attenuation, the gain of the IF
DGA is 15 dB; at maximum attenuation, the gain is 3 dB. The
attenuation is controlled by addressing the IF_ATTN bits in
Register 0x23, Bits[4:0]. The attenuation step size is 0.5 dB.
REF
IFIN+
IFIN–
IFOUT1+
IFOUT1–
IFOUT2+
IFOUT2–
ATTENUATOR
R
IN
R
S
R
OUT
R
L
+5V
gm
AMP
LOGIC
11489-041
15
16
11
8
9
10
Figure 68. Simplified IF DGA Schematic
An independent internal voltage reference circuit sets the dc
voltage level at the input of the amplifier to approximately 1.5 V.
This reference is not accessible and cannot be adjusted.
The IF DGA consumes 35 mA through the VCC2 pin (Pin 12)
and 75 mA through the two output choke inductors. The IF
DGA can be powered down by disabling the IF_AMP_EN bit
(Register 0x01, Bit 11). In its power-down state, the IF DGA
current reduces to 6 mA. The dc bias level at the input remains
at approximately 1.5 V when the DGA is disabled.
At minimum attenuation, the gain of the IF DGA is 15 dB when
driving a 150 Ω load. The source and load resistance of the
amplifier is set to 150 Ω in a matched condition. If the load or
the source resistance is not equal to 150 Ω, the following equations
can be used to determine the resulting gain and input/output
resistances.
Voltage Gain = AV = 0.044 × (1000||RL)
RIN = (1000 + RL)/(1 + 0.044 × RL)
S21 (Gain) = 2 × RIN/(RIN + RS) × AV
ROUT = (1000 + RS)/(1 + 0.044 × RS)
The dc current to the outputs of each amplifier is supplied
through two external choke inductors. The inductance of the
chokes and the resistance of the load, in parallel with the output
resistance of the device, add a low frequency pole to the response.
The parasitic capacitance of the chokes adds to the output capa-
citance of the part. This total capacitance, in parallel with the
load and output resistance, sets the high frequency pole of the
device. In general, the larger the inductance of the choke, the
higher the parasitic capacitance. Therefore, this trade-off must be
considered when the value and type of the choke are selected.
For each polarity, the amplifier has two output pins that are
oriented in an alternating fashion: IFOUT1+ (Pin 8), IFOUT1−
(Pin 9), IFOUT2+ (Pin 10), and IFOUT2− (Pin 11). When
designing the board, minimize the parasitic capacitance caused
by routing the corresponding outputs together. See the Layout
section for the recommended printed circuit board (PCB)
layout.
ADRF6620 Data Sheet
Rev. 0 | Page 26 of 52
LO GENERATION BLOCK
The ADRF6620 offers two modes for sourcing the LO signal to
the mixer. The first mode uses the on-chip PLL and VCO. This
mode of operation provides a high quality LO that meets the
performance requirements of most applications. Using the on-
chip synthesizer and VCO removes the burden of generating
and distributing a high frequency LO signal.
The second mode bypasses the integrated LO generation block
and allows the LO to be supplied externally. This second mode
can provide a very high quality signal directly to the mixer core.
Sourcing the LO signal externally may be necessary in demanding
applications that require the lowest possible phase noise
performance.
External LO Mode
External or internal LO mode can be selected via the VCO_SEL
bits (Register 0x22, Bits[2:0]). To configure for external LO mode,
set Register 0x22, Bits[2:0] to 011 and apply the differential LO
signals to Pin 44 (LOIN−) and Pin 45 (LOIN+). The external LO
frequency range is 350 MHz to 3.2 GHz. The ADRF6620 offers the
flexibility of using a higher LO frequency signal and dividing it
down before it drives the mixer. The LO divider can be found in
the LO_DIV_A bits (Register 0x22, Bits[4:3]), where options
include ÷1, ÷2, ÷4, or ÷8.
The external LO input pins present a broadband differential 50 Ω
input impedance. The LOIN+ and LOIN− input pins must be
ac-coupled. When not in use, LOIN+ and LOIN− can be left
unconnected.
Internal LO Mode
The ADRF6620 includes an on-chip VCO and PLL for LO
synthesis. The PLL, shown in Figure 69, consists of a reference
input, phase and frequency detector (PFD), charge pump, and a
programmable integer divider with prescaler. The reference path
takes in a reference clock and divides it down by a factor of 1, 2, 4,
or 8 or multiplies it by a factor of 2 before passing it to the PFD.
The PFD compares this signal to the divided down signal from the
VCO. Depending on the PFD polarity selected, the PFD sends an
up/down signal to the charge pump if the VCO signal is slow/fast
compared to the reference frequency. The charge pump sends
a current pulse to the off-chip loop filter to increase or decrease
the tuning voltage (VTUNE).
The ADRF6620 integrates three VCO cores that cover an octave
range from 2.8 GHz to 5.7 GHz. Table 11 summarizes the fre-
quency range for each VCO. The desired VCO can be selected
by addressing the VCO_SEL bits (Register 0x22, Bits[2:0]).
Table 11. VCO Range
VCO_SEL (Register 0x22, Bits[2:0]) Frequency Range (GHz)
000 5.2 to 5.7
001
4.1 to 5.2
010 2.8 to 4.1
011 External LO
The N-divider divides down the differential VCO signal to the PFD
frequency. The N-divider can be configured for fractional mode or
integer mode by addressing the DIV_MODE bit (Register 0x02,
Bit 11). The default configuration is set for fractional mode.
+
PFD
CHARGE
PUMP
CP
÷2
N = INT +FRAC
MOD
÷1, ÷2,
÷4, ÷8
LOIN–
VTUNE
EXTERNAL
LOOP
FILTER
LPF
LOIN+
VCO_SEL
REG 0x22[ 2: 0]
LO_DIV_A
REG 0x22[ 4: 3]
DIV_M ODE: RE G 0x02[11]
INT_DIV: REG 0x02[ 10: 0]
FRAC_DIV: RE G 0x03[10: 0]
MOD_DIV: REG 0x04[ 10: 0]
CP_CTRL
REG 0x20[ 13: 0]
×1
×2
÷8
÷4
÷2
REFIN
REFSEL
REG 0x21[ 2: 0]
PFD_POLARITY
REG 0x21[ 3]
LOOUT+
TO MIXER
LOOUT–
TO MIXER
11489-042
Figure 69. LO Generation Block Diagram
Data Sheet ADRF6620
Rev. 0 | Page 27 of 52
The following equations can be used to determine the N value and
PLL frequency:
N
f
fVCO
PFD ×
=
2
MOD
FRAC
INTN+=
LO_DIVIDER
Nf
f
PFD
LO
××
=2
where:
fPFD is the phase frequency detector frequency.
fVCO is the voltage controlled oscillator frequency.
N is the fractional divide ratio (INT + FRAC/MOD)
INT is the integer divide ratio programmed in Register 0x02.
FRAC is the fractional divider programmed in Register 0x03.
MOD is the modulus divide ratio programmed in Register 0x04.
fLO is the LO frequency going to the mixer core when the loop is
locked.
LO_DIVIDER is the final divider block that divides the VCO
frequency down by 1, 2, 4, or 8 before it reaches the mixer
(see Table 12). This control is located in the LO_DIV_A bits
(Register 0x22, Bits[4:3]).
Table 12. LO Divider
LO_DIV_A (Register 0x22, Bits[4:3]) LO_DIVIDER
00 1
01 2
10 4
11 8
The lock detect signal is available as one of the selectable outputs
through the MUXOUT pin; a logic high indicates that the loop
is locked. The MUXOUT pin is controlled by the REF_MUX_SEL
bits (Register 0x21, Bits[6:4]); the PLL lock detect signal is the
default configuration.
To ensure that the PLL locks to the desired frequency, follow the
proper write sequence of the PLL registers. The PLL registers must
be configured accordingly to achieve the desired frequency, and the
last writes must be to Register 0x02 (INT_DIV), Register 0x03
(FRAC_DIV), or Register 0x04 (MOD_DIV). When one of these
registers is programmed, an internal VCO calibration is initiated,
which is the last step in locking the PLL.
The time it takes to lock the PLL after the last register is written
can be broken down into two parts: VCO band calibration and
loop settling.
After the last register is written, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration takes approximately 5120 PFD cycles. For a 40 MHz
fPFD, this corresponds to 128 µs. After calibration is complete, the
feedback action of the PLL causes the VCO to eventually lock to
the correct frequency. The speed with which this locking occurs
depends on the nonlinear cycle-slipping behavior, as well as the
small-signal settling of the loop. For an accurate estimation of
the lock time, download the ADIsimPLL tool, which correctly
captures these effects. In general, higher bandwidth loops tend
to lock more quickly than lower bandwidth loops.
Additional LO Controls
To access the LO signal going to the mixer core through the
LOOUT+ and LOOUT− pins (Pin 21 and Pin 22), enable the
LO_DRV_EN bit in Register 0x01, Bit 7. This setting offers direct
monitoring of the LO signal to the mixer for debug purposes; or the
LO signal can be used to daisy-chain many devices synchronously.
One ADRF6620 can serve as the master where the LO signal is
sourced, and the subsequent slave devices share the same LO signal
from the master. This flexibility substantially eases the LO require-
ments of a system with multiple LOs.
The LO output drive level is controlled by the LO_DRV_LVL
bits (Register 0x22, Bits[8:7]). Table 13 shows the available drive
levels.
Table 13. LO Drive Level
LO_DRV_LVL (Register 0x22, Bits[8:7]) Amplitude (dBm)
00 −4
01 0.5
10 3
11 4.5
SERIAL PORT INTERFACE (SPI)
The SPI port of the ADRF6620 allows the user to configure the
device through a structured register space provided inside the
chip. Registers are accessed via the serial port interface and can
be written to or read from via the serial port interface.
The serial port interface consists of three control lines: SCLK,
SDIO, and CS. SCLK (serial clock) is the serial shift clock. The
SCLK signal clocks data on its rising edge. SDIO (serial data
input/output) is an input or output depending on the instruction
being sent and the relative position in the timing frame. CS
(chip select bar) is an active low control that gates the read and
write cycles. The falling edge of CS, in conjunction with the rising
edge of SCLK, determines the start of the frame. All SCLK and
SDIO activity is ignored when CS is high. Table 6 and Figure 2
show the serial timing and its definitions.
The ADRF6620 protocol consists of seven register address bits,
followed by a read/write indicator and 16 data bits. Both the
address and data fields are organized from MSB to LSB.
On a write cycle, up to 16 bits of serial write data are shifted in,
MSB to LSB. If the rising edge of CS occurs before the LSB of
the serial data is latched, only the bits that were clocked in are
written to the device. If more than 16 data bits are shifted in,
the 16 most recent bits are written to the device. The ADRF6620
input logic level for the write cycle supports a logic level as low
as 1.8 V.
On a read cycle, up to 16 bits of serial read data are shifted out,
MSB to LSB. Data shifted out beyond 16 bits is undefined. It is
not necessary for readback content at a given register address to
correspond with the write data of the same address. The output
logic level for a read cycle is 2.5 V.
ADRF6620 Data Sheet
Rev. 0 | Page 28 of 52
BASIC CONNECTIONS
IFOUT1+
IFOUT1–
IFOUT2+
IFOUT2–
GND
SPI
INTERFACE
ADRF6620
REFIN
MUXOUT
VCC5
SDIO
SCLK
CSB
CS
EXPOSED
PADDLE
+5V
+5V
470nH
(0603)
470nH
(0603)
39nH
(0402)
39nH
(0402) 0.1µF
(0402)
1µH1µH
0.1µF
(0402)
100pF
(0402)
0.1µF
(0402)
2.7nF
(0603)
6.8pF
(0402) 22pF
(0402)
22pF
(0402)
100pF
(0402)
0Ω
(0402)
0Ω
(0402)
3kΩ
(0402)
49.9Ω
(0402)
0Ω
(0402)
4
3
1 6
TC1-1-43A+
LOOUT
100pF
(0402)
LOOUT+
LOOUT–
100pF
(0402)
4
3
1 6
TC1-1-43A+
LOIN
4
3
2
1 6
LOIN
VTUNE_TP
OPEN
100pF
(0402)
LOIN+
LOIN–
VTUNE
CP
100pF
(0402)
100pF
(0402)
OPEN
(0402)
REF_IN
RFIN3
100pF
(0402)
RFIN3
RFIN1
100pF
(0402)
RFIN1
RFIN2
100pF
(0402)
RFIN2
RFIN0
100pF
(0402)
RFIN0
MUXOUT
10kΩ
(0402) 10kΩ
(0402)
DECL4
IFIN–
IFIN+
MXOUT+
MXOUT–
42 41 404 5 17 20 23 25 27 28 30 31 33 34 36 48 18 19 15 16
9
8
11
10
21
22
45
44
47
3
14 13 12 46 37 7 2
124
10kΩ
(0402)
10kΩ
(0402)
6
26
32
29
35
38
39
43
RFSW0
S1
RFSW1
3.3V
S2
3.3V
100pF
(0402)
0.1µF
(0402)
VCC4
100pF
(0402)
0.1µF
(0402)
VCC3
100pF
(0402)
0.1µF
(0402)
VCC2
100pF
(0402)
0.1µF
(0402)
VCC1
100pF
(0402)
0.1µF
(0402)
10µF
(0603) 0.1µF
(0402) 100pF
(0402)
10µF
(0603) 0.1µF
(0402) 100pF
(0402)
100pF
(0402) 0.1µF
(0402) 10µF
(0603)
100pF
(0402) 0.1µF
(0402) 10µF
(0603)
+5V
RED
LDO
VCO LDO
LO LDO
2.5V LDO
3.3V
LOCK_DET
VPTAT
CHARGE
PUMPCP
÷8
÷4
÷2
×1
×2
+
PFD
LOIN–
VTUNE
LOIN+
÷1, ÷2,
÷4, ÷8
÷2
N = INT + FRAC
MOD
DNP
DNP
TCM3-1T+
SCLK
SDIO
DECL3
DECL2
DECL1
11489-043
DNP
DNP
Figure 70. Basic Connection Diagram
Table 14. Basic Connections
Pin No. Mnemonic Description Basic Connection
5 V Power
1 VCC1 LO, VCO, mixer power supply Decouple all power supply pins to ground using 100 pF and 0.1 µF
capacitors. Place the decoupling capacitors close to the pins.
12 VCC2 IF DGA power supply
13 VCC3 Factory calibration pin
14 VCC4 Factory calibration pin
24 VCC5 RF front-end power supply
PLL/VCO
3 CP Synthesizer charge pump
output
Connect this pin to the VTUNE pin through the loop filter.
6 REFIN Synthesizer reference
frequency input
The nominal input level of this pin is 1 V p-p. The input range is
12 MHz to 464 MHz. This pin is internally biased and must be ac-
coupled and terminated externally with a 50 Ω resistor. Place
the ac coupling capacitor between the pin and the resistor.
When driven from an 50 Ω RF signal generator, the recommended
input level is 4 dBm.
21, 22 LOOUT+, LOOUT− Differential LO outputs The differential output impedance of these pins is 50 Ω. The pins
Data Sheet ADRF6620
Rev. 0 | Page 29 of 52
Pin No. Mnemonic Description Basic Connection
are internally biased to 2.5 V and must be ac-coupled.
44, 45 LOIN−, LOIN+ Differential LO inputs The differential input impedance of these pins is 50 Ω. The pins
are internally biased to 2.5 V and must be ac-coupled.
43 MUXOUT PLL multiplex output This output pin provides the PLL reference signal or the PLL lock
detect signal.
47 VTUNE VCO tuning voltage This pin is driven by the output of the loop filter; its nominal
input voltage range is 1.5 V to 2.5 V.
RF Inputs
26, 29, 32, 35 RFIN3, RFIN2
RFIN1, RFIN0
RF inputs The single-ended RF inputs have a 50 Ω input impedance and
are internally biased to 2.5 V. These pins must be ac-coupled.
Terminate unused RF inputs with a dc blocking capacitor to
GND to improve isolation. Refer to the Layout section for the
recommended PCB layout for optimized channel-to-channel
isolation.
38, 39 RFSW0, RFSW1 Pin control of the RF inputs See Table 10 for the pin settings for RF input pin control. For
logic high, connect these pins to 2.5 V logic.
IF DGA
8, 9, 10, 11 IFOUT1+, IFOUT1−,
IFOUT2+, IFOUT2−
IF DGA outputs The differential IF DGA outputs have two output pins for each
polarity. They are oriented in alternating fashion: IFOUT1+ (Pin 8),
IFOUT1− (Pin 9), IFOUT2+ (Pin 10), and IFOUT2− (Pin 11).
Connect the positive pins such that IFOUT1+ and IFOUT2+ are
tied together. Similarly, connect the negative pins such that
IFOUT1− and IFOUT2− are tied together. Refer to the Layout
section for a recommended layout that minimizes parasitic
capacitance and optimizes on performance.
The output stage of the IF DAG is an open-collector configuration
that requires a dc bias of 5 V. Use bias choke inductors to
achieve this configuration. Choose the bias choke inductors
such that they can handle a maximum current of 50 mA on
each side. By design, the IF DGA is optimized for linearity when
the source and load are terminated with 150 Ω.
15, 16 IFIN−, IFIN+ IF DGA inputs AC couple the mixer outputs to the IF DGA inputs. See the
Interstage Filtering Requirements section for the recommended
filter designs.
Mixer Outputs
18, 19
MXOUT+, MXOUT−
Differential mixer outputs
The output stage of the mixer is an open collector configuration
that requires a dc bias of 5 V. Use bias choke inductors to achieve
this configuration. Carefully choose the bias choke inductors
such that they can handle a maximum current of 50 mA on each
side. The differential output impedance of the mixer is 255 Ω.
Serial Port Interface
40 CS SPI chip select Active low. 3.3 V logic levels.
41 SCLK SPI clock 3.3 V tolerant logic levels.
42
SDIO
SPI data input and output
3.3 V tolerant logic levels.
LDO Decoupling
2 DECL1 3.3 V LDO decoupling Decouple all DECLx pins to ground using 100 pF, 0.1 µF, and 10 µF
capacitors. Place the decoupling capacitors close to the pin.
7 DECL2 2.5 V LDO decoupling
37 DECL3 LO LDO decoupling
46 DECL4 VCO LDO decoupling
GND
4, 5, 17, 20, 23, 25,
27, 28, 30, 31, 33,
34, 36, 48
GND Ground Connect these pins to the GND of the PCB.
49 (EPAD) Exposed pad (EPAD) The exposed thermal pad is on the bottom of the package.
The exposed pad must be soldered to ground.
ADRF6620 Data Sheet
Rev. 0 | Page 30 of 52
RF INPUT BALUN INSERTION LOSS OPTIMIZATION
As shown in Figure 71 to Figure 74, the gain of the ADRF6620
mixer has been characterized for every combination of BAL_CIN
and BAL_COUT (Register 0x30). As shown, a range of BAL_CIN
and BAL_COUT values can be used to optimize the gain of the
ADRF6620. The optimized values do not change with temperature.
After the values are chosen, the absolute gain changes over tem-
perature; however, the signature of the BAL_CIN and BAL_COUT
values is fixed.
–6
–5
–4
–3
–2
–1
0
0123456701234567012345670123456701234567012345670123456701234567
01234567
GAIN (dB)
BAL_CIN/BAL_COUT
BAL_COUT
BAL_CIN
–40°C
+25°C
+85°C
11489-044
Figure 71. Gain vs. BAL_CIN and BAL_COUT at RF = 900 MHz
–12
–10
–8
–6
–4
–2
0
0123456701234567012345670123456701234567012345670123456701234567
01234567
GAIN (dB)
BAL_CIN/BAL_COUT
–40°C
+25°C
+85°C
BAL_COUT
BAL_CIN
11489-046
Figure 72. Gain vs. BAL_CIN and BAL_COUT at RF = 2100 MHz
At lower input frequencies, more capacitance is needed. This
increase is achieved by programming higher codes into BAL_CIN
and BAL_COUT. At high frequencies, less capacitance is required;
therefore, lower BAL_CIN and BAL_COUT codes are appropriate.
Table 16 provides a list of recomended BAL_CIN and BAL_COUT
codes for popular radio frequencies. Use Figure 71 to Figure 74
and Table 16 only as guides; do not interpret them in the absolute
sense because every application and PCB design varies. Addi-
tional fine-tuning may be necessary to achieve the maximum gain.
–10
–9
–
4
–
5
–
6
–
7
–
8
–
3
–
2
–
1
0
0123456701234567012345670123456701234567012345670123456701234567
01234567
GAIN (dB)
BAL_CIN/BAL_COUT
BAL_COUT
BAL_CIN
–40°C
+25°C
+85°C
11489-045
Figure 73. Gain vs. BAL_CIN and BAL_COUT at RF = 1900 MHz
–18
–14
–10
–6
–2
–16
–12
–8
–4
0
0123456701234567012345670123456701234567012345670123456701234567
01234567
GAIN (dB)
BAL_CIN/BAL_COUT BAL_COUT
BAL_CIN
–40°C
+25°C
+85°C
11489-047
Figure 74. Gain vs. BAL_CIN and BAL_COUT at RF = 2700 MHz
Data Sheet ADRF6620
Rev. 0 | Page 31 of 52
IP3 AND NOISE FIGURE OPTIMIZATION
The ADRF6620 can be configured for either improved perfor-
mance or reduced power consumption. In applications where
performance is critical, the ADRF6620 offers IP3 or noise figure
optimization. However, if power consumption is the priority, the
mixer bias current can be reduced to save on the overall power
at the expense of degraded performance. Whatever the application
specific needs are, the ADRF6620 offers configurability that
balances performance and power consumption.
Adjustments to the mixer bias setting have the most impact on
performance and power. For this reason, mixer bias should be
the first adjustment. The active mixer core of the ADRF6620 is a
linearized transconductor. With increased bias current, the
transconductor becomes more linear, resulting in higher IP3.
The improved IP3, however, is at the expense of degraded noise
figure and increased power consumption (see Figure 75). For a
1-bit change of the mixer bias (MIXER_BIAS, Register 0x31,
Bits[11:9]), the current increases by 7.71 mA.
150
155
160
165
170
175
180
185
190
195
200
205
210
215
220
01234567
I
CC
(mA)
MIX E R BIAS
900MHz
1900MHz
2100MHz
2600MHz
RF FREQ:
Δ1
Δ7.71 mA
11489-057
Figure 75. Change in Current Consumption vs. MIXER_BIAS
Inevitably, there is a limit on how much the bias current can
increase before the improvement in linearity no longer justifies the
increase in power and noise. The mixer core reaches a saturation
point where further increases in bias current do not translate to
improved performance. When that point is reached, it is best to
decrease the bias current to a level where the desired performance
is achieved. Depending on the system specifications of the cus-
tomer, a balance between linearity, noise figure, and power can
be attained.
In addition to bias optimization, the ADRF6620 also has
configurable distortion cancellation circuitry. The linearized
transconductor input of the ADRF6620 is made up of a main path
and a secondary path. Through adjustments of the amplitude and
phase of the secondary path, the distortion generated by the main
path can be canceled, resulting in improved IPd3 performance.
The amplitude and phase adjustments are located in the following
serial interface bits: MIXER_RDAC (Register 0x31, Bits[8:5])
and MIXER_CDAC (Register 0x31, Bits[4:0]).
ADRF6620 Data Sheet
Rev. 0 | Page 32 of 52
Figure 76 to Figure 83 show the IIP3 and noise figure sweeps for
all MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS combi-
nations. The IIP3 vs. MIXER_RDAC and MIXER_CDAC figures
show both a surface and a contour plot in one figure. The contour
plot is located directly underneath the surface plot. The best
approach for reading the figure is to localize the peaks on the
surface plot, which indicate maximum IIP3, and to follow the
same color pattern to the contour plot to determine the optimized
MIXER_RDAC and MIXER_CDAC values. The overall shape
of the IIP3 plot does not vary with the MIXER_BIAS setting;
therefore, only MIXER_BIAS = 011 is displayed.
11489-093
0
5
10
15 0510 15
20
25
30
35
40
MIXER_RDAC
MIXER_CDAC
II P 3 ( dBm)
Figure 76. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 900 MHz
11489-094
0510 15
0
5
10
15
20
25
30
35
40
MIXER_CDAC
MIXER_RDAC
IIP3 (dBm)
Figure 77. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 1900 MHz
The data shows that MIXER_BIAS has the largest impact on
performance. As previously mentioned and evident in the data,
IIP3 improves with increased MIXER_BIAS, and noise figure is
optimized at the lowest bias setting. Taking a more detailed look
at the data, the different MIXER_RDAC and MIXER_CDAC
combinations can result in a ~5 dB to +10 dB change in IIP3, but
the noise figure changes by only ~0.5 dB. These trends become
very important in deciding the trade-offs between IP3, noise figure,
and power consumption. The total current consumption of the
ADRF6620 does not change with MIXER_RDAC and MIXER_
CDAC and varies only with the mixer bias settings (see Figure 75).
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
NOISE FIGURE (dB)
MIXER_RDAC
MIXER_CDAC
900-0
900-2
900-4
900-6
900-7
MIX E R BIAS
012
150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7150 7 150 7
345 78 10 11 13 146 9 12 15
11489-062
Figure 78. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 900 MHz
MIXER_RDAC
MIXER_CDAC
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
21.0
21.5
15.0
22.0
012
150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7150 7 150 7
345 78 10 11 13 146 9 12 15
NOISE FIGURE (dB)
1900-0
1900-2
1900-4
1900-6
1900-7
MI X E R BIAS
11489-063
Figure 79. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 1900 MHz
Data Sheet ADRF6620
Rev. 0 | Page 33 of 52
0510 15 0510 15
15
20
25
30
35
40
45
MIXER_RDAC
MIXER_CDAC
IIP3 (dBm)
11489-060
Figure 80. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 2100 MHz
0510 15 0
10
20
15
20
25
30
35
40
45
II P 3 ( dBm)
11489-061
MIXER_RDAC
MIXER_CDAC
Figure 81. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 2700 MHz
MIXER_RDAC
MIXER_CDAC
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
21.0
21.5
22.0
22.5
23.0
15.0
23.5
012
150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7150 7 150 7
345 78 10 11 13 146 9 12 15
NOISE FIGURE (dB)
2100-0
2100-2
2100-4
2100-6
2100-7
MIX E R BIAS
11489-064
Figure 82. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 2100 MHz
MIXER_RDAC
MIXER_CDAC
012
150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7 150 7150 7 150 7
345 78 10 11 13 146 9 12 15
NOISE FIGURE (dB)
2600-0
2600-2
2600-4
2600-6
2600-7
MI X E R BIAS
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
21.0
21.5
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
26.5
11489-065
Figure 83. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 2700 MHz
ADRF6620 Data Sheet
Rev. 0 | Page 34 of 52
As an example, the MIXER_RDAC, MIXER_CDAC, and MIXER_
BIAS settings of the ADRF6620 were carefully selected, based on
three individual goals that resulted in three sets of MIXER_RDAC,
MIXER_CDAC, and MIXER_BIAS values. The first goal was for
optimized IIP3. To achieve the most optimal IIP3 performance,
the MIXER_BIAS was set to a higher current setting, and MIXER_
RDAC and MIXER_CDAC were selected at the peaks. This
configuration allowed for the most optimal IIP3 performance.
However, it also consumed the most power, and the noise figure
was degraded. The second goal was to achieve a balance among
IIP3, the noise figure, and power consumption. Finally, the third
goal was for an optimized noise figure. This configuration resulted
in the lowest power consumption while IIP3 was not optimized.
Table 15 summarizes the test conditions; Table 16 shows the cor-
responding MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS
values. The resulting IIP3 and noise figure performance for the
specific MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS
settings are shown in Figure 84.
0
5
10
15
20
25
30
35
40
45
50
0.6 1.1 1.6 2.1 2.6
IIP3 (dBm)/NOISE FIGURE (dB)
RF F RE QUENC Y (GHz)
IIP3
NOISE
FIGURE
IIP3: OPT IIP3
IIP3: OPT NOISE FIGURE
IIP3: IIP3AND NOISE FIGURE BALANCE
NF: OPT IIP3
NF: OPT NOISE FIGURE
NF: IIP3 AND NOISE FIGURE BALANCE
11489-066
Figure 84. Example IIP3 and Noise Figure Optimization
Table 15. Mixer Optimization Summary
Parameter Test Conditions/Comments
Optimized IIP3 MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS were configured for optimized IIP3 performance.
Noise Figure, IIP3, and
Power Consumption
Balance
MIXER_BIAS was limited to 0, 1, or 2 decimal for improved noise figure while allowing IIP3 to degrade. MIXER_RDAC and
MIXER_CDAC were chosen for optimized IIP3 because MIXER_RDAC and MIXER_CDAC have a larger impact on IIP3
than on noise figure.
Optimized Noise Figure
MIXER_BIAS was set to 0 decimal for the best noise figure. MIXER_RDAC and MIXER_CDAC were chosen for optimized
IIP3 because they have a larger impact on IIP3 than on noise figure.
Table 16. Recommended BAL_CIN, BAL_COUT, MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS Settings (in Decimal)
RF Frequency
(MHz) BAL_CIN BAL_COUT
Optimized IIP3 IIP3 and Noise Figure Balance Optimized Noise Figure
RDAC CDAC BIAS RDAC CDAC BIAS RDAC CDAC BIAS
600 7 7 6 10 4 4 15 2 4 15 0
700 7 7 5 14 4 4 15 2 4 15 0
800 5 5 3 13 3 3 14 2 2 15 0
900 3 4 0 15 0 3 13 2 2 14 0
940 3 3 5 12 4 5 11 2 2 13 0
1000 2 3 5 11 4 4 10 2 3 11 0
1100 1 2 5 10 4 3 10 1 2 11 0
1200 1 2 5 9 4 3 9 1 2 10 0
1300 0 2 8 8 4 3 9 1 2 10 0
1400 0 2 6 7 4 4 8 1 2 9 0
1500
0
2
6
7
4
5
7
2
3
8
0
1600 0 2 8 7 4 5 7 2 2 8 0
1700 0 1 6 6 4 5 6 2 4 7 0
1800 0 1 9 6 4 5 6 2 4 7 0
1840 0 1 9 6 5 5 6 2 3 7 0
1900 0 1 9 6 5 6 5 2 3 7 0
2000 0 1 7 5 5 3 6 0 3 6 0
2100 1 1 9 5 5 5 5 1 3 6 0
2140 1 1 9 5 4 5 5 1 3 6 0
2200 2 0 7 4 4 5 5 1 3 6 0
2300 2 0 7 4 4 5 5 1 3 6 0
2400 1 0 7 4 4 5 5 1 3 6 0
2500 1 0 7 4 4 5 5 1 3 6 0
2600 1 0 7 4 4 5 5 1 3 6 0
2700 1 0 7 4 4 5 5 1 3 6 0
2800 1 0 7 4 4 4 15 2 4 15 0
2900 1 0 7 4 4 4 15 2 4 15 0
3000 0 0 7 4 4 3 14 2 2 15 0
Data Sheet ADRF6620
Rev. 0 | Page 35 of 52
INTERSTAGE FILTERING REQUIREMENTS
Filtering at the mixer output may be necessary for improved
linearity performance. For applications where the frequency plan
requires low RF frequency inputs and IF outputs, the resulting sum
term at the mixer outputs, fRF + fLO, may fall within the band of
interest. The unwanted sum term may cause the IF DGA to
operate in its nonlinear region because of the unnecessary presence
of additional signal power. As a result, the linearity performance
degrades where OIP3 and OIP2 decrease substantially. For this
reason, a low-pass filter is necessary to attenuate the unwanted
signal while maintaining the integrity of the wanted signal within
the band of interest. In addition, the low-pass filter serves to
suppress the LO feedthrough. Because of the absence of blockers
in a typical DPD receive application, a lower order filter, such as
a third-order Chebyshev, is typically adequate.
The low-pass filter resides between the mixer outputs and the IF
DGA inputs, as shown in Figure 85. The signal flow starts with the
differential outputs of the mixer being dc biased to positive
supply (5 V) via a pair of pull-up inductors, L1 and L2. The
inductor value is determined by the low frequency cutoff of the
signal band of interest. Next, the third-order low-pass filter
attenuates the high frequency sum term. The combination of
the pull-up inductors and the low-pass filter results in a band-
pass filter profile. The outputs of the filter are then ac-coupled
through series capacitors and routed to the on-chip IF DGA via
the IFIN+ and IFIN− pins.
MXOUT+
MXOUT–
IFIN+
IFIN–
IFOUT1–
IFOUT1+
IFOUT2–
IFOUT2+
RF
+5V
L2
L1
L3
L4
C1 C2
0.1µF
0.1µF
11489-048
LO
18
19
16
15
9
8
11
10
Figure 85. Low-Pass IF Filter
When designing the low-pass filter, it is important to consider
the output impedance of the mixer and the input impedance of
the IF DGA. The output impedance of the mixer has both a real
and reactive component, and its equivalent model is shown in
Figure 86. Correspondingly, Figure 87 shows the impedance vs.
frequency for the mixer output.
MXOUT+
MXOUT–
1.1pF
2.5pF
82.5Ω
90Ω
82.5Ω
+
+
11489-049
Figure 86. Equivalent Model of the Mixer Output Impedance
0
1
2
3
4
5
6
7
8
9
10
0100 200 300 400 500
FREQUENCY (MHz)
600 700 800 900 1000
150
170
190
210
230
250
270
290
PARALLEL CAPACITANCE ( pF)
PARALLEL RESISTANCE (Ω)
PARALLEL CAPACITANCE
PARALLEL RESISTANCE
11489-050
Figure 87. Mixer Output Impedance vs. Frequency
Likewise, Figure 88 shows the impedance vs. frequency for the
IF DGA. The four-port S parameter files for the IF DGA and
mixer are available on analog.com and can serve as a useful tool
to accurately capture the input and output impedance when
designing the interstage filter. As a first-order approximation
at low frequencies, the mixer output has a fixed impedance of
approximately 255 Ω, and the input impedance of the IF DAG is
approximately 150 Ω. Therefore, design the low-pass filter to
have an input impedance of 255 Ω and an output impedance of
150 Ω.
0
50
100
150
200
250
300
350
400
450
500
0
2
4
6
8
10
12
14
16
18
20
0100 200 300 400 500 600 700 800 900 1000
PARALLEL RESISTANCE (Ω)
PARALLEL CAPACITANCE ( pF )
FREQUENCY (MHz)
OUTPUT CAPACITANCE
INP UT CAPACITANCE
OUTPUT RESISTANCE
INP UT RESISTANCE
PARALLEL CAPACITANCE
PARALLEL RESISTANCE
11489-051
Figure 88. IF DGA Input/Output Impedance vs. Frequency
ADRF6620 Data Sheet
Rev. 0 | Page 36 of 52
Most important, the low-pass interstage filter must attenuate the
sum term (fRF + fLO) and LO feedthrough to prevent unnecessary
overdrive of the DGA. The level of attenuation that is required to
achieve optimal OIP3 performance is shown in Figure 89, where
OIP3 vs. (fRF + fLO) amplitude is plotted. To maintain performance,
attenuate the amplitude of the sum term to at least −16 dBm (see
Figure 89). Beyond this point, the OIP3 degrades decibel per
decibel for increased amplitudes.
30
32
34
36
38
40
42
44
46
–20 –18 –16 –14 –12 –10 –8 –6 –4
OIP3 (dBm)
AMPLITUDE ( dBm)
11489-052
Figure 89. OIP3 vs. (fRF + fLO) Amplitude
The ADRF6620 is optimized for use in digital predistortion
(DPD) receivers. An example filter design for DPD is shown in
Figure 91. Table 17 lists the interstage filter design targets.
In most DPD systems for cellular transmission, the pass band
is between 50 MHz and 500 MHz. For this reason, the pull-up
inductors have a low frequency cutoff of 50 MHz, and the pass-
band edge of the interstage low-pass filter is 500 MHz. This results
in a band-pass filter profile with a maximally flat pass band from
50 MHz to 500 MHz. The stop-band attenuation at 1400 MHz is
20 dB, which typically provides the necessary attenuation of the
mixer sum term with some margin.
Table 17. Example Filter Design
Parameter Value
RS 255 Ω
RL 150 Ω
Pass-Band Edge 500 MHz
Attenuation at Pass-Band Edge 0.5 dB
Stop-Band Edge 1400 MHz
Attenuation at Stop-Band Edge 20 dB
Filter Type Third-order Chebyshev
Using filter equations from a textbook or filter design software,
a third-order Chebyshev filter can be designed to satisfy all the
specifications in Table 17, as shown in Figure 91. The mixer output
capacitance of 1.1 pF can be absorbed into the filter, resulting in a
reduction in C1 from 2 pF to 0.8 pF. In addition, depending on the
PCB board stack-up, C2 can be further reduced, or eliminated,
because the capacitance of the PCB board can be used as the
third pole of the filter. The components used in the simulation
were the Coilcraft 0805CS inductors and Murata GRM15 series
capacitors. Figure 90 shows the filter profile that satisfies all the
filter specifications in Table 17.
–
40
–
35
–
30
–
25
–
20
–
15
–
10
–
5
0
0200 400 600 800 1000 1200 1400 1600 1800 2000
AMPLITUDE ( dBm)
FREQUENCY (MHz)
11489-054
Figure 90. Third-Order Chebyshev Filter Profile
1.1pF
2.5pF
82.5Ω
82.5Ω
90Ω
MXOUT+
R
S
R
L
MXOUT–
L3
24nH
L4
24nH 0.1µF
0.1µF
+5V
IFIN+
IFIN–
MIXER OUTPUT IM PEDANCE
EQUIVAL ENT MODEL THI RD- ORDER CHEBY SHEV
FILTER DC BLOCKI NG
CAPS
150Ω
IDEAL IF AMP
INPUT IM PE DANCE
L1
470nH L2
470nH
C1
0.8pF C2
1pF
+ + ++
+ +
11489-053
Figure 91. Low-Pass Interstage Filter Design
Data Sheet ADRF6620
Rev. 0 | Page 37 of 52
Maintaining the same third-order Chebyshev filter design shown
in Figure 91, the component values can be tuned to optimize
performance with some trade-offs. To achieve maximally flat pass-
band response, the trade-off is signal bandwidth (see Figure 92).
The L3 and L4 inductors are replaced with 47 nH, and the
capacitors are not populated. This configuration results in the
flattest pass-band ripple; however, the signal bandwidth starts to
roll off at 300 MHz. A narrower bandwidth translates to more
attenuation of the mixer sum and LO leakage, which is a desirable
effect if the wider signal bandwidth is not a requirement. Use the
results shown in Figure 92 only as a guide, and design the interstage
filter to the specific PCB board conditions. The plots in Figure 92
were measured using the ADRF6620 evaluation board.
4
5
6
7
8
9
10
11
12
50 100 150 200 250 300 350 400 450 500
GAI N ( dB)
IF FREQUENCY (MHz)
L3 = L4 = 47nH, C1 = C2 = OPEN
L3 = L4 = 39nH, C1 = C2 = OPEN
L3 = L4 = 24nH, C1 = 0.8pF, C2 = 1pF
11489-055
Figure 92. Interstage Filter Design Trade-Offs
Because the capacitance of the ADRF6620 evaluation board
closely approximates the C1 and C2 capacitors, they can be
removed from the design. However, this may not be the case
for every PCB design with different stack-ups.
Figure 93 compares the OIP3 and OIP2 performance of the
ADRF6620 with and without filtering at the mixer output.
15
25
35
45
55
65
75
85
50 100 150 200 250 300 350 400 450 500
OIP2 (dBm)/OIP3 (dBm)
IF FREQUENCY (MHz)
OIP3 WITH NO FILTER
OIP3 WITH FILTER
OIP2 WITH NO FILTER
OIP2 WITH FILTER
11489-056
Figure 93. OIP2/OIP3 Performance With and Without Filtering at
the DGA Output; RF Frequency = 900 MHz; High-Side LO Injection, LO Sweep
ADRF6620 Data Sheet
Rev. 0 | Page 38 of 52
IF DGA VS. LOAD
By design, the IF DGA is optimized for performance in a matched
condition where the source and load resistances are both 150 Ω.
If the load or the source resistance is not equal to 150 Ω (see the
Digitally Programmable Variable Gain Amplifier (DGA) section),
use the following equations to determine the resulting gain and
input/output resistances:
Voltage Gain = AV = 0.044 × (1000||RL)
RIN = (1000 + RL)/(1 + 0.044 × RL)
S21 (Gain) = 2 × RIN/(RIN + RS) × AV
ROUT = (1000 + RS)/(1 + 0.044 × RS)
In a configuration where the mixer outputs of the ADRF6620
are routed to the IF DGA inputs, the matched condition is no
longer satisfied because the source impedance, as seen by the IF
DGA, is the 255 Ω output impedance of the mixer outputs. As a
result, the gain and output resistance of the amplifier vary from
the expected 15 dB (see Figure 94).
255Ω R
IN
R
OUT
R
L
11489-067
Figure 94. Mixer Loading of the IF DGA
The ideal load is 150 Ω for the matched condition; however, this
may not be the most readily available load impedance.
As a result, load vs. performance trade-offs must be considered.
In the matched condition, the IF DGA is optimized for linearity;
therefore, the third-order intermodulation product degrades with
load. Table 18 shows some common output loads, and Figure 95,
Figure 96, and Figure 97 show the effects of loading on gain,
IMD2, and IMD3.
As the equations in this section indicate, the manner in which
the IF DGA is loaded affects the input resistance, RIN, of the
amplifier. RIN, in turn, determines the load resistance of the
interstage filter between the mixer outputs and the IF DGA
inputs. The interstage filter has a source impedance of 255 Ω from
the mixer outputs and a load impedance of RIN for the particular
RL load (see Table 18). As a result of the impedance mismatch,
the insertion loss of the interstage filter must be included in the
level planning calculations.
0
2
4
6
8
10
12
14
16
18
20
0100 200 300 400 500 600 700 800 900 1000
IF DGA GAIN ( dB)
FREQUENCY (MHz)
R
L
= 150Ω
R
L
= 500Ω
R
L
= 73Ω
R
L
= 50Ω
11489-068
Figure 95. IF DGA Gain vs. Frequency for Different Loads
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
40 120 200 280 360 440 520 600 680
IF DGAI M D3 ( dBc)
FREQUENCY (MHz)
R
L
= 150Ω
R
L
= 500Ω
R
L
= 73Ω
R
L
= 50Ω
11489-069
Figure 96. IF DGA IMD3 vs. Frequency for Different Loads
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
IF DGA IMD2 (dBc)
FREQUENCY (MHz)
150ΩLOAD
50ΩLOAD
500ΩLOAD
73ΩLOAD
11489-070
Figure 97. IF DGA IMD2 vs. Frequency for Different Loads
Table 18. Common Output Loads
RS (Ω) RIN (Ω) AV (Linear) AV (dB) S21 (Linear) S21 (dB) ROUT (Ω) RL (Ω)
255 65 14.7 23.3 6 15.5 102.7 500
255 151 5.7 15.2 4.3 12.6 102.7 150
255 255 3 9.5 3 9.5 102.7 73
255 328 2.1 6.4 2.4 7.5 102.7 50
Data Sheet ADRF6620
Rev. 0 | Page 39 of 52
ADC INTERFACING
The integrated IF DGA of the ADRF6620 provides variable and
sufficient drive capability for both buffered and unbuffered ADCs.
It also provides isolation between the sampling edges of the ADC
and the mixer core. As result, only an antialiasing filter is required
when interfacing with an ADC.
The ADRF6620 is optimized for use in cellular base station digital
predistortion (DPD) systems. Predistortion is used to improve
the linearity of transmitter power amplifiers (PA). Because the
input signal to the DPD path is the known transmitted signal, the
hardware specifications are not typically as stringent as the main
receive path. The signal-to-noise ratio (SNR) of the ADC is not
paramount, due to the autocorrelation with the known transmitted
signal. For this reason, lower resolution ADCs are usually adequate,
and 11-bit to 14-bit resolution typically suffices. A more critical
consideration is the analog bandwidth of the converter. Traditional
DPD systems require 3× to 5× the transmit bandwidth. Therefore,
for a 100 MHz Tx bandwidth, the DPD bandwidth must be at
least 500 MHz for fifth-order correction.
The AD9434 complements the ADRF6620 very well in a DPD
design. The AD9434 is a 12-bit, 370 MSPS/500 MSPS buffered
ADC. Its full power analog bandwidth is 1 GHz, making it wide
enough for fifth-order correction with substantial margin. The
sampling rate of the AD9434 is insufficient in satisfying the
sampling theorem; however, this may be acceptable in DPD
applications where undersampling is often permissible. Because
the receive signal in the DPD path is the known transmitted signal,
the desired signal and its aliases are clearly distinguished.
The antialiasing filter resides between the ADRF6620 and the
AD9434. Because aliasing is common practice in a DPD receive
chain, the antialiasing filter requirements can be relaxed. A
second-order or third-order filter is sufficient in reducing the
high frequency noise from folding back into the band of interest.
When designing the antialiasing filter, it is important to consider
the output impedance of the IF DGA of the ADRF6620 and the
input impedance of the AD9434. The differential resistance of
the AD9434 is 1 kΩ, and the parallel capacitance is 1.3 pF. For the
matched load condition, where the IF DGA is optimized for gain
and linearity, load the IF DGA with 150 Ω. To do this, place a
176 Ω resistor in parallel with the input of the ADC.
The parallel combination of the 176 Ω with the 1 kΩ of the ADC
input impedance results in an equivalent 150 Ω differential output
load as seen by the IF DGA of the ADRF6620. In addition, the
input capacitance of the AD9434 can be used as the fourth pole
of the antialiasing filter. The final schematic design is shown in
Figure 99. The antialiasing filter is maximally flat, with a pass-
band bandwidth of 500 MHz. Table 19 shows the component
values for the antialiasing filter design for DPD. Figure 98 shows
the simulated antialiasing filter design.
Table 19. Component Values for 500 MHz Antialiasing Filter
Design
Parameter Value Type Manufacturer
L1 = L2 470 nH 0805CS Coilcraft
C1 DNP GRM15 Murata
L3 = L4 39 nH 0805CS Coilcraft
C2 DNP GRM15 Murata
L5 = L6 1 µH 0805LS Coilcraft
L7 = L8 15 nH 0805CS Coilcraft
C3 2.7 pF GRM15 Murata
L9 = L10 27 nH 0805CS Coilcraft
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
0200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
AMPL IT UDE ( dB)
11489-100
Figure 98. Simulated Antialiasing Filter Design
AD9434
255Ω
ADRF6620
MIXER
OUTPUT
+5V +5V
ADRF6620
IF AMP
L1 L2 L5 L6
L3
L4
L9
L10
L7
L8
C1 C2 C3 1kΩ 1.3pF
88Ω
88Ω
+
+
+
+
+
+ +
+
0.1µF0.1µF
0.1µF
0.1µF
11489-071
Figure 99. ADRF6620 Interface to the AD9434
ADRF6620 Data Sheet
Rev. 0 | Page 40 of 52
POWER MODES
The ADRF6620 has many building blocks, and these blocks can
be independently powered off by writing to Register 0x01 (see
Table 23).
External LO Mode
In external LO mode, the internal PLL and VCO are disabled,
which reduces the current consumption by approximately 100 mA.
Table 20 lists the register settings that are required to configure
external LO mode.
Table 20. Serial Port Configuration for External LO Mode
Bit Name State Register
LDO_3P3_EN On 0x01 = 0x8B53
VCO_LDO_EN On 0x01 = 0x8B53
CP_EN Off 0x01 = 0x8B53
DIV_EN
Off
0x01 = 0x8B53
VCO_EN On 0x01 = 0x8B53
REF_BUF_EN Off 0x01 = 0x8B53
LO_DRV_EN Off 0x01 = 0x8B53
LO_PATH_EN On 0x01 = 0x8B53
MIX_EN On 0x01 = 0x8B53
IF_AMP_EN On 0x01 = 0x8B53
LO_LDO_EN On 0x01 = 0x8B53
VCO_SEL External LO 0x22, Bits[2:0] = 011
IF DGA Disable Mode
In applications where the IF DGA is not used, it can be powered
down. Power-down is achieved by disabling the IF_AMP_EN bit
(Register 0x01, Bit 11 = 0). By disabling the amplifier, the current
consumption of the ADRF6620 decreases by approximately 25 mA,
along with a 35 mA to 50 mA current savings through each bias
inductor at the output of the amplifier. When the IF DGA is
disabled, its input and output impedance is high-Z. For this reason,
the input and output pins can be left open. If the preference is
not to leave the nodes open, the alternative option is to terminate
the pins to ground via a 1 kΩ resistor.
LAYOUT
Careful layout of the ADRF6620 is necessary for optimizing
performance and minimizing stray parasitics. Because the
ADRF6620 supports four RF inputs, the layout of the RF section
is critical in achieving isolation between each channel. Figure 100
shows the recommended layout for the RF inputs. Each RF input,
RFIN0 to RFIN3, is isolated between ground pins, and the best
layout approach is to keep the traces short and direct. To achieve
this layout, connect the pins directly to the center ground pad
of the exposed pad of the ADRF6620. This approach minimizes
the trace inductance and promotes better isolation between the
channels. In additional, for improved isolation, do not route the
RFIN0 to RFIN3 traces in parallel to each other; instead, spread
the traces immediately after each one leaves the pins. Keep the
traces as far away from each other as possible (and at an angle,
if possible) to prevent cross coupling.
The input impedance of the RF inputs is 50 Ω, and the traces
leading to the pin must also have a 50 Ω characteristic impedance.
Terminate unused RF inputs with a dc blocking capacitor to
ground.
11489-072
RFIN0
RFIN1
RFIN2
RFIN3
GND
GND
GND
GND
GND
GND
GND
GND
Figure 100. Recommended Layout for the RF Inputs
The IF DGA outputs on the ADRF6620 have two output pins for
each polarity, and they are oriented in an alternating fashion, as
follows: IFOUT1+ (Pin 8), IFOUT1− (Pin 9), IFOUT2+ (Pin 10),
and IFOUT2− (Pin 11). When designing the board, minimize the
parasitic capacitance due to the routing that connects the corre-
sponding outputs together. A good practice is to avoid any ground
or power plane under this routing region and under the chokes
to minimize the parasitic capacitance. Figure 101 shows the
recommended layout. The IF DGA output pins with the same
polarity are tied together on the bottom of the board with the
blue traces and vias.
IFOUT1+
IFOUT1–
IFOUT2+
IFOUT2–
11489-073
Figure 101. Recommended Layout for the IF DGA Outputs
(Green traces are routings on top of the board,
and blue traces are routings on the bottom of the board.)
Data Sheet ADRF6620
Rev. 0 | Page 41 of 52
REGISTER MAP
Table 21. Register Map Summary Table
Reg Name Bits
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reset RW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00 SOFT_RESET [15:8] RESERVED 0x00000 W
[7:0] RESERVED SOFT_RESET
0x01 Enables [15:8] LO_LDO_EN RESERVED RESERVED RESERVED IF_AMP_EN RESERVED MIX_EN LO_PATH_EN 0x8B7F RW
[7:0]
LO_DRV_EN
RESERVED
REF_BUF_EN
VCO_EN
DIV_EN
CP_EN
VCO_LDO_EN
LDO_3P3_EN
0x02 INT_DIV [15:8] RESERVED DIV_MODE INT_DIV[10:8] 0x0058 RW
[7:0] INT_DIV[7:0]
0x03 FRAC_DIV [15:8] RESERVED FRAC_DIV[10:8] 0x0250 RW
[7:0] FRAC_DIV[7:0]
0x04 MOD_DIV [15:8] RESERVED MOD_DIV[10:8] 0x0600 RW
[7:0] MOD_DIV[7:0]
0x20 CP_CTL [15:8] RESERVED RESERVED CSCALE RESERVED 0x0C26 RW
[7:0] RESERVED BLEED_DIR BLEED
0x21 PFD_CTL [15:8] RESERVED 0x0003 RW
[7:0] RESERVED REF_MUX_SEL PFD_POLARITY REFSEL
0x22
FLO_CTL
[15:8]
RESERVED
LO_DRV_LVL[1]
0x000A
RW
[7:0] LO_DRV_LVL[0] RESERVED LO_DIV_A VCO_SEL
0x23 DGA_CTL [15:8] RESERVED RFSW_MUX RFSW_SEL RFDSA_SEL[3] 0x0000 RW
[7:0] RFDSA_SEL[2:0] IF_ATTN
0x30 BALUN_CTL [15:8] RESERVED 0x00000 RW
[7:0] BAL_COUT RESERVED BAL_CIN RESERVED
0x31 MIXER_CTL [15:8] RESERVED MIXER_BIAS MIXER_RDAC[3] 0x08EF RW
[7:0] MIXER_RDAC[2:0] RESERVED MIXER_CDAC
0x40 PFD_CTL2 [15:8] RESERVED 0x0010 RW
[7:0] RESERVED ABLDLY CPCTRL CLKEDGE
0x42 DITH_CTL1 [15:8] RESERVED 0x000E RW
[7:0]
RESERVED
DITH_EN
DITH_MAG
DITH_VAL
0x43 DITH_CTL2 [15:8] DITH_VAL[15:8] 0x0001 RW
[7:0] DITH_VAL[7:0]
ADRF6620 Data Sheet
Rev. 0 | Page 42 of 52
REGISTER ADDRESS DESCRIPTIONS
REGISTER 0x00, RESET: 0x00000, NAME: SOFT_RESET
Table 22. Bit Descriptions for SOFT_RESET
Bit Bit Name Settings Description Reset Access
0 SOFT_RESET Soft reset 0x0000 W
REGISTER 0x01, RESET: 0x8B7F, NAME: ENABLES
Table 23. Bit Descriptions for Enables
Bits Bit Name Settings Description Reset Access
15 LO_LDO_EN Power up LO LDO 0x1 RW
11 IF_AMP_EN IF DGA enable 0x1 RW
9 MIX_EN Mixer enable 0x1 RW
8 LO_PATH_EN External LO path enable 0x1 RW
7 LO_DRV_EN LO driver enable 0x0 RW
5 REF_BUF_EN Reference buffer enable 0x1 RW
4 VCO_EN Power up VCOs 0x1 RW
3 DIV_EN Power up dividers 0x1 RW
2 CP_EN Power up charge pump 0x1 RW
1 VCO_LDO_EN Power up VCO LDO 0x1 RW
0 LDO_3P3_EN Power up 3.3 V LDO 0x1 RW
Data Sheet ADRF6620
Rev. 0 | Page 43 of 52
REGISTER 0x02, RESET: 0x0058, NAME: INT_DIV
Table 24. Bit Descriptions for INT_DIV
Bits Bit Name Settings Description Reset Access
11 DIV_MODE 0x0 RW
0 Fractional
1 Integer
[10:0] INT_DIV Set divider INT value 0x58 RW
REGISTER 0x03, RESET: 0x0250, NAME: FRAC_DIV
Table 25. Bit Descriptions for FRAC_DIV
Bits Bit Name Settings Description Reset Access
[10:0] FRAC_DIV Set divider FRAC value 0x250 RW
REGISTER 0x04, RESET: 0x0600, NAME: MOD_DIV
Table 26. Bit Descriptions for MOD_DIV
Bits Bit Name Settings Description Reset Access
[10:0] MOD_DIV Set divider MOD value 0x600 RW
ADRF6620 Data Sheet
Rev. 0 | Page 44 of 52
REGISTER 0x20, RESET: 0x0C26, NAME: CP_CTL
Table 27. Bit Descriptions for CP_CTL
Bits Bit Name Settings Description Reset Access
[13:10] CSCALE Charge pump current 0x3 RW
0001 250 μA
0011 500 μA
0111 750 μA
1111 1000 μA
5 BLEED_DIR Charge pump bleed direction 0x1 RW
0 Sink
1 Source
[4:0] BLEED Charge pump bleed 0x06 RW
00000 0 μA
00001 15.625 μA
…
… N × 15.625 μA
…
11110 468.75 μA
11111 484.375 μA
Data Sheet ADRF6620
Rev. 0 | Page 45 of 52
REGISTER 0x21, RESET: 0x0003, NAME: PFD_CTL
Table 28. Bit Descriptions for PFD_CTL
Bits Bit Name Settings Description Reset Access
[6:4] REF_MUX_SEL Set REF output divide ratio/VPTAT/LOCK_DET 0x0 RW
000 LOCK_DET
001 VPTAT
010 REFCLK
011 REFCLK/2
100 REFCLK × 2
101 RESERVED
110 REFCLK/4
111 RESERVED
3 PFD_POLARITY Set PFD polarity 0x0 RW
0 Positive KV VCO
1 Negative KV VCO
[2:0] REFSEL Set REF input divide ratio 0x3 RW
000 ×2
001 ×1
010 DIV2
011 DIV4
100 DIV8
ADRF6620 Data Sheet
Rev. 0 | Page 46 of 52
REGISTER 0x22, RESET: 0x000A, NAME: FLO_CTL
Table 29. Bit Descriptions for FLO_CTL
Bits Bit Name Settings Description Reset Access
[8:7] LO_DRV_LVL LO amplitude 0x0 RW
00 −4 dBm
01 0.5 dBm
10 +3 dBm
11 +4.5 dBm
[4:3] LO_DIV_A LO_DIV_A 0x1 RW
00 DIV1
01 DIV2
10 DIV4
11 DIV8
[2:0] VCO_SEL Select VCO core/external LO 0x2 RW
000 5.2 GHz to 5.7 GHz
001 4.1 GHz to 5.2 GHz
010 2.8 GHz to 4.1 GHz
011 EXT LO
100 VCO_PWRDWN
101 VCO_PWRDWN
110 VCO_PWRDWN
111 VCO_PWRDWN
Data Sheet ADRF6620
Rev. 0 | Page 47 of 52
REGISTER 0x23, RESET: 0x0000, NAME: DGA_CTL
Table 30. Bit Descriptions for DGA_CTL
Bits Bit Name Settings Description Reset Access
11 RFSW_MUX Set switch control. 0x0 RW
0 Serial CNTRL
1 Pin CNTRL
[10:9] RFSW_SEL Set RF input. 0x0 RW
00 RFIN0
01 RFIN1
10 RFIN2
11 RFIN3
[8:5] RFDSA_SEL Set RFDSA attenuation. Range: 0 dB to 15 dB in steps of 1 dB. 0x0 RW
0000 0 dB
0001 1 dB
...
1110 14 dB
1111 15 dB
[4:0] IF_ATTN IF Attenuation. Range: 3 dB to 15 dB in steps of 0.5 dB. 0x0 RW
00000 3 dB
00001 3.5 dB
...
10111 14.5 dB
11000 15 dB
ADRF6620 Data Sheet
Rev. 0 | Page 48 of 52
REGISTER 0x30, RESET: 0x00000, NAME: BALUN_CTL
Table 31. Bit Descriptions for BALUN_CTL
Bits Bit Name Settings Description Reset Access
[7:5] BAL_COUT Set balun output capacitance 0x0 RW
000 Minimum capacitance
... ...
111 Maximum capacitance
[3:1] BAL_CIN Set balun input capacitance 0x0 RW
000 Minimum capacitance
... ...
111 Maximum capacitance
REGISTER 0x31, RESET: 0x08EF, NAME: MIXER_CTL
Table 32. Bit Descriptions for MIXER_CTL
Bits Bit Name Settings Description Reset Access
[11:9] MIXER_BIAS Set mixer bias value 0x4 RW
000 Minimum
...
111 Maximum
[8:5] MIXER_RDAC Set mixer RDAC value 0x7 RW
[3:0] MIXER_CDAC Set mixer CDAC value 0xF RW
Data Sheet ADRF6620
Rev. 0 | Page 49 of 52
REGISTER 0x40, RESET: 0x0010, NAME: PFD_CTL2
Table 33. Bit Descriptions for PFD_CTL2
Bits Bit Name Settings Description Reset Access
[6:5] ABLDLY Set antibacklash delay 0x0 RW
00 0 ns
01 0.5 ns
10 0.75 ns
11 0.9 ns
[4:2] CPCTRL Set charge pump control. 0x4 RW
000 Both on
001 Pump down
010 Pump up
011 Tristate
100 PFD
[1:0] CLKEDGE Set PFD edge sensitivity 0x0 RW
00 Div and REF down edge
01 Div down edge, REF up edge
10 Div up edge, REF down edge
11 Div and REF up edge
ADRF6620 Data Sheet
Rev. 0 | Page 50 of 52
REGISTER 0x42, RESET: 0x000E, NAME: DITH_CTL1
Table 34. Bit Descriptions for DITH_CTL1
Bits Bit Name Settings Description Reset Access
3 DITH_EN Set dither enable 0x1 RW
0 Disable
1 Enable
[2:1] DITH_MAG Set dither magnitude 0x3 RW
0 DITH_VAL Set dither value 0x0 RW
REGISTER 0x43, RESET: 0x0001, NAME: DITH_CTL2
Table 35. Bit Descriptions for DITH_CTL2
Bits Bit Name Settings Description Reset Access
[15:0] DITH_VAL Set dither value 0x1 RW
Data Sheet ADRF6620
Rev. 0 | Page 51 of 52
OUTLINE DIMENSIONS
COM P LIANT T O JEDE C S TANDARDS M O-220-WKKD.
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
1
0.50
BSC
BOTTOM VIEW
TOP VI EW
PI N 1
INDICATOR
48
13
24
36
37
EXPOSED
PAD
PI N 1
INDICATOR
5.65
5.50 S Q
5.35
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 RE F
COPLANARITY
0.08
0.30
0.23
0.18
06-06-2012-B
7.10
7.00 S Q
6.90
0.20 M IN
5.50 RE F
Figure 102. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
7 mm × 7 mm Body, Very Very Thin Quad
(CP-48-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
ADRF6620ACPZ-R7 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-48-9
ADRF6620-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
ADRF6620 Data Sheet
Rev. 0 | Page 52 of 52
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11489-0-7/13(0)