MiIcROCHIP PIC16C5X EPROM-Based 8-Bit CMOS Microcontroller Series FEATURES High-Performance RISC-like CPU * Only 33 single word instructions to learn * All single cycle instructions (200ns) except for program branches which are two-cycle Operating speed: DC - 20 MHz clock input DC - 200ns instruction cycle 12-bit wide instructions 8-bit wide data path 512 - 2K x 12 on-chip EPROM program memory 25 - 72 x 8 general purpose registers (SRAM) Seven special function hardware registers Two-level deep hardware stack Direct, indirect and relative addressing modes for data and instructions oeooeee @ Peripheral Features * 12-20 1/0 pins with individual direction control * 8-bit real time clock/counter (RTCC) with 8-bit programmable prescaler * Power-On Reset FIGURE A - PIN CONFIGURATIONS Oscillator Start-up Timer Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Security EPROM fuse for code-protection Power saving SLEEP mode EPROM fuse selectable oscillator options: - Low-cost RC oscillator: RC - Standard crystal/resonator: XT - High-speed crystal/resonator: HS - Power saving, low frequency crystal: LP CMOS Technology * Low-power, high-speed CMOS EPROM technology * Fully static design * Wide-operating voltage range: - Commercial: 2.5V to 6.25V - Industrial: 2.5V to 6.25V - Automotive: 2.5V to 6.0V * Low-power consumption - <2mA typical @ 5V, 4 MHz - 15pA typical @ 3V, 32 KHz - < 3A typical standby current @ 3V, 0C to 70C PDIP, SOIC, CERDIP Window ~a RA2 [| 1 Vv 18 RA1 ~~ <<. RAS 2 17D RAO <> atccO3 3B 16 oscrvcikin< ~wcta 4 89 150 oscacLKoUT ~Vss (15 @ 141 Veo <= RBo 16 Gg 13D Ree ~<,rBi 7 & 121 RB6 <= ~< pe [8 11 RBS <> ~t RBS [1 9 10 [] RB4 ~<a SsOoP were 2D RA ~ RA [] 2 19 0 RAO <> artco 43 3 = 18 0) OSC1/CLKIN~ MCIR 4 Sk 170 oscacikouT > Vss (15 3 o 16 0 Voo = ~vss 6 wa 151] Vo ~pre 7 7 * 140 R57 ~~ RBi [8 130 RB6 +> ~t> FAB2 (9 12 1] RBS =< +> ABS 110 11 RB4 > PDIP, SOIC, CERDIP Window ~rrce +1 ~~ 28D MCR ~=< Voo 2 27 [1 OSCI/CLKINA we 4 3 26 [1] OSC2/CLKOUT +> ~ vss T] 4 230 RC7~. we (5 uv 24) RC6=> ter 6 OBO 2 RC ~t RAI 7 aa 220 RC4<0-> ~t Ra2 CT] 8 00 210 Rca. ~=te Raa 9 9 # 20D RCo ~ ABO CT 10 19 RC1<+ ~<+ > Rei C11 18D RCO ~+ > AB2 Cf 12 1710 RB7~ ~<t > ABS 13 16] RB6=< ~t Apa [14 is 7] RBS<> SSOP ws >Vss [01 28 0) MCLR ~+ i atce O 2 27 1 OSCI/CLKIN< voo 3 26 1 OSC2/CLKOUT ~> + Voo [| 4 25 [7 AC7 = era G5 vu 240 Rcwe Aaa 6 OOF 1230 RCs ~t > RAZ q 7 @Bo 2D Re ~t AAB 8 oO0 210 RCO=> ~,rnp Go GB 2 Aco + AB1 CF 10 90 RCI ~t > Re2 C11 18D RCO +> ABs CT 12 17 RB7 = ~t~ ABs C13 16] Re6 ~~ vss [14 15 RBS <> 1994 Microchip Technology Inc. 2-3 DS30015K-page 1PIC16C5X Series at Prototype Programmers Ta ble Of Contents | 3 21,2 Production Quality Programmers .. 141 Applications ... "3 21.3 Gang Programmers... 2.0 Architectural Description .3 214 Factory Programming 24 Harvard Architecture .. 3 Index . . 22 Clocking Scheme/instruction Cycle . 3 Connecting to Microchip BBS 23 Data Register File ............. 4 Sales and Support ... 2.4 Arithmetic/Logic Unit (ALU) 4 25 Program Memory 4 . 3.0 _ PIC16C5X Series Overview .. 5 Table of Figures 3.1 UV Erasable Devices ........ 5 2.1.1 PIC16C5X Series Block Diagram... 3.2 One-Time-Programmable (OTP) Devices . 5 2.2.1 Clock/Instruction Cycle............ 3.3 Quick-Turnaround-Production (QTP) Devices . 5 4.1.1. RTCC Block Diagram (Simplified) . 40 Operational Register Files 6 4.2.1. PIC16C5X Data Memory Map... 41 Indirect Data Addressing 6 4.2.2A RTCC Timing: INT Clock/No Prescale . 4.2 Real Time Clock/Counter Register (RTCC) .. 6 4.2.28 RTCC Timing: INT Clock/Prescale 1:2. 4.2.1. Using RTCC with External Clock 6 4.2.3 RTCC Timing with Extemal Clock . 43 Program Counter 8 4.3.1. Program Memory Organization . 44 Stack 4.5.1 Status Word Register ...... 45 STATUS Word Register . .4.1 Equivalent Circuit for a Single /O Pin .. 4.5.1 Carry/Borrow and Digit Carry/Borro 5.5.2.1 VO Port Read/Write Timing 45.2 Time Out and Power Down Status Bits (T' 0, PD) 7.5.1 OPTION Register ............. 4.5.3 Program Page Preselect (PIC16C56, PIC16C57 Only) .. 9.0.1 Block Diagram RTCC/WOT Prescaler.. 46 4 File Select Register (FSR) .. 12.2.1. Crystal Operation (or Ceramic Resonator} . 5.0 VO Registers (Ports) .. 12.2.2 External Clock Input Operation . 5.1 PORTA 12.3.1 FAC Oscillator (RC type only) .. 5.2 PORTB 13.1.1 External Power on Reset Circuit 5.3 PORTC 13.1.2 Brown Out Protection Circuit .. 5.4 \/O Interfacing 13.1.3 Brown Out Protection Circuit .. 5.5 VO Programming Considerations 13.1.4 Simplified Power on Reset Block Diagram . 5.5.1 Bidirectional (/O Ports ... 13.1.5 Using External Reset Input ...............02 . 5.5.2 Successive Operations on /O Ports ... 13.1.6 Using On-Chip POR (Fast Voo Rise Time) 1 6.0 General Purpose Registers .. 13.1.7 Using On-Chip POR (Slow Voo Rise Time) 227 7.0 Special Purpose Registers 16.9.1 Electrical Structure of {/O Pins (RA, RB, RC). 36 7A W Working Register ....... 16.9.2 Electrical Structure of MCLR and RTCC Pins 36 7.2 TRISA I/O Control Register for PORTA ... 17.0.1 RTCC Timing ........seceesesee 36 7.3 TRISB V/O Control Register for PORTB .. 17.0.2 Oscillator Start-up Timing (PIC16 RC) 36 74 TRISC I/O Control Register for PORTC .. 17.0.3 Input/Output Timing for VO Ports (PIC1G6C5XAC) . 36 75 OPTION Prescaler/RTCC Option Register 18.0.1 Typical RC Oscillator Frequency vs. Temperature 37 8.0 Reset Condition 18.0.2 Typical RC Oscillator Frequency vs Voo .. 37 9.0 Pi U 18.0.3 Typical RC Oscillator Frequency vs Vo... 37 9.1 Switching Prescaler Assignment . 18.0.4 Typical RC Oscillator Frequency vs Vpo... 38 10.0 Basic Instruction Set Summary 18.0.5 Typical lpp vs Voo (Watchdog Disabled 25C) .. 38 10.1 instruction Description ... 18.0.6 Typical ipo vs Vop (Watchdog Enabled 25C) 38 11.0 Watchdog Timer (WOT) 18.0.7 Maximum Ippo vs Vop (Watchdog Disabled) 39 11.1. WOT Period..............-. 18.0.8 Maximum lep vs Voo (Watchdog Enabled) . 39 11.2 WDT Programming Considerations 18.0.9 Vt (Input Threshold Voltage) of I/O Pins vs Voo . 39 12.0 Oscillator Circuits 18.0.10 Vin, Vi for MCLR, RTCC and OSC1 12.4 Oscillator Types .. (ire RC Mada) V8 VOD. secscsssee 12.2 Crystal Oseill 18.0.11 Vix (Input Threshold Voltage) of OSC1 Input (in XT, 12.3 RC Oscillator HS, and LP Modes) vs Voo...... 13.0 Oscillator Start-up Timer (OST) 18.0.12 Typical Ipp vs Freq (Ext Clock, 25C) . 13.1 Power-On Reset (POR) .... 18.0.13 Maximum Ipp vs Freq (Ext Clock, -40 - 14.0 Power Down Mode (SLEEP) 18.0.14 Maximum lpp vs Freq (Ext Clock, -55 to +125" Cc) 42 14.1 Wake-Up... 18.0.15 WDT Timer Time-out Period vs Voo ... 42 15.0 Configuration Fuses 18.0.16 Transconductance (gm) of HS Oscillator vs Vop 42 15.1 Customer ID Code . 18.0.17 Transconductance (gm) of LP Oscillator vs Voo 15.2 Code Protection 18.0.18 Transconductance (gm) of XT Oscillator vs Voo 15.2.1 Verifying a Code-Prot 18.0.19 lon vs Vou, Voo = 3V .... 16.0 Electricat Characteristics ...... 18.0.20 loH vs Vor, Voo = 5V 16.1 Absolute Maximum Ratings . 18.0.21 lo. vs Voi, Voo = 3V. 16.3. OC Characteristics: PiC16C5X-RC, XT, HS, LP (Com) 18.0.22 low vs Voi, Von = 5V 16.4 DC Characteristics: PiC16C5XI-AC, XT, HS, LP (ind)... 20.2 + PICMASTER System Configuration . 16.5 DC Characteristics: PIC1GCSXE-AC, XT, HS, LP (Auto) .32 16.6 DC Characteristics: PIC16C5X-RC, XT, HS, LP (Com) Table of Tables and PIC16C5xXI-RC, XT, HS, LP (Ind)... 1.0.1 Overview of PIC16C5X Devices . 16.7 OC Characteristics: PIC16C5X-RC, XT, HS, LP (Auto) ...34 2.1.1 Pin Functions ...........sesucse 16.8 AC Characteristics: PIC16C5X-AC, XT, HS, LP (Com) 4.3.1 Program Counter Stack Width . and PIC16C5XI-RC, XT, HS, LP (Ind) and (Auto) 4.5.2.1 Events Affecting PD/TO Status 16.9 Electrical Structure of Pins 45.2.2 PD/TS Status After Reset . 17.0 = Timing Diagrams .... 10.0.1 Instruction Set Summary 18.0 DC & AC Charcteristics Graphs/Tables 12.2.1 Capacitor Selection for Ceramic Resonators 19.0 Packaging information 12.2.2 Capacitor Selection for Crystal Oscillator .. 19.1. Package Marking Information . 16.2 Pin Descriptions ............. 29 20.0 Development Support 18.0.1 RC Oscillator Frequencies 38 20.1 Development Toots .... 18.0.2 Input Capacitance for PIC16C54/56 44 20.2 PICMASTER: High Performance Universat in-Circuit 18.0.3 Input Capacitance for PIC16C55/57 44 Emulator 47 21.2.1 List of Third Party Programmers . . 56 20.3. PRO MATE: Universal Programmer .. 20.4 PICSTART Programmer 20.5 Assembler ........... 20.6 = Software Simulator . 20.7 Development Systems .. 21.0 EPROM Programming .........0ccsscecccessteesserereeersesenseceese DS30015K-page 2 1994 Microchip Technology Inc.PIC16C5X Series 1.0 GENERAL DESCRIPTION The PIC16C5X from Microchip Technology is a family low-cost, high-performance, 8-bit, fully static, EPROM- based CMOS microcontrollers. It employs a RISC-like architecture with only 33 single word/single cycle in- structions to learn. All instructions are single cycle (200ns) except for program branches which take two cycles. The PIC16C5xX delivers performance an order of magnitude higher than its competitors in similar price category. The 12-bit wide instructions are highly sym- metrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C5X products are equipped with special microcontroller like features that reduce system cost and power requirements. The Power-On Reset and oscillator start-up timer eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost-saving RC oscillator. Power saving SLEEP mode, watchdog timer and code protection features improves system cost, power and reliablity. The UV-erasable cerdip-packaged versions are ideal for code development, while the cost-effective One Time TABLE 1.0.1 - OVERVIEW OF PIC16C5X DEVICES Programmable (OTP) versions are suitable for produc- tion in any volume. The customer can take full advan- tage of Microchips price leadership in OTP microcon- troller while benefiting from the OTP flexibility. The PIC16C5X products are supported by an assem- bler, a software simulator, an in-circuit emulator and a production quality programmer. All the tools are sup- ported by IBM PC and compatible machines. 1.1 Applications The PIC16C5X series fits perfectly in applications rang- ing from high-speed automotive and appliance motor controlto low-power remote transmitters/receivers, point- ing devices and telecom processors. The EPROM tech- nology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages for through hole or surface mounting make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high perfor- mance, ease of use and I/O flexibility make the PIC16C5X series very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, replacement of "glue" logic in larger systems, co-processor applications). Part # EPROM RAM* | VO | Package Options PIC16C54| 512x12 | 32x8 | 12 | 18L windowed CERDIP, 18L PDIP, 18L SOIC (300 mil), 20L SSOP PIC16C55| 512x12 | 32x8 | 20 | 28L windowed CERDIP, 28L PDIP (600 mil), 28L PDIP (300 mil), 28L SOIC (300 mil), 28L SSOP PIC16C56| 1K x12 | 32x8 | 12 | 18L windowed CERDIP, 18L PDIP, 18L SOIC (300 mil), 20L SSOP PIC16C57| 2K x12 | 80x8 | 20 | 28L windowed CERDIP, 28L PDIP (600 mil), 28L PDIP (300 mil), 28L SOIC (300 mil), 28L SSOP * Including special function registers. 2.0 ARCHITECTURAL DESCRIPTION 2.1 Harvard Architecture The PIC16C5X single-chip microcomputers are low- power, high-speed, full static CMOS devices containing EPROM, RAM, I/O and a central processing unit on a single chip. The architecture is based on a register file concept with separate bus and memories for data and instructions (Harvardarchitecture). The databus and memory (RAM) are 8-bits wide, while the program bus and program memory (EPROM) have a width of 12-bits. This concept allows a simple yet powerful instruction set designed to emphasize bit, byte and register operations under high speed with overlapping instruction fetch and execution cycles. That means that, while one instruction is ex- ecuted, the following instruction is already being read from the program memory. A block diagram of the PIC16C5xX series is given in Figure 2.1.1. 2.2 Clocking Scheme/Instruction Cycle The clock input (from pin OSC1) is internally divided by four to generate four non overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, PC is incre- mented every Q1, instruction is fetched from program memory and latched into instruction register in Q4. Itis decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 2.2.1. 1994 Microchip Technology Inc. DS30015K-page 3PIC16C5X Series FIGURE 2.1.1 - PIC16C5X SERIES BLOCK DIAGRAM EPROM STACK 1 ae CONFIGURATION EPROM | OSC1 OSC2 MCLR 512K 12TO 2048 x 12 STACK 2 Osc SELECT {2 OSCILLATORY INSTRUCTION TIMING & REGISTER CONTROL 9 WOT TIME WOTATCC CLKOUT { 12 , our PRESCALER 8 "SLEEP" INSTRUCTION DECODER DIRECT ADDRESS DIRECT RAM ADDRESS . r 7) GENERAL 8 PURPOSE 5, REGISTER 4 FILE E [| TOC | Fsr_ | Ae 8 + DATA BUS $ ALU 4 7 FROM W 8 8 A TRIS 7. | trisac| PORTC q 8 ACO-RC7 (PIC16C55/C57 ONLY) TABLE 2.1.1 - PIN FUNCTIONS Name Function RAO - RA3 VO PORTA RBO - RB7 VO PORTB RCo - RC7 VO PORTC (C55/57 only) RTCC Real Time Clock/Counter MCLR Master Clear OSC1/CLKIN Oscillator (input) OSC2/CLKOUT Oscillator (output) Vop Power supply Vss Ground N/C No (internal) Connection 2.3 Data Register File The 8-bit data bus connects two basic functional ele- ments together: the Register File composed of up to 80 addressable 8-bit registers including the 1/O Ports, and an 8-bit wide Arithmetic Logic Unit. The 32 bytes of RAM are directly addressable while a "banking" scheme, with banks of 16 bytes each, is employed to address larger data memories (Figure 4.2.1). Data can be addressed direct, or indirect using the file select register. Immediate data addressing is supported by special "literal" instruc- tions which load data from program memory into the W register. The register file is divided into two functional groups: operational registers and general purpose registers. The operational registers include the Real Time Clock Counter (RTCC) register, the Program Counter (PC), the Status Register, the i/O registers (PORTs) and the File Select Register. The general purpose registers are used for data and control information under command of the instructions. In addition, special purpose registers are used to control the I/O port configuration and the prescaler options. 2.4 Arithmetic/Logic Unit (ALU) The 8-bit wide ALU contains one temporary working register (W Register). It performs arithmetic and Bool- ean functions between data held in the W Register and any file register. It also does single operand operations on either the W register or any file register. 2.5 Program Memory Up to 512 words of 12-bit wide on-chip program memory (EPROM) can be directly addressed. Larger program memories can be addressed by selecting one of up to four available pages with 512 words each (Figure 4.3.1). Sequencing of microinstructions is controlled via the Program Counter (PC) which automatically increments DS30015K-page 4 2-6 1994 Microchip Technology Inc.FIGURE 2.2.1 - CLOCKS/INSTRUCTION CYCLE PIC16C5X Series a y" y ye | a [\* : J | intone | 1 J" PT as a \ i \ / / : (Progam Comte, ( Ea i Posi i PCs oseacucouT KOC Nf (RC Mode) 1 Fetch INST (PC) ' Execute INST (PC-1) Fetch INST (PC+1} t TFC) Fetch INST(PU+) Sd ' Execute INST (PC+1) { to execute in-line programs. Program control opera- Time-Programm TP) D tions, supporting direct, indirect, relative addressing modes, can be performed by Bit Test and Skip instruc- tions, Call instructions, Jump instructions or by loading computed addresses into the PC. In addition, an on-chip two-level stack is employed to provide easy to use subroutine nesting. 3.0 PIC16C5X SERIES OVERVIEW A wide variety of EPROM and RAM sizes, number of \/O pins, oscillator types, frequency ranges and packag- ing options are available. Depending on application and production requirements the proper device option can be selected using the information and tables in this section. When placing orders, please use the "PIC16C5X Product Identification System on the back page of this data sheet to specify the correct part number. 3.1 UV Erasable Devices Four different device versions, as listed in Table 1.0.1, are available to accommodate the different EPROM, RAM, and l/Oconfigurations. These devices are optimal for prototype development and pilot series. The desired oscillator configuration is EPROM programmable as "RC", "XT", HS* or*LP". An erased device is configured as "RC" type by default. Depending on the selected oscillator type and frequency, the operating supply volt- age must be within the same range as a OTP/QTP part would be specified for. The availability of OTP devices is especially useful for customers expecting frequent code changes and up- dates. OTP devices have the oscillator type pre-config- ured by the factory, and they are tested only for this special configuration (including voltage and frequency ranges, current consumption). The program EPROM is erased, allowing the user to write the application code into it. In addition, the watch- dog timer can be disabled, and/or the code protection logic can be activated by programming special EPROM fuses. The 16 special EPROM bits for ID code storage are also user programmable. 3.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who chose not to program a medium to high quantity of units and whose code patterns have stabi- lized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production ship- ments are available. Please contact your Microchip Technology sales office for more details. 1994 Microchip Technology Inc. DS30015K-page 5PIC16C5X Series 4.0 OPERATIONAL REGISTER FILES 4.1 Indirect Data Addressing(INDF) This is not a physically implemented register. Address- ing INDF calls for the contents of the File Select Register to be used to select a file register. INDF is useful as an indirect address pointer. For example, in the instruction ADDWF INDF, W will add the contents of the register pointed to by the FSR to the content of the W Register and place the result in W. if INDF itself is read through indirect addressing (i.e. FSR = Oh), then 00h is read. If INDF is written to via indirect addressing, the result will be a NOP. 4.2 Real Time Clock/Counter Register (RTCC) This register can be loaded and read by the program as any other register. In addition, its contents can be incremented by an external signal edge applied to the RTCC pin, or by the intemal instruction cycle clock (CLKOUT=fose/4). Figure 4.1.1 is a simplified block diagram of RTCC. An 8-bit prescaler can be assigned to the RTCC by writing the proper values to the PSA bit and the PS bits in the OPTION register. OPTION register is a special register (not mapped in data memory) addressable using the OPTION' instruction. See Section 7.5 for details. If the prescaler is assigned to the RTCC, instructions writing to RTCC (e.g. CLRF RTCC, or BSF RTCC,5, ...etc.) clear the prescaler. The bit "RTS" (RTCC signa! Source) in the OPTION register determines if RTCC is incremented internally or externally. RTS=1: The clock source for the RTCC or the pres- caler, if assigned to it, is the signal on the RTCC pin. Bit 4 of the OPTION register (RTE) deter- mines, if an increment occurs on the falling (RTE=1) or rising (RTE=0) edge of the signal presented to the RTCC pin. RTS=0: The RTCC register or its prescaler, respec- tively, will be incremented with the internal instruction clock (= Fose/4). The "RTE" bit in the OPTION register and the RTCC pin are don't care in this case. The RTCC pin must not be left floating (tie to either Vop or Vss). This prevents unintended entering of test modes and to reduce the current consumption in low power applications. As long as clocks are applied to the RTCC (from internal or external source, with or without prescaler}, RTCC keeps incrementing and just rolls over when the value "FFh" is reached. All increment pulses for RTCC are delayed by two instruction cycles. After writing to RTCC, for example, no increment takes place for the following two instruction cycles. This is independent if internal or external clock source is selected. If a prescaler is as- signed to the RTCC, the output of the prescaler will be delayed by two cycles before RTCC is incremented. This is true for instructions that either write to or read- modify-write RTCC (e.g. MOVF RTCC, CLRF RTCC). For applications where RTCC needs to be tested for zero without affecting its count, use of MOVF RTCC, W instruction is recommended. Timing diagrams in Figure 4.2.2 show RTCC read, write and increment timing. 1 ING R TERN K When extemal clock input is used for RTCC, it is syn- chronized with the internal phase clocks. Therefore, the external clock input must meet certain requirements. Also, there is some delay from the occurance of the extemal clock edge to the actual incrementing of RTCC. Referring to Figure 4.1.1, the synchronization is done after the prescaler. The output of the prescaler is sampled twice in every instruction cycle to detect rising or falling edges. Therefore, itis necessary for PsouT to be high for at feast 2 tosc and low forat least 2 tosc where tosc = oscillator time period. FIGURE 4.1.1 - RTCC BLOCK DIAGRAM (SIMPLIFIED) arco (08/4 PIN RTE PRESCALER PROGRAMMABLE PS2, PS1, PSO Notes: 1. Bits, RTE, RTS, PS2, PS1, PSO are located in option register. 2. The prescaler is shared with Watchdog Timer (see Figure 9.0.1). DATA BUS | SYNC WITH INTERNAL Psour RTCC (8) CLOCKS (2 CYCLE DELAY) PSA DS30015K-page 6 2-8 a 1994 Microchip Technology Inc.PIC16C5X Series FIGURE 4.2.1 - PIC16C5X DATA MEMORY MAP FILE ADDRESS 76543210 00 INDIRECT ADDR. (*) o1 RTCC CALL 109876543210 09876543210 RETLW oz | ato [a [as PC STACK 1 |}-| STACK 2 03 STATUS FSA + s 76543210 05 PORTA TRISA 06 PORT B TRISB 543210 07 PORT C (**) TRISC [ OPTION 08 09 - OA GENERAL TO AND FROM 0B . REGISTER FILE | PURPOSE __ | VIA ALU ce reoeren | a 0b | FILE: oF oF L FROM PROGRAM MEMORY BIT 6, 5 OF FSR: BANK SELECT (PIC16C57 ONLY) 00 01 10 1 10 30 50 70 "1 12 13 14 15 16 GENERAL PURPOSE GENERAL PURPOSE v REGISTER REGISTER FILE 18 FILE (ALL TYPES) (PIC16C57 ONLY) 19 1A 1B 1c 1D (BANK 0) (***} (BANK 1) (**) (BANK 2) (***) (BANK 3) (***) 1E 1F 3F 5F 7F () NOT A PHYSICALLY IMPLEMENTED REGISTER. SEE SECTION 4.0 FOR DETAILS. (*) FILE ADDRESS 7h IS A GENERAL PURPOSE REGISTER ON THE PIC16C54/C56 ("**) BANK 0 IS AVAILABLE ON ALL MICROCONTROLLERS WHILE BANK 1 TO BANK 3 ARE ONLY AVAILABLE ON THE PIC16C57, (SEE SECTION 4.6 FOR DETAILS) 1994 Microchip Technology Inc. DS30015K-page 7 2-9PIC16C5X Series When no prescaler is used, Psout (Prescaler output, see Figure 4.1.1) is the same as RTCC clock input and therefore the requirements are: TrRTH = RTCC high time 2 2tosc + 20 ns TRIL = RTCC low time 2 2tosc + 20 ns When prescaleris used, the RTCC inputis divided by the asynchronous ripple counter-type prescaler and so the prescaler output is symmetrical. Then: Psout high time = PsouT low time = N Tat/2 where TraT = RTCC input period and N = prescale value (2, 4, ...., 256). The requirement is, therefore N TRT/2 2 2 tosc + 20 ns, or TRT2 Atos + 40ns . The user will notice that no requirement on RTCC high time or low time is specified. However, if the high time or low time on RTCC is too small then the pulse may not be detected, hence a minimum high or low time of 10ns is required. In summary, the RTCC input requirements are: Trt = RTCC period 2 (4 tosc + 40ns)/N TrTH = RTCC high time 2 10ns Trt. = RTCC low time > 10ns ( I cl ; Since the prescaler output is synchronized with the internal clocks, there is a smail delay from the time the external clock edge occurs to the time the RTCC is actually incremented. Referring to Figure 4.2.3, the reader can see that this delay is between 3 tosc and 7 tosc. Thus, for example, measuring the interval between two edges (e.g. period) will be accurate within +4 tosc (t200 ns @ 20 MHz). 4.3 Program Counter The program counter generates the addresses for up to 2048 x 12 on-chip EPROM cells containing the program instruction words (Figure 4.3.1). Depending on the device type, the program counter and its associated two-level hardware stack is 9 - 11-bits wide. TABLE 4.3.1 - PROGRAM COUNTER STACK WIDTH Part # PC width | Stack width PIC16C54/PIC16C55 9-bit 9-bit PIC16C56 10-bit 10-bit PIC16C57 11-bit 11-bit The program counter is set to afl "1"s upon a RESET condition. Ouring program execution it is auto incremented with each instruction unless the result of that instruction changes the PC itself: a) "GOTO" instructions allow the direct loading of the lower nine program counter bits (PC <8:0>). Incase of PIC16C56/PIC16C57, the upper two bits of PC (PC<10:9>) are loaded with page select bits PA1, PAO (bits 6,5 status register). Thus, GOTO allows jump to any location on any page. CALL" instructions load the lower 8-bits of the PC directly, while the ninth bit is cleared to 0". The PC value, incremented by one, will be pushed into the stack. In case of PIC16C56, PIC16C57, the upper 2-bits of PC (PC<10:9>) are loaded with Page Select bits PA1, PAO (bits 6,5 status register). b) FIGURE 4.2.2A - RTCC TIMING: INT CLOCK/NO PRESCALE G11 G2 1.03 14) G11 G2 1 G31 Ott G11 2 1 3 EOF! 112 031 G4 G11 1.03 1 Os | O11 OR CB 1 4! O11 Ce 1.031 OF * G11 a2 1.031 OF! ' ec Co ret x PC k PO+t k PC +2 C PC+3 x Po+4 x PC +5 x PC+6 : ' 1 1 1 : (PROGRAM | | INST) y MOVFAITCC, Wo: MOVFATOC,W 1 MOVFRTCC,W ) MOVFRTCC,W 1 MOVEATCS, W ' COUNTER) , | MOVWFFL 5 ' ' ' 1 1 4 a t 1 4 4 1 a 1 ' 1 1 ATCC t Frey. Rr+iX fAr+2 X. ATX NAT YX. _NATs 1X. _NAT+2 4. _NAT23 X, ; 4 4 4 ; ; ' ' ' ' ' ' ' ' ' ' WriteATCC ' ReadRTCC ReadRTCC | ReadRTCC ReadATCC | Read ATCC! \ | executed | feadsNRT =| readsNRT =| feadsNAT+1 | readeNAT+2 | readsNAT+3 | FIGURE 4.2.2B - RTCC TIMING: INT CLOCK/PRESCALE 1:2 QV F218 1G N12 13 14 | O11 G21. OG 1 OF! Gt CR 13 16) O11 2 13 14! O11 C2 103104! O11 CLC 1 Os! OTF ce Ga Ge! V 1 r PC { PC-1 x Fe Xx PC +1 k PE+2 x PC +3 t PC +4 k PO +5 x PE+6 ' t ' , 1 1 OoNTeD) \ | MOWWERTCC | MOVFRTCC,W1 MOVFRTCC,W 1 MOVFATCC,W; MOVFRTCC,W 1 MOVFRTCC, Wi ' ' ' . i ' i ' ' t ' ' ' a 4 , t 1 1 a 4 1 RTCG L Am xX RT+1 Ko 1 NAT. 1 1 Xu NAT +1 , 1 ; 4 4 4 4 4 i 4 ; ' + ' ' 1 ' ' ' ' ' ' WrteRTCC | ReadRTCC + AleadRTCC | ReadATCG ReadRTCC ' Read RICO ' i | executed readsNAT ' readsNRT ' eadsNAT =! readsNRT =| readsNRT | DS30015K-page 8 1994 Microchip Technology Inc, 2-10PIC16C5X Series c) RETLW* instructions load the program counter with the top of stack contents. lf PC is the destination in any instruction (e.g. MOVWF PC, ADDWF PC, or BSF PC,5) then the computed 8-bit result will be loaded into the lower 8-bits of program counter. The ninth bit of PC will be cleared. Incase of PIC16C56/PIC16C57, PC<10:9> will be loaded with Page Select bits PA1, PAO (bits 6,5 in status register). qd) It should be noted that because bit 8 (ninth bit) of PC is cleared in CALL instruction or any instruction which writes to the PC (e.g. MOVWF PC), all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). MORE ON PROGRAM MEMORY PA ELECT PIC PiC1 NLY): Incrementing the program counter when it is pointing to the last address of a selected memory page is also possible and will cause the program to continue in the next higher page. However, the page pre-select bits inf3 will not be changed, and the next "GOTO", "CALL", ADDWF PC", "MOVWF PC instruction will retum to the Previous page, unless the page pre-select bits have been updated under program control. For example, a NOP" at location 1FF" (page 0) increments the PC to "200" (page 1). A GOTO xxx" at "200" will retum the program to address "xxx" on page O" (assuming that the page preselect bits in file register STATUS are *0"). Upon a RESET condition, page 0 is pre-selected while the program counter addresses the last location in the last page. Thus, a*GOTO" instruction at this location will automatically cause the program to continue in page 0. 4.4 Stack The PIC16C5X series employs a two-level hardware push/pop stack (Figure 4.3.1). CALL instructions push the current program counter value, incremented by "1", into stack level 1. Stack level 1 is automatically pushed to level 2. If more than two subsequent "CALL's are executed, only the most recent two return addresses are stored. For the PIC16C56 and PIC16C57, the page preselect bits of STATUS will be loaded into the most significant bits of the program counter. The ninth bit is always cleared to "0 upon a CALL instruction. This means that subroutine entry addresses have to be located always within the lower half of a memory page (addresses 000- OFF, 200-2FF, 400-4FF, 600-6FF). However, as the stack has always the same width as the PC, subroutines can be called from anywhere in the program. RETLW instructions load the contents of stack level 1 into the program counter while stack level 2 gets copied into level 1. If more than two subsequent "RETLW's are executed, the stack will be filled with the address previ- ously stored in level 2. For the PIC16C56 and PIC16C57, the return will be always to the page from where the subroutine was called, regardiess of the current setting of the page pre-select bits in file register STATUS. Note that the W register will be loaded with the litera! value specified in the RETLW instruction. This is particularly useful for the implementation of "data" tables within the program memory. FIGURE 4.2.3 - RTCC TIMING WITH EXTERNAL CLOCK EXT CLOCK INPUT OR } PRESCALER OUT (NOTE 2} AM, EXT CLOCK/PRESCALER OUTPUT AFTER SAMPLING INCREMENT RTCC (Q4) ' l 1 ' T FQN C2 1314 (at a@eias1a4ari@iasias'atjazias; at! 1 Small pulse 1 '_{~\ misses sampling T 1 | tot at t Notes: RTCC R 1. Delay from clock input change to RTCC increment is 3 tosc to 7 tosc. (Duration of Q = tosc). Therefore, the error in measuring the interval between two edges on RTCC input = + 4 tosc max. 2. External clock if no prescaler selected, Prescaler output otherwise. 3 The arrows indicate the points in time where sampling occurs. R+2 1994 Microchip Technology inc. 0S30015K-page 9PIC16C5X Series FIGURE 4.3.1 - PROGRAM MEMORY ORGANIZATION GOTO, CALL, INST WITH PC AS DESTINATION ... . FROM STATUS<6> PIC16C57 ONLY) GOTO, CALL, INST WITH PC AS DESTINATION .... ... FROM STATUS<5> PIC16C56/C57 ONLY) GOTO .. DIRECT FROM INSTRUCTION WORD CALL, INST WITH PC AS DESTINATION ......... ALWAYS "0" GOTO, CALL 0. ccessesessesesseeesnsnnsnsneereseese DIRECT FROM INSTRUCTION WORD INST WITH PC AS DESTINATION ......... FROM ALU PC | | RETLW, CALL A10 AQ A8 A<7:0> STACK LEVEL 1 [ c 9-11 BIT 41 8 STACK LEVEL 2 42 000 MAX. EPROM ADDRESS FOR: 00 OFF PAGE O 100 1FF PIC16C54/PIC16C55 200 01 2FF os PAGE 1 300 3FF PIC16C56 400 10 4FF PAGE 2 500 5FF 600 u 6FF PAGE 3 700 7FF PIC16C57 0S30015K-page 10 1994 Microchip Technology Inc. 2-12PIC16C5X Series 4.5 STATUS Word Register This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bits for larger program memories than 512 words (PIC16C56, PIC16C57). The STATUS register can be destination for any instruc- tion like any other register. However, the STATUS bits are set after the following write. Furthermore, TO and PD bits are not writable. Therefore, the result of an instruction with STATUS register as destination may be FIGURE 4.5.1 - STATUS WORD REGISTER different than intended. For example, CLRF STATUS will clear all bits except for TO and PD and then set the Z bit and leave status register as OOOUU100 (where U = unchanged). It is recommended, therefore, that only BCF, BSF and MOVWF instructions are used to alter the STATUS registers because these instructions do not affect any STATUS bit. For other instructions, affecting any STATUS bits, see Section Instruction Set Summary" (Table 10.0.1). i) 6) 4 8 a (0) oO | paz | par | pao | TO | FO | z | m | c \_/ RESET CONDITION: PA2,PA1, PAO cleared to 0'. TO, PD are set or reset as shown in Table 4.5.2.1 Z, DC, C are unknown on power on reset and unchanged in any other reset. CARRY/BORROW BIT: For ADOWF and SUBWF instructions, this bit is set if there is a carry out from the most significant bit of the resultant. Note that a subtraction is executed by adding the two's complement of the second operand. For rotate (RAF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. DIGIT CARRY/BORROW BIT: For ADDWF and SUBWF instructions, this bit is set if there is a carry out from the 4th low order bit of the resultant. ZERO BIT: Set if the result of an arithmetic or logic operation is zero. POWER DOWN BIT: Set to "1" during power up or by a CLRWDT command. This bit is reset to O" by a SLEEP instruction. TIME-OUT BIT: Set to "1" during power up and by the CLRWDT and SLEEP command. This bit is reset to "0" by a watchdog timer time out. PIC16C54/C55_ - Two general purpose read/write bits PIC16C56 : BITS ... Page preselect bit 0 = Page 0 (000 - 1FF) 1 = Page 1 (200 - 3FF) BIT 6 ... General purpose read/write bit PIC16C57 : Two page preselect bits 00 = Page 0 (000 - 1FF) 01 = Page 1 (200 - 3FF) 10 = Page 2 (400 - 5FF) 11 = Page 3 (600 - 7FF) BIT 7: General purpose read/write bit (reserved for future use) 1994 Microchip Technology Inc. DS30015K-page 11PIC16C5X Series 4. RRY, iGl R BORROW BITS: The Carry bit (C) is a carry out in addition operation (ADDWF) and a borrow out in subtract operation (SUBWF). It is also affected by RRF and RLF instructions. The following examples explain carry/borrow bit operation: ;SUBWF Example #1 clrt 0x20 ;(20h)=0 movlw 1 zwreg=1 subwf 0x20 ;(20h)=f(20h) -wreg=0-1=FFh ;Carry=0: Result is negative ;SUBWF Example #2 movlw OxFF ; movwf 0x20 ;(20h)=FFh clrw ;wreg=0 subwf 0x20 ;(20h)=(20h)-wreg=FFh- O=FFh ;Carry=1:Result is positive i The digit carry operates in the same way as the carry bit, i.e. it is a borrow in subtract operation. 4.5.2 TIME QUT AND POWER DOWN STATUS BITS (TO, PD) The TO and PD bits in the STATUS register can be tested to determine if a RESET condition has been caused by a Watchdog Timer time-out, a power-up condition, or a wake-up from SLEEP by the Watchdog Wimer or MCLR pin. These STATUS bits are only affected by events listed in Table 4.5.2.1. TABLE 4.5.2.1 - EVENTS AFFECTING PD/ TO STATUS BITS Event TO PD | Remarks Power-up 1 1 WODT Timeout 0 X No effect on PD SLEEP instruction 1 0 CLRWODT instruction | 1 1 Note: | AWDT timeout will occur regardless of the status of the TO bit. A SLEEP instruction will be executed, regardiess of the status of the PD bit. Table 4.5.2.2 reflects the status of PD and TO after the corresponding event. TABLE 4.5.2.2 - PD/TO STATUS AFTER RESET RESET was caused by WDT wake-up from SLEEP WDT time-out (not during SLEEP) MCLR wake-up from SLEEP Power-up = Low pulse on MCLR input xa 2m OO x2 O=090 Note: The PD and TO bit maintain their status (X) until an event of Table 4.5.2.1 occurs. A low-pulse on the MCLR input does not change the PD and TO status bits. 4. RAM PA PIC16C57 ONLY) Bits 5-6 of the STATUS register are defined as PAGE address bits PAO<1:0>, and are used to preselect a program memory page. When executing a GOTO, CALL, or an instruction with PC as destination (e.g. MOVWF PC), PA<1:0> are loaded into bit A<10:9> of the program counter, selecting one of the available program memory pages. The direct address specified in the instruction is only valid within this particular memory page. RETLW instructions do not change the page preselect bits. Upon a RESET condition, PA<2:0> are cleared to "O's. 4.6 File Select Register (FSR) PIC16054/C55/C56 Bits 0-4 select one of the 32 available file registers in the indirect addressing mode (that is, calling the INDF register in any of the file oriented instructions). TP Bits 5-7 of the FSR are read-only and are always read as one's. If no indirect addressing is used, the FSR can be used as a 5-bit wide general purpose register. PiC16C57 ONLY Bits 5 and 6 of the FSR select the current data memory bank (Figure 4.2.1). The lower 16 bytes of each bank are physically identical and are always selected when bit 4 of the FSR (in case of indirect addressing) is 0, or bit 4 of the direct file register address of the currently executing instruction is 0 (e.g. MOVWE 08). Only if bit 4 in the above mentioned cases is "1, bits 5 and 6 of the FSR select one of the four available register banks with 16 bytes each. Bit 7 is read-only and is always read as one. DS30015K-page 12 2-14 1994 Microchip Technology Inc.PIC16C5X Series 5.0 VO REGISTERS (PORTS) The I/O registers can be written and read under program control like any other register of the register file. How- ever, "read" instructions (e.g. MOVF PORTB,W) always read the I/O pins, regardless if a pin is defined as "input" or output. Upon a RESET condition, all /O ports are defined as "input" (= high impedance mode) as the I/O control registers (TRISA, TRISB, TRISC) are all set to ones. The execution of a TRIS f" instruction with correspond- ing zeros in the W-register is necessary to define any of the I/O pins as output. 5.1 PORTA 4-bit I/O register. Low order 4-bits only are used (RAO - RA3). Bits 4 -7 are unimplemented and read as "zeros." .2 PORTB 8-bit 1/O register. 5.3 PORTC PIC16C55/C57: 8-bit I/O register. PIC16C54/C56: General purpose register. 5.4 VO Interfacing The equivalent circuit for an VO port bit is shown in Figure 5.4.1. All ports may be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g. MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the correspond- ing direction control bit (in TRISA, TRISB, TRISC) must be set to zero. For use as an input, the corresponding TRIS bit must be one. Any I/O pin can be programmed individually as input or output. FIGURE 5.4.1 - EQUIVALENT CIRCUIT FOR A SINGLE V/O PIN FROM D Q veo DATA DATA LATCH at "WRITE" cK a r } > P TODATABUS _4 a ; : PIN "READ" FROM D Q -RE W-REGISTER vo CONTROL aa aren |) "TRIS f* a| ~ set 9 Vss _ "RESET" = 1994 Microchip Technology Inc. 2-15 0S30015K-page 13PIC16C5X Series 5.5 VO Programming Considerations A | TIONAL I/O PORT: Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-output the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For ex- ample, a BSF operation on bit 5 of PORTB will cause all eight bits of f6 to be read into the CPU. Then the BSF operation takes place on bit 5 and PORTB is re-output to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (say bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit 0 is switched into output mode later on, the content of the data latch may now be unknown. FIGURE 5.5.2.1 - /O PORT READ/WRITE TIMING A pin actively outputting a "0" or "1" should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", *wired-and). The resulting high outputcurrents may damage the chip. IVE_OPERATI VO Pi The actual write to an /O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (see Figure 5.5.2.1). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or an other instruction not accessing this 1/O port. , at] G2] a3} 4" ai] G2] as] a4! at} ce] aa! a4! a1! G2] csi ar! Note: Fo X PC x PC+1 XK) PG+2 x PC+3 | | This example shows Instruction 1 MOVWF PORTB 1 MOVF PORTB,W: = NOP ' NOP | write to PORTB followed fetched ' WritetoPORTB ' ReadPORTB + '! ' ' | by a read from PORTB. ' ' t ( ' { 1 1 1 \ Note that the data setup 0} | 1 1 time = (0.25 TCY - TPD) AB (7:0) f t A T ' where TCY = instruction ' ' fort pin ' | cycle. Therefore, at ' 1 , +t Sampled here , 1 higher clock frequencies, ' ' i! 1 \ write followed by a read ' ' Execute iTPO Execute ' Execute ' may be problematic. ' MOVWF PORTB ' MOVF PORTB, W! NOP ' DS30015K-page 14 2-16 1994 Microchip Technology Inc.PIC16C5X Series. 6.0 GENERAL PURPOSE REGISTERS PIC16C54/C55/C56: f08h-f1Fh: are general purpose register files. PIC1 7 only: f08h-fOFh: are general purpose register files which are always selected, independent of bank select. f10h-f1Fh: general purpose register files in memory bank 0. f20h -f2Fh: physically identical to f00 - fOF. f30h-f3Fh: general purpose register files in memory bank 1. f40h-f4Fh: physically identical to f00 - fOF. f50h-fSFh: general purpose register files in memory bank 2. f60h -f6Fh: physically identical to f00 - f0. {70h -f7Fh: general purpose register files in memory bank 3. 7.0 SPECIAL PURPOSE REGISTERS 7.1 W Working Register Hoids second operand in two operand instructions and/ or supports the internal data transfer. FIGURE 7.5.1 - OPTION REGISTER 7.2 TRISA YO Control Register For PORTA Only bits 0 - 3 are available. The corresponding I/O port (f5) is only 4-bit wide. 7.3 TRISB VO Control Register For PORTB 7.4 TRISC UO Control Register For PORTC The I/O control registers will be loaded with the content of the W register by executing of the TRIS f instruction. A "1" in the I/O control register puts the corresponding VO pin into a high impedance mode. A "0" puts the contents of file register PORTA, PORTB, or PORTC, respectively, out on the selected I/O pins. These registers are "write-only and are set to all ones upon a RESET condition. 7.5 QPTION Prescaler/RTCC Option Register Defines prescaler assignment (RTCC or WDT), pres- caler value, signal source and signal edge for the RTCC. The OPTION register is write-only and is 6-bit wide. By executing the "OPTION" instruction, the contents of the "W" register will be transferred to the option register. Upon a RESET condition, the option register is set to all ones. 4 3 5 | ars | 1... 2 1 9 ATE PSA | PS2 | PSi1 | PSO RESET VALUE: 111111b PRESCALER VALUE | ATCC RATE| WOT RATE 0 0 0 1:2 1:1 Qo 0 1 1:4 1:2 0 1 0 1:8 tid 0 1 1 1:16 1:8 1 0 0 1: 32 1: 16 1 9 1 1: 64 1:32 1 1 0 1: 128 1: 64 1 1 1 1: 256 1: 128 PRESCALER ASSIGNMENT BIT: 0... RTCC 1... WOT RTCC SIGNAL EOGE: 0.... INCREMENT ON LOW-TO-HIGH TRANSITION ON RTCC PIN 1... INCREMENT ON HIGH-TO-LOW TRANSITION ON ARTCC PIN RTCC SIGNAL SOURCE: 0.... INTERNAL INSTRUCTION CYCLE CLOCK (CLKOUT) TRANSITION ON RTCC PIN 1994 Microchip Technology Inc. 2-17 DS30015K-page 15PIC16C5X Series 8.0 RESET CONDITION ARESET condition can be caused by applying power to the chip (power-up), pulling the MCLR input low, or by a Watchdog Timer timeout. The device will stay in RESET as tong as the oscillator start-up timer (OST) is active or the MCLR input is "low." The oscillator start-up timer is activated as soon as MCLR input is sensed to be high. This implies that in case of Power-On Reset with MCLR tied to Voo the OST starts from power-up. In case of WDT time-out, it will start at the end of the time-out (since MCLR is high). In case of MCLR reset, the OST will start when MCLR goes high. The nominal OST time-out period is 18ms. See Section 13.0 for detailed information on OST and power on reset. During a RESET condition the state of the PIC16C5X is defined as : The oscillator is running, or will be started (power- up or wake-up from SLEEP). * AIlI/O port pins (RAO - RA3, RBO - RB7, RCO - RC7) are put into the high-impedance state by setting the "TRIS" registers to all "ones" (= input mode). * The Program Counter is set to all ones (1FFh in PIC16C54/55, 3FFh in PIC16C56 and 7FFh in PIC16C57). The OPTION register is set to all "ones". The Watchdog Timer and its prescaler are cleared. * The upper-three bits (page select bits) in the STATUS Register are cleared to "zero." * "RC" devices only: The "CLKOUT" signal on the OSC2 pin is held at alow" level. 9.0 PRESCALER An8-bit counter is available as a prescaler forthe RTCC, or as a post-scaler for the Watchdog Timer, respectively (Figure 9.0.1). For simplicity, this counter is being re- ferred to as "prescaler* throughout this data sheet. Note that there is only one prescaler available which is mutu- ally exclusively shared between the RTCC and the Watchdog Timer. Thus, a prescaler assignment for the RTCC means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PSO-PS2 bits in the OPTION register determine the prescaler assignment and pre-scale ratio. When assigned to the RTCC, all instructions writing to the RTCC (e.g. CLRF RTCC, MOVWF RTCC, BSF RTCC,x....etc.) will clear the prescaler. When assigned to WOT, a CLRWOT instruction will clear the prescaler along with the Watchdog Timer. 9.1 Switching Prescaler Assignment NGI E TO WDT The prescaler assignment is fully under software con- trol, i.e., it can be changed on the fly* during program execution. To avoid an unintended device RESET, the following instruction sequence must be executed when changing the prescaler assignment from RTCC to WDT: 1. MOVLW B'xxOxOxxx' _; Select internal clock and select new 2. OPTION ; prescaler value. If new prescale value ; is = '000' or '001', then select any other ; prescale value temporarily. 3. CLRF 4 ; Clear RTCC and prescaler. 4, MOVLW Bcooclox' =; Select WDT, do not change prescale ; value. 5. OPTION ; 6. CLRWOT; Clears WDT and prescaler. le MOVLW Boooxtoa' _; Select new prescale value. 8. OPTION ; Steps 1 and 2 are only required if an external RTCC source is used. Steps 7 and 8 are necessary only if the desired prescale value is 000 or '001'. CHANGING PRESCALER FROM WDT TO ATCC To change prescaler from WDT to RTCC use the foliow- ing sequence: 1. CLRWOT; 2. MOVLWB' 1000x0200 Clear WOT and prescaler ; Select RTCC, new prescale value sand clock source 3. OPTION : DS30015K-page 16 2-18 1994 Microchip Technology Inc.PIC16C5X Series FIGURE 9.0.1 - BLOCK DIAGRAM RTCC/WDT PRESCALER CLKOUT (=Fosc/4) 0 1 RTCC PIN RTE | 0 RTS DATA BUS 8 SYNC 2 ATCC (11) CYCLES 8-BIT COUNTER WATCH boa TIMER | 8-TO-1 MUX PSA g WOT ENABLE EPROM FUSE WOT TIMEOUT Note: RTE, RTS, PSA, PSO-PS2 are bits in the OPTION register. 10.0 BASIC INSTRUCTION SET SUMMARY Each PIC16CS5xX instruction is a 12-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the opera- tion of the instruction. The PIC16C5xX instruction set summary in Table 10.0.1 lists byte-oriented, bit-ori- ented, and literal and control operations. For byte-oriented instructions, f" represents a file regis- ter designator and "d* represents a destination designa- tor. The file register designator specifies which one of the 32 PIC16CS5X file registers is to be utilized by the instruction. For the PIC16C57, bits 5 and 6 in the FSR determine the selected register bank. The destination designator specifies where the result of the operation is to be placed. If d" is zero, the result is placed in the W register. If "d" is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, "b" represents a bit field designator which selects the number of the bit affected by the operation, while "ft" represents the number of the file in which the bit is located. For literal and control operations, "k" represents an 8- or 9-bit constant or literal value. All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this 1994 Microchip Technology Inc. case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruc- tion execution time is 1 usec. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 usec. Notes to Table 10.0.1 Note 1: The ninth bit of the program counter will be forced to a zero by any instruction that writes to the PC except for GOTO (e.g. CALL, MOVWF PC etc.). See Section 4.3 on page 8 for details. Note 2: When an 1/O register is modified as a function of itself ( e.g. MOVF PORTB,1 ), the vatue used will be that value present on the pins them- selves. For example, if the data latch is "1" for a pin configured as output and is driven low by an external device, the data will be written back with a O'. Note 3: The instruction "TRIS f* , where f = 5,6, or 7 causes the contents of the W register to be written to the tristate latches of the specified file (port). A one forces the pin to a high imped- ance state and disables the output buffers. If this instruction is executed on file register RTCC (and, where applicable, d=1), the pres- caler will be cleared if assigned to the RTCC. Note 4: DS30015K-page 17 2-19PIC16C5X Series TABLE 10.0.1 - INSTRUCTION SET SUMMARY (11-6) (5) (4-0) BYTE -ORIENTED FILE REGISTER OPERATIONS opcooe | a | rues | d = 0 for destination W d= 1 for destination f Instruction-Binary (Hex) Name Mnemonic, Operands Operation Status Affected Notes 0001 lidf ffFF icf Add Wandf ADDWF ft,d W+fod C,DC,Z 1,2,4 0001 O1df fEE 14 AND Wandf ANDWF f,d W&fod Z 2,4 0000 O11f FLEE OGE Clearf CLRF f Of Zz 4 0000 0100 0000 040 ClearW CLRW F- 0>W Zz 0010 Qldft f 24 Complementf COMF f,d fod Zz 2,4 0000 1lldf ff OCf Decrementf DECF f,d f-1-d Z 2,4 0010 11df Ef 2cf Decrementf,Skipif Zero DECFSZ i,d f-1 4d, skip if zero None 2,4 0010 Lodf ffEE 28f Incrementf INCF fd f+tod Z 2,4 0011 11df fEE 3cf Incrementf,Skipifzero INCFSZ {,d f+1-d, skipifzero None 2,4 0001 O0df FEE 10 Inclusive OR Wand f ORWF f,d Wvfod Zz 2,4 0010 O0df fFFEE 20 Move f MOVF f,d fod Zz 24 0000 OO1f FEEE O2 MoveWtof MOVWF f Wf None 1,4 0000 0000 0000 000 No Operation NOP - - None 0011 Olaf EE 34f Rotate lett f RLF f,d f(n) > d(n+1), C d(0), (7) = c 2,4 0011 O0df FLEE 30f Rotate rightf RRF f,d f(n) > d(n-1), C > d(7), (0) > C c 2,4 0000 10df fff O8 Subtract W fromf SUBWF f,d f-Wod[f+W+1d] C,DC,Z 1,2,4 0011 10df fff 38 Swap halvesf SWAPF f,d_ f(0-3) o f(4-7) 3d None 2,4 0001 lodf fff 18 Exclusive OR Wand f XORWF [,d W@fod Zz 2,4 (11-8) (7-5) (4-0) BIT- ORIENTED FILE REGISTER OPERATIONS | OPCODE | b(BIT #)| (FILE #) | Instruction-Binary (Hex) Name Mnemonic, Operands Operation Status Affected Notes 0100 bbbf ffff 4bf Bit Clearf BCF f,b O-> f(b) None 2,4 0101 bbbf ffFf Sbf Bit Setf BSF f,b 1 {(b) None 2,4 0110 bbbf ffff 6bf Bit Test f,Skip if Clear BIFSC f,b Test bit (b) in file (f): Skip if clear None 0111 bbbf ffffF 7bf Bit Test f, Skip if Set BIFSS {,b Test bit (b) in file (f): Skip if set None (11-8) (7-0) Instruction-Binary (Hex) Name Mnemonic, Operands Operation Status Affected Notes 1110 kkkk kkkk Ekk ANDO Literal and W ANDLW k k& WoW Zz 1001 kkkk kkkk 9kk Call subroutine CALL k PC + 1 Stack, k PC None 1 0000 0000 0100 004 _ Clear Watchdog timer CLRWDT - 0 WDT (and prescaler, if assigned) TO, PD 101k kkkk kkkk Akk GoToaddress(kis9bit) GOTO k k PC (9 bits) None 1101 kkkk kkkk Dkk _ Incl. OR Literal and W IORLW ek kvWo3W Zz 1100 kkkk kkkk Ckk Move Literal to W MOVLW k k>W None 0000 0000 0010 002 Load OPTION register OPTION - W OPTION register None 1000 kkkk kkkk 8kk Return,place LiteralinW RETLW k k > W, Stack - PC None 0000 0000 0011 003 Go into standby mode SLEEP - 0 > WDT, stop oscillator TO, PD 0000 0000 OfF OOF Tristate portf TRIS f W- 1/0 control register f None 3 1111 kkkk kkkk Fkk Excl. OR LiteralandW XORLW k k@wow Z Notes: See previous page DS30015K-page 18 1994 Microchip Technology Inc. 2-20PIC16C5X Series 10.1 Instruction Description ADDWE ADD Wtof Syntax: ADDWF fd Encoding: Words: 1 Cycles: 1 Operation: (W+f)>d Status bits: C, DC, Z Description: Add the contents of the W register to register f. If d is 0 the result is stored in the W register. If d is 1 the result is stored back in register f. ANDLW AND Literal and W Syntax: ANDLW) k Encoding: Words: 1 Cycles: 1 Operation: (W.AND.k) > W Status bits: Z Description: The contents of W register are ANDed with the 8-bit literal k. The result is placed in the W register. ANDWE AND W witht Syntax: ANDWF fd Encoding: Words: 1 Cycles: 1 Operation: (W.AND. f) od Status bits: Z Description: AND the W register with register f. ifd is 0 the result is stored in the W register. If d is 1 the result is stored back in register f. BCF Bit Clear f Syntax: BCF f,b Words: 1 Cycles: 1 Operation: 0 f(b) Status bits: None Description: Bit b in register f is reset to 0. BSF Bit Set f Syntax: BSF f,b Encoding: Words: 1 Cycles: 1 Operation: 1 - f(b) Status bits: | None Description: Bit b in register ? is set to 1. BIFSC Bit Test, skip if Clear Syntax: BTFSC f,b Encoding: Words: 1 Cycles: 1(2) Operation: _ skip if f(b) = 0 Status bits: None Description: _ If bit b in register f is O then the next instruction is skipped. If bitb is 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed in- stead making this a two-cycle instruction. BTFSS Bit Test, skip if Set Syntax: BIFSS f,b Encoding: Words: 1 Cycles: 1 (2) Operation: skip if f(b) = 1 Status bits: None Description: If bit b in register f is 1 then the next instruction is skipped. Ifbit*b"is "1", the nextinstruction, fetched during the current instruction execution, is discarded and a NOP is executed in- stead making this a two-cycle instruction. CALL Subroutine Call Syntax: CALL k Encoding: Words: 1 Cycles: 2 Operation: PC+1- TOS; k > PC<7:0>, '0' -+ PC<8>, PA2, PA1, PAQ > PC<11:9>; Status bits: None 1994 Microchip Technology Inc. 2-21 DS30015K-page 19PIC16C5X Series Description: Subroutine call. First, return address (PC + 1) is pushed into the stack. The eight bit value is loaded into PC bits <7:0>. PC bit Sis cleared. PA <2:0> bits are loaded into PC <11:9>. CALL is a two cycle instruc- tion. CLRF Clear f Syntax: CLRF f Encoding: Words: 1 Cycles: 1 Operation: O0Oh-f Status bits: Z Description: The contents of register are set to 0. CLRW Clear W Register Syntax: CLRW Encoding: Words: 1 Cycles: 1 Operation: O0h-W Status bits: Z Description: Wregisterediscleared. Zero bit (Z) is set. CLRWDT__ Clear Watchdog Timer Syntax: CLRWDT Encoding: Words: 1 Cycles: 1 Operation: 00h -WDT, 0 WDT prescaler, Status bits; 170,12 PD Description: CLRWDT instruction resets the Watchdog Timer.|t also resets the prescaler of the WDT. Status bits TO and PD are set. COME Complement f Syntax: COMF fd Encoding: Words: 1 Cycles: 1 Operation: f> d Status bits: Z Description: The contents of register f are comple- mented. Ifd is Othe resuitis storedin W. lf d" is 1 the result is stored back in register f. DECE Decrement_f Syntax: Encoding: Words: Cycles: Operation: Status bits: Description: DECFSZ DECF fd 1 1 (1) 3d Zz Decrement register ?. Ifd is 0 the result is stored in the W register. If d is 1 the result is stored back in register f. Decrement f, skip if 0 Syntax: Encoding: Words: Cycles: Operation: Status bits: Description: GOT Syntax: Encoding: Words: Cycles: Operation: Status bits: Description: INCE Syntax: Encoding: Words: Cycles: Operation: Status bits: DECFSZ fd 0010 | lldf | ffff 1 1 (2) (f- 1) d; skip if result = 0 None The contents of register f are decre- mented. If d is O the result is placed in the W register. !f d is 1 the result is placed back in register f. If the result is 0 the next instruction is skipped. lf the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two- cycle instruction. nconditional Branch GOTO k 1 2 k > PC<8:0>, PA2, PA1, PAO => PC<11:9>; None The tow order nine bits come from the immediate value. The upper-three bits are loaded from the PA <2:0> bits in the STATUS register. Increment f INCF f,d 1 { (f+ 1) 3d zZ DS30015K-page 20 1994 Microchip Technology Inc.Description: The contents of register ? are incre- mented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register ?. INCFSZ Increment f, skip if 0 Syntax: INCFSZ_ f,d Words: 1 Cycles: 1 (2) Operation: (f+ 1) > d, skip if result = 0 Status bits: | None Description: The contents of register 7 are incre- mented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. If the result is 0 the next instruction is skipped. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two- cycle instruction. IORLW Inclusive OR Literal with W Syntax: IORLW sk Words: 1 Cycles: 1 Operation: (W.OR.k)>W Status bits: Z Description: The contents of the W register are ORed with the 8-bit literal k. The result is placed in the W register. lORWE Inclusive OR W with f Syntax: IORWF fd Words: 1 Cycles: 1 Operation: (W.OR.f) od Status bits: Z Description: Inclusive OR the W register with register f". If d is 0 the result is stored in the W register. Ifd is 1 the result is stored back in register f. a 1994 Microchip Technology Inc. PIC16C5X Series MOVE Move f Syntax: MOVF f,d Words: 1 Cycles: 1 Operation: (f}od Status bits: Z Description: The contents of register "f* are moved. If d" is O the result is placed in the W register. If "d" is 1 the result is placed back in register "f". MOVLW____ Move Literal to W Syntax: MOVLW_ k Encoding: Words: 1 Cycles: 1 Operation: koW Status bits: None Description: The 8-bitliteralk is loadedinto W register. MOVWE Move W tof Syntax: MOVWFE | f Words: 1 Cycles: 1 Operation: W-f Status bits: None Description: Move data from W register to register f. NOP No Operation Syntax: NOP Encoding: Words: 1 Cycles: 1 Operation: No operation Status bits: None Description: No operation OPTION Load Option Register Syntax: OPTION Words: 1 Cycles: 1 Operation: W OPTION; Status bits: None Description: Thecontents ofthe W register is loaded in the OPTION register. DS30015K-page 21PIC16C5X Series RETLW Return Literal to W Syntax: RETLW_ k Words: 1 Cycles: 2 Operation: k -W; TOS PC; Status bits: None Description: The W register is loaded with the eight bit literal k. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. RLF Rotate Left_f through Car Syntax: RLF f,d Encoding: Words: 1 Cycles: 1 Operation: = f<n> > d<n4+1>, f<7>> C, C > d<0>; Status bits: C Description: The contents of register f are rotated one bit to the left through the Carry Flag. It d is O the result is placed in the W register. Ifd is 1 the resultis stored back in register ?. RRE Rotate Right _f through Car Syntax: RRF f,d Encoding: Words: 1 Cycles: 1 Operation: f<n> od<n-1>, f<0> ~C, C7 d<7>; Status bits: C Description: The contents of register f are rotated one bit to the right through the Carry Flag. lf d is O the result is placed in the W register. If d is 1 the result is placed back in register f. SLEEP Syntax: SLEEP Encoding: Words: 1 Cycles: 1 Operation: O>PD,1 >TO; 00h + WDT, 0 + WDT prescaler; Status bits: TO, PD Description: The power-down status bit (PD) is cleared. Time-out status bit (TO) is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See section on SLEEP mode for more details. SUBWE Subtract W_from f Syntax: SUBWF i,d Encoding: Words: 1 Cycles: 1 Operation: (fW) ~d Status bits: C, DC, Z ;SUBWF Example #1 clrf 0x20 ;{20h)=0 movlw 1 zwreg=1 subwf 0x20 ;f(20h)=f(20h)-wreg=0-1=FFh ;Carry=0; Result is negative ; SUBWF Example #2 movlw 0xFF ; movwf 0x20 ;(20h)=FFh clrw z7wreg=0 subwf 0x20 ;f(20h)=(20h) -wreg=FFh- O=FFh ;Carry=1:Result is positive Description: Subtract (2's complement method) the W register from register f. If d is 0 the result is stored in the W register. If d is 1 the result is stored back in register f. SWAPF Swap f Syntax: SWAPF fd Words: 1 Cycles: 1 Operation: f<0:3> > d<4:7>, f<4:7> > d<0:3>; Status bits: None Description: The upper and lower nibbles of register? are exchanged. if d is 0 the result is placed in W register. If d is 1 the result is placed in register f. TRIS Load TRIS Register Syntax: TRIS f Encoding: Words: 1 Cycles: 1 Operation: W TRIS register f; Status bits: | None Description: TRIS register f (f= 5, 6 or 7) is loaded with the contents of the W register. DS30015K-page 22 1994 Microchip Technology Inc.XORLW Exclusive OR literal with W Syntax: XORLW_ sk Encoding: Words: 1 Cycles: 1 Operation: (W .XOR.k}) > W Status bits: Z Description: Thecontents ofthe W register are XOR'ed with the 8-bit literal k. The result is placed in the W register. XORWE Exclusive OR W with f Syntax: XORWF fd Encoding: Words: 1 Cycles: 1 Operation: (W .XOR. f)>d Status bits: Z Description: Exclusive OR the contents of the W reg- ister with register f. If d is O the result is stored in the W register. If d is 1 the result is stored back in register f. 11.0 WATCHDOG TIMER (WDT) The Watchdog Timer is realized as a free running on- chip RC oscillator which does not require any external components. That means that the WDT will run, even if the clock on the OSC1/OSC2 pins of the device has been stopped, for example, by execution of a SLEEP instruction. A WDT timeout generates a device RESET condition. The WDT can be permanently disabled by programming a "zero" into a special EPROM fuse which is not part of the normal program memory EPROM. 11.1 WDT Period The WOT has a nominal time-out period of 18ms, (with no prescaler). The time-out periods vary with tempera- ture, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.5 seconds can be realized. The *CLRWDT" and "SLEEP" instructions clear the WDT and the prescaler count, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. The status bit, TO, in the STATUS register, wil! be cleared upon a Watchdog Timer timeout. PIC16C5X Series The WDT period is a function of the supply voltage, operating temperature, and will also vary from unit to unit due to variations in the manufacturing process. Please refer to the graphs in Section 18.0 and DC specs for more details. 11.2 WDT Programming Considerations It should also be taken in account that under worst case conditions (Vop = Min., Temperature = Max., max. WOT prescaler) it may take several seconds before a WOT timeout occurs. 12.0 OSCILLATOR CIRCUITS 12.1 Oscillator Types The PIC16C5X series is available with four different oscillator options. On windowed devices, a particular oscillator circuit can be selected by programming the configuration EPROM accordingly. On OTP and QTP devices, the oscillator configuration is programmed by the factory and the parts are tested only to the according specifications. 12.2 Crystal Oscillator The PIC16C5X-XT, -HS, or LP needs a crystal or ce- ramic resonator connected to the OSC1 and OSC2 pins to establish oscillation (Figure 12.2.1). XT = Standard crystal oscillator, HS = High speed crystal oscillator. The series resistor RS may be required for the "HS" oscilla- tor, especially at lower than 20 MHz oscillation fre- quency. It may also be required in XT mode with AT strip-cut type crystals to avoid overdriving. 12.3 RC Oscillator For timing insensitive applications the "RC" device op- tion offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values and the operation temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process param- eter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation to due tolerance of external R and C components used. Figure 12.3.1 shows how the R/C combination is connected to the PIC16C5X. For Rext values below 2.2 kOhm, the oscillator operation may become unstable, or stop com- pletely. For very high Rext values (e.g. 1 MOhm), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 5 kOhm and 100 kOhm. Although the oscillator will operate with no extemal capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small extemal capacitance, the oscillation frequency can vary dramatically due to changes in external capaci- tances, such as PCB trace capacitance or package lead frame capacitance. 1994 Microchip Technology Inc. 2-25 DS30015K-page 23PIC16C5X Series See the table in Section 18.0 for RC frequency variation trom part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). See characteristics in Section 18.0 for variation of oscil- lator frequency due to Von for given Rext/Cext values as wellas frequency variation due to operating temperature for given R, C and Vop values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 2.2.1 for timing). Higher capacitance increases the stability of oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resona- tor manufacturer for appropriate vaiues of external com- ponents. FIGURE 12.2.1 - CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP TYPES ONLY) osci "~~ ~"> PICIGCSX a \ ! rua 1 t l y-t- C2 XTAL 1 1 \ ,4 SLEEP 1 U osc2| -r- 1 + - @----& Be TO INTERNAL LOGIC Rs may be required in HS and XT modes for AT strip-cut crystals to avoid overdriving. See Tables 12.2.1 and 12.2.2 FIGURE 12.2.2 - EXTERNAL CLOCK INPUT OPERATION (HS, XT, or LP TYPES ONLY) CLOCK FROM > osc EXT. SYSTEM PIC16CSX OPEN ~<@l| osc2 TABLE 12.2.2 - CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Osc Freq C1 C2 Type LP 32 KHz 15 pF 15 pF XT 100 KHz 15 - 30 pF 200 - 300 pF 200 KHz 15 - 30 pF 100 - 200 pF 455 KHz 15 - 30 pF 15 - 100 pF 1 MHz 15 - 30 pF 15 - 30 pF 2 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF HS 4 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF 20 MHz 15 pF 15 pF Higher capacitance increases the stability of oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. FIGURE 12.3.1 - RC OSCILLATOR for recommended values of C1, C2 per oscillator type and (RC TYPE ONLY) frequency. Voo TABLE 12.2.1 - CAPACITOR SELECTION nen FOR CERAMIC osc Intemal RESONATORS XY clock Cext == N Oscillator Resonator Capacitor Range - PICTECSXRC Type Frequency c1=C2 Vss = ~=t_7 OSC2/CLKOUT xT 455 KHz 150 - 330 pF Fosc/4 2.0 MHz 20 - 330 pF 4.0 MHz 20 - 330 pF HS 8.0 MHz 20 - 200 pF DS30015K-page 24 1994 Microchip Technology Inc. 2-26PIC16C5X Series FIGURE 13.1.1 - EXTERNAL POWER ON RESET CIRCUIT Vico D R Ri} MCLR Cc rr PIC16C5X Notes: ~ 1. External power on reset circuit is required only if Voo power-up slope is too slow or if a low frequency crystal oscillator is being used that need a long Start-up time. The diode D helps discharge the capacitor quickly when VDD powers down. 2 R < 40 KQ must be observed to make sure that voltage drop across R does not exceed 0.2 V (max leakage current spec on MCLR pin is 5 pA). A larger voltage drop will degrade VH level on MCLR pin. 3. Ri= 1000 to 1KQ will limit any current flowing into MCLR_ from external capacitor C in the event of MCLR pin breakdown due to ESD or EOS. FIGURE 13.1.2 - BROWN OUT PROTECTION CIRCUIT Von Voo aE MCLR = PIC16C5X Notes: 1. This circuit will activate reset when VOD goes below (VZ + 0.7 V) where VZ = Zener voltage. FIGURE 13.1.3 - BROWN OUT PROTECTION CIRCUIT Vo Voo RI J Qi MCLR Fe P3 = PIC16C5X Notes: 1. This brown circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VOD is below a certain level such that: Ri _ =07V. VODs R1+R2 13.0 OSCILLATOR START-UP TIMER (OST) Oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. An on-chip oscillator start-up timer is provided which keeps the device in a RESET condition for approximately 18ms after the voltage on the MCLR pin has reached a logic high (VIHMC) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allowing for savings in cost- sensitive and/or space restricted applications. The OST will also be triggered upon a Watchdog Timer timeout. This is particularly important for applications using the WDT to awake the PIC16C5X from SLEEP mode automatically. The OST is not adequate for low frequency crystals which require much longer than 18ms to start-up and stabilize. 13.1 Power-On Reset (POR) The PIC16C5X incorporates an on chip Power-On Re- set (POR) circuitry which provides internal chip reset for most power-up situations. To use this feature the user merely needs to tie MCLR pin to Vo. A simplified block diagram of the on-chip power on reset circuit is shown in Figure 13.1.4. The Power-On Reset circuit and the oscillator start-up timer circuit are closely related. On power-up the reset latch is set and the start-up timer (see Figure 13.1.4) is reset. The start-up timer begins count- ing once it detects MCLR to be high. After the time-out period, which is typically 18ms, it will reset the reset- latch and thus end the on-chip reset signal. Figures 13.1.5 and 13.1.6 are two power-up situations with relatively fast rise time on Voo. In Figure 13.1.5, Vop is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset tOST ms after MCLR goes high. In Figure 13.1.6, the on chip Power-On Reset feature is being utilized (MCLR and Vpo are tied together). The Voo is stable before the start-up timertimes out and there is no problem in getting a proper reset. Figure 13.1.7 depicts a potentially problematic situation where VDD rises too slowly. In this situation, when the start-up timer times out, Vpp has not reached the Vop (min) value and the chip is, therefore, not guaranteed to function correctly. To summarize, the on-chip Power-On Reset is guaran- teed to work if the rate of rise of Vop is no slower than 0.05 V/ms. Itis also necessary that the Vop starts from OV. The on-chip Power-On Reset is also not adequate for low frequency crystals which require much longer than 18ms to start-up and stabilize. For such situations, we recommend that external RC circuits are used for longer Power-On Reset. 1994 Microchip Technology Inc. 2-27 DS30015K-page 25PIC16C5X Series FIGURE 13.1.4 - SIMPLIFIED POWER ON RESET BLOCK DIAGRAM > (J POWER-UP POR (POWER-ON RESET) OETECT VDD XI {> | >e WOT TIMEOUT 1__ MCLR PIN RESET sa ON-CHIP | TH 8-BIT ASYNCH RC OSC RIPPLE COUNTER (START-UP TIMER) R Qe_> CHIP RESET FIGURE 13.1.5 ~ USING EXTERNAL RESET INPUT Voo MCLR INTERNAL POR OST TIME-OUT INTERNAL RESET Note 1: The tost time-out is invoked every time the chip comes out of reset. FIGURE 13.1.6 - USING ON-CHIP POR (FAST Vop RISE TIME) Vpp a 4 MCLR INTERNAL POR tosT OST TIME-OUT INTERNAL RESET DS30015K-page 26 @ 1994 Microchip Technology Inc. 2-28PIC16C5X Series FIGURE 13.1.7 - USING ON-CHIP POR (SLOW Vop RISE TIME) (INTERNAL POR | __ voo OV MCLA ll eee 5V v1 OST TIME-OUT + tost > INTERNAL RESET When Von tises slowly, the internal time-out period expires long before Vpb has reached its final value. In this example, the chip will reset properly if, and only if, V12 VDDMIN. 14.0 POWER DOWN MODE (SLEEP) The power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps ftunning, the bitPD in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP command was executed (driving high, low, or hi-imped- ance). For lowest current consumption in this mode, all |/O pins should be either at Vop, or Vss, with no external circuitry drawing current from the I/O pin. I/O pins that are in the High-Z mode should be pulled high or low externally to avoid switching currents caused by floating inputs. The RTCC input should also be at Vop or Vss_ for lowest current consumption. The MCTR pin must be at VIHMC. 14.1 Wake-Up The device can be awakened by a Watchdog Timer timeout (if it is enabled) or an externally applied low*" pulse at the MCLR pin. In both cases the PIC16C5X will stay in RESET mode for one oscillator start-up timer period (triggered from rising edge on MCLR or WDT timeout) before normal program execution resumes. The PD bit in the STATUS register, which is set to one during power-on , but cleared by the "SLEEP" com- mand, can be used to determine if the processor was powered up or awakened from the power-down mode (Table 4.5.1.2). The TO bit in the STATUS register can be used to determine if the wake up" was caused by an extemal MCTR signal or a Watchdog Timer timeout. NOTE: Some applications may require external R/C networks on the MCLR pin in order to allow for oscillator startup times longer than one OST period. In this case, a WOT wake up from power-down mode is not recom- mended, because a RESET generated by a WDT time out does not discharge the external capacitor, and the PIC16C5X will be in RESET only for the Oscillator Start- up Timer period. 15.0 CONFIGURATION FUSES The configuration EPROM consists of four EPROM fuses which are not part of the normal EPROM for program storage. Two are for the selection of the oscillator type, one is the Watchdog Timer enable fuse, and one is the code protection fuse. OTP or QTP devices have the oscillator configuration programmed by the factory and the parts are tested accordingly. The packages are marked with the suffixes "XT", "RC", "HS" or LP following the part number to identify the oscillator type and operating range. 15.1 Customer ID Code The PIC16C5X series has 16 special EPROM bits which are not part of the normal program memory. These bits are available to the user to store an Identifier (ID) code, checksum, or other informative data. They cannot be accessed during normal program execution. 1994 Microchip Technology Inc. DS30015K-page 27PIC16C5X Series 15.2 Code Protection The program code written into the EPROM can be protected by programming the code protection fuse with "0". When code protected, the contents of the program EPROM cannot be read out in a way that the program code can be reconstructed. In addition, all memory locations starting at 040h and above are protected against programming. It is still possible to program locations 000h - 03Fh, the 1D locations and the contiguration fuses. Note that the configuration fuses and the ID bits can still be read, even if the code protection logic is active. 15.2.1 Verifyi P When code protected verifying any program memory location will read a scrambled output which looks like "O0000000XXXX" (binary) where X is 1 or 0. To verifya device after code protection, follow this procedure: a. First, program and verify a good device without code protecting it. b. Next, blow its code protection fuse and then load its contents in a file. c. Verify any code-protected Part against this file. 0S30015K-page 28 2-30 1994 Microchip Technology Inc.PIC16C5X Series 16.0 ELECTRICAL CHARACTERISTICS 16.1 Absolute Maximum Ratings* Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress Ambient temperature under bias........ 55C to +125C rating only and functionat operation of the device at those or any Storage Temperature 0.0.0.1... - 65C to +150C other conditions above those indicated in the operation listings Voltage on any pin with respect to Vss of this specification is not implied. Exposure to maximum rating (except Vop and MCLR) .............. -0.6V to VDD +0.6 V conditions for extended periods may affect device reliability. Voltage on Voo with respect to VSS .............. Ot0+7.5V Voltage on MCLR with respect to Vss Notes: 1. Total power dissipation should not exceed 800 (Note 2)... eecsceces sneer tscsseeeseceseesenteesesetees 0to+14V mW for the package. Power dissipation is Total power Dissipation (Note 1). .. 800 mW calculated as follows: Max. Current out of Vss pin ... .. 150 MA Pdis = Von x {lop - loh} + 3 {(VoD-Voh) x loh} Max. Current into VDD pin... eee nseceeeseeeces 50 mA + X(Voi x lol) Max. Current into an input pin ............. cc +500 pA 2. Voltage spikes below Vss at the MCLR pin, Input clamp current, lik (Vi<O or Vi>VDD) ........ +20 mA inducing currents greater than BOmA, may Output clamp current, lok (VO<0 or VO>VppD) . +20 mA cause latch-up. Thus, a series resistor of 50- Max. Output Current sinked by any V/O pin....... 25 mA 1002 should be used when applying a low Max. Output Current sourced by any I/O pin ....20 mA level to the MCLR pin rather than pulling this Max. Output Current sourced by a single pin directly to Vss. VO port (Port A, B, OF C) oo... ccecsscceessesseeeneeeres 40 mA Max. Output Current sinked by a single VO port (Port A, B, OF C)......eccsccessecsssccsessensessees 50mA TABLE 16.2 - PIN DESCRIPTIONS Name Function Description RAO - RA3 VO PORTA Four input/output lines. RBO - RB7 VO PORTB Eight input/output lines. RCO - RC7 VO PORTC Eight input/output lines, (P1C16C55/C57 only). RTCC Real Time Clock/Counter Schmitt Trigger Input. Clock input to RTCC register. Must be tied to Vss or Voo if not in use to avoid unintended entering of test modes and to reduce current consumption. MCLR Master Clear Schmitt Trigger Input. A Low voltage on this input generates a RESET condition for the PIC16C5X microcontroller. A rising voltage triggers the on-chip oscillator start-up timer which keeps the chip in RESET mode for about 18ms. This input must be tied directly, or via a pull-up resistor, to VoD. OSC1 Oscillator (input) *XT", "HS" and "LP" devices: Input terminal for crystal, ceramic resonator, or external clock generator. "RC" devices : Driver terminal for external RC combination to establish oscillation. OSC2/CLKOUT Oscillator (output) For XT, "HS" and "LP" devices: Output terminal for crystal and ceramic resonator. Do not connect any other load to this output. Leave open if external clock generator is used. For "RC* devices : A "CLKOUT" signal with a frequency of 1/4 Fosc1 is put out on this pin. Vop Power supply Vss Ground N/C No (internal) Connection a Nee 1994 Microchip Technology Inc. DS30015K-page 29 2-31PIC16C5X Series 16.3 RA ISTICS: Pl - DC CHARACTERISTICS, Standard Operating Conditions POWER SUPPLY PINS Operating temperature 0<TA<-+70C, unless otherwise stated Operating voltage Vopd = 3.0V to 5.5V unless otherwise stated Typ Characteristic Sym | Min | (Note 1)} Max |Units Conditions Supply Vottage PIC16C5X-XT Vop 3.0 6.25 |V Fose = DC to 4 MHz PIC 16C5X-RC 3.0 6.25 |V Fosc = DC to 4 MHz PIC16C5X-HS 45 55 |V Fose = DC to 20 MHz PIC16C5X-LP 2.5 6.25 | V Fosc = DC to 40 KHz RAM Data Retention Vor 1.5 Vv Device in SLEEP mode Voltage (Note 3) Vop start voltage to VPOR Vss Vv See Section 13.1 for details on power on guarantee power on reset reset Vop rise rate to guarantee Svpo 0.057 Vims | See Section 13.1 for details on power on power on reset Supply Current (Note 2) PIC16C5X-XT loo 1.8 3.3. |mA_ | Fose = 4 MHz, Vop = 5.5V PIC16C5X-RC (Note 5) 1.8 3.3. |mA | Fosc = 4 MHz, Voo= 5.5V PIC16C5X-HS 48 10 mA Fose =10 MHz, Voo = 5.5V 9.0 20 mA _ | Fosc = 20 MHz, Vpp= 5.5V PIC16C5X-LP 15 32 pA Fose = 32 KHz, Vop=3.0V, WDT disabled Power Down Current (Note 4) PIC16C5X lpp 4 12 HA Vop = 3.0V, WDT enabled 0.6 9 pA Vod = 3.0V, WDT disabled * These parameters are based on characterization and are not tested. Note 1: Note 2: Note 3: Note 4: Note 5: Data in the column labeled "Typical" is based on characterization results at 25C. This data is for design guidance only and is not tested for, or guaranteed by Microchip Technology. The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all lop measurements in active operation mode are: OSC1=external square wave, from rail to rail; all |/O pins tristated, pulled to Vop, RT = Vop, MCLR = Voo; WDT enabled/disabled as specified. b) For stand-by current measurements, the conditions are the same, except that the device is in SLEEP mode. This is the limit to which Vpb can be lowered in SLEEP mode without losing RAM data. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to VoD and Vss. Does not include current through Rext. The current through the resistor can be estimated by the formula Ir = VoD/2Rext (mA) with Rext in kKOhm. DS30015K-page 30 1994 Microchip Technology Inc. 2-32PIC16C5X Series 16.4 HARACTERISTICS: PIC1 I-RC, XT. HS, LP (in DC CHARACTERISTICS, Standard Operating Conditions POWER SUPPLY PINS Operating temperature -40 < Ta < +85C, unless otherwise stated Operating voltage Vob = 3.5V to 5.5V unless otherwise stated Typ Characteristic Sym | Min (Note 1) Max | Units Conditions Supply Voltage PIC16C5X-XT Vpb 3.0 6.25 Vv Fosc = DC to 4 MHz PIC16C5X-RC 3.0 6.25 | V Fose = DC to 4 MHz PIC16C5X-HS 45 5.5 Vv Fose = DC to 20 MHz PIC16C5X-LP 25 6.25 Vv Fose = DC to 40 KHz RAM Data Retention VDR 1.5 Vv Device in SLEEP mode Voltage (Note 3) Vop start voltage to VPOR Vss Vv See section 13.1 for details on power on guarantee power on reset reset Voo rise rate to guarantee |Svop | 0.05" Vims | See section 13.1 for details on power on power on reset reset Supply Current (Note 2) PIC16C5X-XT IpD 18 |33 mA Fose = 4 MHz, VoD = 5.5V PIC16C5X-RC (Note 5) 18 [3.3 mA_ | Fose = 4 MHz, Vob = 5.5V PIC16C5X-HS 48 10.0 mA Fose = 10 MHz, Vpp = 5.5V 9.0 20.0 mA Fose = 20 MHz, Voo = 5.5V PIC16C5X-LP 19 40 pA Fose = 32 KHz, VoD = 3.0V, WDT disabled Power Down Current (Note 4) PIC16C5X IPD 5 14 pA Vpp = 3.0V, WDT enabled 0.8 12 pA Vop = 3.0V, WOT disabled * These parameters are based on characterization and are not tested. Note 1: Note 2: Note 3: Note 4: Note 5: Data in the column labeled Typical" is based on characterization results at 25C. This data is for design guidance only and is not tested for, or guaranteed by Microchip Technology. The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all lob measurements in active operation mode are: OSC1= extemal square wave, from rail to rail; all /O pins tristated, pulled to Vop, RT = VoD, MCLR = Vop; WOT enabled/disabled as specified. b) For stand-by current measurements, the conditions are the same, except that the device is in SLEEP mode. This is the limit to which Voo can be lowered in SLEEP mode without losing RAM data. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to Vpp and Vss. Does not include current through Rext. The current through the resistor can be estimated by the formula Ir = Vob/2Rext (mA) with Rext in kOhm. 1994 Microchip Technology Inc. DS30015K-page 31 2-33PIC16C5X Series 16.5 DC CHARACTERISTICS: PICIGCSXE-RC, XT. HS, LP (Automotive) DC CHARACTERISTICS, Standard Operating Conditions POWER SUPPLY PINS Operating temperature -40 < Ta < +125C, unless otherwise stated Operating voltage Vpp = 3.5V to 5.5V unless otherwise stated Typ Characteristic Sym | Min (Note 1) Max | Units Conditions Supply Voltage PIG16C5X-XT Vop 3.25 6.0 Vv Fosc = DC to 4 MHz PIC16C5X-RCG 3.25 6.0 Vv Fose = DC to 4 MHz PIC16C5X-HS 45 5.5 Vv Fose = DC to 20 MHz PIC16C5X-LP 2.5 6.0 Vv Fosc = DC to 40 KHz RAM Data Retention VbR 1.6 v Device in SLEEP mode Voltage (Note 3) Voo start voltage to VPoR Vss v See section 13.1 for details on power on guarantee power on reset reset Voo rise rate to guarantee |Svop | 0.05" Vims | See section 13.1 for details on power on power on reset reset Supply Current (Note 2) PIC16C5X-XT lop 18 1/33 mA Fosc = 4 MHz, Voo = 5.5V PIC16C5X-RC (Note 5) 18 |33 mA Fosc = 4 MHz, Vob = 5.5V PIC16C5X-HS 48 |10.0 | mA Fose = 10 MHz, Vop = 5.5V 9.0 20.0 mA Fose = 16 MHz, Vop = 5.5V PIC16C5X-LP 25 55 pA Fose = 32 KHz, Vpb = 3.25V, WDT disabled Power Down Current (Note 4) PIC16C5X lPo 5 22 pA Vpb = 3.25V, WDT enabled 08 |18 BA Voo = 3.25V, WDT disabled * These parameters are based on characterization and are not tested. Note 1: Note 2: Note 3: Note 4: Note 5: Data in the column labeled "Typical" is based on characterization results at 25C. This data is for design guidance only and is not tested for, or guaranteed by Microchip Technology. The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattem, and temperature also have an impact on the current consumption. a) The test conditions for all lop measurements in active operation mode are: OSC1= external square wave, from rail to rail; all /O pins tristated, pulled to Voo, RT = Vop, MCLR = Vop; WDT enabled/disabled as specified. b) For stand-by current measurements, the conditions are the same, except that the device is in SLEEP mode. This is the limit to which Vop can be lowered in SLEEP mode without losing RAM data. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to Vop and Vss. Does not include current through Rext. The current through the resistor can be estimated by the formula Ir = Vob/2Rext (mA) with Rext in kOhm. DS30015K-page 32 1994 Microchip Technology Inc. 2-34a _PIC1 6C5X Series 16.6 DC CHARACTERISTICS: PIC16C5X-RC, XT. HS, LP (Commercial) PIC1 Fi rial DC CHARACTERISTICS, Standard Operating Conditions (unless otherwise stated) ALL PINS EXCEPT POWER SUPPLY Operating temperature -40 < Ta < +85C for industrial and 0C < Ta < +70C for commercial Operating voltage Vpp range as described in DC spec tables 16.3 and 16.4 Characteristic Sym Min Typ Max Units Conditions (Note 1) Input Low Voltage /O ports VIL Vss 0.2 Vpp v Pin at hi-impedance MCLR (Schmitt trigger) Vss 0.15 Vop Vv RTCC (Schmitt trigger) Vss 0.15 Voo Vv OSC1 (Schmitt trigger) Vss 0.15 Voo v PIC16C5XRC only (Note 5) OSCc1 Vss 0.3 Vob v PIC16C5X-XT, HS, LP Input High Voltage VO ports VIH 0.45 Vop Vop Vv For all Vpb (Note 6) 2.0 Voo Vv 4.0V < Vo0 < 5.5 V (Note 6) 0.36 Vop Vop v Von > 5.5 V MCLR (Schmitt trigger) 0.85 Vop Vop Vv RTCC (Schmitt trigger) 0.85 Vop Vop v OSC1 (Schmitt trigger) 0.85 Vop Vob Vv PIC16C5X-RC only (Note 5) OSC1 0.7 Vob Vop Vv PIC16C5X-XT, HS, LP Input Leakage Current For Vop < 5.5V (Notes 3, 4) V/O ports lit -1 0.5 +1 pA | Vss < VPIN < VoD, Pin at hi-impedance MCLR 5 HA | VPIN = Vss + 0.25V MCLR 0.5 +5 HA | VPIN = VDD RTCC 3 0.5 +3 A | Vss < VPIN < VoD Osc 3 0.5 +3 HA | Vss< VPIN< VoD, PIC16C5X-XT, HS, LP Output Low Voitage VO Ports VoL 0.6 v lo. = 8.7 mA, VoD = 4.5V OSC2/CLKOUT 0.6 Vv lot = 1.6 mA, Vop = 4.5V (PIC16C5X-RC) Output High Voltage /O Ports (Note 4) VOH Vob-0.7 Vv lOH = -5.4 mA, Vob = 4.5V OSC2/CLKOUT Vop-0.7 v IOH = -1.0 MA, VoD = 4.5V (PiIC16C5X-RC) Note 1: Data in the column labeled "Typical" is based on characterization results at 25 * C. This datais for design guidance only and is not tested for, or guaranteed by Microchip Technology. Note 2 : Total power dissipation as stated under absolute maximum ratings must not be exceeded. Note 3 : The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Note 4 : Negative current is defined as coming out of the pin. Note 5 : For PIC1GCSXRC devices, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. Note 6: The user may use better of the two specifications. 1994 Microchip Technolagy Inc. 0S30015K-page 33 2-35PIC16C5X Series 16.7 OC CHARACTERISTICS; PIC16C5X-RC, XT, HS, LP (Automotive) DC CHARACTERISTICS, Standard Operating Conditions (unless otherwise stated) ALL PINS EXCEPT POWER SUPPLY Operating temperature -40 < TA < +125C Operating voltage Vop range as described in DC spec tables 16.3 and 16.4 Characteristic Sym Min Typ Max Units Conditions (Note 1) Input Low Voltage 1/0 ports VIL Vss 0.15 Vpb Vv Pin at high-impedance MCLR (Schmitt trigger) Vss 0.15 Vop Vv RTCC (Schmitt trigger) Vss 0.15 Vop v OSC1 (Schmitt trigger) Vss 0.15 Vop Vv PIC 16C5XRC only (Note 5) osc Vss 0.3 Vop Vv PIC16C5X-XT, HS, LP Input High Voltage VO ports ViH 0.45 Yoo Vob Vv For al! Vop (Note 6) 2.0 Vob Vv 4.0 V < Von < 5.5 V (Note 6) 0.36 VDD Voo Vv Von > 5.5 V MCLR (Schmitt trigger) 0.85 VoD Voo v RTCC (Schmitt trigger) 0.85 Vop Vop v OSC1 (Schmitt trigger) 0.85 Vop Vpb Vv PIC 16C5X-RC only (Note 5) OSsC1 0.7 VpD Vpb v PIC 16C5X-XT, HS, LP Input Leakage Current For Vpp <5.5V (Notes 3, 4) V/O ports lit -1 0.5 +1 HA | Vss < VPIN < VOD, Pin at hi-impedance MCLR 5 uA | VeIN = Vss + 0.25V MCLR 0.5 +5 HA | VPIN = VDD RTCC -3 0.5 +3 HA | Vss < VPIN s VoD osc 3 0.5 +3 HA | Vss< VPIN< VoD, PIC16C5X-XT, HS, LP Output Low Voltage VO Ports Vor 0.6 Vv lo. = 8.7 mA, VDD = 4.5V OSC2/CLKOUT 0.6 Vv lo. = 1.6 mA, Voo = 4.5V (PIC16C5X-RC) Output High Voltage VO Ports (Note 4) VOR VopD-0.7 v loH = -5.4 mA, VDD = 4.5V OSC2/CLKOUT Vop-0.7 v lon = -1.0 mA, VoD = 4.5V (PIC16C5X-RC) Note 1: Datain the column labeled "Typical" is based on characterization results at 25 C. This datais for design guidance only and is not tested for, or guaranteed by Microchip Technology. Note 2 : Total power dissipation as stated under absolute maximum ratings must not be exceeded. Note 3 : The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Note 4 : Negative current is defined as coming out of the pin. Note 5 : For PIC16CSXRC devices, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. Note 6: The user may use better of the two specifications. DS30015K-page 34 1994 Microchip Technology Inc. 2-36PIC16C5X Series 16.8 AC CHARACTERISTICS: PIC16CS5X-RC, XT, HS, LP (Commercial) Pl 1. H In rial I Xi- T, HS, LP (Automotiv Standard Operating Conditions (unless otherwise stated AC CHARACTERISTICS Operating temperatcre TA= vias +85'C (industrial), Ta = -40C to +125C (automotive) and 0C < Ta < +70C (commercial) Operating voltage Vop range as described in DC spec tables 16.3 and 16.4 Characteristic Sym Min Typ Max | Units Conditions (Note 1) External CLOCKIN Fosc DC 4 MHz | RC mode Frequency (Note 2) bc 4 MHz | XT mode DC 20 MHz | HS mode (Com/Ind) DC 16 MHz | HS mode (Automotive) DC 40 KHz LP mode Oscillator Frequency Fosc DC 4 MHz | RC mode (Note 2) 0.1 4 MHz | XT mode 4 20 MHz | HS mode (Com/Ind) 4 16 MHz | HS mode (Automotive) OC 40 KHz LP mode Instruction Cycle Time Tcy 1.0 4/Fasc DC ps RC mode (Note 2) 1.0 DC ys XT mode 0.2 oc ps HS mode 100 DC ps LP mode External Clock in Timing (Note 4) Clock in (OSC1) High or Low Time XT oscillator type TCKHLXT | 50* ns LP oscillator type TCKHLLP | 2 ys HS oscillator type TCKHLHS | 20* ns Clock in (OSC1) Rise or Fall Time XT oscillator type TCKREXT | 25* ns LP oscillator type TCKRFLP | 50* ns HS oscillator type TCKRFHS | 25* ns RESET Timing MCLR Pulse Width (low) TMCL 100 ns RTCC Input Timing, No Prescaler RTCC High Putse Width TRTH 0.5 Tcy+ 20* ns Note 3 RTCC Low Pulse Width TRTL 0.5 Tcv+ 20* ns Note 3 RTCC Input Timing, With Prescaler RTCC High Pulse Width TRTH 10 ns Note 3 RTCC Low Pulse Width TRTL 10* ns Note 3 RTCC Period TRIP Tov +40 * ns Note 3. Where N = prescale N value (2,4, ..., 256) Watchdog Timer Timeout Period (No Prescaler) TwoT 9* 18* 30* | ms Voo = 5.0V Oscillation Start-up Timer Period Tost 9* 18* 30* | ms Vop = 5.0V 1/0 Timing \/0 Pin Input Valid Before CLKOUTT (RC Mode) Tos 0.25 Tcv+ 30* ns \/0 Pin Input Hold After CLKQUTT (RC Mode) TDH Q* ns 1/0 Pin Output Valid After CLKOUT (RC Mode) TPp 40" | ns * Guaranteed by characterization, but not tested. (Notes on next page) 1994 Microchip Technology Inc. 2-37 DS30015K-page 35PIC16C5X Series NOTES TO TABLE 16.8: 1. Data in the column labeled Typical is based on characterization results at 25C. This data is for design guidance only and is not tested for, or guaranteed by Microchip Technology. 2. Instruction cycle period (Tcy) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may 16.9 Et i ir in FIGURE 16.9.1 - ELECTRICAL STRUCTURE OF I/O PINS (RA, RB, RC) result in an unstable oscillator operation and/or higher than ex- pected current consumption. All devices are tested to operate at min. values with an external clock applied to the OSC1 pin. When an external clock input is used, the Max. cycie time limit is "DC" (no clock) for all devices. 3. For a detailed explanation of RTCC input clock requirements see section 4.2.1. 4. Clock-in high-timeis the duration for which clockinputis at VIHOSC or higher. Clock-in fow-time is the duration for which clock input is at VILOSC or lower. 17.0 TIMING DIAGRAMS FIGURE 17.0.1 - RTCC TIMING Voo P]}- BT, vss vss = ea : Tare 4 FIGURE 16.9.2 - ELECTRICAL STRUCTURE OF MCLR AND RTCC PINS wan ei MCLR Toy tt Tey ! Rin 1 ' j : Tost oT 'o1 f ! : MLR, Schmitt trigger I rd input buffer cuour,) ___--------- - , 1 ' Devic! .i FETCH 1.INSTRUCTION 1} FETCH 2.INSTRUCTION ; Vv Vv FUNCTION RESET | EXECUTE "FORCED" NOP | EXECUTE 1. INSTRUCTION f ss Ss ' ' Notes to Figures 16.9.1 an 16.9.2: The diodes and the grounded gate (or output driver) NMOS device are carefully designed to protect against ESD (Electrostatic discharge) and EOS (Electrical overstress}. Rin is a small resistance to further protect the input buffer from ESD. FIGURE 17.0.3 - INPUT/OUTPUT TIMING FOR I/O PORTS (PIC16C5XRC*) ! ro | 11 : I oscar ' ' ' CLKOUT fo 0ti<tsti 1 Tdh , ! ' Tds ' weut LLL ___ VARI WZ LLL her Magne "Td | Ted | OUTPUT Tene 4 x * The CLKOUT output is availabla only on PIC16C5XAC devices. 0S30015K-page 36 1994 Microchip Technology Inc. 2-38PIC16C5X Series 18.0 DC AND AC CHARACTERISTICS GRAPHS/TABLES: The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified Vpp range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical sum- mary of data collected on units from different lots over a period of time. Typical represents the mean of the distribution while max or 'min' represents (mean + 3c) and (mean - 3c) respectively where o is standard deviation. FIGURE 18.0.2 - TYPICAL RC OSCILLATOR FREQUENCY vs Vop* 5.5 5.0 45 4.0 3.6 3.0 Fosc (Mhz) 25 20 1.0 Cext = 20pF, T = 25C 05 0 3.0 35 4.0 45 5.0 5.5 60 VoD (Volts) * Measured on DIP packages. FIGURE 18.0.1 - TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FREQUENCY NORMALIZED TO +25C Roext 2 10K Cext = 100pF FIGURE 18.0.3 - TYPICAL RC OSCILLATOR FREQUENCY vs Voo* Freq. (Mhz) 0.8 0.6 04 0.2 0 3.0 35 45 5.0 5.5 6.0 4.0 Vo (Votts) * Measured on DIP packages. 1994 Microchip Technology Inc. 2-39 DS30015K-page 37PIC16C5X Series FIGURE 18.0.4- TYPICAL RC OSCILLATOR FREQUENCY vs Vpp" 800 a 700 [-~ R=3.3k pe 600 | | [-~_] 500 R=Sk < % 400 Ww p+ 300 200 100 R=100k 0 | 30 35 40 45 50 55 6.0 VoD (Volts) * Measured on DIP packages. FIGURE 18.0.5 - TYPICAL Ipd vs Vop WATCHDOG DISABLED 25C TABLE 18.0.1 - RC OSCILLATOR FREQUENCIES* Cext Rext Average Fosc @ SV, 25C 20pF 3.3k 4.973 MHz + 27% 5k 3.82 MHz +21% 10k 2.22 MHz +21% 100k 262.15 KHz 31% 100pF 3.3k 1.63 MHz 13% 5k 1.19 MHz +13% 10k 648.64 KHz + 18% 100k 71.56 KHz +25% 300pF 3.3k 660.0 KHz +10% 5k 484.1 KHz + 14% 10k 267.63 KHz +15% 100k 29.44 KHz +19% * Measured on DIP packages. The percentage variation indicated here is part to part variation due to normal process distribution. The varia- tion indicated is +3 standard deviation from average value for Vop = 5V. FIGURE 18.0.6 - TYPICAL Ipd vs Vop WATCHDOG ENABLED 25C 25 / 4 15 Zw L =< = =) QR = 2 3g 3 2 1 6 7 L 4 LZ 0s 2 0 0 25 30 35 40 45 50 55 60 25 30 35 40 45 50 55 60 VoD (Volts) VoD (Volts) DS30015K-page 38 1994 Microchip Technology Inc. 2-40PIC16C5X Series FIGURE 18.0.7 - MAXIMUM Ipd vs Vop FIGURE 18.0.8 - MAXIMUM ipd vs Vob WATCHDOG DISABLED WATCHDOG ENABLED* 100 60 TI Temp. ("C) 50 fy 85 | Temp. (C) = 125 jz! 19 | 85 40 fi 70 VY / / => / S$ 8 z i\ AL 2 -40 3 i? ONL 4 |H|-40 fF NA 7 a 1 a0 | 128 || L a ie Bz ALTO 85 L- 4758 - SHA th 10 fd | rote bo 0 0 25 30 35 40 45 50 55 60 65 7.0 25 30 35 40 45 50 55 60 65 7.0 Vcpb (Volts) VoD (Volts) IPD, with watchdog timer enabled, has two components: The leakage current which increases with higher temperature and the operating current of the watchdog timer logic which increases with lower temperature. At -40C, the latter dominates explaining the apparently anomalous behavior. FIGURE 18.0.9 - VTH (INPUT THRESHOLD VOLTAGE) OF VO PINS vs Vpp VTH (Input threshold voltage) of I/O pins 2.00 | wee L 1.80 per 1.60 =~ | . Pe [| 2 1.40 28 oT > . zr Ln -c10 ol| E 1.20 sain (Ao - |_| |_| 1.00 = 0.80 / 0.60 25 3.0 3.5 40 45 5.0 5.5 6.0 Vbb (volts) 1994 Microchip Technology Inc. DS30015K-page 39 2-41PIC16C5X Series FIGURE 18.0.10 - Vin, Vi. OF MCLR, RTCC AND OSC1 (IN RC MODE) vs Vop VIH, ViL (volts) Vir, TYP, 25C Vit, min to 25 3.0 3.5 40 45 5.0 5.5 6.0 Vo (volts) Note: These input pins have Schmitt trigger input buffer. FIGURE 18.0.11 - VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs Vop 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 VTH (volts) 2.5 3.0 3.5 40 45 5.0 5.5 6.0 Vob (volts) 0S30015K-page 40 1994 Microchip Technology tnc. 2-42PIC16C5X Series FIGURE 18.0.12 - TYPICAL lop vs FREQ (EXT CLOCK, 25C) 10 0.01 10K 100K 1M 10M 100M External Clock freq (Hz) FIGURE 18.0.13 - MAXIMUM lob vs FREQ (EXT CLOCK, -40 to +85C) 10 1.0 8 0.1 0.01 10K 100K 1M 10M 100M External Clock freq (Hz) a 1994 Microchip Technology Inc. DS30015K-page 41 2-43PIC16C5X Series FIGURE 18.0.14 - MAXIMUM Ipp vs FREQ (EXT CLOCK, -55 to +125C) 10 IDD (ma) 1 o 0.01 10K 100K 1M External Clock freq (Hz) 10M FIGURE 18.0.15 - WDT Timer Time-out Period FIGURE 18.0.16 - Transconductance (gm) of HS Oscillator vs Vopb vs VoD 50.0 45.0 \ 40.0 \ 35.0 A RB 30.0 M. c Qa Ke Oo 250 Ma, = IP] . ON 20.0 Typ, 250 15.0 M - in, O ~ ee 10.0 SS Min, -40C 5.0 | 2 3 4 5 6 VoD (Volts) gm (UAV) 8000 7000 6000 5000 4000 3000 2000 1000 / Kee mA 3 4 5 6 7 Vc (Volts) DS30015K-page 42 2-44 1994 Microchip Technology Inc.PIC16C5X Series FIGURE 18.0.17 - Transconductance (gm) of FIGURE 18.0.18 - Transconductance (gm) of LP Oscillator vs Vop XT Oscillator vs Vop 45.0 / 2500 40.0 A / a) G 360 2000 S Ve" w 30.0 eo /| | L / | UA , / AS 1000 -} a 15.0 7 Yo << r gm (nA) R a gm (HAV) : c L. K win, 88 10.0 7 500 50 a ZO 1) 0 oars 3 4 5 6 7 2 a 4 5 6 7 Veo (Volts) Voo (Volts) FIGURE 18.0.19 - oH vs VoH, VoD = 3V FIGURE 18.0.20 - loH vs VoH, VDD = 5V 0 0 [ee] 4) Min @ 85C 6 L / | | / / -10 [Min @ 485C SD /| GQ _ / & < => E | < x $/| - E 5 Iayp 028 G 5 -20 7 s f VY fo -30 -20 LS t oO wax * F e gs = 25 -40 0 0.5 1 15 2 2.5 3 15 2 25 3 3.5 4 45 Vor (Volts) Vor (Volts) 1994 Microchip Technology Inc. DS30015K-page 43 2-45PIC16C5X Series FIGURE 18.0.21 - loL vs VOL, VoD = 3V FIGURE 18.0.22 - lo. vs VOL, VoD = 5V ee " @ 40C 40 7 ae 80 7 Max @ -40C Lo os'C => 25 =z / wp 8? Z rt 7 2 [Typ @ 25 3 J . / VA | atin @ +85C . LK / 04 / / MN 5 10 7 0 0 0 05 1 15 2 25 3 0 05 1 15 2 25 3 VoL (Volts) VoL (Volts) TABLE 18.0.2 - INPUT CAPACITANCE FOR TABLE 18.0.3 - INPUT CAPACITANCE FOR PIC16C54/56 * PIC16C55/57 * Typical Capacitance (pF) Typical Capacitance (pF) Pin Name Pin Name 18L PDIP 18L SOIC 28L PDIP 28L SOIC (600 mil) RA port 5.0 4.3 RB port 5.0 43 RA port 5.2 4.8 MCLR 17.0 17.0 RB port 5.6 47 OSC 4.0 3.5 RC port 5.0 44 OSC2/CLKOUT 43 3.5 MCLR 17.0 17.0 RTCC 3.2 2.8 osc 6.6 3.5 OSC2/CLKOUT 46 3.5 * All capacitance values are typical at 25C and mea- RTCC 4.5 3.5 sured at 1 MHz. A partto part variation of +25% (three standard deviations) should be taken into account. DS30015K-page 44 1994 Microchip Technology Inc. 2-46PIC16C5X Series 19.0 PACKAGING INFORMATION See Section 11 of the Data Book. 19.1 Package Marking Information Example 18L PDIP MMMMMMMMMMMMXXX PIC16C56- O MMMMMMMMXXXXXXX RCI/P456 AS\AABB CDE AS\9123 CBA 18L SOIC Example MMMMMMMMM PICL6C54- MMMMMMMMM XTI/S02198 fOABB CDE mY 118 CDK 28L SOIC Example x PIC16C57-XT/SO XXXKXXKKKXKXKKXKKKKK oS ane CDE ofS 9051 caK Example 28L PDIP (.300 mil) XXXXXXKXXXXXKXK XXXXXXXKXXXXXXK PIC16C56- RCI/P456 A123 CBA ASMAABB CDE 28L SSOP Exampie XXXXXXXXXKKK PIC16C57-XT XXXXXXXXXXXK oS aazs coe fDi 9225 cBK 20L SSOP Example XXKXKXXX PIC16C54 XXXXKXXX XTI/218 OAD AABE CDE 0051 CBP Legend: MNM...M_ Microchip part number information XX...X Gustomer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week '01') Cc Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number can not be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. *Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev #, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are incuded in QTP price. a Oe DS30015K-page 45 1994 Microchip Technology inc. Note: 2-47PIC16C5X Series 19.1 ckage Marki t 28L PDIP (.600 mil) Example XX PIc16c55- MMMMMMMMXXXXXXX XTI/P126 ) ORO 0 O O AABB CDE 9042 CDA O xX Meceocte Oo MicnacaP 18L Cerdip Example MMMMMMMM PIC16C54 D aS MMMMMMMM D x Mucrnocan AABB CDE Pcmecea 9101 CBA 28L Cerdip Example WV WV MicrRocHP MiceacHie MMMMMMMMMM PIC16C57 MMMMMM AABB CDE 9038 CBA Legend: MM..M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week '01')) c Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number can not be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, maskrev #, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. Cee ee DS30015K-page 46 1994 Microchip Technology Inc. 2-48PIC16C5X Series 20.0 DEVELOPMENT SUPPORT 20.1 Development Tools The PIC16C5X and PIC16CXX microcontrollers are supported with a full range of hardware and software development tools: PICMASTER Real-Time tn-Circuit Emulator PRO MATE Universal Programmer PICSTART Low-Cost Prototype Programmer e Assembler Software Simulator 20.2 PICMASTER: High Performance Universal In-Circuit Emulator The PICMASTER Universal In-Circuit Emulator is in- tended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC16C5X, PIC16CXX and PIC17CXX families. Interchangeable target probes allow the system to be easily reconfigured for emulation of different proces- sors. The universal architecture of the PICMASTER allows expansion to support all new PIC16C5X, PIC16CXX and PIC17CXX microcontrollers. The Emulator System is designed to operate on PC compatible machines ranging from 80286-AT class ISA-bus systems through the new 80486 EISA-bus machines. The development software runs in the Microsoft Windows 3.1 environment, allowing the op- erator access to a wide range of supporting software and accessories. The PICMASTER has been designed as a real-time emulation system with advanced features generally found on more expensive development tools. The AT platform and Windows 3.1 environment was chosen to best make these features available to you, the end user. The PICMASTER Emulator Universal System consists Primarily of four major components: Host-Interface Card * Emulator Control Pod * Target-Specific Emulator Probe e PC Host Emulation Control Software The Windows 3.1 System is a multitasking operating system which will allow the developer to take full advan- tage of the many powerful features and functions of the PICMASTER system. PICMASTER emulation can operate in one window, while a text editor is running in a second window. Dynamic Data Exchange (DDE), a feature of Windows 3.1, will be available in this and future versions of the software. DDE allows data to be dynamically transferred between two or more Windows programs. With this feature, data collected with PICMASTER can be auto- matically transferred to a spreadsheet or database pro- gram for further analysis. Under Windows 3.1, two or more PICMASTER emula- tors can run simultaneously on the same PC making development of multi-microcontroller systems possible (e.g., asystem containing a PIC16CXX processor anda PIC17CXX processor). 20.3 PRO MATE: Universal Programmer The PRO MATE Universal Programmer is a production quality programmer capable of operating in stand alone mode as well as PC-hosted mode. The PRO MATE has programmable Vpp and VrP sup- plies which allows it to verify programmed memory at Vbp min and Vop max for maximum reliability . It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand alone mode the PRO MATE can read, verify or program PIC16C5X, PIC16CXX and PIC17CXX devices. it can also set fuse configuration and code-protect in this mode. Its EEPROM memory holds data and parametric information even when powered down. It is ideal for low to moderate volume production. FIGURE 20.2 - PICMASTER SYSTEM CONFIGURATION Common Interface Card PC Compatible Computer . (AT/ISA Bus) (for industry Standard Architecture) 5v Power Supply In-Line ||-< 90-250 VAC (Optional) PICMASTER Emulator Pod Power Switch Power Connector Aux. PC-Intertace Interchangeable Emulator Probe Logic Probes 1994 Microchip Technology Inc. 2-49 0DS30015K-page 47PIC16C5X Series In PC-hosted mode, the PRO MATE connects to the PC via one of the COM (RS232) ports. A PC based user- interface software makes using the programmer simple and efficient. The user interface is full-screen and menu- based. Full screen display and editing of data, easy selection of fuse configuration and part type, easy selec- tion of VoD min, VDD max and Ver levels, load and store to and from disk files (intel hex format) are some of the features of the software. Essential commands such as read, verify, program, blank check can be issued from the screen. Additionally, serial programming support is possible where each part is programmed with a different serial number, sequential or random. The PRO MATE has a modular "programming socket module. Different socket modules are required for different processor types and/or package types. PRO MATE supports all PIC16C5X, PIC16CXX and PIC17CXX processors. 20.4 PICSTART Programmer The PICSTART programmer is an easy to use, very low-cost prototype programmer. It connects to the PC via one of the COM (RS232) ports. A PC based user interface software makes using the programmer simple andefficient. The user interface is full-screen and menu- based. 20.5 Assembler (MPASM) Cross Assembler is a PC hosted symbolic assembler. It supports all microcontroller series including the PIC16C5X CMOS, PIC16CXX and PIC 17CXxX families. MPASM offers fully featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from the Micro- chip Universal Emulator System (PICMASTER). MPASM has the following features to assist in develop- ing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro Assembly Capability * Provides Object, Listing, Symbol and special files required for debugging with one of the Microchip Emulator systems. Supports Hex (defauit), Decimal and Octal source and listing formats. MPASM provides a full feature directive language repre- sented by four basic classes of directives: Data Directives are those that control the allocation of memory and provide a way to refer to data items symbolically, by meaningful names. * Listing Directives control the MPASM listing dis play. They allow the specification of titles and sub- titles, page ejects and other listing control. Control Directives permit sections of conditionally assembled code. Macro Directives control the execution and data allocation within macro body definitions. 20.6 Softwar MPSIM The Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16C5X and PIC16CXX series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide extemal stimulus to any of the pins. The input/output radix can be set by the user and the execution can be performed in single step, execute until break or ina trace mode. Two forms of symbolic debugging are available: an intemal symbol table for disassembling opcodes and the displaying of source code from a listing file. The Software Simulator offers the low cost flexibility to de- velop and debug code outside of the laboratory environ- ment making it an excellent multi-project software devel- opment tool. 20.7 Development Systems For convenience, the development tools are packaged into comprehensive systems as listed in Table 19-1: TABLE 20-1: DEVELOPMENT SYSTEM PACKAGES Item | Name System Description 1. |PICMASTER | PICMASTER In-Circuit Emutator System with your choice of Target Probe, PRO MATE Programmer, Assembler, Software Simulator and Samples. 2. |PICSTART PICSTART Low-Cost Prototype System Programmer, Assembler, Software Simulator and Sampies 20.8 Pro ification The PICMASTER probes currently meet the following specifications: PROBE PICMASTER Devices Maximum Operating PROBE Supported |Frequency Voltage PROBE - 16A | PIG16C54, 4 MHZ 4.5V - 5.5V PIC16C55, PIC16C56, and PIC16C57 PROBE - 16D | PIC16C54, 20 MHz 4.5V - 5.5V PIC16C55, PIC16C56, PIC16C57, and PIC16C58 0S30015K-page 48 2-50 1994 Microchip Technology Inc.PIC16C5X Series 21.0 EPROM PROGRAMMING 21.1 Prototype Programmers Microchip's proprietary iow cost PICSTART program- mer is ideal for programming during development and Prototyping. It is not recommended for production programming. 21.2 Production Quality Programmers Microchip's PRO MATE programmer can be used for reliable programming for production. High volume pro- gramming is also supported by production quality pro- grammers from third party sources. See Table 21.2.1. Microchip assumes no responsibility for replacing defec- tive units related to mechanical and/or electrical prob- lems of any third party programming equipment or the improper use of such equipment. Programming of the code protection bit (also called security bit" or "security fuse") implies that the contents of the PIC16C5X EPROM can nolonger be verified, thus making programming related failure analysis an impos- sibility. Microchip warrants that PIC16C5X units will not exceed a programming failure rate of 1% of shipment quality. Programming related failures beyond this fevel can be returned for replacement, again, if the security bit has not been programmed. 21.3 Gang Programmers Gang programmers are available from third party sources. See Table 21.2.1. 21.4 Factory Programming High volume factory programming (QTP) is an available service from Microchip Technology. A small price adder and minimum quantity requirements apply. TABLE 21.2.1 - LIST OF THIRD PARTY PROGRAMMERS* Company Model Contact Company Model Contact ADVIN Systems, Inc. PILOT-U40 408-243-7000 U.S. HI-LO ALL-03 02 7640215 Taiwan Application Solutions Ltd. | Programmer 273 476608 U.K. Link Computer Graphics | CLK-3100 201-808-8990 U.S. Gang Programmer Baradine Products Ltd. Micro-Burner |604-988-9853 Canada || Logical Devices, Inc. ALLPRO-88 305-428-6868 U.S. BP Microsystems CP-1128 800-225-2102 U.S. 713-668-4600 U.S. Parallax, Inc. PIC16C5X-PGM 916-624-8333 U.S. Citadel Products Ltd. PC-82 44-819-511-848 U.K. || Stag Microsystems PP39 44-707-332-148 UK. Data /0 Corporation Unisite with 800-332-8246 U.S. Transdata PGM16 (214) 980 2960 Site-48 module /31(0) 6622866 Europe PGM 16x8 (03) 432-6991 Japan Gang Programmer Elan Digital Systems Ltd. | EF-PER 0489 579 799 U.K. 5000 Series (800) 541-3526 U.S. * For a compiete listing of all Microchip third party support, please refer to the Third Party Support Handbook (DS00104A). All trademarks shown in table 21.2.1 belong to their respective hokers. 1994 Microchip Technology Inc. 2-51 DS30015K-page 49PIC16C5X Series Index Absolute maximum ratingS ..........scecceesseesseeeeeees 29 AC characteristics (XT,RC,HS,LP) COMIIND ......... 35 Block diagrams: Chip tase wae VO PIM oe eeeeceeseecncneeseceeesessenesssaeeesnsecesesesceaesses 13 Power On Reset .. 26 RTCC (Simplified) ................. 6 RTCC & WOT once 17 Brown-out protection circuit .. 25 Code protection .................. +28 Configuration fuses . 27 Data MEMOrY MAP uu... cece ccs escceeeseneeenececeeeneseeneeeee 7 DC characteristics (XT,RC,HS,LP) COM .... 30, 33, 35 DC characteristics (XT,RC,HS,LP) IND ...... 31, 33, 35 Development tools oo... ee sceescssceserssssseesseesenes External Power-On Reset circuit .. F@atureS OVEFVIEW oo... ects escecceseseeeeesssesersensenseae File register descriptions INDF RTCC PC... STATUS FSR I/O ports ID 1OCATIONS oo. eee eceeeecseaeteeeseesssceeessesenserseeaeses 27 Indirect addressing .............seeecceeeeeesseeessesceeesstenseseaee 6 Instruction set....... 18 OPTION register .. we 0+!) (0) 23-25 Oscillator Start-up Timer .............. 25 OTP devices... cee cceeesecesessssecnstseeeesssseseeessenesteeee 5 Package information ................ 45-46 Page select (Program memory) ... 9,10 PD Dit woe eeeteneeenee we 12 Pin-out information ............. 1,29 Power Down mode (SLEEP) .............cccccssssssesssessenes 27 Power-On ReSet ..........cccceeeceseescesssesesseseseeeeeees 25-27 Prescaler (RTCC/WDT) . 16,17 Program Counter ........... wee 8 Program MeEMOTrY MAP ...........:cccsceessssseesssssessssseaseses 10 Programming information ............-.-sseccesssesessesseess 56 QTP deViCeS o.oo. eee ceeeetceseeescereseceseeseseeeneesseseensee 5 Real Time Clock/Counter (RTCC) Typical characteristics graphs lob vs freq IOH vs VOH .. lot vs VOL IPD vs Vop RC osc freq vs temp RC osc freq vs Vob Vin, ViL of MCLR, RTCC and OSC1 vs Voo .... 40 VtH of I/O Pins vs VDD.............. VTH of OSC1 Input vs Vob eee Transconductance of HS Oscillator vs Vpbo ...... 42 Transconductance of LP Oscillator vs Vop Transconductance of XT Oscillator vs Vop WDT Timer Time-out Period vs Vob.... UV Erasable devices ............... eee W register .............. wo WOT 0... cecceeesssceeneesctensseceneeaceenseenenseseeeeeseeteneensenes RESET oo. ccescsessccsenesoeeeseccaecesesesesensessesaeasesssseeass 16 SLEEP........... 27 Stack .......... 9 Status reQister oe. eeeescsssssseseessessscssseseesseseeeeees 11 Timing diagrams VO PIM occ sees nessseeseeeeteeeeseneteeseesseeeseesees 13,36 Oscillator Start-up timing 0.0... ee eeeceeeeeeees 36 Power On Reset ..........scccccseees -25,26 __ RTCC timing... eee 8,9,36 TO bit we we 12 TRIS registers 200... cceccceeesseceeessseeetesseneeseeeresees 15 DS30015K-page 50 1994 Microchip Technology Inc. 2-52CONNECTING TO MICROCHIP BBS Connect worid wide to the Microchip BBS using the CompuServe communications network. In most cases a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore you do not need Compuserve membership to join Microchip's BBS. The procedure to connect will vary slightly from country to country. Please check with your iocal CompuServe agent for details if you have a problem. CompuServe services allows multiple users at baud rates up to 9600. To connect: 1. Set your modem to 8 bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. 2. Dial your local CompuServe phone number. 3. Depress <ENTER> and a garbage string will appear because CompuServe is expecting a 7E1 setting. 4. Type + <ENTER> and Host Name: will appear. 5. Type MCHIPBBS<ENTER> and you will be con- nected to the Microchip BBS. In the United States, to find CompuServe's phone num- ber closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600 baud connection. After the system responds with Host Name:, type NETWORK<ENTER> and follow CompuServe's direc- tions. For voice information (or calling from overseas), you may call (614) 457-1550 for your local CompuServe number. PIC1 6C5X Series Trademarks: PIC is a registered trademark of Microchip Technology Incorporated in the U.S.A. The Microchip logo and name are trademarks of Microchip Technology Incorporated. PICMASTER, PRO MATE and PICSTART are trademarks of Microchip Technology Incorporated. IBM PC and AT are registered trademarks of IBM Corpora- tion. MS-DOS and Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Inc. All other trademarks mentioned herein are the property of their respective companies. 1994 Microchip Technology Inc. 2-53 DS30015K-page 51PIC16C5X Series Ic1 X Pr Identificati m To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO. - XX X (KX XXX Pattern: 3-Digit Pattern Code for QTP (blank for OTP and Window Parts) Package: P= PDIP SS = SSOP (209 mil) SO = 300 mil SOIC (Gull Wing Lead) = JW*_ = CERDIP Window SP = 28L PDIP (300 mil) S_ = Die in Waffle Pack Temperature - = OC to +70C (T for tape/reel) Range: ( = -40C to +85C (S for tape/reel) E -40C to +125C Examples: RC, H . . creer xT. Hig a) PIC16CS54 - XT/PXXX = "XT" oscillator, commercial , temp., PDIP, QTP pattern b) PIC16C55-XTV/SO = "XT" oscillator, industrial Device: PIC16C54 temp., SOIC {OTP device) PIC16C55 c) PICI6C55 - JW = Commercial temp. PIC16C56 CERDIP with WINDOW PIC16C57 d) PIC16C57-RCI/S = RC oscillator", industrial temp., dice in waffle pack. Notes: * For UV-erasable devices, the oscillator type is RC by default (= erased device). The user can select XT, HS, or LP oscillators by programming the appropriate fuses. Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip's Bulletin Board, via your local Compuserve number. Please specify which device, revision of silicon and Data Sheet {include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. DS30015K-page 52 1994 Microchip Technology Inc. 2-54