Ultralow Profile, 500 mA, 6 MHz, Synchronous,
Step-Down, DC-to-DC Converters
Data Sheet ADP2126/ADP2127
Rev. B
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FEATURES
1.20 V and 1.26 V fixed output voltage options
Clock signal enable
Logic signal enable also available on certain models
6 MHz operating frequency
Spread spectrum frequency modulation to reduce EMI
500 mA continuous output current
Input voltage: 2.1 V to 5.5 V
0.3 μA (typical) shutdown supply current
Pin-selectable power-saving mode
Compatible with tiny multilayer inductors
Internal synchronous rectifier
Internal compensation
Internal soft start
Output-to-ground short-circuit protection
Current-limit protection
Undervoltage lockout
Thermal shutdown protection
0.330 mm height (maximum), 6-ball BUMPED_CHIP (ADP2126)
0.200 mm height (maximum), 6-pad EWLP (ADP2127)
APPLICATIONS
Mobile phones
Digital still/video cameras
Digital audio
Portable equipment
Camera modules
Image stabilization systems
TYPICAL APPLICATIONS CIRCUIT
A2
C2
B2 A1
B1
C1
VIN
GND FB
SW
EXTCLK MODE
C
IN
2.2µF C
OUT
2.2µF
INPUT
VOLTAGE
2.1V TO 5.5V
L
1.0µH
ADP2126/
ADP2127
OUTPUT
VOLTAGE
1.20V O R 1. 26V
OFF ON
OFF ON
AUTO PWM
OR
09658-001
*LO G IC HIG H E NABL E I S O NL Y AVAIL ABL E O N CERTAIN M O DE L S .
*
Figure 1.
GENERAL DESCRIPTION
The ADP2126/ADP2127 are high frequency, step-down, dc-to-
dc converters optimized for portable applications in which board
area and battery life are critical constraints. The fixed 6 MHz
operating frequency enables the use of tiny ceramic inductors
and capacitors and the regulators use spread spectrum frequency
modulation to reduce EMI. Additionally, synchronous rectification
improves efficiency and results in fewer external components.
At high load currents, the ADP2126/ADP2127 use a voltage
regulating pulse-width modulation (PWM) mode that maintains
a constant frequency with excellent stability and transient response.
Light load operation is determined by the state of the MODE pin.
In forced PWM mode, the converter continues operating in PWM
for light loads. Under light load conditions in auto mode, the
ADP2126/ADP2127 automatically enter a power-saving mode,
which uses pulse frequency modulation (PFM) to reduce the
effective switching frequency, thus ensuring the longest battery
life in portable applications.
The ADP2126/ADP2127 are enabled by a 6 MHz to 27 MHz
external clock signal applied to the EXTCLK pin. Certain models
can also be enabled with a logic high signal. When the external clock
is not switching and in a low logic state, the ADP2126/ADP2127
stop regulating and shut down to draw less than 0.3 μA (typical)
from the source.
The ADP2126/ADP2127 have an input voltage range of 2.1 V to
5.5 V, allowing the use of single Li+/Li polymer cell, three-cell
alkaline, NiMH cell, and other standard power sources. The
ADP2126/ADP2127 are internally compensated to minimize
external components and can source up to 500 mA. Other key
features, such as cycle-by-cycle peak current limit, soft start,
undervoltage lockout (UVLO), output-to-ground short-circuit
protection, and thermal shutdown provide protection for internal
and external circuit components.
ADP2126/ADP2127 Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Overview...................................................................................... 11
External Clock (EXTCLK) Enable........................................... 11
Spread Spectrum Oscillator ...................................................... 12
Mode Selection ........................................................................... 12
Internal Control Features .......................................................... 12
Protection Features .................................................................... 13
Timing Constraints.................................................................... 13
Applications Information .............................................................. 14
Inductor Selection ...................................................................... 14
Input Capacitor Selection.......................................................... 14
Output Capacitor Selection....................................................... 15
Thermal Considerations............................................................ 15
PCB Layout Guidelines.................................................................. 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
3/12—Rev. A to Rev. B
Combined Figure 1 and Figure 2; Renumbered Sequentially..... 1
Changes to Undervoltage Lockout (UVLO) Section,
Added Figure 29, Renumbered Sequentially .............................. 13
Changes to Table 6.......................................................................... 14
Changes to Ordering Guide .......................................................... 18
5/11—Rev. 0 to Rev. A
Changes to Figure 35...................................................................... 17
5/11—Revision 0: Initial Version
Data Sheet ADP2126/ADP2127
Rev. B | Page 3 of 20
SPECIFICATIONS
VIN = 3.6 V, TA = 25°C for typical specifications, and TA = TJ = −40°C to +85°C for minimum and maximum specifications, unless
otherwise noted. All specifications at temperature extremes are guaranteed via correlation using the standard statistical quality control
(SQC) methods. Typical specifications are not guaranteed.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Operating Input Voltage Range VIN 2.1 5.5 V
PWM Mode Quiescent Current No load, VMODE = VIN 12 mA
Auto Mode Quiescent Current No load, VMODE = 0 V, VFB > VOUT, SW = open 300 500 μA
Shutdown Current1 V
EXTCLK = 0 V, open loop 0.3 1.5 μA
UNDERVOLTAGE LOCKOUT
Rising VIN Threshold 1.9 2.1 V
Falling VIN Threshold 1.5 1.8 V
OUTPUT
Continuous Output Current2 I
LOAD V
IN = 2.1 V to 5.5 V 500 mA
PWM Mode Output Accuracy3 VOUT V
IN = 2.1 V to 5.5 V, no load VOUT − 2% VOUT + 2% V
PFM Mode Output Accuracy3, 4 V
IN = 2.1 V to 5.5 V VOUT − 3% VOUT + 3% V
FB Bias Current VFB = VOUT 4 9 μA
FB Pull-Down Resistance RDSCHG V
EXTCLK = 0 V, IFB = 10 mA 110 180 Ω
SWITCHING CHARACTERISTICS
PMOS On Resistance ISW = 500 mA 180 340 mΩ
NMOS On Resistance ISW = 500 mA 250 mΩ
SW Leakage Current VSW = 0 V, VIN = 5.5 V 10 μA
PMOS Switch Current Limit Open loop 770 1000 1291 mA
PFM Current Limit VMODE = 0 V, VIN = 3.6 V 170 260 305 mA
Oscillator Frequency fSW 4.8 6 6.8 MHz
SHORT-CIRCUIT PROTECTION
Rising VOUT Threshold 0.55 0.7 V
Falling VOUT Threshold 0.4 0.52 V
EXTCLK INPUT
High Threshold Voltage VEXTCLK(H) V
IN = 2.1 V to 5.5 V 1.3 V
Low Threshold Voltage VEXTCLK(L) V
IN = 2. 1 V to 5.5 V 0.4 V
Leakage Current VIN = 5.5 V, VEXTCLK = 2.1 V to 5.5 V 0.01 1 μA
Duty Cycle Operating Range DEXTCLK 40 60 %
Frequency Operating Range fEXTCLK 6 27 MHz
MODE INPUT LOGIC
High Threshold Voltage VMODE(H) V
IN = 2.1 V to 5.5 V 1.3 V
Low Threshold Voltage VMODE(L) V
IN = 2.1 V to 5.5 V 0.4 V
Leakage Current VEXTCLK = 0 V, VIN = VMODE = 5.5 V 0.005 1 μA
THERMAL SHUTDOWN5 PWM mode only
Thermal Shutdown Threshold 146 °C
Thermal Shutdown Hysteresis 13 °C
ADP2126/ADP2127 Data Sheet
Rev. B | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TIMING See Figure 2 and Figure 3
VIN High to EXTCLK On2 t1 V
IN = 2.1 V to 5.5 V 200 μs
EXTCLK On to VOUT Rising t2 (CLOCK) D
EXTCLK = 40% to 60%, fEXTCLK = 6 MHz 250 320 400 μs
D
EXTCLK = 40% to 60%, fEXTCLK = 27 MHz 250 320 400 μs
EXTCLK On to VOUT Rising t2 (LOGIC) EXTCLK = logic high 285 315 385 μs
VOUT Power-Up Time (Soft Start)2 t
3 C
OUT = 2.2 μF, RLOAD = 3.6 Ω 70 200 μs
EXTCLK Off to VOUT Falling t5 (CLOCK) D
EXTCLK = 40% to 60%, fEXTCLK = 6 MHz to 27 MHz 9 17 μs
EXTCLK Off to VOUT Falling t5 (LOGIC) EXTCLK = logic high, no load 0 μs
VOUT Power-Down Time t6 C
OUT = 2.2 μF, RLOAD = 3.6 Ω 16 μs
C
OUT = 2.2 μF, no load 465 μs
Minimum Shutdown Time2 t
5 + t6 C
OUT = 2.2 μF, no load 1400 μs
Minimum Power-Off Time2 t
7 500 μs
1 The total shutdown current is the addition of VIN shutdown current and SW leakage.
2 Guaranteed by design.
3 Transients not included in voltage accuracy specifications.
4 The PFM output voltage will be higher than the PWM output voltage. See the Typi section. cal Performance Characteristics
5 Thermal shutdown protection is only active in PWM mode.
TIMING DIAGRAMS
t
6
t
7
t
5
t
3
t
2
t
1
VOUT(NOM) × 10%
VIN × 10%
VIN × 90%
VIN
VOUT
EXTCLK
09658-003
Figure 2. Clock Enable I/O Timing Diagram
t
6
t
7
t
5
t
3
t
2
t
1
VOUT(NOM) × 10%
VIN × 10%
VIN × 90%
VIN
VOUT
EXTCLK
09658-004
Figure 3. Logic Enable I/O Timing Diagram (Logic High Enable Feature Available Only on Certain Models)
Data Sheet ADP2126/ADP2127
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VIN to GND −0.3 V to +6 V
EXTCLK to GND −0.3 V to +6 V
SW, MODE to GND −0.3 V to VIN
FB to GND −0.3 V to +3.6 V
Operating Ambient Temperature (TA) –40°C to +85°C1
Operating Junction Temperature (TJ)
at ILOAD = 500 mA
–40°C to +125°C
Soldering Conditions JEDEC J-STD-020
1 The maximum operating junction temperature (TJ (MAX)) supersedes the
maximum operating ambient temperature (TA (MAX)). See the Thermal
Considerations section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination.
THERMAL CONSIDERATIONS
The maximum operating junction temperature (TJ (MAX))
supersedes the maximum operating ambient temperature
(TA (MAX)) because the ADP2126/ADP2127 may be damaged
when the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that TJ is within the
specified temperature limits.
In applications with high power dissipation and poor PCB
thermal resistance, the maximum ambient temperature may
need to be derated. In applications with moderate power
dissipation and good PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits.
The operating junction temperature (TJ) of the device is dependent
on the ambient temperature (TA), the power dissipation of the
device (PD), and the junction-to-ambient thermal resistance of
the package (θJA). TJ is calculated using the following formula:
TJ = TA + (PD × θJA) (1)
See the Applications Information section for further information
on calculating the operating junction temperature for a specific
application.
THERMAL RESISTANCE
θJA of the package is based on modeling and calculation using a
4-layer board. θJA is highly dependent on the application and
board layout. In applications where high maximum power
dissipation exists, attention to thermal board design is required.
The value of θJA may vary, depending on PCB material, layout,
and environmental conditions.
θJA is specified for worst-case conditions, that is, a device soldered
on a circuit board for surface-mount packages. θJA is determined
according to JEDEC Standard JESD51-9 on a 4-layer printed
circuit board (PCB).
Table 3. Thermal Resistance (4-Layer PCB)
Package Type θJA Unit
6-Ball Bumped Bare Die Sales 105 °C/W
6-Pad Embedded Wafer Level Package 105 °C/W
ESD CAUTION
ADP2126/ADP2127 Data Sheet
Rev. B | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
MODE VIN
SW
FB GND
1
A
B
C
2
BALL
A
1
INDICATOR
EXTCLK
TOP VIEW
BALL/PAD SIDE DOWN
BUMPS/PADS ON OPPOSITE SIDE
(Not to Scale)
09658-005
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
A1 MODE
Mode Select. This pin toggles between auto mode (PFM and PWM switching) and PWM mode. Set MODE low to
allow the part to operate in auto mode. Pull MODE high to force the part to operate in PWM mode. The voltage
applied to MODE should never be higher than the voltage applied to VIN. Do not leave this pin floating.
A2 VIN Power Supply Input.
B1 SW Switch Node.
B2 EXTCLK
External Clock Enable Signal. The ADP2126/ADP2127 power up when a clock signal (6 MHz to 27 MHz) or a logic high
signal (EXTCLK ≥ 1.3 V) is detected on this pin. (The logic high enable feature is only available on certain models.)
C1 FB Feedback Divider Input. Connect the output capacitor from FB to GND to set the output voltage ripple and to
complete the control loop.
C2 GND Ground.
Data Sheet ADP2126/ADP2127
Rev. B | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, fEXTCLK = 10 MHz, VOUT = 1.20 V, L = 1.0 µH (CKP1608S1R0), CIN = 2.2 µF (GRM153R60J225ME95), COUT = 2.2 µF
(GRM153R60G225M), and TA = 25°C, unless otherwise noted.
90
0
10
20
30
40
50
60
70
80
1 10 100 1000
EFFICIENCY (%)
LOAD CURRENT (mA)
V
IN
= 2.1V
V
IN
= 2.5V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.5V
AUTO MODE
PWM MODE
09658-006
Figure 5. Efficiency vs. Load Current
90
30
40
50
60
70
80
2.1 5.14.64.13.63.12.6
EFFICIENCY (%)
INPUT VOLTAGE (V)
09658-007
I
LOAD
= 50mA, PWM MODE
I
LOAD
= 100mA, PWM MODE
I
LOAD
= 10mA, PFM MODE
I
LOAD
= 50mA, PFM MODE
I
LOAD
= 100mA, PFM MODE
I
LOAD
= 250mA, PFM MODE
Figure 6. Efficiency vs. Input Voltage
1.24
1.23
1.22
1.21
1.19
1.20
1 10 100 1000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
V
IN
= 2.1V
V
IN
= 2.5V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.5V
09658-008
Figure 7. Auto Mode Output Voltage Accuracy
1.205
1.204
1.203
1.202
1 10 100 1000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
V
IN
= 2.1V
V
IN
= 2.5V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.5V
09658-009
Figure 8. PWM Mode Output Voltage Accuracy
250
200
150
100
50
0
2.3 5.55.14.74.33.93.53.12.7
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
PWM OPERATION
PFM OPERATION
09658-010
Figure 9. Auto Mode Switching Threshold vs. Input Voltage
60
0
10
20
30
40
50
0 100 200 300 400 500
OUTPUT VOLTAGE RIPPLE (mV)
LOAD CURRENT (mA)
09658-011
V
IN
= 2.1V
V
IN
= 3.6V
V
IN
= 5.5V
Figure 10. Output Voltage Ripple vs. Load Current
ADP2126/ADP2127 Data Sheet
Rev. B | Page 8 of 20
1.2
0
0.2
0.4
0.6
0.8
1.0
2.1 5.14.64.13.63.12.6
SHUTDOWN CURRENT (µA)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
09658-012
Figure 11. Shutdown Current vs. Input Voltage
500
200
250
300
350
400
450
2.1 5.14.64.13.63.12.6
PFM MODE QUIESCENT CURRENT (µA)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
09658-013
Figure 12. PFM Mode Quiescent Current vs. Input Voltage
17
5
7
9
11
13
15
2.1 5.14.64.13.63.12.6
PWM MODE QUIESCENT CURRENT (mA)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
09658-014
Figure 13. PWM Mode Quiescent Current vs. Input Voltage
450
150
200
250
300
350
400
2.1 5.14.64.13.63.12.6
N-CHANNEL RDSON (mΩ)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +105°C
I
SW
= 500mA
09658-015
Figure 14. NMOS Drain-to-Source On Resistance
400
100
150
200
250
300
350
2.1 5.14.64.13.63.12.6
P-CHANNEL RDSON (mΩ)
INPUT VOLTAGE (V)
T
A
= –40°C
T
A
= +25°C
T
A
= +105°C
I
SW
= 500mA
09658-016
Figure 15. PMOS Drain-to-Source On Resistance
TIME (200µs/DIV)
OUTPUT VOLTAGE (200mV/DIV)
INDUCTOR CURRENT (1A/DIV)
09658-017
1
4
Figure 16. Output Short-Circuit Response
Data Sheet ADP2126/ADP2127
Rev. B | Page 9 of 20
TIME (40µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.20V OFFSET
LOAD CURRENT (100mA/DIV)
V
IN
= 2.1V
09658-018
1
4
Figure 17. Load Transient Response, 0 mA to 150 mA, VIN = 2.1 V
TIME (40µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.20V OFFSET
LOAD CURRENT (100mA/DIV)
V
IN
= 3.6V
09658-019
1
4
Figure 18. Load Transient Response, 0 mA to 150 mA, VIN = 3.6 V
TIME (40µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.20V OFFSET
LOAD CURRENT (100mA/DIV)
V
IN
= 5.5V
09658-020
1
4
Figure 19. Load Transient Response, 0 mA to150 mA, VIN = 5.5 V
TIME (20µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.20V OFFSET
LOAD CURRENT (200mA/DIV)
V
IN
= 2.1V
09658-021
1
4
Figure 20. Load Transient Response, 250 mA to 420 mA, VIN = 2.1 V
TIME (20µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.20V OFFSET
LOAD CURRENT (200mA/DIV)
V
IN
= 3.6V
09658-022
1
4
Figure 21. Load Transient Response, 250 mA to 420 mA, VIN = 3.6 V
TIME (20µs/DIV)
OUTPUT VOLTAGE (50mV/DIV)
1.20V OFFSET
LOAD CURRENT (200mA/DIV)
V
IN
= 5.5V
09658-023
1
4
Figure 22. Load Transient Response, 250 mA to 420 mA, VIN = 5.5 V
ADP2126/ADP2127 Data Sheet
Rev. B | Page 10 of 20
TIME (100µs/DIV)
OUTPUT VOLTAGE (500mV/DIV)
INDUCTOR CURRENT (200mA/DIV)
EXTCLK PIN VOLTAGE (5V/DIV)
NO LOAD
09658-024
1
4
2
Figure 23. Startup, No Load
TIME (100µs/DIV)
OUTPUT VOLTAGE (500mV/DIV)
INDUCTOR CURRENT (200mA/DIV)
EXTCLK PIN VOLTAGE (5V/DIV)
R
LOAD
= 3.6Ω
09658-025
1
2
4
Figure 24. Startup, RLOAD = 3.6 Ω
5.50
5.45
5.40
5.35
5.30
5.25
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
FREQUENCY (MHz)
TIME (ns)
09658-026
Figure 25. Spread Spectrum Switching Frequency
TIME (400ns/DIV)
OUTPUT VOLTAGE (20mV/DIV)
1.20V OFFSET
INDUCTOR CURRENT (200mA/DIV)
SW PIN VOLTAGE (5V/DIV)
I
LOAD
= 100mA
09658-027
1
2
4
Figure 26. Typical PFM Mode Operation, ILOAD = 100 mA
TIME (100ns/DIV)
OUTPUT VOLTAGE (10mV/DIV)
1.20V OFFSET
INDUCTOR CURRENT (200mA/DIV)
SW PIN VOLTAGE (5V/DIV)
I
LOAD
= 150mA
09658-028
1
4
4
Figure 27. Typical PWM Mode Operation, ILOAD = 150 mA
Data Sheet ADP2126/ADP2127
Rev. B | Page 11 of 20
THEORY OF OPERATION
09658-029
SHOOT-
THROUGH
CONTROL
LOGIC
AND
PFM/PWM
CONTROL
THERMAL
SHUTDOWN
SOFT START
BANDGAP
BG
FB
BG
AGND
R1
FB
R2
V
OUT
AGND
AGND
FB
6MHz
OSCILLATOR
B2
THRESHOLD
DETECT*
THRESHOLD
DETECT
V
OUT
DISCHARGE
CLK
DETECT
SHORT-CIRCUIT
PROTECTION
COMPENSATION
EAMP
R
DSCHG
110Ω
RAMP
V(V
IN
)
ZXCOMP
PILIM
PDRIVE
PWM
COMP
PV
IN
C
IN
AVIN
NDRIVE
PREF
C
OUT
V
OUT
1.20V OR
1.26V
L
PGND
VIN
GND
SW
AGND
NREF
EXTCLK
C2
B1
A2
C1
A1
MODE
OFF ON
ON
OFF
PWM
AUTO
OR
ADP2126/ADP2127
*
*
THE LOGIC HIGH ENABLE FEATURE IS ONLY AVAILABLE ON CERTAIN MODELS.
V
IN
2.1V TO 5.5V
Figure 28. Internal Block Diagram
OVERVIEW
The ADP2126/ADP2127 are high efficiency, synchronous, step-
down, dc-to-dc regulators that operate from a 2.1 V to 5.5 V
input voltage. They provide up to 500 mA of continuous output
current at a fixed output voltage. The 6 MHz operating frequency
enables the use of tiny external components. External control
for mode selection provides a power-saving option. The internal
control schemes of the ADP2126/ADP2127 give excellent
stability and transient response. Other internal features, such
as cycle-by-cycle peak current limit, soft start, undervoltage
lockout, output-to-ground short-circuit protection, and thermal
shutdown provide protection for internal circuit components.
EXTERNAL CLOCK (EXTCLK) ENABLE
The ADP2126/ADP2127 are enabled by a 6 MHz to 27 MHz
external clock signal applied to the EXTCLK pin. Certain models
can also be enabled with a logic high signal (see Figure 2, Figure 3,
and Figure 28). When the ADP2126/ ADP2127 are enabled, the
converter is able to power up, and the output voltage rises to its
nominal value. When the external clock is not switching and in
a low logic state, the ADP2126/ADP2127 stop regulating and
shut down to draw less than 0.3 µA (typical) from the source.
ADP2126/ADP2127 Data Sheet
Rev. B | Page 12 of 20
SPREAD SPECTRUM OSCILLATOR
The ADP2126/ADP2127 incorporate spread spectrum
functionality to modulate electromagnetic interference (EMI)
for EMI sensitive applications. A typical switching converter
with a regulated switching frequency has a narrow frequency
spectrum centered at the target switching frequency. This
results in a high spectral density around the target frequency
with peak emission levels that can exceed the regulatory levels
for EMI in many portable, cellular, and wireless applications.
To maintain acceptable levels of EMI, the ADP2126/ADP2127
employs spread spectrum via a controlled variance of the switching
frequency over a wider band of frequencies. Figure 25 shows the
variance of the frequency over time. This distribution of the
frequency content spreads the spectral density over a wider
bandwidth, resulting in lower peak emission levels.
MODE SELECTION
The ADP2126/ADP2127 have two modes of operation (PWM
mode and auto mode), determined by the state of the MODE pin.
Pull the MODE pin high to force the converter to operate in
PWM mode, regardless of the output current. Otherwise, set
MODE low to put the converter into auto mode and allow the
converter to automatically transition from PWM mode to the
power-saving PFM mode at light load currents. Do not leave
this pin floating.
Pulse-Width Modulation (PWM) Mode
The PWM mode forces the part to maintain a fixed frequency
of 6 MHz (maximum) under all load conditions. The ADP2126/
ADP2127 use a proprietary, hybrid voltage-mode control scheme
to control the duty cycle under all load current and line voltage
variations. This control scheme provides excellent stability,
transient response, and output regulation. PWM mode results
in lower efficiencies at light load currents.
Auto Mode (PFM and PWM Switching)
Auto mode is a power-saving feature that enables the converter
to switch between PWM and PFM in response to the output
load. Auto mode is enabled when the MODE pin is pulled low.
In auto mode, the ADP2126/ADP2127 operate in PFM mode for
light load currents and switch to PWM mode for medium and
heavy load currents.
Pulse Frequency Modulation (PFM) Mode
When the converter is operating under light load conditions,
the effective switching frequency and supply current are decreased
and varied using PFM to regulate the output voltage. This results in
improved efficiencies and lower quiescent currents. In PFM mode,
the converter only switches when necessary to keep the output
voltage within the PFM limits set by an internal comparator.
Switching stops when the upper limit is reached and resumes
when the lower limit is reached.
When the upper level is reached, the output stage and most
control circuitry turn off to reduce the quiescent current. During
this stage, the output capacitor supplies the current to the load.
As the output capacitor discharges and the output voltage reaches
the lower PFM comparator threshold, switching resumes and the
process repeats.
Mode Transition
When the MODE pin is low, the converter switches between
PFM and PWM modes automatically to maintain optimal
transient response and efficiency. The mode transition point
depends on the input voltage. Hysteresis exists in the transition
point to prevent instability and decreased efficiencies that could
result if the converter were able to oscillate between PFM and
PWM for a fixed input voltage and load current. See Figure 9 for
the typical PFM and PWM mode boundaries of the
ADP2126/ADP2127.
A switch from PFM to PWM occurs when the output voltage dips
below the nominal value of the output voltage option. Switching
to PWM allows the converter to maintain efficiency and supply
a larger current to the load. The output voltage in PFM mode is
slightly higher to keep the ADP2126/ADP2127 from oscillating
between modes, ensuring stable operation.
The switch from PWM to PFM occurs when the output current
is below the PFM threshold for multiple consecutive switching
cycles. Switching to PFM allows the converter to save power by
supplying the lighter load current with fewer switching cycles.
INTERNAL CONTROL FEATURES
Synchronous Rectification
In addition to the P-channel MOSFET switch, the ADP2126/
ADP2127 include an N-channel MOSFET switch to build the
synchronous rectifier. The synchronous rectifier improves
efficiency, especially for small load currents, and reduces cost
and board space by eliminating the need for an external rectifier.
Soft Start
To prevent excessive input inrush current at startup, the ADP2126/
ADP2127 operate with an internal soft start. When EXTCLK
begins to oscillate, or when the part recovers from a fault (UVLO,
TSD, or SCP), a soft start timer begins. During this time, the
peak current limit is gradually increased to its maximum. The
output voltage increases in stages to ensure that the converter is
able to start up effectively and in proper sequence. After the soft
start period expires, the peak PMOS switch current limit remains
at 1 A (typical), and the part begins normal operation.
Data Sheet ADP2126/ADP2127
Rev. B | Page 13 of 20
reshold, EXTCLK must be powered with the logic high signal
ed
whe
d Figure 3 for the timing specifications and
PROTECTION FEATURES
Overcurrent Protection
To ensure that excessively high currents do not damage the
MOSFET switches, the ADP2126/ADP2127 incorporate cycle-by-
cycle overcurrent protection. This function is accomplished by
monitoring the instantaneous peak current on the power PMOS
switch. If this current exceeds the PMOS switch current limit
(1 A typical), then the PMOS is immediately turned off. This
minimizes the potential for damage to power components during
certain faults and transient events.
Output Short-Circuit Protection (SCP)
If the output voltage is shorted to GND, a standard dc-to-dc
controller delivers maximum power into that short. This may
result in a potentially catastrophic failure. To prevent this, the
ADP2126/ADP2127 sense when the output voltage is below the
SCP threshold (typically 0.52 V). At this point, the controller
turns off for approximately 450 µs and then automatically initiates a
soft start sequence. This cycle repeats until the short is removed
or the part is disabled. Figure 16 shows the operating behavior of
the ADP2126/ADP2127 during a short-circuit fault. The SCP
dramatically reduces the power delivered into the short circuit,
yet still allows the converter to recover when the fault is removed.
Thermal Shutdown (TSD) Protection
The ADP2126/ADP2127 also include TSD protection when the
part is in PWM mode only. If the die temperature exceeds 146°C
(typical), the TSD protection activates and turns off both MOSFET
power devices. They remain off until the die temperature falls to
133°C (typical), at which point the regulator restarts.
Undervoltage Lockout (UVLO)
If the input voltage drops below the UVLO falling threshold, the
ADP2126/ADP2127 automatically turn off the power switches and
enter a low power consumption mode. This prevents potentially
erratic operation at low input voltages. The parts remain in this
state until the input voltage rises above the UVLO rising threshold.
The UVLO levels have approximately 100 mV of hysteresis to
ensure glitch-free startup.
For the logic high enable option, during startup and UVLO
recovery after the input voltage drops below the UVLO falling
after VIN. If VIN dips below the UVLO falling threshold and
EXTCLK is powered before VIN with a logic high signal, the
UVLO does not become active. If VIN and EXTCLK are
powered from the same source, an RC circuit (see Figure 1)
is recommended to ensure that the ADP2126/ADP2127 are
powered correctly. Rτ and Cτ should be selected so that the
RC time constant (τ) is greater than the 200 µs minimum
specification for VIN high to EXTCLK on (t1). τ is calculat
using the following equation:
τ = Rτ × Cτ
re τ ≥ t1.
See Table 1 an
diagrams.
09658-036
A2
B2
C2
VIN
EXTCLK
GND
OFF
ON
V
IN
C
IN
()
R
C
Figure 29. Recommended Logic Enable Startup Ci it
TIMING CO
6/ADP2127 enter shutdown mode after the
ereby triggering UVLO, the ADP2126/
t
al
rcu
NSTRAINTS
Shutdown Time
When the ADP212
EXTCLK signal is removed, the ADP2126/ADP2127 must remain
in shutdown mode for a minimum of 1400 µs, if no load is applied,
before the EXTCLK signal can be reapplied. This allows all internal
nodes to discharge to an off state.
Power-Off Time
When VIN drops, th
ADP2127 have a minimum power-off time (t7) of 500 µs tha
must elapse before VIN can be reapplied. This allows all intern
nodes to discharge enough power so that all internal devices are
in an off state.
t
7
V
IN
× 10%
09658-030
Figure 30. Power-Off Time
th
ADP2126/ADP2127 Data Sheet
Rev. B | Page 14 of 20
APPLICATIONS INFORMATION
The low-profile ADP2126/ADP2127 are compatible with chip
inductors and multilayer ceramic capacitors that are ideal for
use in portable applications due to their small footprint and low
height. The recommended components for low-profile applications
may change as this technology advances. Table 5 and Table 6 list
compatible inductors and capacitors.
This section describes the selection of external components.
The component value ranges are limited to optimize efficiency
and transient performance while maintaining stability over the
full operating range.
INDUCTOR SELECTION
The high switching frequency of the ADP2126/ADP2127 allows for
minimal output voltage ripple, even with small inductors. Inductor
sizing is a trade-off between efficiency and transient response.
A small value inductor leads to a larger inductor current ripple,
which provides excellent transient response but degrades efficiency.
A small footprint and low height chip inductor can be used for an
overall smaller solution size but has a higher dc resistance (DCR)
value and lower current rating that can degrade performance.
Shielded ferrite core inductors are advantageous for their low core
losses and low electromagnetic interference (EMI). For optimal
performance and stability, use inductor values between 1.5 µH
and 0.5 µH. Recommended inductors are shown in Table 5.
The inductor peak-to-peak current ripple, IL, is calculated from
(
)
SW
IN
OUT
IN
OUT
LfLV
VVV
I××
−×
=Δ (2)
where:
fSW is the switching frequency.
L is the inductor value.
It is important that the minimum dc current rating of the inductor
be greater than the peak inductor current (IPK) in the application.
IPK is calculated from
IPK = ILOAD(MAX) + IL/2 (3)
The dc current rating of the inductor should be greater than the
calculated IPK to prevent core saturation.
INPUT CAPACITOR SELECTION
The input capacitor must be rated to support the maximum input
operating voltage. Higher value input capacitors reduce the input
voltage ripple caused by the switch currents on the VIN pin.
Maximum rms input current for the application is calculated using
()
IN
OUT
IN
OUT
MAXLOADCINMAXRMS V
VVV
II −×
×= )()(_ (4)
Place the input capacitor as close as possible to the VIN pin to
minimize supply noise.
In principle, different types of capacitors can be considered, but
for battery-powered applications, the best choice is the multilayer
ceramic capacitor, due to its small size, low equivalent series
resistance (ESR), and low equivalent series inductance (ESL).
It is recommended that the VIN pin be bypassed with at least a
2.2 µF input capacitor. For a 0.22 mm height solution using the
ADP2127, at least 2 × 1.0 µF capacitors will be necessary on the
input. The input capacitor can be increased without any limit for
better input voltage filtering. X5R or X7R dielectrics with a voltage
rating of 6.3 V or higher are recommended.
Table 5. Inductor Selection
Manufacturer Series Inductance (μH) DCR (mΩ) (Typ)
Current
Rating (mA) Size (L × W × H) (mm) Package
Murata LQM18PN1R0-A52 1.0 520 500 1.6 × 0.8 × 0.33 0603
Taiyo Yuden CKP1608S1R5M 1.5 420 500 1.6 × 0.8 × 0.33 0603
Table 6. Input/Output Capacitor Selection
Manufacturer Part Number Capacitance (μF) Voltage Rating (V)
Temperature
Coefficient Size (L × W × H) (mm) Package
Murata GRM153R60J225ME95 2.2 ± 20% 6.3 X5R 1.0 × 0.5 × 0.33 0402
GRM153R60G225M 2.2 ± 20% 4 X5R 1.0 × 0.5 × 0.33 0402
Taiyo Yuden JMK105BJ225MP 2.2 ± 20% 6.3 X5R 1.0 × 0.5 × 0.33 0402
AMK105BJ225MP 2.2 ± 20% 4 X5R 1.0 × 0.5 × 0.33 0402
AMK105BJ105MC 1.0 ± 20% 4 X5R 1.0 × 0.5 × 0.22 0402
ADC105BJ105ME 1.0 ± 20% 4 X5R 1.0 × 0.5 × 0.20 0402
JMK105BJ474KC 0.47 ± 10% 6.3 X5R 1.0 × 0.5 × 0.22 0402
JMK105BJ474MC 0.47 ± 20% 6.3 X5R 1.0 × 0.5 × 0.22 0402
TDK CGB2A3X5R0J105K 1.0 ± 10% 6.3 X5R 1.0 × 0.5 × 0.33 0402
CGB2A3X5R0J105M 1.0 ± 20% 6.3 X5R 1.0 × 0.5 × 0.33 0402
Data Sheet ADP2126/ADP2127
Rev. B | Page 15 of 20
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the converter. For a given loop
crossover frequency (the frequency at which the loop gain drops
to 0 dB), the maximum voltage transient excursion (overshoot)
is inversely proportional to the value of the output capacitor.
When choosing output capacitors, it is important to account for
the loss of capacitance due to output voltage dc bias. This may
result in using a capacitor with a higher rated voltage to achieve
the desired capacitance value. Additionally, if ceramic output
capacitors are used, the capacitor’s rms ripple current rating
should always meet or exceed the application requirements.
The rms ripple current is calculated from
()
(
)
)(
)(
32
1
MAXIN
SW
OUT
MAXIN
OUT
COUTRMS VfL
VVV
I××
−×
×= (5)
At nominal load currents, the converter operates in forced PWM
mode, and the overall output voltage ripple is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage ripple
caused by charging and discharging the output capacitor.
VOUT = IL × (ESR + 1/(8 × COUT × fSW)) (6)
The largest voltage ripple occurs at the highest input voltage.
The ADP2126/ADP2127 are designed to operate with one
small 2.2 µF capacitor. For a 0.22 mm height solution using the
ADP2127, at least 2 × 1.0 µF capacitors will be necessary on the
output. X5R or X7R dielectrics that have low ESR, low ESL, and
a voltage rating of 4 V or higher are recommended. These low
ESR components help the ADP2126/ADP2127 meet tight
output voltage ripple specifications.
THERMAL CONSIDERATIONS
The operating junction temperature (TJ) of the device is
dependent on the ambient operating temperature (TA) of the
application, the power dissipation of the ADP2126/ADP2127
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). The operating junction temperature (TJ) is
calculated from
TJ = TA + (PD × θJA) (7)
where θJA is 105°C/W, as provided in Table 3.
The ADP2126/ADP2127 may be damaged when the operating
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits.
• In applications with high PD and poor PCB thermal
resistance, the maximum ambient temperature may
need to be derated.
• In applications with moderate PD and good PCB thermal
resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is
within specification limits.
The power dissipation (PD) of the ADP2126/ADP2127 is only a
portion of the power loss of the overall application. For a given
application with known operating conditions, the application
power loss is calculated by combining the following equations
for power loss (PLOSS) and efficiency (η):
PLOSS = PIN − POUT (8)
100×=
IN
OUT
P
P
η
(9)
The resulting equation uses the output power and the efficiency
to determine the PLOSS.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−= 1
100
η
OUT
LOSS PP (10)
The power loss calculated using this approach is the combined
loss of the ADP2126/ADP2127 device (PD), the inductor (PL),
input capacitor (PCIN), and the output capacitor (PCOUT), as
shown in the following equation:
PLOSS = PD + PL + PCIN + PCOUT (11)
The power loss for the inductor, input capacitor, and output
capacitor is calculated using
PL = IRMS2 × DCR (12)
CIN
RMS
CIN ESR
I
P×
⎟
⎠
⎞
⎜
⎝
⎛
=
2
2 (13)
PCOUT = (∆IOUT)2 × ESRCOUT (14)
If multilayer chip capacitors with low ESR are used, the power
loss in the input and output capacitors is negligible and
PD + PL >> PCIN + PCOUT (15)
PLOSS ≈ PD + PL (16)
The final equation for calculating PD can be used in Equation 7 to
ensure that the operating junction temperature is not exceeded.
L
OUT
L
LOSS
DPPPPP −
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−≈−≈ 1
100
η
(17)
ADP2126/ADP2127 Data Sheet
Rev. B | Page 16 of 20
PCB LAYOUT GUIDELINES
09658-031
Figure 31. ADP2126/ADP2127 Recommended Top Layer Layout
09658-032
Figure 32. ADP2126/ADP2127 Recommended Bottom Layer Layout
For high efficiency, good regulation, and stability, a well-designed
and manufactured PCB is required.
Use the following guidelines when designing PCBs:
• Keep the low ESR input capacitor, CIN, close to VIN
and GND.
• Keep high current traces as short and as wide as possible.
• Avoid routing high impedance traces near any node
connected to SW or near the inductor to prevent
radiated noise injection.
• Keep the low ESR output capacitor, COUT, close to the FB
and GND pins of the ADP2126/ADP2127. Long trace
lengths from the part to the output capacitor add series
inductance that may cause instability or increased ripple.
To ensure package reliability, consider the following guidelines
when designing the footprint for the ADP2126/ADP2127. The
BUMPED_CHIP device footprint must ultimately be determined
according to application and customer specific reliability
requirements, PCB fabrication quality, and PCB assembly
capabilities.
• The Cu pad on the PCB for each solder bump should be
80% to 100% of the width of the solder bump. A smaller
pad opening favors solder joint reliability (SJR) performance,
whereas a larger pad opening favors drop test performance.
The maximum pad size, including tolerance, should not
exceed 180 µm.
• Electroplated nickel, immersion gold (ENIG) and organic
solderability preservative (OSP) were used for internal
reliability testing and are recommended.
• Nonsolder mask defined (NSMD) Cu pads are recommended
for the BUMPED_CHIP package.
• The solder mask opening should be approximately 100 µm
larger than the pad opening.
• The trace width should be less than two-thirds the size of
the pad opening.
• The routing of traces from the Cu pads should be symmetrical
in X and Y directions. Symmetrical routing of the traces
prevents part rotation due to uneven solder wetting/surface
tension forces.
• Stencil design is important for proper transfer of paste onto
the Cu pads. Area ratio (AR), the relationship between the
surface area of the stencil aperture and the inside surface
area of the aperture walls, is critically important. Stencil
thickness has the greatest impact on this ratio. AR values
from 0.66 to 0.8 provide the best paste transfer efficiency
and repeatability. The AR is calculated from
Aw
Ap
AR =
where:
Ap is the area of the aperture opening.
Aw is the wall area.
Data Sheet ADP2126/ADP2127
Rev. B | Page 17 of 20
OUTLINE DIMENSIONS
0.40 REF
0.80
REF
1.340
1.300
1.260
0.940
0.900
0.860
0.40
REF
A
12
B
C
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
BALL A1
IDENTIFIER
05-10-2010-A
0.225 TYP
0.09 TYP
0.330
0.315
0.300
END VIEW
0.190
0.170
0.150
COPLANARITY
0.05 NOM
SEATING
PLANE
Figure 33. 6-Ball Bumped Bare Die Sales [BUMPED_CHIP]
(CD-6-4)
Dimensions shown in millimeters
04-25-2011-A
0.40 REF
0.80
REF
1.340
1.300
1.260
0.940
0.900
0.860
SEATING
PLANE
0.200
0.175
0.150
A
12
B
C
TOP VIEW
(PAD SIDE DOWN)
BOTTOM VIEW
(PAD SIDE UP)
0.17
DIA.
DETAIL A
BARE Cu FIDUCIAL
0.15 DIA.
DETAIL A
ROTATED 90° CCW
0.008
MIN
0.40
PAD PITCH
0.13
DIA.
Figure 34. 6-Pad Embedded Wafer Level Package [EWLP]
(CN-6-1)
Dimensions shown in millimeters
DIRECTION OF FEED
THE ADP2126 HAS AN A1 BALL IDENTIFIER THAT IS VISIBLE
ON THE TOP OF THE PART.
THE ADP2127 HAS NO VISIBLE MARKING ON THE TOP,
BUT THE A1 PIN LOCATION IS THE SAME.
1
A
B
C
2
09658-035
Figure 35. Tape and Reel Orientation for the ADP2126/ADP2127
ADP2126/ADP2127 Data Sheet
Rev. B | Page 18 of 20
ORDERING GUIDE
Model1
Output
Voltage
EXTCLK
Enable Type
Temperature
Range Package Description
Package
Option2 Branding3
ADP2126ACDZ-1.20R7 1.20 V Clock and logic −40°C to +85°C 6-Ball Bumped Bare Die Sales [BUMPED_CHIP] CD-6-4 LHY
ADP2127ACNZ-1.20R7 1.20 V Clock and logic −40°C to +85°C 6-Pad Embedded Wafer Level [EWLP] CN-6-1
ADP2127ACNZ1.260R7 1.26 V Clock only −40°C to +85°C 6-Pad Embedded Wafer Level [EWLP] CN-6-1
ADP2126-1.2-EVALZ 1.20 V Clock and logic Evaluation Board for ADP2126
1 Z = RoHS Compliant Part.
2 These package options are halide free.`
3 The ADP2127 does not have a Pin 1 indicator or a branding code. The bare Cu fiducial on the pad side can be used for device orientation.
Data Sheet ADP2126/ADP2127
Rev. B | Page 19 of 20
NOTES
ADP2126/ADP2127 Data Sheet
Rev. B | Page 20 of 20
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09658-0-3/12(B)
