M48T35AY-70PC1 - STMicroelectronics, Inc.

1/25April 2004

M48T35AY

M48T35AV

5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKE EPER® SRAM

FEAT URES SUMMARY

■INTEGRATED, ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL

CONTR OL CIRCUIT AND BATTERY

■BYTEWI D E™ RAM-LI KE CLO CK AC C ESS

■BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES, AND SECONDS

■BATTERY LOW FLAG (BOK)

■FREQUENCY TEST OUTPUT FOR REAL

TIME CLOCK

■AUTOMATIC POWER-FAIL CHIP

DESELECT AND WRITE PROTECTION

■WRITE PRO TECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48T 35A Y : VCC = 4.5 to 5.5V

4.2V ≤ VPFD ≤ 4.5V

– M48T 35A V : VCC = 3.0 to 3.6V

2.7V ≤ VPFD ≤ 3.0V

■SELF-CONTAINED BATTERY AND

CRYSTA L IN THE CAPHAT™ DIP

PACKAGE

■SOIC PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAPHAT®

HOUSING CONTAINING THE BATTERY

AND CRYSTAL

■SNAPHAT® HOUSING (BATTERY AND

CRYSTAL) IS REPLACEABLE

■PIN AND FUNCTION COMPATIBLE WITH

JEDEC STANDARD 32Kb x8 SRAMs

Figure 1. 28-pin, PCDIP CAPHAT™ Package

Figu re 2. 28- pi n S OI C Package

PCDIP28 (PC)

Battery/Crystal

CAPHAT

SNAPHAT (SH)

Battery/Crystal

SOH28 (MH)

M48T35AY, M48T35AV

2/25

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 28-pin, PCDIP CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. SOIC Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. RE AD Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. WRITE Enable Controlle d, WRITE Mode AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 9. Chip Enable Controlled, WRITE Mode AC Wav eforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Figure 10.Checking the BOK Flag Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13.Supply Voltage Protect ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

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M48T35AY, M48T35AV

Figure 15.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PAC KAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16.PCDIP28 – 28-pin Plastic DIP, batte ry CAPHAT™, Pa ckage Outline . . . . . . . . . . . . . . 19

Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data. . . . . . . 19

Figure 17.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 20

Table 13. SOH28 – 28-lead Plastic Small Outline, 4- socket battery SNAPHAT, Pack. Mech. Data20

Figure 18.SH – 4-pin SNAPHA T Housing for 48mAh Ba ttery & Crystal, Package Outline . . . . . . . 21

Table 14. SH – 4-pin SNAP HA T Housing for 48mAh Battery & Crystal, Package Mech. Data . . . . 21

Figure 19.SH – 4-pin SNAPHA T Housing for 120mAh B attery & Crystal, Pack age Ou tline . . . . . . 22

Table 15. SH – 4-pin SNAP HA T Housing for 120mAh Battery & Crystal, Package Mech. Data . . . 22

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

M48T35AY, M48T35AV

4/25

S UM MARY DE SCRIPTIO N

Th e M48 T35AY/ V TI MEKEEPE R® RAM is a 32Kb

x 8 non-volatile static RAM and real time clock.

The monolithic chip is available in two special

packages to provide a highly integrated battery

backed-up me mory and real time clock solution.

The M48T35AY/V is a non-volatile pin and func-

tion equivalent to any JEDEC standard 32Kb x 8

SRAM. It also easily fits into many ROM, EPROM,

and EEPROM sockets, providing the non-volatil ity

of PROMs without any requirement for special

WRITE timing or limitations on the number of

WRITEs that can be performed.

The 28-pin, 600mil DIP CAPHAT™ houses the

M48T35AY/V silicon with a quartz crystal and a

long-life lithium button cell in a single package.

The 28-pin, 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT® housing con-

taining the battery and crysta l. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process. Inser-

tion of the SNAPHAT housing after reflow pre-

vents pote ntial b attery and crystal dam age due to

the high temperatures required for device s urface-

mounting. The SNAPHAT housing i s keyed to pre-

vent reverse insertion.

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form.

For the 28-lead SOIC, the battery/crystal package

(e.g. SNAPHAT) part number is “M4T28-BR12SH”

(see Table 17., page 23).

Figure 3. Logic Diagram Table 1. Signal Names

AI02797B

A0-A14

DQ0-DQ7

VCC

M48T35AY

M48T35AV

VSS

A0-A14 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

EChip Enable

GOutput Enable

WWRITE Enable

VCC Supply Voltage

VSS Ground

5/25

M48T35AY, M48T35AV

Figu re 4. DIP C on ne ction s Figu r e 5. S OI C Co nn e ct io ns

Figu re 6. Blo ck Diagram

DQ0

A13

A10

DQ7

A11

DQ5DQ1

DQ2 DQ3VSS DQ4

DQ6

A12

A14 VCC

AI02798B

14 16

M48T35AY

M48T35AV

AI02799

DQ0

A13

A10

DQ7

A11

DQ5DQ1

DQ2 DQ3VSS DQ4

DQ6

A12

A14 VCC

M48T35AY

M48T35AV

AI01623

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8 x 8 BiPORT

SRAM ARRAY

32,760 x 8

SRAM ARRAY

A0-A14

DQ0-DQ7

POWER

M48T35AY, M48T35AV

6/25

OPERATION MODES

As Figure 6., page 5 shows, the static memory ar-

ray and the quartz c ontrolled clock oscillator of the

M48T35AY/V are integrated on one silicon chip.

The two circuits are interconnected at the upper

eight memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with

addresses 7FF8h-7FFFh.

The clock locations contain the year, month, date,

day, hour, minute, and second in 24 hour BCD for-

mat. Corrections f or 28, 29 (leap yea r - valid unt il

2100), 30, and 31 day months are made automat-

ically. Byte 7FF8h is the clock control register. This

byte controls user access to the clock inform ation

and also stores the clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT™ READ/WRITE memory

cells. The M48T35AY/V includes a clock control

circuit which updates the clock bytes with current

information once per second. The information can

be accessed by the user in the same manner as

any other location in the static memory array.

The M48T35A Y/V also has its own Power-fail De-

tect circuit. The control circuitry constantly moni-

tors the single 3V supply for an out of tolerance

condition. When VCC is out of toler ance, the circuit

write protects the SRAM, providing a high degree

of data sec urity in t he midst of unpredictable sys-

tem operation brought on by low VCC. As VCC falls

below the Battery Back-up Switchover Voltage

(VSO), the control circuitry connects the battery

which maintains data and clock operation until val-

id power returns.

Table 2. Operating Modes

No te: X = V IH or VIL; VSO = Battery Bac k-up Switchover Volta ge.

1. See Tabl e 11., p age 18 for details.

Mode VCC E G W DQ0-DQ7 Power

Deselect

4.5 to 5.5V

3.0 to 3.6V

VIH X X High Z Standby

WRITE VIL XVIL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High Z Active

Deselect VSO to VPFD (min)(1) X X X High Z CMOS Standby

Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode

7/25

M48T35AY, M48T35AV

READ Mode

The M48T35AY/V is in the READ Mode whenever

W (WRITE Enable) is h igh and E (Chip Enable) is

low. The unique address specified by the 15 ad-

dress inputs defines which one of the 32,768 bytes

of dat a is to be acce ssed . Vali d data w ill be av ail-

able at the Data I/O pins within Address Access

time (tAVQV) after the last address input signal is

stable, providing that the E and G access times

are also satisfied.

If the E and G access times are not met, valid data

will be av a i la ble afte r the la t te r of the C hip Enable

Acce ss time (tELQV) or Output Enable Access time

(tGLQV).

The state of the eight three-s tate Da ta I/O si gnals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active,

out put dat a will re main valid for Ou tput D ata H old

time (tAXQX) but will go indeterminate until the next

Address A ccess.

Figure 7. READ Mode AC Waveforms

No te: WRI T E Enable (W ) = Hig h.

Table 3. RE AD M ode AC Characteristic s

Note: 1. Vali d for Ambi ent Op erat in g T em pera ture : TA = 0 to 70°C or –40 to 85°C; V CC = 4.5 to 5.5V o r 3.0 t o 3.6V (except where noted).

2. CL = 5pF.

Symbol Parameter(1)

M48T35AY M48T35AV

Unit–70 –100

MinMaxMinMax

tAVAV READ Cycle Time 70 100 ns

tAVQV Address Valid to Output Valid 70 100 ns

tELQV Chip Enable Low to Output Valid 70 100 ns

tGLQV Output Enable Low to Output Valid 35 50 ns

tELQX(2) Chip Enable Low to Output Transition 5 10 ns

tGLQX(2) Output Enable Low to Output Transition 5 5 ns

tEHQZ(2) Chip Enable High to Output Hi-Z 25 50 ns

tGHQZ(2) Output Enable High to Output Hi-Z 25 40 ns

tAXQX Address Transition to Output Transition 10 10 ns

AI00925

tAVAV

tAVQV tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A14

DQ0-DQ7

VALID

M48T35AY, M48T35AV

8/25

WRITE Mode

The M48T35AY/V is in the WRITE Mode whenev-

er W and E are low. The start of a WRITE is refer-

enced from the latter occurring falling edge of W or

E. A WRITE is terminated by the earlier rising

edge of W or E. The addresses must be held valid

throughout the cycle. E or W must return hi gh for

a minimum of tEHAX from Chip Enable or tWHAX

from WRITE Enable prior to the initiation of anoth-

er READ or WRITE cycle. Data-in must be valid tD-

VWH prior to the end of WRITE and remain valid for

tWHDX afterward. G should be kept high during

WRITE cyc les to avoid bus contention; however, if

the output bus has been a ctivated by a low on E

and G, a low on W will disable the outputs tWLQZ

after W falls.

Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveform

Figure 9. Chip Enable Controlled, WRITE Mode AC Wavefor m s

AI00926

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A14

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI00927

tAVAV

tEHAX

tDVEH

A0-A14

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

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M48T35AY, M48T35AV

Table 4. WRITE Mode AC Characteristics

Note: 1. Vali d for Ambi ent Op erat in g T em pera ture : TA = 0 to 70°C or –40 to 85°C; V CC = 4.5 to 5.5V o r 3.0 t o 3.6V (except where noted).

2. CL = 5pF.

3. If E goes low simultaneously with W going low, the ou tputs remain in the hi gh i m peda nce stat e.

Symbol Parameter(1)

M48T35AY M48T35AV

Unit–70 –100

Min Max Min Max

tAVAV WRITE Cycle Time 70 100 ns

tAVWL Address Valid to WRITE Enable Low 0 0 ns

tAVEL Address Valid to Chip Enable Low 0 0 ns

tWLWH WRITE Enable Pulse Width 50 80 ns

tELEH Chip Enable Low to Chip Enable High 55 80 ns

tWHAX WRITE Enable High to Address Transition 0 10 ns

tEHAX Chip Enable High to Address Transition 0 10 ns

tDVWH Input Valid to WRITE Enable High 30 50 ns

tDVEH Input Valid to Chip Enable High 30 50 ns

tWHDX WRITE Enable High to Input Transition 5 5 ns

tEHDX Chip Enable High to Input Transition 5 5 ns

tWLQZ(2,3) WRITE Enable Low to Output Hi-Z 25 50 ns

tAVWH Address Valid to WRITE Enable High 60 80 ns

tAVEH Address Valid to Chip Enable High 60 80 ns

tWHQX(2,3) WRITE Enable High to Output Transition 5 10 ns

M48T35AY, M48T35AV

10/25

Data Retention Mode

With valid VCC applied, the M48T35AY/V operates

as a conventional BYTEWIDE™ static RAM.

Should the supply voltage decay, the RAM will au-

tomatically power-fail de select, write protec ting it-

self when VCC falls within the VPFD (max), VPFD

(min) window (see Figure 15, Table 10, and Table

11., page 18). All outputs become high imped-

ance, and all inputs are trea ted as “don't care.”

Note: A power failure during a WRITE cycle may

corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's con-

tent. At voltages below VPFD (min), the user can be

assured the memory will be in a write protected

state, provided t he VCC fall time is not less than t F.

The M48 T35AY /V m ay res pond to transie nt noise

spikes on VCC that reach into the deselect window

during the time the device is sampling VCC. There-

fore, decoupling of the power supply lines is rec-

ommended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T35AY/V

for an accumulated period of at least 7 years when

VCC is less than VSO. As system power returns

and VCC rises above VSO, the battery is discon-

nected and the power supply is s witched to exter-

nal VCC. Write protection continues until VCC

reaches VPFD (min) plus trec (min). E should be

kept high as VCC rises past VPFD (min) t o prevent

inadvertent WRITE cycles prior t o processor stabi-

lization. Normal RAM operation can resume trec af-

ter VCC exceeds VPFD (max).

Also, as VCC rises, the battery voltage is checked.

If the voltage is less than approximately 2.5V, an

internal Battery Not OK (BOK) fla g will be set. The

BOK flag can be checked after power up. If the

BOK flag is set, the first W RITE attempted will be

blocked. The fl ag is automatically cleared after the

first WRITE, and normal RAM operation resumes.

Figure 10 illustrates how a BOK check routine

could be structured.

For more information on Battery Storage Life refer

to the App lication Note AN101 2.

Figu re 10 . Checki ng t he B OK Flag Status

READ DATA

AT ANY ADDRESS

AI00607

IS DATA

COMPLEMENT

OF FIRST

READ?

(BATTERY OK)

POWER-UP

YES

WRITE DATA

COMPLEMENT BACK

TO SAME ADDRESS

READ DATA

AT SAME

ADDRESS AGAIN

NOTIFY SYSTEM

OF LOW BATTERY

(DATA MAY BE

CORRUPTED)

WRITE ORIGINAL

DATA BACK TO

SAME ADDRESS

(BATTERY LOW)

CONTINUE

11/25

M48T35AY, M48T35AV

CL OCK OPERA T IONS

Reading the Clock

Updates to the T IMEKEEPER® registers (see Ta-

ble 5) should be halted before clock data is read to

prevent reading da ta in transition . The Bi PO RT™

TIMEKEEPER cells in the RAM array are only

data registers and not the actual clock counters,

so updating the registers can be halted without

distu rbing the clock itself.

Updating is halted when a '1' is written to the

READ Bit, D6 in the Control Register 7FF8h. As

long as a '1' remains in that position, updating is

halted.

After a halt is issued, the registers reflect the

count; that is, the day, date, and the time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registe rs are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating is within a second af ter the bit

is re se t to a '0.'

Setting the Clock

Bit D7 of the Control Register 7FF8h is the WRITE

Bit. Setting the WRITE Bit to a '1,' like the READ

Bit, halts updates to the TIMEKEEPER® registers .

The user can then load them with the correct day,

date, and time data in 24 hour BCD format (see

Table 5). Resetting the WRITE Bit to a '0' then

transfers the values of all time registers 7FF9h-

7FFFh to the actual TIMEKEEPER counters and

allows normal operation to resume. The FT Bit and

the bits marked as '0' in Table 5 must be written to

'0' t o all ow fo r no rmal TIMEKE EPER and RAM op-

eration. After the WRITE Bit is reset, the next clock

update will oc cu r within one second.

See the Application Note AN923, “TIMEKEEPER®

Rolling Into the 21st Century” for information on

Century Rollover.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

Bit is the MSB of the seconds register. Setting it to

a '1' stops the oscillator. The M48T35AY/V is

shipped from STMicroelectronics with the STOP

Bit set t o a '1.' When reset to a '0,' t he M48T35AY/

V oscillator starts within 1 second.

Table 5. Register Map

Keys : S = SIG N Bit

FT = FREQUENCY TEST Bit (Mus t be set to '0 ' up on power

for normal operation)

R = READ Bit

W = WRI T E Bi t

ST = STOP Bit

0 = Must be set to '0'

CE B = C entury E nable Bi t

CB = Century Bi t

Note: W hen CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (depe ndent upon the initial value set).

When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB.

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

7FFFh 10 Years Year Year 00-99

7FFEh 0 0 0 10 M. Month Month 01-12

7FFDh 0 0 10 Date Date Date 01-31

7FFCh 0 FT CEB CB 0 Day Century/Day 00-01/01-07

7FFBh 0 0 10 Hours Hours Hours 00-23

7FFAh 0 10 Minutes Minutes Minutes 00-59

7FF9h ST 10 Seconds Seconds Seconds 00-59

7FF8h W R S Calibration Control

M48T35AY, M48T35AV

12/25

Ca libra t ing t he Clock

The M48T35AY/ V is driven by a quartz-controlled

oscillator with a nominal frequency of 32,768 Hz.

The devices are tested not to exceed 35 ppm

(parts per million) oscillator frequency error at

25°C, which equates to about ±1.53 minutes per

month. With the calibration bits properly set, the

accuracy of each M48T35AY/V improves to better

than +1/ –2 ppm at 25°C.

The oscillation rate of any crystal changes with

temperature (see Figure 11., page 13). Most clock

chips compensate for crystal frequency and tem-

perature shift error with c umbersome “trim” capac-

itors. The M48T35AY/V design, however, employs

periodic count er corre ction . The c alibration circuit

adds or subtracts counts from the osci llator divider

circuit at the divide by 256 stage, as shown in Fig-

ure 12., page 13. T he num ber of time s pulses are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five calibration bits found in

the Control Register. Adding counts speeds the

clock up, subtracting counts slows t he cloc k down.

The Calibration Byte occupies the five lower order

bits (D4-D0) i n the Control Register 7FF8h. These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is the Sign Bit; '1' in-

dicates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 6 2 m inutes in the cycle m ay , onc e

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minute s in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibration register. Ass um ing that

the oscillator is in fact running at exactly 32,768

Hz, each of the 31 increments in the Calibration

Byte would represent +10. 7 or –5.35 seconds per

month which c orresponds to a total range of +5.5

or –2.75 minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T35AY/V may re-

quire. The first involves simply setting the clock,

letting it run for a month and comparing it to a

known accurate reference (lik e WWV broadcasts).

While that may seem crude, it allows the designer

to give the end user the ability to calibrate his clock

as his environment may require, even after the fi-

nal product is packaged in a non-user serviceable

enclosure.

The second approach is better suited to a manu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) B it, the seventh-most significant bit i n the Day

ister is a '0' (Oscillator Running), DQ0 will toggle at

512 Hz during a READ of the Seconds Register.

Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of 512.01024

Hz would indicate a +20 ppm oscillator frequency

error, requiring a –10 (WR001010) to be loaded

into the Calibration Byte for c orrection.

Note: Setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The FT Bit MUST be reset to '0' for normal clock

operations to resum e. The FT Bit is automatically

Reset on power-down.

For more information on calibration, see Applica-

ti on Not e AN934, “TIMEKEEPER® Calibration.”

Century Bit

Bit D5 and D4 of Clock Register 7FFCh contain

the CENTURY ENABLE Bit (CEB) and the CEN-

TURY Bit (CB). Setting CEB to a '1' will cause CB

to toggle, either from a '0' to '1' or from '1' to '0' at

the turn of the century (depending upon its initial

state). If CEB is set to a '0,' CB will not toggle.

Note: The WRITE Bit must be set in order to write

to the CENTURY Bit.

13/25

M48T35AY, M48T35AV

Figure 11. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 12 . Cl ock C al ib r at i on

AI02124

-80

-60

-100

-40

-20

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

∆F= -0.038 (T - T

)

± 10%

Fppm

= 25 °C

ppm

°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48T35AY, M48T35AV

14/25

VCC Noise And Negative Go ing Transients

ICC transients, including those produced by output

switching, can produce voltage fluctuations, re-

sulting in spikes on the VCC bus. These transients

can be reduced if capacitors are used to store en-

ergy which stabilizes the VCC bus. The energy

stored in the bypass capacitors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A bypass ca-

pacitor value of 0.1µF (as shown in Figure 13) is

recommended in order to provide the needed fil-

tering.

In addition to t ransients that are caused by normal

SRAM operation, power cycling can generate neg-

ative voltage s pikes on VCC that drive it to values

below VSS by as much as one volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, it is recommended to con-

nect a schottky diode from VCC to VSS (cathode

connected to VCC, ano de to VSS). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

Figure 13. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

15/25

M48T35AY, M48T35AV

MAXI MUM RA T IN G

Stressing the device ab ove t he rating l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indic at-

ed in the Operating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 6. Absolute Maximum Ratings

Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer

than 30 secon ds).

2. For SO package, st andard (SnP b) lead finish: Reflo w at peak t e m pera ture of 2 25°C (t ot al thermal budget not to exceed 180 °C for

between 90 to 15 0 s e c o nds).

3. For SO pac kage , Lea d-f ree ( Pb-free) l ead fin i sh: Reflow at p eak tem pera ture of 260°C (total th erm al budget not to exceed 245° C

for greater than 30 seconds).

CAUTION: Negativ e undershoots bel ow –0.3V are not allowed on any pin while i n th e Batte ry Back -up m ode.

CAUTION: Do NOT wa ve s ol d er SOIC t o avoid da m aging SN APHAT so ckets.

Symbol Parameter Value Unit

TAAmbient Operating Temperature Grade 1 0 to 70 °C

Grade 6 –40 to 85 °C

TSTG Storage Temperature (VCC Off, Oscillator Off) –40 to 85 °C

TSLD(1,2,3) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltages M48T35AY –0.3 to 7 V

M48T35AV –0.3 to 4.6 V

VCC Supply Voltage M48T35AY –0.3 to 7 V

M48T35AV –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M48T35AY, M48T35AV

16/25

DC AND AC PA RAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Charact eristic tables are

derived from tests pe rform ed under the Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 7. Operating and AC Measurem en t Conditions

Note: Out put Hi- Z is def i ned as the point where dat a i s no longer dri ven.

Figu re 14 . AC Measurem ent Lo a d Circui t

Note: 50pF for M48T35 AV.

Table 8. Capacitance

Note: 1. Effective capa citan ce measure d wi t h power supply at 5V; sam pl ed on ly , n ot 100% tested.

2. At 25° C, f = 1MHz.

3. Outputs des el ected.

Parameter M48T35AY M48T35AV Unit

Supply Volt age (VCC)4.5 to 5.5 3.0 to 3.6 V

Ambient Operating Temperature (TA)Grade 1 0 to 70 0 to 70 °C

Grade 6 –40 to 85 –40 to 85

Load Capacitance (CL)100 50 pF

Input Rise and Fall Times ≤ 5 ≤ 5ns

Input Pulse Voltages 0 to 3 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 1.5 V

AI02586

CL = 100pF

(or 5pF)

CL includes JIG capacitance

645Ω

DEVICE

UNDER

TEST

1.75V

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

COUT(3) Output Capacitance 10 pF

17/25

M48T35AY, M48T35AV

Table 9. DC Characteristics

Note: 1. Vali d for Ambi ent Op erat in g T em pera ture : TA = 0 to 70°C or –40 to 85°C; V CC = 4.5 to 5.5V o r 3.0 t o 3.6V (except where noted).

2. Outputs des el ected.

3. Ne gativ e spikes of –1V al l owed fo r up to 10ns onc e per Cycl e .

Symbol Parameter Test Condition(1)

M48T35AY M48T35AV

Unit–70 –100

Min Max Min Max

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 ±1 µA

ILO(2) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC Supply Current Outputs open 50 30 mA

ICC1 Supply Current (Standby)

TTL E = VIH 32mA

ICC2 Supply Current (Standby)

CMOS E = VCC – 0.2V 32mA

VIL(3) Input Low Voltage –0.3 0.8 –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1 mA 0.4 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 2.4 V

M48T35AY, M48T35AV

18/25

Figure 15. Power Down /U p Mode AC Waveform s

Table 10. Power Down/U p AC Characteri stics

Note: 1. Vali d for Ambi ent Op erat in g T em pera ture : TA = 0 to 70°C or –40 to 85°C; V CC = 4.5 to 5.5V o r 3.0 t o 3.6V (except where noted).

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pa ss-

es VPFD (mi n).

3. VPFD ( min) to VSS fall time of less th an tFB may cause corruption of RA M data.

4. trec (min) = 20ms for industrial temperature Grade 6 device.

Table 11. Power Down/Up Trip Points DC Characteristics

Note: 1. Vali d for Ambi ent Op erat in g T em pera ture : TA = 0 to 70°C or –40 to 85°C; V CC = 4.5 to 5.5V o r 3.0 t o 3.6V (except where noted).

2. All voltages referenced to VSS.

3. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top tDR = 7 years (typ ) .

4. Usi ng l arger M 4T 32-BR12SH6 SNA PHAT top (recomm ende d for Industri al Te m perature Ra nge - Grade 6 de vice) .

5. At 25° C, VCC = 0V.

Symbol Parameter(1) Min Max Unit

tPD E or W at VIH before Power Down 0µs

tF(2) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB(3) VPFD (min) to VSS VCC Fall Time M48T35AY 10 µs

M48T35AV 150 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1µs

trec(4) VPFD (max) to Inputs Recognized 40 200 ms

Symbol Parameter(1,2) Min Typ Max Unit

VPFD Power-fail Deselect Voltage M48T35AY 4.2 4.35 4.5 V

M48T35AV 2.7 2.9 3.0 V

VSO Battery Back-up Switchover Voltage M48T35AY 3.0 V

M48T35AV VPFD –100mV V

tDR(5) Expected Data Retention Time Grade 1 10(3) YEARS

Grade 6 10(4) YEARS

AI01168C

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tF tFB tR

tPD tRB

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

trec

19/25

M48T35AY, M48T35AV

P ACKAGE MECHANICA L INFO RMATIO N

Figure 16. PCDIP28 – 28-pin Pla stic DIP, battery CAPHAT™, Package Outline

No te : D rawing is not to scale.

Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 8.89 9.65 0.350 0.380

A1 0.38 0.76 0.015 0.030

A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021

B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012

D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722

e1 2.29 2.79 0.090 0.110

e3 29.72 36.32 1.170 1.430

eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N 28 28

PCDIP

B1 B e1

M48T35AY, M48T35AV

20/25

Figure 17. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAP HAT, Package Ou tline

No te : D rawing is not to scale.

Table 13. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N 28 28

CP 0.10 0.004

SOH-A

LA1 α

21/25

M48T35AY, M48T35AV

Figure 18. SH – 4- p i n SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline

No te : D rawing is not to scale.

Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Batte ry & Cry s ta l, Pac kage Mech . D ata

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

M48T35AY, M48T35AV

22/25

Figure 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

No te : D rawing is not to scale.

Table 15. SH – 4-pin SNAPHAT Housi ng for 120mAh Battery & Crystal, Package Mech. Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

23/25

M48T35AY, M48T35AV

PART NUMBERING

Table 16. Ordering Information Scheme

Note: 1. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under the part number “M4TXX-

BR12SH” in pl asti c tube or “M4TXX-B R12SHTR” in Tape & Re el form (s ee Tabl e 17).

2. Available i n SOIC package only .

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-

tery.

For other options, or for more information on any aspect of this device, please contact the ST Sales Office

nearest you.

Table 17. SNAPHAT Battery Table

Example: M48T 35AY –70 MH 1 E

Device Type

M48T

Supply Voltage and Write Protect Voltage

35AY = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V

35AV = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V

Speed

–70 = 70ns (35AY)

–10 = 100ns (35AV)

Package

PC = PCDIP28

MH(1) = SOH28

Tempera ture Rang e

1 = 0 to 70°C

6 = –40 to 85°C(2)

Shipping Method

For SOH28:

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

For PCDIP28:

blank = Tubes

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

M48T35AY, M48T35AV

24/25

REVISION HISTORY

Table 18. Document Revi sion History

Date Rev. # Revision Details

November 1999 1.0 First Issue

21-Apr-00 2.0 From Preliminary Data to Data Sheet

29-May-00 2.1 tFB change (Table 10)

20-Jul-01 3.0 Reformatted; temp./voltage info. added to tables (Table 8, 9, 3, 4, 10, 11); add Century

Bit text

20-May-02 3.1 Modify reflow time and temperature footnotes (Table 6)

31-Mar-03 4.0 v2.2 template applied; data retention condition updated (Table 11)

01-Apr-04 5.0 Reformatted; updated with Lead-free package information (Table 6, 16)

25/25

M48T35AY, M48T35AV

Information fur nished is believed to b e accurate and relia ble. However, STMicroelectronics a ssumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

author i zed for use as critic al components in lif e supp ort de vices or sy stem s with out expre ss writt en app roval of STMi cr oel ectronics.

The ST l ogo is a reg i st ered trademark of STM i croe l ec tron ics.

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