CD74HC4538EE4 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS123E

Features

• Retriggerable/Resettable Capability

• Trigger and Reset Propagation Delays Independent of

RX, CX

• Triggering from the Leading or Trailing Edge

• Q and Q Buffered Outputs Available

• Separate Resets

• Wide Range of Output Pulse Widths

• Schmitt Trigger Input on A and B Inputs

• Retrigger Time is Independent of CX

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Pinout CD54HC4538, CD54HCT4538

(CERDIP)

CD74HC4538

(PDIP, SOIC, SOP, TSSOP)

CD74HCT4538

(PDIP, SOIC)

TOP VIEW

Description

The ’HC4538 and ’HCT4538 are dual

retriggerable/resettable monostable precision multivibrators

for ﬁxed voltage timing applications. An external resistor

(RX) and an external capacitor (CX) control the timing and

the accuracy for the circuit. Adjustment of RXand CX

provides a wide range of output pulse widths from the Q and

Q terminals. The propagation delay from trigger input-to-

output transition and the propagation delay from reset input-

to-output transition are independent of RX and CX.

Leading-edge triggering (A) and trailing edge triggering (B)

inputs are provided for triggering from either edge of the

input pulse. An unused “A” input should be tied to GND and

an unused B should be tied to VCC. On power up the IC is

reset. Unused resets and sections must be terminated. In

normal operation the circuit retriggers on the application of

each new trigger pulse. To operate in the non-triggerable

mode Q is connected to B when leading edge triggering (A)

is used or Q is connected to A when trailing edge triggering

(B) is used. The period (τ) can be calculated from τ= (0.7)

RX, CX; RMIN is 5kΩ. CMIN is 0pF.

GND

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC4538F3A -55 to 125 16 Ld CERDIP

CD54HCT4538F3A -55 to 125 16 Ld CERDIP

CD74HC4538E -55 to 125 16 Ld PDIP

CD74HC4538M -55 to 125 16 Ld SOIC

CD74HC4538MT -55 to 125 16 Ld SOIC

CD74HC4538M96 -55 to 125 16 Ld SOIC

CD74HC4538NSR -55 to 125 16 Ld SOP

CD74HC4538PW -55 to 125 16 Ld TSSOP

CD74HC4538PWR -55 to 125 16 Ld TSSOP

CD74HC4538PWT -55 to 125 16 Ld TSSOP

CD74HCT4538E -55 to 125 16 Ld PDIP

CD74HCT4538M -55 to 125 16 Ld SOIC

CD74HCT4538MT -55 to 125 16 Ld SOIC

CD74HCT4538M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4538, CD74HC4538,

CD54HCT4538, CD74HCT4538

High-Speed CMOS Logic Dual Retriggerable

Precision Monostable Multivibrator

[

/Title

(

CD54

C453

D74

C453

D74

CT45

Sub-

ect

(

High

peed

MOS

ogic

June 1998 - Revised October 2003

Functional Diagram

2R 13

2A 12

92Q

2B MONO 2

VCC

15 14

2Cx 2RxCx

1R 3

71Q

MONO 1

VCC

1Cx 1RxCx

1Cx 1Rx

2Cx 2Rx

GND = 8

VCC = 16

TRUTH TABLE

INPUTS OUTPUTS

RABQQ

LXXLH

XHXLH

XXLLH

HL↓

H↑H

H = High Level, L = Low Level, ↑ = Transition from Low to High,

↓ = Transition from High to Low, One High Level Pulse,

One Low Level Pulse, X = Irrelevant. FIGURE 1. FF DETAIL

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

FIGURE 2. LOGIC DIAGRAM (1 MONO)

FUNCTIONAL TERMINAL CONNECTIONS

FUNCTION

VCC TO

TERMINAL NUMBER GND TO

TERMINAL NUMBER INPUT PULSE TO

TERMINAL NUMBER OTHER

CONNECTIONS

MONO1MONO2MONO1MONO2MONO1MONO2MONO1MONO2

Leading-Edge

Trigger/Retriggerable 3, 5 11, 13 4 12

Leading-Edge

Trigger/Non-Retriggerable 3 13 4 12 5-7 11-9

Trailing-Edge

Trigger/Retriggerable 313412511

Trailing-Edge

Trigger/Non-Retriggerable 3 13 5 11 4-6 12-10

NOTES:

1. A retriggerable one-shot multivibrator has an output pulse width which is extended one full time period (T) after application of the last

trigger pulse.

2. A non-triggerable one-shot multivibrator has a time period (T) referenced from the application of the first trigger pulse.

FIGURE 3. INPUT PULSE TRAIN FIGURE 4. RETRIGGERABLE MODE

PULSE WIDTH (A MODE) FIGURE5. NON-RETRIGGERABLEMODE

PULSE WIDTH

(A MODE)

CL CL Q

R2R1 FF

VCC

2(14)

1(15)

3(13)

4(12)

5(11)

VCC

HIGH Z

VCC

COMP II

+6(10)

7(9)

VCC

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 3)

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Times, tr, tf

Reset Input:

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Trigger Inputs A or B:

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited (Max)

External Timing Resistor, RX (Note 4) . . . . . . . . . . . . . . . .5kΩ (Min)

External Timing Capacitor, CX (Note 4) . . . . . . . . . . . . . . . . .0 (Min)

Package Thermal Impedance, θJA (see Note 5):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

3. Unless otherwise specified, all voltages are referenced to ground.

4. The maximum allowable values of RXand CXare a function of leakage of capacitor CX, the leakage of the ’HC4538, and leakage due to

board layout and surface resistance. Values of RXand CXshould be chosen so that the maximum current into pin 2 or pin 14 is 30mA.

Susceptibility to externally induced noise signals may occur for RX > 1MΩ.

5. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current A, B, R IIVCC or

GND -6--±0.1 - ±1-±1µA

Input Leakage

Current RXCX

(Note 6)

-6--±0.05 - ±0.5 - ±0.5 µA

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

Active Device Current

Q = High & Pins 2, 14

at VCC/4

ICC VCC or

GND 0 6 - - 0.6 - 0.8 - 1 mA

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND - 5.5 - ±0.1 - ±1-±1µA

Input Leakage

Current RXCX

(Note 6)

- 5.5 - - ±0.05 - ±0.5 - ±0.5 µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Active Device Current

Q = High & Pins 2, 14

at VCC/4

ICC VCC or

GND 0 5.5 - - 0.6 - 0.8 - 1 mA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC

(Note 7) VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTES:

6. When testing IIL the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path

from VDD to the test pin will cause a current far exceeding the specification.

7. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

HCT Input Loading Table

INPUT UNIT LOADS

All 0.5

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.

360µA max at 25oC.

Prerequisite for Switching Speciﬁcations

PARAMETER SYMBOL VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

HC TYPES

Input Pulse Widths tWH, tWL

A, B 2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns

614--17- -20--ns

WL 2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns

614--17- -20--ns

Reset Recovery Time tREC 25--5--5--ns

4.5 5 - - 5 - - 5 - - ns

65--5--5--ns

Retrigger Time

(Figure 11) trT 5 - 175 - - - - - - - ns

HCT TYPES

Input Pulse Widths tWH, tWL

A, B 4.5 16 - - 20 - - 24 - - ns

WL 4.5 20 - - 25 - - 30 - - ns

Reset Recovery Time tREC 4.5 5 - - 5 - - 5 - - ns

Retrigger Time

(Figure 11) trT 5 - 175 - - - - - - - ns

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns, RX = 10KΩ, CX = 0

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay tPLH CL = 50pF

A, B to Q 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

A, B to Qt

PHL CL = 50pF 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

R to Q tPHL CL = 50pF 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

R to Qt

PLH CL = 50pF 2 - - 250 - 315 - 375 ns

4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

CL = 50pF 6 - - 43 - 54 - 64 ns

Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Output Pulse Width

RX = 10k, CX = 0.1µFτCL = 50pF 3 0.64 - 0.78 0.612 0.812 0.605 0.819 ms

5 0.63 - 0.77 0.602 0.798 0.595 0.805 ms

Output Pulse Width Match,

Same Package -- -±1- - - - - %

Power Dissipation Capacitance

(Notes 8, 9) CPD CL = 15pF 5 - 136 - - - - - pF

Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF

HCT TYPES

Propagation Delay tPLH

A, B to Q CL = 50pF 4.5 - - 55 - 69 - 83 ns

CL = 15pF 5 - 23 - - - - - ns

A, B to Qt

PHL CL = 50pF 4.5 - - 55 - 69 - 83 ns

CL = 15pF 5 - 23 - - - - - ns

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

R to Q tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns

CL = 15pF 5 - 17 - - - - - ns

R to Qt

PLH CL = 50pF 4.5 - - 50 - 63 - 75 ns

CL = 15pF 5 - 21 - - - - - ns

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns

Output Pulse Width

RX = 10k, CX = 0.1µFτCL = 50pF 5 0.63 - 0.77 0.602 0.798 0.595 0.805 ms

Output Pulse Width Match,

Same Package ----±1- - - - - %

Power Dissipation Capacitance

(Notes 8, 9) CPD CL = 15pF 5 - 134 - - - - - pF

Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF

NOTES:

8. CPD is used to determine the dynamic power consumption, per one shot.

9. PD=(C

PD +C

X)V

CC2fi∑(CLVCC2fO) where fi= input frequency, fO= output frequency, CL= output load capacitance,

CX = external capacitance VCC = supply voltage assuming fi «

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns, RX = 10KΩ, CX = 0 (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Typical Performance Curves

FIGURE 8. K FACTOR vs DC SUPPLY VOLTAGE (VCC) - V FIGURE 9. K FACTOR vs DC SUPPLY VOLTAGE (VCC) - V

FIGURE 10. K FACTOR vs CXFIGURE 11. MINIMUM RETRIGGER TIME vs TIMING

CAPACITANCE

0.70

0.69

0.68

0.67

2 3 4 4.5 5 5.5 6

VCC, DC SUPPLY VOLTAGE (V)

K FACTOR

10kΩ, 10nF

10kΩ, 100nF

100kΩ, 100nF

100kΩ, 10nF

HC4538 - TA11646C

TA = 25oC0.70

0.69

0.68

0.67

2 3 4 4.5 5 5.5 6

VCC, DC SUPPLY VOLTAGE (V)

K FACTOR

10kΩ, 10nF

10kΩ, 100nF

100kΩ, 100nF

100kΩ, 10nF

HCT4538 - TA13646C

TA = 25oC

1.3

1.1

0.9

0.6

10 102103104105

CX, TIMING CAPACITANCE (pF)

K FACTOR

2kΩ

10kΩ

100kΩ

HC/HCT4538

VCC = 5V, TA = 25oC

1.2

1.0

0.8

0.7

104

102

10 102103104

CX, TIMING CAPACITANCE (pF)

trr, TYP MIN RETRIGGER TIME (ns)

VCC = 4.5V

TA = 25oC

RX = 10kΩ

103

VCC = 5V

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

Power-Down Mode

During a rapid power-down condition, as would occur with a

power-supply short circuit with a poorly ﬁltered power supply,

the energy stored in CXcould discharge into Pin 2 or 14. To

aviod possible device damage in this mode, when CXis ≥

0.5µF, a protection diode with a 1 ampere or higher rating

(1N5395 or equivalent) and a separate ground return for CX

should be provided as shown in Figure 12.

An alternate protection method is shown in Figure 13, where

a51Ωcurrent-limiting resistor is inserted in series with CX.

Note that a small pulse width decrease will occur however,

and RXmust be appropriately increased to obtain the origi-

nally desired pulse width.

FIGURE 12. RAPID POWER-DOWN PROTECTION CIRCUIT

IN5395

EQUIVALENT RX

≥0.5µF

1(15)

2(14)

VCC

FIGURE 13. ALTERNATE RAPID POWER-DOWN PROTECTION

CIRCUIT

≥0.5µF1(15)

2(14)

VCC

51Ω

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-8688601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8688601EA

CD54HC4538F3A

CD54HC4538F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4538F

CD54HC4538F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8688601EA

CD54HC4538F3A

CD54HCT4538F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HCT4538F3A

CD74HC4538E ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4538E

CD74HC4538EE4 ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4538E

CD74HC4538M ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538M96 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538M96E4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538M96G4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538ME4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538MG4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538MT ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538NSR ACTIVE SO NS 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4538M

CD74HC4538PW ACTIVE TSSOP PW 16 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538

CD74HC4538PWR ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538

CD74HC4538PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

CD74HC4538PWT ACTIVE TSSOP PW 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4538

CD74HCT4538E ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4538E

CD74HCT4538M ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4538M

CD74HCT4538M96 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4538M

CD74HCT4538MT ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4538M

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 3

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC4538, CD54HCT4538, CD74HC4538, CD74HCT4538 :

•Catalog: CD74HC4538, CD74HCT4538

•Automotive: CD74HC4538-Q1, CD74HC4538-Q1

•Military: CD54HC4538, CD54HCT4538

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC4538M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD74HC4538NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD74HC4538PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HC4538PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HCT4538M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC4538M96 SOIC D 16 2500 333.2 345.9 28.6

CD74HC4538NSR SO NS 16 2000 367.0 367.0 38.0

CD74HC4538PWR TSSOP PW 16 2000 367.0 367.0 35.0

CD74HC4538PWT TSSOP PW 16 250 367.0 367.0 35.0

CD74HCT4538M96 SOIC D 16 2500 333.2 345.9 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

CD74HC4538E CD74HC4538M CD74HC4538EE4 CD74HC4538M96 CD74HC4538M96E4 CD74HC4538M96G4

CD74HC4538ME4 CD74HC4538MG4 CD74HC4538MT CD74HC4538NSR CD74HC4538PW CD74HC4538PWG4

CD74HC4538PWR CD74HC4538PWRG4 CD74HC4538PWT