74VHC573FT CMOS Digital Integrated Circuits Silicon Monolithic 74VHC573FT 1. Functional Description * Octal D-Type Latch with 3-State Outputs 2. General The 74VHC573FT is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 3. Features (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: Topr = -40 to 125 (3) High speed: tpd = 4.5 ns (typ.) at VCC = 5.0 V (4) Low power dissipation: ICC = 4.0 A (max) at Ta = 25 (5) High noise immunity: VNIH = VNIL = 28% VCC (min) (6) Power-down protection is provided on all inputs. (7) Balanced propagation delays: tPLH tPHL (8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V (9) Low noise: VOLP = 1.0 V (max) (10) Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 573 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. Packaging TSSOP20B Start of commercial production (c)2016 Toshiba Corporation 1 2013-03 2017-02-22 Rev.4.0 74VHC573FT 5. Pin Assignment 6. Marking 7. IEC Logic Symbol (c)2016 Toshiba Corporation 2 2017-02-22 Rev.4.0 74VHC573FT 8. Truth Table INPUT OE INPUT LE INPUT D OUTPUT H X X Z L L X Qn L H L L L H H H X: Z: Qn: Don't care High impedance Q outputs are latched at the time when the LE input is taken to low logic level. 9. System Diagram (c)2016 Toshiba Corporation 3 2017-02-22 Rev.4.0 74VHC573FT 10. Absolute Maximum Ratings (Note) Characteristics Symbol Note Rating Unit Supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to 7.0 V VOUT -0.5 to VCC + 0.5 V IIK -20 mA Output diode current IOK 20 mA Output current IOUT 25 mA VCC/ground current ICC Power dissipation PD Storage temperature Tstg Output voltage Input diode current (Note 1) 75 mA 180 mW -65 to 150 Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: 180 mW in the range of Ta = -40 to 85 . From Ta = 85 to 125 a derating factor of -3.25 mW/ shall be applied until 50 mW. 11. Operating Ranges (Note) Characteristics Supply voltage Input voltage Output voltage Symbol Rating Unit 2.0 to 5.5 V VIN 0 to 5.5 V VOUT 0 to VCC V VCC Operating temperature Topr Input rise and fall times dt/dv Note: Test Condition -40 to 125 VCC = 3.3 0.3 V 0 to 100 ns/V VCC = 5.0 0.5 V 0 to 20 The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs and bus inputs must be tied to either VCC or GND. (c)2016 Toshiba Corporation 4 2017-02-22 Rev.4.0 74VHC573FT 12. Electrical Characteristics 12.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Test Condition High-level input voltage VIH Low-level input voltage VIL High-level output voltage VOH VCC (V) Min Typ. Max Unit 2.0 1.50 V 3.0 to 5.5 VCC x 0.7 Low-level output voltage VOL 2.0 VIN = VIH or VIL 0.50 3.0 to 5.5 VCC x 0.3 2.0 1.9 2.0 3.0 2.9 3.0 4.5 4.4 4.5 IOH = -4 mA 3.0 2.58 IOH = -8 mA 4.5 3.94 IOL = 50 A 2.0 0.0 0.1 3.0 0.0 0.1 IOH = -50 A VIN = VIH or VIL 4.5 0.0 0.1 IOL = 4 mA 3.0 0.36 IOL = 8 mA 4.5 0.36 IOZ VIN = VIH or VIL VOUT = VCC or GND 5.5 0.25 Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 0.1 Quiescent supply current ICC VIN = VCC or GND 5.5 4.0 3-state output OFF-state leakage current V V V A 12.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics High-level input voltage Symbol VIH Test Condition VCC (V) Min Max Unit 2.0 1.50 V 3.0 to 5.5 VCC x 0.7 Low-level input voltage High-level output voltage Low-level output voltage 3-state output OFF-state leakage current VIL VOH VOL VIN = VIH or VIL VIN = VIH or VIL IOH = -50 A 2.0 0.50 3.0 to 5.5 VCC x 0.3 2.0 1.9 3.0 2.9 4.5 4.4 IOH = -4 mA 3.0 2.48 IOH = -8 mA 4.5 3.80 IOL = 50 A 2.0 0.1 3.0 0.1 4.5 0.1 IOL = 4 mA 3.0 0.44 IOL = 8 mA 4.5 0.44 2.50 IOZ VIN = VIH or VIL VOUT = VCC or GND 5.5 Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 1.0 Quiescent supply current ICC VIN = VCC or GND 5.5 40.0 (c)2016 Toshiba Corporation 5 V V V A 2017-02-22 Rev.4.0 74VHC573FT 12.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage 3-state output OFF-state leakage current Symbol VIH VIL VOH VOL Test Condition VCC (V) VIN = VIH or VIL IOH = -50 A VIN = VIH or VIL Min Max Unit V 2.0 1.50 3.0 to 5.5 VCC x 0.7 2.0 0.50 3.0 to 5.5 VCC x 0.3 2.0 1.9 3.0 2.9 V V 4.5 4.4 IOH = -4 mA 3.0 2.40 IOH = -8 mA 4.5 3.70 IOL = 50 A 2.0 0.1 3.0 0.1 4.5 0.1 IOL = 4 mA 3.0 0.55 IOL = 8 mA 4.5 0.55 10.0 A V IOZ VIN = VIH or VIL VOUT = VCC or GND 5.5 Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 2.0 A Quiescent supply current ICC VIN = VCC or GND 5.5 80.0 A (c)2016 Toshiba Corporation 6 2017-02-22 Rev.4.0 74VHC573FT , Input: tr = tf = 3 ns) 12.4. Timing Requirements (Unless otherwise specified, Ta = 25 25 Characteristics Symbol Test Condition VCC (V) Limit Unit Minimum pulse width (LE) tw(H) 3.3 0.3 5.0 ns 5.0 0.5 5.0 ns Minimum setup time tS 3.3 0.3 3.5 ns 5.0 0.5 3.5 ns 3.3 0.3 1.5 ns 5.0 0.5 1.5 ns Minimum hold time th 12.5. Timing Requirements (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) 85 Characteristics Symbol Test Condition VCC (V) Limit Unit Minimum pulse width (LE) tw(H) 3.3 0.3 5.0 ns 5.0 0.5 5.0 Minimum setup time tS 3.3 0.3 3.5 5.0 0.5 3.5 3.3 0.3 1.5 5.0 0.5 1.5 Minimum hold time th ns ns 12.6. Timing Requirements (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Limit Unit Minimum pulse width (LE) tw(H) 3.3 0.3 5.0 ns 5.0 0.5 5.0 Minimum setup time tS 3.3 0.3 4.5 5.0 0.5 4.0 Minimum hold time th 3.3 0.3 1.5 5.0 0.5 1.5 (c)2016 Toshiba Corporation 7 ns ns 2017-02-22 Rev.4.0 74VHC573FT 12.7. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (LE-Q) Symbol Note Test Condition VCC (V) CL (pF) Min 3.3 0.3 15 50 tPLH,tPHL Typ. Max Unit 7.6 11.9 ns 10.1 15.4 15 5.0 7.7 50 6.5 9.7 15 7.0 11.0 50 9.5 14.5 15 4.5 6.8 50 6.0 8.8 15 7.3 11.5 50 9.8 15.0 15 5.2 7.7 50 6.7 9.7 3.3 0.3 50 10.7 14.5 5.0 0.5 50 6.7 9.7 3.3 0.3 50 1.5 5.0 0.5 50 1.0 5.0 0.5 Propagation delay time (D-Q) tPLH,tPHL 3.3 0.3 5.0 0.5 3-state output enable time tPZL,tPZH RL = 1 k 3.3 0.3 5.0 0.5 3-state output disable time Output skew Input capacitance tPLZ,tPHZ RL = 1 k tosLH,tosHL (Note 1) ns ns ns ns CIN 4 10 pF Output capacitance COUT 6 pF Power dissipation capacitance CPD 29 pF (Note 2) Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|) Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per latch) And the total CPD when n pcs. of latch operate can be gained by the following equation. CPD (total) = 21 + 8 x n 12.8. AC Characteristics (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (LE-Q) Symbol Note Test Condition VCC (V) CL (pF) Min Max Unit 3.3 0.3 15 1.0 14.0 ns 50 1.0 17.5 15 1.0 9.0 50 1.0 11.0 15 1.0 13.0 50 1.0 16.5 15 1.0 8.0 50 1.0 10.0 15 1.0 13.5 50 1.0 17.0 15 1.0 9.0 tPLH,tPHL 5.0 0.5 Propagation delay time (D-Q) tPLH,tPHL 3.3 0.3 5.0 0.5 3-state output enable time tPZL,tPZH RL = 1 k 3.3 0.3 5.0 0.5 3-state output disable time Output skew Input capacitance tPLZ,tPHZ RL = 1 k tosLH,tosHL (Note 1) CIN ns ns 50 1.0 11.0 3.3 0.3 50 1.0 16.5 5.0 0.5 50 1.0 11.0 3.3 0.3 50 1.5 5.0 0.5 50 1.0 ns 10 pF ns ns Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|) (c)2016 Toshiba Corporation 8 2017-02-22 Rev.4.0 74VHC573FT 12.9. AC Characteristics (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns) Characteristics Symbol Propagation delay time (LE-Q) Note Test Condition VCC (V) CL (pF) Min Max Unit 3.3 0.3 15 1.0 16.0 ns 50 1.0 19.5 15 1.0 10.5 50 1.0 12.5 15 1.0 15.0 50 1.0 18.5 15 1.0 9.0 50 1.0 11.0 15 1.0 15.5 50 1.0 19.0 15 1.0 10.5 50 1.0 12.5 3.3 0.3 50 1.0 18.5 5.0 0.5 50 1.0 12.5 3.3 0.3 50 1.5 5.0 0.5 50 1.0 10 tPLH,tPHL 5.0 0.5 Propagation delay time (D-Q) tPLH,tPHL 3.3 0.3 5.0 0.5 3-state output enable time tPZL,tPZH RL = 1 k 3.3 0.3 5.0 0.5 3-state output disable time Output skew tPLZ,tPHZ RL = 1 k tosLH,tosHL (Note 1) Input capacitance CIN ns ns ns ns pF Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|) , Input: tr = tf = 3 ns) 25 12.10. Noise Characteristics (Unless otherwise specified, Ta = 25 Characteristics Symbol Test Condition VCC (V) Typ. Limit Unit V Quiet output maximum dynamic VOL VOLP CL = 50 pF 5.0 0.8 1.0 Quiet output minimum dynamic VOL VOLV CL = 50 pF 5.0 -0.8 -1.0 Minimum high-level dynamic input voltage VIHD CL = 50 pF 5.0 3.5 Maximum low-level dynamic input voltage VILD CL = 50 pF 5.0 1.5 13. Input Equivalent Circuit (c)2016 Toshiba Corporation 9 2017-02-22 Rev.4.0 74VHC573FT Package Dimensions Unit: mm Weight: 0.071 g (typ.) Package Name(s) Nickname: TSSOP20B (c)2016 Toshiba Corporation 10 2017-02-22 Rev.4.0 74VHC573FT RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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