LTC1196-1ACS8#TRPBF - Linear Technology

LTC1196/LTC1198

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TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

8-Bit, SO-8, 1Msps ADCs

with Auto-Shutdown Options

Single 5V Supply, 1Msps, 8-Bit Sampling ADC

n High Speed Data Acquisition

n Disk Drives

n Portable or Compact Instrumentation

n Low Power or Battery-Operated Systems

n High Sampling Rates: 1MHz (LTC1196)

750kHz (LTC1198)

n Low Cost

n Single Supply 3V and 5V Speciﬁ cations

n Low Power: 10mW at 3V Supply

50mW at 5V Supply

n Auto-Shutdown: 1nA Typical (LTC1198)

n ±1/2LSB Total Unadjusted Error over Temperature

n 3-Wire Serial I/O

n 1V to 5V Input Span Range (LTC1196)

n Converts 1MHz Inputs to 7 Effective Bits

n Differential Inputs (LTC1196)

n 2-Channel MUX (LTC1198)

n SO-8 Plastic Package

The LTC

1196/LTC1198 are 600ns, 8-bit A/D converters

with sampling rates up to 1MHz. They are offered in 8-pin

SO packages and operate on 3V to 6V supplies. Power

dissipation is only 10mW with a 3V supply or 50mW with

a 5V supply. The LTC1198 automatically powers down

to a typical supply current of 1nA whenever it is not

performing conversions. These 8-bit switched-capacitor

successive approximation ADCs include sample-and-

holds. The LTC1196 has a differential analog input; the

LTC1198 offers a software selectable 2-channel MUX.

The 3-wire serial I/O, SO-8 packages, 3V operation and

extremely high sample rate-to-power ratio make these

ADCs an ideal choice for compact, high speed systems.

These ADCs can be used in ratiometric applications or

with external references. The high impedance analog in-

puts and the ability to operate with reduced spans below

1V full scale (LTC1196) allow direct connection to signal

sources in many applications, eliminating the need for

gain stages.

The A-grade devices are speciﬁ ed with total unadjusted

error of ±1/2LSB maximum over temperature.

Effective Bits and S/(N + D) vs Input Frequency

INPUT FREQUENCY (Hz)

S/(N + D) (dB)

10k 100k 1M

11968 TA01b

EFFECTIVE NUMBER OF BITS (ENOBs)

VREF =V

CC = 2.7V

fSMPL = 383kHz (LTC1196)

fSMPL = 287kHz (LTC1198)

VREF =V

CC = 5V

fSMPL = 1MHz (LTC1196)

fSMPL = 750kHz (LTC1198)

TA= 25°C

5V1μF

ANALOG INPUT

0V TO 5V RANGE

1196/98 TA01

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP,

OR SHIFT REGISTERS

–IN

GND

VCC

CLK

DOUT

+IN

LTC1196

VREF

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

LTC1196/LTC1198

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ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

TOP VIEW

VCC

CLK

DOUT

VREF

S8 PACKAGE

8-LEAD PLASTIC SO

+IN

–IN

GND

TJMAX = 150°C, θJA = 175°C/W

TOP VIEW

VCC (VREF)

CLK

DOUT

DIN

CH0

CH1

GND

S8 PACKAGE

8-LEAD PLASTIC SO

CS/

SHUTDOWN

TJMAX = 150°C, θJA = 175°C/W

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1196-1ACS8#PBF LTC1196-1ACS8#TRPBF 11961A 8-Lead Plastic SO 0°C to 70°C

LTC1196-1BCS8#PBF LTC1196-1BCS8#TRPBF 11961B 8-Lead Plastic SO 0°C to 70°C

LTC1196-2ACS8#PBF LTC1196-2ACS8#TRPBF 11962A 8-Lead Plastic SO 0°C to 70°C

LTC1196-2BCS8#PBF LTC1196-2BCS8#TRPBF 11962B 8-Lead Plastic SO 0°C to 70°C

LTC1198-1ACS8#PBF LTC1198-1ACS8#TRPBF 11981A 8-Lead Plastic SO 0°C to 70°C

LTC1198-1BCS8#PBF LTC1198-1BCS8#TRPBF 11981B 8-Lead Plastic SO 0°C to 70°C

LTC1198-2ACS8#PBF LTC1198-2ACS8#TRPBF 11982A 8-Lead Plastic SO 0°C to 70°C

LTC1198-2BCS8#PBF LTC1198-2BCS8#TRPBF 11982B 8-Lead Plastic SO 0°C to 70°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

Supply Voltage (VCC) to GND .................................... 7V

Voltage

Analog Reference ....................... –0.3V to VCC + 0.3V

Digital Inputs ......................................... –0.3V to 7V

Digital Outputs ........................... –0.3V to VCC + 0.3V

Power Dissipation .............................................. 500mW

Operating Temperature Range

LTC1196-1AC, LTC1198-1AC, LTC1196-1BC,

LTC1198-1BC, LTC1196-2AC, LTC1198-2AC,

LTC1196-2BC, LTC1198-2BC ................. 0°C to 70°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................ 300°C

LTC1196 LTC1198

LTC1196/LTC1198

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RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN

LTC1196-1

LTC1198-1

TYP MAX MIN

LTC1196-2

LTC1198-2

TYP MAX UNITS

VCC Supply Voltage 2.7 6 2.7 6 V

VCC = 5V Operation

fCLK Clock Frequency

0.01

14.4

12.0

0.01

12.0

9.6

MHz

tCYC Total Cycle Time LTC1196

LTC1198

CLK

tSMPL Analog Input Sampling Time 2.5 2.5 CLK

thCS Hold Time CS LOW After Last CLK↑10 13 ns

tsuCS Setup Time CS↓ Before First CLK↑

(See Figures 1, 2)

20 26 ns

thDI Hold Time DIN After CLK↑LTC1198 20 26 ns

tsuDI Setup Time DIN Stable Before CLK↑LTC1198 20 26 ns

tWHCLK CLK HIGH Time fCLK = fCLK(MAX) 40% 40% 1/fCLK

tWLCLK CLK LOW Time fCLK = fCLK(MAX) 40% 40% 1/fCLK

tWHCS CS HIGH Time Between Data Transfer Cycles 25 32 ns

tWLCS CS LOW Time During Data Transfer LTC1196

LTC1198

CLK

The l denotes the speciﬁ cations which apply over

the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

CONVERTER AND MULTIPLEXER CHARACTERISTICS

PARAMETER CONDITIONS

LTC1196-1A/LTC1196-2A

LTC1198-1A/LTC1198-2A

LTC1196-1B/LTC1196-2B

LTC1198-1B/LTC1198-2B

UNITSMIN TYP MAX MIN TYP MAX

No Missing Codes Resolution l8 8 Bits

Offset Error l±1/2 ±1 LSB

Linearity Error (Note 3) l±1/2 ±1 LSB

Full-Scale Error l±1/2 ±1 LSB

Total Unadjusted Error (Note 4) LTC1196, VREF = 5.000V

LTC1198, VCC = 5.000V

l±1/2 ±1 LSB

Analog and REF Input Range LTC1196 –0.05V to VCC + 0.05V V

Analog Input Leakage Current (Note 5) l±1 ±1 μA

The l denotes the speciﬁ cations

which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX)

as deﬁ ned in Recommended Operating Conditions, unless otherwise noted.

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which

apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VCC = 5.25V l2.0 V

VIL Low Level Input Voltage VCC = 4.75V l0.8 V

IIH High Level Input Current VIN = VCC l2.5 μA

IIL Low Level Input Current VIN = 0V l–2.5 μA

VOH High Level Output Voltage VCC = 4.75V, IO = 10μA

VCC = 4.75V, IO = 360μA

4.5

2.4

4.74

4.71

LTC1196/LTC1198

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DIGITAL AND DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which

apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA l0.4 V

IOZ Hi-Z Output Leakage CS = HIGH l±3 μA

ISOURCE Output Source Current VOUT = 0V –25 mA

ISINK Output Sink Current VOUT = VCC 45 mA

IREF Reference Current, LTC1196 CS = VCC

fSMPL = fSMPL(MAX)

0.001

0.5

μA

ICC Supply Current CS = VCC, LTC1198 (Shutdown)

CS = VCC, LTC1196

fSMPL = fSMPL(MAX), LTC1196/LTC1198

0.001

μA

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as deﬁ ned in Recommended Operating Conditions,

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN

LTC1196

TYP MAX MIN

LTC1198

TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion 500kHz/1MHz Input Signal 47/45 47/45 dB

THD Total Harmonic Distortion 500kHz/1MHz Input Signal 49/47 49/47 dB

Peak Harmonic or Spurious Noise 500kHz/1MHz Input Signal 55/48 55/48 dB

IMD Intermodulation Distortion fIN1 = 499.37kHz

fIN2 = 502.446kHz

51 51 dB

Full-Power Bandwidth 8 8 MHz

Full Linear Bandwidth [S/(N + D) > 44dB 1 1 MHz

AC CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as deﬁ ned in Recommended Operating Conditions,

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN

LTC1196-1

LTC1198-1

TYP MAX MIN

LTC1196-2

LTC1198-2

TYP MAX UNITS

tCONV Conversion Time (See Figures 1, 2)

600

710

900

fSMPL(MAX) Maximum Sampling Frequency LTC1196

LTC1196

LTC1198

1.20

1.00

0.90

0.75

1.00

0.80

0.75

0.60

MHz

tdDO Delay Time, CLK↑ to DOUT Data Valid CLOAD = 20pF

55 64

68 78

tDIS Delay Time CS↑ to DOUT Hi-Z l70 120 88 150 ns

ten Delay Time, CLK↓ to DOUT Enabled CLOAD = 20pF l30 50 43 63 ns

thDO Time Output Data Remains Valid After

CLK↑CLOAD = 20pF l30 45 30 55 ns

tfDOUT Fall Time CLOAD = 20pF l515 1020ns

trDOUT Rise CLOAD = 20pF l515 1020ns

CIN Input Capacitance Analog Input On Channel

Analog Input Off Channel

Digital Input

LTC1196/LTC1198

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RECOMMENDED OPERATING CONDITIONS

The l denotes the speciﬁ cations which apply over

the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V operation.

SYMBOL PARAMETER CONDITIONS MIN

LTC1196-1

LTC1198-1

TYP MAX MIN

LTC1196-2

LTC1198-2

TYP MAX UNITS

fCLK Clock Frequency

0.01

5.4

4.6

0.01

MHz

tCYC Total Cycle Time LTC1196

LTC1198

CLK

tSMPL Analog Input Sampling Time 2.5 2.5 CLK

thCS Hold Time CS LOW After Last CLK↑20 40 ns

tsuCS Setup Time CS↓ Before First CLK↑

(See Figures 1, 2)

40 78 ns

thDI Hold Time DIN After CLK↑LTC1198 40 78 ns

tsuDI Setup Time DIN Stable Before CLK↑LTC1198 40 78 ns

tWHCLK CLK HIGH Time fCLK = fCLK(MAX) 40% 40% 1/fCLK

tWLCLK CLK LOW Time fCLK = fCLK(MAX) 40% 40% 1/fCLK

tWHCS CS HIGH Time Between Data Transfer

Cycles

50 96 ns

tWLCS CS LOW Time During Data Transfer LTC1196

LTC1198

CLK

CONVERTER AND MULTIPLEXER CHARACTERISTICS

The l denotes the speciﬁ cations

which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V, VREF = 2.5V,

fCLK = fCLK(MAX) as deﬁ ned in Recommended Operating Conditions, unless otherwise noted.

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply

over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VCC = 3.6V l1.9 V

VIL Low Level Input Voltage VCC = 2.7V l0.45 V

IIH High Level Input Current VIN = VCC l2.5 μA

IIL Low Level Input Current VIN = 0V l–2.5 μA

VOH High Level Output Voltage VCC = 2.7V, IO = 10μA

VCC = 2.7V, IO = 360μA

2.3

2.1

2.60

2.45

VOL Low Level Output Voltage VCC = 2.7V, IO = 400μA l0.3 V

IOZ Hi-Z Output Leakage CS = HIGH l±3 μA

PARAMETER CONDITIONS

LTC1196-1A/LTC1196-2A

LTC1198-1A/LTC1198-2A

LTC1196-1B/LTC1196-2B

LTC1198-1B/LTC1198-2B

UNITSMIN TYP MAX MIN TYP MAX

No Missing Codes Resolution l8 8 Bits

Offset Error l±1/2 ±1 LSB

Linearity Error (Note 3) l±1/2 ±1 LSB

Full-Scale Error l±1/2 ±1 LSB

Total Unadjusted Error (Note 4) LTC1196, VREF = 2.5.000V

LTC1198, VCC = 2.700V

l±1/2 ±1 LSB

Analog and REF Input Range LTC1196 –0.05V to VCC + 0.05V V

Analog Input Leakage Current (Note 5) l±1 ±1 μA

LTC1196/LTC1198

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DIGITAL AND DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply

over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ISOURCE Output Source Current VOUT = 0V –10 mA

ISINK Output Sink Current VOUT = VCC 15 mA

IREF Reference Current, LTC1196 CS = VCC

fSMPL = fSMPL(MAX)

0.001

0.25

3.0

0.5

μA

ICC Supply Current CS = VCC = 3.3V, LTC1198 (Shutdown)

CS = VCC = 3.3V, LTC1196

fSMPL = fSMPL(MAX), LTC1196/LTC1198

0.001

1.5

2.0

3.0

4.5

6.0

μA

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as deﬁ ned in Recommended Operating Conditions,

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN

LTC1196

TYP MAX MIN

LTC1198

TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion 190kHz/380kHz Input Signal 47/45 47/45 dB

THD Total Harmonic Distortion 190kHz/380kHz Input Signal 49/47 49/47 dB

Peak Harmonic or Spurious Noise 190kHz/380kHz Input Signal 53/46 53/46 dB

IMD Intermodulation Distortion fIN1 = 189.37kHz

fIN2 = 192.446kHz

51 51 dB

Full-Power Bandwidth 5 5 MHz

Full Linear Bandwidth [S/(N + D) > 44dB 0.5 0.5 MHz

AC CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as deﬁ ned in Recommended Operating Conditions,

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN

LTC1196-1

LTC1198-1

TYP MAX MIN

LTC1196-2

LTC1198-2

TYP MAX UNITS

tCONV Conversion Time (See Figures 1, 2)

1.58

1.85

2.13

2.84

μs

fSMPL(MAX) Maximum Sampling Frequency LTC1196

LTC1196

LTC1198

450

383

337

287

333

250

187

kHz

tdDO Delay Time, CLK↑ to DOUT Data Valid CLOAD = 20pF

100 150

180

130 200

250

tDIS Delay Time CS↑ to DOUT Hi-Z l110 220 120 250 ns

ten Delay Time, CLK↓ to DOUT Enabled CLOAD = 20pF l80 130 100 200 ns

thDO Time Output Data Remains Valid After

CLK↑CLOAD = 20pF l45 90 45 120 ns

tfDOUT Fall Time CLOAD = 20pF l10 30 15 40 ns

trDOUT Rise CLOAD = 20pF l10 30 15 40 ns

CIN Input Capacitance Analog Input On Channel

Analog Input Off Channel

Digital Input

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

LTC1196/LTC1198

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FREQUENCY (MHz)

SUPPLY CURRENT (mA)

1196/98 G01

216

468

10 14

TA = 25°C

CS = 0V

VREF = VCC

VCC = 5V

VCC = 2.7V

SUPPLY VOLTAGE (V)

2.5

04.0 5.0

1196/98 G02

3.0 3.5 4.5 5.5 6.0

SUPPLY CURRENT (mA)

TA = 25°C

0.000002

LTC1196

LTC1198

ACTIVE MODE

CS = 0V

SHUTDOWN MODE

CS = VCC

LTC1198

SAMPLE RATE (Hz)

0.01

SUPPLY CURRENT (mA)

0.1

100 10k 100k

1196/98 G03

0.001

1k 1M

LT1196 VCC = 5V

LT1196 VCC = 2.7V

LT1198 VCC = 5V

LT1198 VCC = 2.7V

TA = 25°C

TEMPERATURE (°C)

–55

SUPPLY CURRENT (mA)

0–15 25 45 125

1196/98 G04

–35 5 65 85 105

CS = 0V

VCC = 5V

VCC = 2.7V

REFERENCE VOLTAGE (V)

0.5

MAGNITUDE OF OFFSET (LSB = s VREF)

5.0

1196/98 G05

3.52.5 4.0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

01.0 2.0

1.5 4.53.0

TA = 25°C

VCC = 5V

fCLK = 12MHz

256

SUPPLY VOLTAGE (V)

2.5

MAGNITUDE OF OFFSET (LSB)

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5 3.5 4.5 5.0

1196/98 G06

3.0 4.0 5.5 6.0

TA = 25°C

VREF = VCC

fCLK = 3MHz

Note 2: All voltage values are with respect to GND.

Note 3: Integral nonlinearity is deﬁ ned as deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 4: Total unadjusted error includes offset, full scale, linearity,

multiplexer and hold step errors.

Note 5: Channel leakage current is measured after the channel selection.

ELECTRICAL CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current vs Clock Rate Supply Current vs Supply Voltage Supply Current vs Sample Rate

Supply Current vs Temperature Offset vs Reference Voltage Offset vs Supply Voltage

LTC1196/LTC1198

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TYPICAL PERFORMANCE CHARACTERISTICS

Linearity Error

vs Reference Voltage Linearity Error vs Supply Voltage Supply Current vs Sample Rate

Minimum Clock Rate for

0.1LSB* Error

ADC Noise vs Referenced

and Supply Voltage

Sample-and-Hold Acquisition

Time vs Source Resistance

Gain vs Supply Voltage

Maximum Clock Frequency

vs Supply Voltage

Maximum Clock Frequency

vs Source Resistance

REFERENCE VOLTAGE (V)

LINEARITY ERROR (LSB)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1196/98 G07

0.5 5.0

3.52.5 4.0

1.0 2.0

1.5 4.53.0

TA = 25°C

VCC = 5V

fCLK = 12MHz

SUPPLY VOLTAGE (V)

2.5

LINEARITY ERROR (LSB)

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5 3.5 4.5 5.0

1196/98 G08

3.0 4.0 5.5 6.0

TA = 25°C

VREF = VCC

fCLK = 3MHz

REFERENCE VOLTAGE (V)

MAGNITUDE OF GAIN ERROR (LSB)

4.0

1196/98 G09

1.0 2.0 3.0 5.0

0.5 1.5 2.5 3.5 4.5

TA = 25°C

VCC = 5V

fCLK = 12MHz

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

SUPPLY VOLTAGE (V)

2.5

MAGNITUDE OF GAIN ERROR (LSB)

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5 3.5 4.5 5.0

1196/98 G10

3.0 4.0 5.5 6.0

TA = 25°C

fCLK = 3MHz

VREF = VCC

SUPPLY VOLTAGE (V)

2.5

4.0 5.0

1196/98 G11

3.0 3.5 4.5 5.5 6.0

MAXIMUM CLOCK FREQUENCY (MHz)

TA = 25°C

VREF = VCC

SOURCE RESISTANCE (Ω)

CLOCK FREQUENCY (MHz)

1100 1k 100k

1196/98 G12

10 10k

TA = 25°C

VCC = VREF = 5V

RSOURCE–

VIN +IN

–IN

TEMPERATURE (°C)

–55

MINIMUM CLOCK FREQUENCY (kHz)

100

0–15 25 45 125

1196/98 G13

–35 5 65 85 105

VCC = 5V

VREF = 5V

SUPPLY VOLTAGE (V)

2.5

0.35

0.30

0.25

0.20

0.15

0.10

0.05

4.0 5.0

1196/98 G14

3.0 3.5 4.5 5.5 6.0

PEAK-TO-PEAK ADC NOISE (LSB)

TA = 25°C

VREF = VCC

SOURCE RESISTANCE (Ω)

100

S&H ACQUISITION TIME (ns)

1000

10000

100 10k

1196/98 G15

10 1k

TA = 25°C

VCC = VREF = 5V

RSOURCE+

VIN +IN

–IN

*AS THE FREQUENCY IS DECREASED FROM 12MHz, MINIMUM CLOCK FREQUENCY (ΔERROR ≤ 0.1LSB) REPRESENTS THE

FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 12MHz VALUE IS FIRST DETECTED.

LTC1196/LTC1198

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TYPICAL PERFORMANCE CHARACTERISTICS

Differential Nonlinearity

vs Code at 2.7V

Effective Bits and S/(N + D)

vs Input Frequency

Digital Input Logic Threshold

vs Supply Voltage

DOUT Delay Time

vs Supply Voltage DOUT Delay Time vs Temperature

Input Channel Leakage Current

vs Temperature Integral Nonlinearity

vs Code at 5V

Differential Nonlinearity

vs Code at 5V

SUPPLY VOLTAGE (V)

2.5

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

4.0 5.0

1196/98 G16

3.0 3.5 4.5 5.5 6.0

LOGIC THRESHOLD (V)

TA = 25°C

SUPPLY VOLTAGE (V)

2.5

140

120

100

4.0 5.0

1196/98 G17

3.0 3.5 4.5 5.5 6.0

DOUT DELAY TIME, tdDO (ns)

TA = 25°C

VREF = VCC

TEMPERATURE (°C)

–60

DOUT DELAY TIME, tdDO (ns)

160

140

120

100

0100

1196/98 G18

–20 20 60 140

–40 040 80 120

VCC = 5V

VREF = VCC

VCC = 2.7V

Integral Nonlinearity

vs Code at 2.7V

TEMPERATURE (°C)

–60

LEAKAGE CURRENT (nA)

1000

100

0.1

0.01

100

1196/98 G19

–20 20 60 140

–40 040 80 120

VCC = 5V

VREF = 5V

ON CHANNEL

OFF CHANNEL

CODE

INTEGRAL NONLINEARITY ERROR (LSB)

0.5

64 128 160

1196/98 G20

32 96 192 224 256

–0.5

VCC = 5V

VREF = 5V

fCLK = 12MHz

CODE

DIFFERENTIAL NONLINEARITY ERROR (LSB)

0.5

64 128 160

1196/98 G21

32 96 192 224 256

–0.5

VCC = 5V

VREF = 5V

fCLK = 12MHz

CODE

INTEGRAL NONLINEARITY ERROR (LSB)

0.5

64 128 160

1196/98 G22

32 96 192 224 256

–0.5

VCC = 2.7V

VREF = 2.5V

fCLK = 3MHz

CODE

DIFFERENTIAL NONLINEARITY ERROR (LSB)

0.5

64 128 160

1196/98 G23

32 96 192 224 256

–0.5

VCC = 2.7V

VREF = 2.5V

fCLK = 3MHz

INPUT FREQUENCY (Hz)

S/(N + D) (dB)

10k 100k 1M

1196/98 G24

EFFECTIVE NUMBER OF BITS (ENOBs)

VREF =V

CC = 2.7V

fSMPL = 383kHz (LTC1196)

fSMPL = 287kHz (LTC1198)

VREF =V

CC = 5V

fSMPL = 1MHz (LTC1196)

fSMPL = 750kHz (LTC1198)

TA= 25°C

LTC1196/LTC1198

119698fb

TYPICAL PERFORMANCE CHARACTERISTICS

4096 Point FFT Plot at 5V

FFT Output of 455kHz AM Signal

Digitized at 1Msps

4096 Point FFT Plot at 2.7V

FREQUENCY (kHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 400

1196/98 G25

100 200 300 500

VCC = 5V

fIN = 29kHz

fSMPL = 882kHz

MAGNITUDE (dB)

FREQUENCY (kHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 150

1196/98 G26

50 100 200

VCC = 2.7V

fIN = 29kHz

fSMPL = 340kHz

MAGNITUDE (dB)

FREQUENCY (kHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 400

1196/98 G27

100 200 300 500

VCC = 5V

fIN = 455kHz WITH 20kHz AM

fSMPL = 1MHz

MAGNITUDE (dB)

Power Supply Feedthrough

vs Ripple Frequency

Power Supply Feedthrough

vs Ripple Frequency

S/(N + D) vs Reference Voltage

and Input Frequency

RIPPLE FREQUENCY (Hz)

–10

–20

–30

–40

–50

–60

–70

10k 100k 1M

1196/98 G28

FEEDTHROUGH (dB)

TA = 25°C

VCC (VRIPPLE = 20mV)

fCLK = 12MHz

RIPPLE FREQUENCY (Hz)

–10

–20

–30

–40

–50

–60

–70

10k 100k 1M

1196/98 G29

FEEDTHROUGH (dB)

TA = 25°C

VCC (VRIPPLE = 10mV)

fCLK = 5MHz

REFERENCE VOLTAGE (V)

1.25

SIGNAL TO NOISE PLUS DISTORTION (dB)

25 2.75 3.75 5.25

1196/98 G30

1.75 2.25 3.25 4.25 4.75

VCC = 5V

fIN = 500kHz

fIN = 200kHz

fIN = 100kHz

Intermodulation Distortion at 2.7V Intermodulation Distortion at 5V S/(N + D) vs Input Level

FREQUENCY (kHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 200

1196/98 G31

50 100 150 250

VCC = 2.7V

f1 = 100kHz

f2 = 110kHz

fSMPL = 420kHz

MAGNITUDE (dB)

FREQUENCY (kHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 300

1196/98 G32

100 200 400

VCC = 5V

f1 = 200kHz

f2 = 210kHz

fSMPL = 750kHz

MAGNITUDE (dB)

INPUT LEVEL (dB)

–40

SIGNAL TO NOISE-PLUS-DISTORTION (dB)

0–25 –15 0

1196/98 G33

–35 –30 –20 –10 –5

VREF = VCC = 5V

fIN = 500kHz

fSMPL = 1MHz

LTC1196/LTC1198

119698fb

TYPICAL PERFORMANCE CHARACTERISTICS

Spurious-Free Dynamic Range

vs Frequency

Output Amplitude

vs Input Frequency

INPUT FREQUENCY (Hz)

PEAK-TO-PEAK OUTPUT (%)

10M

1196/98 G34

10k 100k 1M

100

VREF = VCC = 2.7V

VREF = VCC = 5V

FREQUENCY (Hz)

1196/98 G35

10k 100k 10M

SPURIOUS-FREE DYNAMIC RANGE (dB)

TA = 25°C

VCC = 3V

fCLK = 5MHz

VCC = 5V

fCLK = 12MHz

PIN FUNCTIONS

LTC1196

CS (Pin 1): Chip Select Input. A logic LOW on this input

enables the LTC1196. A logic HIGH on this input disables

the LTC1196.

IN+ (Pin 2): Analog Input. This input must be free of noise

with respect to GND.

IN– (Pin 3): Analog Input. This input must be free of noise

with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

VREF (Pin 5): Reference Input. The reference input deﬁ nes

the span of the A/D converter and must be kept free of

noise with respect to GND.

DOUT (Pin 6): Digital Data Output. The A/D conversion

result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the se-

rial data transfer.

VCC (Pin 8): Power Supply Voltage. This pin provides power

to the A/D converter. It must be kept free of noise and ripple

by bypassing directly to the analog ground plane.

LTC1198

CS/SHUTDOWN (Pin 1): Chip Select Input. A logic LOW

on this input enables the LTC1198. A logic HIGH on this

input disables the LTC1198 and disconnects the power

to THE LTC1198.

CHO (Pin 2): Analog Input. This input must be free of

noise with respect to GND.

CH1 (Pin 3): Analog Input. This input must be free of noise

with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

DIN (Pin 5): Digital Data Input. The multiplexer address is

shifted into this input.

DOUT (Pin 6): Digital Data Output. The A/D conversion

result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the se-

rial data transfer.

VCC (VREF) (Pin 8): Power Supply and Reference Volt-

age. This pin provides power and deﬁ nes the span of the

A/D converter. It must be kept free of noise and ripple by

bypassing directly to the analog ground plane.

LTC1196/LTC1198

119698fb

BLOCK DIAGRAM

–

CSMPL

BIAS AND

SHUTDOWN CIRCUIT SERIAL PORT

VCC (VCC/VREF) CLK

DOUT

IN+ (CH0)

IN– (CH1)

HIGH SPEED

COMPARATOR

CAPACITIVE DAC

SAR

VREF (DIN)GND

PIN NAMES IN PARENTHESES

REFER TO THE LTC1198

(CS/SHUTDOWN)

1196/98 BD

TEST CIRCUITS

On and Off Channel Leakage Current

IOFF

ION

POLARITY

OFF

CHANNEL

ON CHANNEL

1196/98 TC01

•

Load Circuit for tdDO, tr and tf

DOUT

1.4V

100pF

TEST POINT

1196/98 TC02

Voltage Waveform for DOUT Rise and Fall Times, tr

, tfVoltage Waveform for DOUT Delay Time, tdDO

, thDO

DOUT

VOL

VOH

trtf1196/98 TC04

CLK

DOUT

tdDO

1196/98 TC03

VIH

thDO

VOH

VOL

LTC1196/LTC1198

119698fb

TEST CIRCUITS

Load Circuit for tdis and ten Voltage Waveforms for tdis

DOUT

20pF

TEST POINT

VCC tdis WAVEFORM 2, ten

tdis WAVEFORM 1

1196/98 TC05

DOUT

WAVEFORM 1

(SEE NOTE 1)

VIH

tdis

90%

10%

DOUT

WAVEFORM 2

(SEE NOTE 2)

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

1196/98 TC06

Voltage Waveforms for ten

1196/98 TC07

LTC1196

CLK

DOUT

ten

VOL

234

Voltage Waveforms for ten

1234 5

LTC1198

DIN

CLK

START

DOUT

ten

VOL

1196/98 TC08

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

OVERVIEW

The LTC1196/LTC1198 are 600ns sampling 8-bit A/D con-

verters packaged in tiny 8-pin SO packages and operating

on 3V to 6V supplies. The ADCs draw only 10mW from a

3V supply or 50mW from a 5V supply.

Both the LTC1196 and the LTC1198 contain an 8-bit,

switched-capacitor ADC, a sample-and-hold, and a serial

port (see the Block Diagram). The on-chip sample-and-

holds have full-accuracy input bandwidths of 1MHz.

Although they share the same basic design, the LTC1196

and LTC1198 differ in some respects. The LTC1196 has

a differential input and has an external reference input

pin. It can measure signals ﬂ oating on a DC common

mode voltage and can operate with reduced spans below

1V. The LTC1198 has a 2-channel input multiplexer and

can convert either channel with respect to ground or the

difference between the two. It also automatically powers

down when not performing conversion, drawing only

leakage current.

SERIAL INTERFACE

The LTC1196/LTC1198 will interface via three or four wires

to ASICs, PLDs, microprocessors, DSPs, or shift registers

(see Operating Sequence in Figures 1 and 2). To run at their

fastest conversion rates (600ns), they must be clocked at

14.4MHz. HC logic families and any high speed ASIC or

PLD will easily interface to the ADCs at that speed (see

Data Transfer and Typical Application sections). Full speed

operation from a 3V supply can still be achieved with 3V

ASICs, PLDs or HC logic circuits.

B3B4B5

tsuCS

tdDO

NULL

BITS

Hi-Z

DOUT

1196/98 F01

Hi-Z

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY

B0*

NULL BITSB0

tCYC (12 CLKs)

tCYC (8.5 CLKs)

tSMPL tSMPL

1196/98 F02

POWER

DOWN

SGL/

DIFF

DUMMY

B3B4B5B6

NULL BITS

Hi-Z

HI-Z

START ODD/

SIGN

DON’T CARE

B0*

B2 B1

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY

DUMMY

tdDO

CLK

DIN

DOUT

tsuCS

tCYC (16 CLKs)

tCONV (8.5 CLKs)tSMPL (2.5 CLKs)

Figure 2. LTC1198 Operating Sequence Example: Differential Inputs (CH1, CH0)

Figure 1. LTC1196 Operating Sequence

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

Connection to a microprocessor or a DSP serial port is

quite simple (see the Data Transfer section). It requires no

additional hardware, but the speed will be limited by the

clock rate of the microprocessor or the DSP which limits

the conversion time of the LTC1196/LTC1198.

Data Transfer

Data transfer differs slightly between the LTC1196 and

the LTC1198. The LTC1196 interfaces over three lines:

CS, CLK and DOUT

. A falling CS initiates data transfer as

depicted by the LTC1196 Operating Sequence in Figure 1.

After CS falls, the ﬁ rst CLK pulse enables DOUT

. After two

null bits, the A/D conversion result is output on the DOUT

line. Bringing CS HIGH resets the LTC1196 for the next

data exchange.

The LTC1198 can transfer data with three or four wires.

The additional input, DIN, is used to select the 2-channel

MUX conﬁ guration.

The data transfer between the LTC1198 and the digital

systems can be broken into two sections: Input Data

Word and A/D Conversion Result. First, each bit of the

input data word is captured on the rising CLK edge by the

LTC1198. Second, each bit of the A/D conversion result

on the DOUT line is updated on the rising CLK edge by the

LTC1198. This bit should be captured on the next rising

CLK edge by the digital systems (see the A/D Conversion

Result section).

Data transfer is initiated by a falling chip select (CS) signal

as depicted by the LTC1198 Operating Sequence in Figure 2.

After CS falls, the LTC1198 looks for a START bit. After

the START bit is received, the 4-bit input word is shifted

into the DIN input. The ﬁ rst two bits of the input word

conﬁ gure the LTC1198. The last two bits of the input word

allow the ADC to acquire the input voltage by 2.5 clocks

before the conversion starts. After the conversion starts,

two null bits and the conversion result are output on the

DOUT line. At the end of the data exchange CS should be

brought HIGH. This resets the LTC1198 in preparation for

the next data exchange.

Input Data Word

The LTC1196 requires no DIN word. It is permanently con-

ﬁ gured to have a single differential input. The conversion

result is output on the DOUT line in an MSB-ﬁ rst sequence,

followed by zeros indeﬁ nitely if clocks are continuously

applied with CS LOW.

The LTC1198 clocks data into the DIN input on the ris-

ing edge of the clock. The input data word is deﬁ ned as

follows:

DIN1 DIN2

DOUT1 DOUT2

SHIFT MUX

ADDRESS IN

2 NULL BITS SHIFT A/D CONVERSION

RESULT OUT 1196/98 AI01

SGL/

DIFF

ODD/

SIGN DUMMY

START

MUX

ADDRESS

DUMMY

BITS

119698 AI02

DUMMY

START Bit

The ﬁ rst

logical one

clocked into the DIN input after CS

goes LOW is the START bit. The START bit initiates the data

transfer. The LTC1198 will ignore all leading zeros which

precede this

logical one

. After the START bit is received,

the remaining bits of the input word will be clocked in.

Further inputs on the DIN pin are then ignored until the

next CS cycle.

Multiplexer (MUX) Address

The two bits of the input word following the START bit as-

sign the MUX conﬁ guration for the requested conversion.

For a given channel selection, the converter will measure

the voltage between the two channels indicated by the “+”

and “–” signs in the selected row of the following table.

In single-ended mode, all input channels are measured

with respect to GND.

MUX ADDRESS

SGL/DIFF

ODD/SIGN

CHANNEL #

–

GND

–

SINGLE-ENDED

MUX MODE

DIFFERENTIAL

MUX MODE

1196/98 AI03

LTC1198 Channel Selection

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

Dummy Bits

The last two bits of the input word following the MUX ad-

dress are dummy bits. Either bit can be a

logical one

or a

logical zero

. These two bits allow the ADC 2.5 clocks to

acquire the input signal after the channel selection.

A/D Conversion Result

Both the LTC1196 and the LTC1198 have the A/D conver-

sion result appear on the DOUT line after two null bits (see

the operating sequences in Figures 1 and 2). Data on the

DOUT line is updated on the rising edge of the CLK line.

The DOUT data should also be captured on the rising CLK

edge by the digital systems. Data on the DOUT line remains

valid for a minimum time of thDO (30ns at 5V) to allow the

capture to occur (see Figure 3).

Unipolar Transfer Curve

The LTC1196/LTC1198 are permanently conﬁ gured for

unipolar only. The input span and code assignment for this

conversion type are shown in the following ﬁ gures.

CLK VIH

tdDO

DOUT

1196/98 TC03

thDO

Figure 3. Voltage Waveform for DOUT Delay Time, tdDO and thDO

Unipolar Transfer Curve

0V 1LSB VREF –

2LSB

VREF –

1LSB

VREF

VIN

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

•

1196/98 AI04

Unipolar Output Code

OUTPUT CODE

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

•

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

INPUT VOLTAGE

VREF – 1LSB

VREF – 2LSB

•

1LSB

INPUT VOLTAGE

(VREF = 5.000V)

4.9805V

4.9609V

•

0.0195V

1196/98 AI05

12 3 4

CLK

DATA (DIN/DOUT)START SGL/DIFF ODD/SIGN

DUMMY BITS LATCHED

BY LTC1198

LTC1198 CONTROLS DATA LINE AND SENDS

A/D RESULT BACK TO THE DIGITAL SYSTEM

THE DIGITAL SYSTEM CONTROLS DATA LINE

AND SENDS MUX ADDRESS TO LTC1198

THE DIGITAL SYSTEM MUST RELEASE DATA LINE AFTER

5TH RISING CLK AND BEFORE THE 5TH FALLING CLK

LTC1198 TAKES CONTROL OF

DATA LINE ON 5TH FALLING CLK

1196/98 F04

DUMMY

Figure 4. LTC1198 Operation with DIN and DOUT Tied Together

Operation with DIN and DOUT Tied Together

The LTC1198 can be operated with DIN and DOUT tied

together. This eliminates one of the lines required to com-

municate to the digital systems. Data is transmitted in both

directions on a single wire. The pin of the digital systems

connected to this data line should be conﬁ gurable as either

an input or an output. The LTC1198 will take control of

the data line and drive it LOW on the ﬁ fth falling CLK edge

after the START bit is received (see Figure 4). Therefore,

the port line of the digital systems must be switched to

an input before this happens to avoid a conﬂ ict.

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

REDUCING POWER CONSUMPTION

The LTC1196/LTC1198 can sample at up to a 1MHz rate,

drawing only 50mW from a 5V supply. Power consumption

can be reduced in two ways. Using a 3V supply lowers the

power consumption on both devices by a factor of ﬁ ve,

to 10mW. The LTC1198 can reduce power even further

because it shuts down whenever it is not converting.

Figure 5 shows the supply current versus sample rate for

the LTC1196 and LTC1198 on 3V and 5V. To achieve such

a low power consumption, especially for the LTC1198,

several things must be taken into consideration.

DIN and CLK with CS = HIGH; they can continue to run

without drawing current.

Minimize CS LOW Time (LTC1198)

In systems that have signiﬁ cant time between conver-

sions, lowest power drain will occur with the minimum CS

LOW time. Bringing CS LOW, transferring data as quickly

as possible, then bringing it back HIGH will result in the

lowest current drain. This minimizes the amount of time

the device draws power.

OPERATING ON OTHER THAN 5V SUPPLIES

The LTC1196/LTC1198 operate from single 2.7V to 6V

supplies. To operate the LTC1196/LTC1198 on other than

5V supplies, a few things must be kept in mind.

Input Logic Levels

The input logic levels of CS, CLK and DIN are made to

meet TTL on 5V supply. When the supply voltage varies,

the input logic levels also change (see the Digital Input

Logic Threshold vs Supply Voltage curve in the Typical

Performance Characteristics section). For these two ADCs

to sample and convert correctly, the digital inputs have to

be in the logical LOW and HIGH relative to the operating

supply voltage. If achieving micropower consumption

is desirable on the LTC1198, the digital inputs must go

rail-to-rail between supply voltage and ground (see the

Reducing Power Consumption section).

Clock Frequency

The maximum recommended clock frequency is 14.4MHz

at 25°C for the LTC1196/LTC1198 running off a 5V supply.

With the supply voltage changing, the maximum clock

frequency for the devices also changes (see the Maximum

Clock Rate vs Supply Voltage curve in the Typical Perfor-

mance Characteristics section). If the supply is reduced,

the clock rate must also be reduced. At 3V, the devices

are speciﬁ ed with a 5.4MHz clock at 25°C.

SAMPLE RATE (Hz)

0.01

SUPPLY CURRENT (mA)

0.1

100 10k 100k

1196/98 F05

0.001

1k 1M

LT1198 VCC = 2.87V

LT1196 VCC = 2.87V

LT1198 VCC = 5V

Figure 5. Supply Current vs Sample Rate for LTC1196/LTC1198

Operating on 5V and 2.7V Supplies

Shutdown (LTC1198)

Figure 2 shows the operating sequence of the LTC1198.

The converter draws power when the CS pin is LOW and

powers itself down when that pin is HIGH. For lowest

power consumption in shutdown, the CS pin should be

driven with CMOS levels (0V to VCC) so that the CS input

buffer of the converter will not draw current.

When the CS pin is HIGH (= supply voltage), the LTC1198

is in shutdown mode and draws only leakage current.

The status of the DIN and CLK input has no effect on the

supply current during this time. There is no need to stop

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

Mixed Supplies

It is possible to have a digital system running off a 5V supply

and communicate with the LTC1196/LTC1198 operating on

a 3V supply. Achieving this reduces the outputs of DOUT

from the ADCs to toggle the equivalent input of the digital

system. The CS, CLK and DIN inputs of the ADCs will take

5V signals from the digital system without causing any

problem (see the Digital Input Logic Threshold vs Supply

Voltage curve in the Typical Performance Characteristics

section). With the LTC1196 operating on a 3V supply, the

output of DOUT only goes between 0V and 3V. This signal

easily meets TTL levels (see Figure 6).

BOARD LAYOUT CONSIDERATIONS

Grounding and Bypassing

The LTC1196/LTC1198 are easy to use if some care is

taken. They should be used with an analog ground plane

and single-point grounding techniques. The GND pin

should be tied directly to the ground plane.

The VCC pin should be bypassed to the ground plane with a

1μF tantalum with leads as short as possible. If the power

supply is clean, the LTC1196/LTC1198 can also operate

with smaller 0.1μF surface mount or ceramic bypass ca-

pacitors. All analog inputs should be referenced directly to

the single-point ground. Digital inputs and outputs should

be shielded from and/or routed away from the reference

and analog circuitry.

SAMPLE-AND-HOLD

Both the LTC1196 and the LTC1198 provide a built-in

sample-and-hold (S&H) function to acquire the input

signal. The S&H acquires the input signal from “+” input

during tSMPL as shown in Figures 1 and 2. The S&H of the

LTC1198 can sample input signals in either single-ended

or differential mode (see Figure 7).

4.7μF

MPU

(e.g., 8051) 5V

P1.4

P1.3

P1.2

1196/98 F06

DIFFERENTIAL INPUTS

COMMON MODE RANGE

0V TO 3V

VCC

CLK

DOUT

VREF

LTC1196

–IN

GND

+IN

Figure 6. Interfacing a 3V Powered LTC1196 to a 5V System

CLK

DIN

DOUT

+ INPUT

– INPUT

DLOHELPMAS

+ INPUT MUST

SETTLE DURING

THIS TIME

tSMPL tCONV

START SGL/DIFF DUMMY

1ST BIT TEST:

– INPUT MUST SETTLE DURING THIS TIME

1196/98 F07

ODD/SIGN DUMMY DON’T CARE

Figure 7. LTC1198 “+” and “–” Input Settling Windows

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

Single-Ended Inputs

The sample-and-hold of the LTC1198 allows conversion

of rapidly varying signals. The input voltage is sampled

during the tSMPL time as shown in Figure 7. The sampling

interval begins as the bit preceding the ﬁ rst dummy bit

is shifted in and continues until the falling CLK edge after

the second dummy bit is received. On this falling edge, the

S&H goes into hold mode and the conversion begins.

Differential Inputs

With differential inputs, the ADC no longer converts just a

single voltage but rather the difference between two volt-

ages. In this case, the voltage on the selected “+” input

is still sampled and held and therefore may be rapidly

time varying just as in single-ended mode. However, the

voltage on the selected “–” input must remain constant

and be free of noise and ripple throughout the conversion

time. Otherwise, the differencing operation may not be

performed accurately. The conversion time is 8.5 CLK

cycles. Therefore, a change in the “–” input voltage during

this interval can cause conversion errors. For a sinusoidal

voltage on the “–” input, this error would be:

ERROR(MAX) = VPEAK • 2 • π • f(–) • 8.5/fCLK

where f(“–”) is the frequency of the “–” input voltage, VPEAK

is its peak amplitude and fCLK is the frequency of the CLK.

VERROR is proportional to f(–) and inversely proportional

to fCLK. For a 60Hz signal on the “–” input to generate a

1/4LSB error (5mV) with the converter running at CLK =

12MHz, its peak value would have to be 18.7V.

ANALOG INPUTS

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1196/LTC1198

have one capacitive switching input current spike per

conversion. These current spikes settle quickly and do

not cause a problem. However, if source resistances larger

than 100Ω are used or if slow settling op amps drive the

inputs, care must be taken to insure that the transients

caused by the current spikes settle completely before the

conversion begins.

“+” Input Settling

The input capacitor of the LTC1196 is switched onto

“+” input at the end of the conversion and samples the

input signal until the conversion begins (see Figure 1).

The input capacitor of the LTC1198 is switched onto “+”

input during the sample phase (tSMPL, see Figure 7). The

sample phase is 2.5 CLK cycles before conversion starts.

The voltage on the “+” input must settle completely within

tSMPL for the LTC1196/LTC1198. Minimizing RSOURCE+

will improve the input settling time. If a large “+” input

source resistance must be used, the sample time can be

increased by allowing more time between conversions

for the LTC1196 or by using a slower CLK frequency for

the LTC1198.

“–” Input Settling

At the end of the tSMPL, the input capacitor switches to the

“–” input and conversion starts (see Figures 1 and 7). During

the conversion, the “+” input voltage is effectively “held”

by the sample-and-hold and will not affect the conversion

result. However, it is critical that the “–” input voltage settle

completely during the ﬁ rst CLK cycle of the conversion time

and be free of noise. Minimizing RSOURCE– will improve

settling time. If a large “–” input source resistance must

be used, the time allowed for settling can be extended by

using a slower CLK frequency.

Input Op Amps

When driving the analog inputs with an op amp it is im-

portant that the op amp settle within the allowed time (see

Figures 1 and 7). Again, the “+” and “–” input sampling

times can be extended as described above to accommodate

slower op amps.

To achieve the full sampling rate, the analog input should

be driven with a low impedance source (<100Ω) or a

high speed op amp (e.g., the LT1223, LT1191 or LT1226).

Higher impedance sources or slower op amps can easily

be accommodated by allowing more time for the analog

input to settle as described above.

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

Source Resistance

The analog inputs of the LTC1196/LTC1198 look like

a 25pF capacitor (CIN) in series with a 120Ω resistor

(RON) as shown in Figure 8. CIN gets switched between

the selected “+” and “–” inputs once during each con-

version cycle. Large external source resistors will slow

the settling of the inputs. It is important that the overall

RC time constants be short enough to allow the analog

inputs to completely settle within tSMPL.

REFERENCE INPUT

The voltage on the reference input of the LTC1196 deﬁ nes

the voltage span of the A/D converter. The reference

input has transient capacitive switching currents which

are due to the switched-capacitor conversion technique

(see Figure 9). During each bit test of the conversion

(every CLK cycle), a capacitive current spike will be

generated on the reference pin by the ADC. These high

frequency current spikes will settle quickly and do not

cause a problem if the reference input is bypassed with

at least a 0.1μF capacitor.

The reference input can be driven with standard volt-

age references. Bypassing the reference with a 0.1μF

capacitor is recommended to keep the high frequency

impedance low as described above. Some references

require a small resistor in series with the bypass capaci-

tor for frequency stability. See the individual reference

data sheet for details.

Reduced Reference Operation

The minimum reference voltage of the LTC1198 is limited

to 2.7V because the VCC supply and reference are internally

tied together. However, the LTC1196 can operate with

reference voltages below 1V.

The effective resolution of the LTC1196 can be increased

by reducing the input span of the converter. The LTC1196

exhibits good linearity and gain over a wide range of

reference voltages (see the Linearity and Full-Scale Error

vs Reference Voltage curves in the Typical Performance

Characteristics section). However, care must be taken when

operating at low values of VREF because of the reduced

LSB step size and the resulting higher accuracy require-

ment placed on the converter. The following factors must

be considered when operating at low VREF values.

1. Offset

2. Noise

Offset with Reduced VREF

The offset of the LTC1196 has a larger effect on the output

code when the ADC is operated with reduced reference

voltage. The offset (which is typically a ﬁ xed voltage) be-

comes a larger fraction of an LSB as the size of the LSB is

reduced. The Unadjusted Offset Error vs Reference Voltage

curve in the Typical Performance Characteristics section

depicts how offset in LSBs is related to reference voltage

for a typical value of VOS. For example, a VOS of 2mV which

is 0.1LSB with a 5V reference becomes 0.5LSB with a 1V

reference and 2.5LSB with a 0.2V reference. If this offset is

unacceptable, it can be corrected digitally by the receiving

system or by offsetting the “–” input of the LTC1196.

RON

120Ω

CIN

25pF

LTC1196

LTC1198

INPUT

VIN+

–

INPUT

RSOURCE–

RSOURCE+

VIN–

1196/98 F08

ltSMPL

tSMPLn

Figure 8. Analog Input Equivalent Circuit

5pF TO

30pF

LTC1196

REF

OUT

REF

EVERY CLK CYCLE

GND

1196/98 F09

Figure 9. Reference Input Equivalent Circuit

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

Noise with Reduced VREF

The total input referred noise of the LTC1196 can be

reduced to approximately 2mVP-P using a ground plane,

good bypassing, good layout techniques and minimizing

noise on the reference inputs. This noise is insigniﬁ cant

with a 5V reference but will become a larger fraction of

an LSB as the size of the LSB is reduced.

For operation with a 5V reference, the 2mV noise is only

0.1LSB peak-to-peak. In this case, the LTC1196 noise

will contribute virtually no uncertainty to the output code.

However, for reduced references, the noise may become

a signiﬁ cant fraction of an LSB and cause undesirable jit-

ter in the output code. For example, with a 1V reference,

this same 2mV noise is 0.5LSB peak-to-peak. This will

reduce the range of input voltages over which a stable

output code can be achieved by 1LSB. If the reference is

further reduced to 200mV, the 2mV noise becomes equal

to 2.5LSB and a stable code is difﬁ cult to achieve. In this

case averaging readings is necessary.

This noise data was taken in a very clean setup. Any setup

induced noise (noise or ripple on VCC, VREF or VIN) will

add to the internal noise. The lower the reference voltage

to be used, the more critical it becomes to have a clean,

noise-free setup.

DYNAMIC PERFORMANCE

The LTC1196/LTC1198 have exceptionally high speed

sampling capability. Fast Fourier Transform (FFT) test

techniques are used to characterize the ADC’s frequency

response, distortion and noise at the rated throughput. By

applying a low distortion sine wave and analyzing the digital

output using a FFT algorithm, the ADC’s spectral content

can be examined for frequencies outside the fundamental.

Figure 10 shows a typical LTC1196 FFT plot.

Signal-to-Noise Ratio

The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is

the ratio between the RMS amplitude of the fundamental

input frequency to the RMS amplitude of all other frequency

components at the ADC’s output. The output is band limited

to frequencies above DC and below one half the sampling

frequency. Figure 10 shows a typical spectral content with

a 882kHz sampling rate.

Effective Number of Bits

The Effective Number of Bits (ENOBs) is a measurement

of the resolution of an ADC and is directly related to

S/(N + D) by the equation:

N = [S/(N + D) –1.76]/6.02

FREQUENCY (kHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 400

1196/98 G25

100 200 300 500

VCC = 5V

fIN = 29kHz

fSMPL = 882kHz

MAGNITUDE (dB)

Figure 10. LTC1196 Nonaveraged, 4096 Point FFT Plot

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

where N is the effective number of bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling

rate of 1.2MHz with a 5V supply the LTC1196 maintains

above 7.5 ENOBs at 400kHz input frequency. Above 500kHz

the ENOBs gradually decline, as shown in Figure 11, due

to increasing second harmonic distortion. The noise ﬂ oor

remains low.

Figure 11. Effective Bits and S/(N + D) vs Input Frequency

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the RMS

sum of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half of the sampling frequency. THD

is deﬁ ned as:

THD =++++

20log VVV V

...

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the second

through the Nth harmonics. The typical THD speciﬁ cation

in the Dynamic Accuracy table (see the Electrical Charac-

teristics section) includes the 2nd through 5th harmonics.

With a 100kHz input signal, the LTC1196/LTC1198 have

typical THD of 50dB and 49dB with VCC = 5V and VCC =

3V, respectively.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at sum and difference

frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 2nd order IMD terms include (fa + fb)

and (fa – fb) while 3rd order IMD terms include (2fa + fb),

(2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine

waves are equal in magnitudes, the value (in dB) of the

2nd order IMD products can be expressed by the follow-

ing formula:

IMD f f mplitude f f

()

=±

()

20log a

amplitudeattfa

⎡

⎣

⎢

⎤

⎦

⎥

For input frequencies of 499kHz and 502kHz, the IMD of

the LTC1196/LTC1198 is 51dB with a 5V supply.

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec-

tral component excluding the input signal and DC. This

value is expressed in dBs relative to the RMS value of a

full-scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is reduced

by 3dB for a full-scale input.

The full-linear bandwidth is the input frequency at which

the effective bits rating of the ADC falls to 7 bits. Beyond

this frequency, distortion of the sampled input signal

increases. The LTC1196/LTC1198 have been designed to

optimize input bandwidth, allowing the ADCs to unders-

ample input signals with frequencies above the converters’

Nyquist frequency.

INPUT FREQUENCY (Hz)

S/(N + D) (dB)

10k 100k 1M

11968 F11

EFFECTIVE NUMBER OF BITS (ENOBs)

VREF =V

CC = 2.7V

fSMPL = 383kHz (LTC1196)

fSMPL = 287kHz (LTC1198)

VREF =V

CC = 5V

fSMPL = 1MHz (LTC1196)

fSMPL = 750kHz (LTC1198)

TA= 25°C

LTC1196/LTC1198

119698fb

APPLICATIONS INFORMATION

3V VERSUS 5V PERFORMANCE COMPARISON

Table 1 shows the performance comparison between 3V

and 5V supplies. The power dissipation drops by a factor

of ﬁ ve when the supply is reduced to 3V. The converter

slows down somewhat but still gives excellent performance

on a 3V rail. With a 3V supply, the LTC1196 converts in

1.6μs, samples at 450kHz, and provides a 500kHz linear-

input bandwidth.

Dynamic accuracy is excellent on both 5V and 3V. The

ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic

accuracy at both 3V and 5V. The noise ﬂ oor is extremely

low, corresponding to a transition noise of less than 0.1LSB.

DC accuracy includes ±0.5LSB total unadjusted error at

5V. At 3V, linearity error is ±0.5LSB while total unadjusted

error increases to ±1LSB.

Table 1. 5V/3V Performance Comparison

LTC1196-1 5V 3V

PDISS 50mW 10mW

Max fSMPL 1MHz 383kHz

Min tCONV 600ns 1.6μs

INL (Max) 0.5LSB 0.5LSB

Typical ENOBs 7.9 at 300kHz 7.9 at 100kHz

Linear Input Bandwidth (ENOBs > 7) 1MHz 500kHz

LTC1198-1

PDISS 50mW 10mW

PDISS (Shutdown) 15μW 9μW

Max fSMPL 750kHz 287kHz

Min tCONV 600ns 1.6μs

INL (Max) 0.5LSB 0.5LSB

Typical ENOBs 7.9 at 300kHz 7.9 at 100kHz

Linear Input Bandwidth (ENOBs > 7) 1MHz 500kHz

TYPICAL APPLICATIONS

PLD Interface Using the Altera EPM5064

The Altera EPM5064 has been chosen to demonstrate the

interface between the LTC1196 and a PLD. The EPM5064

is programmed to be a 12-bit counter and an equivalent

74HC595 8-bit shift register, as shown in Figure 12. The

circuit works as follows: bringing ENA HIGH makes the CS

output HIGH and the EN input LOW to reset the LTC1196

and disable the shift register. Bringing ENA LOW, the CS

output goes HIGH for one CLK cycle with every 12 CLK

cycles. The inverted signal, EN, of the CS output makes

the 8-bit data available on the B0-B7 lines. Figures 13 and

14 show the interconnection between the LTC1196 and

EPM5064 and the timing diagram of the signals between

these two devices. The CLK frequency in this circuit can

run up to fCLK(MAX) of the LTC1196.

1196/98 F12

DATA

CLK

12-BIT

CONVERTER

ENA

CLK B0-B7

8-BIT

SHIFT REGISTER

ENA

CLK

DATA

B0-B7

3, 14, 25, 36

EPM5064

CLK

1196/98 F13

VCC

–DATA

9-13, 21,

31, 32, 43

CLK

ENA

–IN

GND

VCC

CLK

DOUT

+IN

LTC1196

VREF

1μF

RESERVE PINS OF EPM5064:

2, 4-8,15-20, 22, 24, 26-30

Figure 12. An Equivalent Circuit of the EPM5064 Figure 13. Interfacing the LTC1196 to the Altera EMP5064 PLD

LTC1196/LTC1198

119698fb

TYPICAL APPLICATIONS

Interfacing the LTC1198 to the TMS320C25 DSP

Figure 15 illustrates the interface between the LTC1198

8-bit data acquisition system and the TMS320C25 digital

signal processor (DSP). The interface, which is optimized

for speed of transfer and minimum processor supervision,

can complete a conversion and shift the data in 4μs with

fCLK = 5MHz. The cycle time, 4μs, of each conversion is

limited by maximum clock frequency of the serial port of

the TMS320C25 which is 5MHz. The supply voltage for

the LTC1198 in Figure 15 can be 2.7V to 6V with fCLK =

5MHz. At 2.7V, fCLK = 5MHz will work at 25°C. See the

Recommended Operating Conditions table in the Electrical

Characteristics section for limits over temperature.

Hardware Description

The circuit works as follows: the LTC1198 clock line

controls the A/D conversion rate and the data shift rate.

Data is transferred in a synchronous format over DIN and

DOUT

. The serial port of the TMS320C25 is compatible

with that of the LTC1198. The data shift clock lines (CLKR,

CLKX) are inputs only. The data shift clock comes from

an external source. Inverting the shift clock is necessary

because the LTC1198 and the TMS320C25 clock the input

data on opposite edges.

The schematic of Figure 15 is fed by an external clock

source. The signal is fed into the CLK pin of the LTC1198

directly. The signal is inverted with a 74HC04 and then

applied to the data shift clock lines (CLKR, CLKX). The

framing pulse of the TMS320C25 is fed directly to the CS

of the LTC1198. DX and DR are tied directly to DIN and

DOUT, respectively.

70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120

DATA

CLK

TIME (ns)

1196/98 F14

Figure 14. The Timing Diagram

1196/98 F15

5MHz CLK

CLKX

CLKR

FSR

FSX

CLK

LTC1198

TMS320C25 CS

DIN

DOUT

CH0

CH1

Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP

LTC1196/LTC1198

119698fb

TYPICAL APPLICATIONS

The timing diagram of Figure 16 was obtained from the

circuit of Figure 15. The CLK was 5MHz for the timing

diagram and the TMS320C25 clock rate was 40MHz.

Figure 17 shows the timing diagram with the LTC1198

running off a 2.7V supply and 5MHz CLK.

Software Description

The software conﬁ gures and controls the serial port of

the TMS320C25.

The code ﬁ rst sets up the interrupt and reset vectors. On

reset the TMS320C25 starts executing code at the label

INIT. Upon completion of a 16-bit data transfer, an inter-

rupt is generated and the DSP will begin executing code

at the label RINT.

In the beginning, the code initializes registers in the

TMS320C25 that will be used in the transfer routine. The

interrupts are temporarily disabled. The data memory page

pointer register is set to zero. The auxiliary register pointer

is loaded with one and auxiliary register one is loaded with

the value 200 hexadecimal. This is the data memory loca-

tion where the data from the LTC1198 will be stored. The

interrupt mask register (IMR) is conﬁ gured to recognize

the RINT interrupt, which is generated after receiving the

last of 16 bits on the serial port. This interrupt is still dis-

abled at this time. The transmit framing synchronization

pin (FSX) is conﬁ gured to be an output. The F0 bit of the

status register ST1, is initialized to zero which sets up the

serial port to operate in the 16-bit mode.

Next, the code in TXRX routine starts to transmit and

receive data. The DIN word is loaded into the ACC and

shifted left eight times so that it appears as in Figure 18.

This DIN word conﬁ gures the LTC1198 for CH0 with respect

to CH1. The DIN word is then put in the transmit register

and the RINT interrupt is enabled. The NOP is repeated

3 times to mask out the interrupts and minimize the cycle

time of the conversion to be 20 clock cycles. All clocking

and CS functions are performed by the hardware.

CLK

DIN

VERTICAL: 5V/DIV

DOUT

NULL

BITS

MSB

(B7)

HORIZONTAL: 1500ns/DIV

LSB

(B0)

1196/98 F16

Figure 16. Scope Trace the LTC1198 Running Off

5V Supply in the Circuit of Figure 15

CLK

DIN

VERTICAL: 5V/DIV

DOUT

NULL

BITS

MSB

(B7)

HORIZONTAL: 500ns/DIV

LSB

(B0)

1196/98 F17

Figure 17. Scope Trace the LTC1198 Running Off

1.7V Supply in the Circuit of Figure 15

L1196/98 F18

B15 B8

START

S/D

O/S

DUMMY

Figure 18. DIN Word in ACC of TMS20C25 for the

Circuit in Figure 15

LTC1196/LTC1198

119698fb

TYPICAL APPLICATIONS

Once RINT is generated the code begins execution at

the label RINT. This code stores the DOUT word from the

LTC1198 in the ACC and then stores it in location 200

hex. The data appears in location 200 hex right-justiﬁ ed

as shown in Figure 19. The code is set up to continually

loop, so at this point the code jumps to label TXRX and

repeats from here.

L1196/98 F19

MSB LSB

X X X X X X X X 7 6 5 4 3 2 1 0

DOUT FROM LTC1198 STORED IN TMS320C25 RAM

> 200

Figure 19. Memory Map for the Circuit in Figure 15

LABEL MNEMONIC COMMENTS

AORG

INIT

ON RESET CODE EXECUTION STARTS AT 0

BRANCH TO INITIALIZATION ROUTINE

AORG

>26

RINT

ADDRESS TO RINT INTERRUPT VECTOR

BRANCH TO RINT SERVICE ROUTINE

INIT

AORG

DINT

LDPK

LARP

LRLK

LACK

SACL

STXM

FORT

>32

AR1, >200

>10

MAIN PROGRAM STARTS HERE

DISABLE INTERRUPTS

SET DATA MEMORY PAGE POINTER TO 0

SET AUXILIARY REGISTER POINTER TO 1

SET AUXILIARY REGISTER 1 TO >200

LOAD IMR CONFIG WORD INTO ACC

STORE IMR CONFIG WORD INTO IMR

CONFIGURE FSX AS AN OUTPUT

SET SERIAL PORT TO 16-BIT MODE

TXRX LACK

SFSM

RPTK

SFL

SACL

EINT

>44

LOAD LTC1198 DIN WORD INTO ACC

FSX PULSES GENERATED ON XSR LOAD

REPEAT NEXT INSTRUCTION 8 TIMES

SHIFTS DIN WORD TO RIGHT POSITION

PUT DIN WORD IN TRANSMIT REGISTER

ENABLE INTERRUPT (DISABLE ON RINT)

RPTK

NOP

2 MINIMIZE THE CONVERSION CYCLE TIME

TO BE 20 CLOCK CYCLES

RINT ZALS

SACL

END

*, 0

TXRX

STORE LTC1198 DOUT WORD IN ACC

STORE ACC IN LOCATION >200

BRANCH TO TRANSMIT RECEIVE ROUTINE

Figure 20. TMS320C25 Code for the Circuit in Figure 15

LTC1196/LTC1198

119698fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.016 – .050

(0.406 – 1.270)

.010 – .020

(0.254 – 0.508)× 45°

0°– 8° TYP

.008 – .010

(0.203 – 0.254)

SO8 0303

.053 – .069

(1.346 – 1.752)

.014 – .019

(0.355 – 0.483)

TYP

.004 – .010

(0.101 – 0.254)

.050

(1.270)

BSC

1234

.150 – .157

(3.810 – 3.988)

NOTE 3

8765

.189 – .197

(4.801 – 5.004)

NOTE 3

.228 – .244

(5.791 – 6.197)

.245

MIN .160 ±.005

RECOMMENDED SOLDER PAD LAYOUT

.045 ±.005

.050 BSC

.030 ±.005

TYP

INCHES

(MILLIMETERS)

NOTE:

1. DIMENSIONS IN

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

LTC1196/LTC1198

119698fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0609 REV B • PRINTED IN USA

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