ASIX ELECTRONICS CORPORATION
2
AX88195 Local CPU Bus Fast Ethernet MAC Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 4
1.1 GENERAL DESCRIPTION:..................................................................................................................................... 4
1.2 AX88195 BLOCK DIAGRAM:.............................................................................................................................. 4
1.3 AX88195 PIN CONNECTION DIAGRAM ............................................................................................................... 5
1.3.1 AX88195 Pin Connection Diagram for ISA Bus Mode................................................................................ 6
1.3.2 AX88195 Pin Connection Diagram for 80x86 Mode................................................................................... 7
1.3.3 AX88195 Pin Connection Diagram for MC68K Mode................................................................................ 8
1.3.4 AX88195 Pin Connection Diagram for MCS-51 Mode ............................................................................... 9
2.0 SIGNAL DESCRIPTION................................................................................................................................. 10
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP................................................................................................... 10
2.2 MII INTERFACE SIGNALS GROUP........................................................................................................................ 11
2.3 EEPROM SIGNALS GROUP .............................................................................................................................. 12
2.4 SRAM INTERFACE PINS GROUP......................................................................................................................... 12
2.5 MISCELLANEOUS PINS GROUP............................................................................................................................ 12
2.6 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 13
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 14
3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 14
3.2 I/O MAPPING................................................................................................................................................... 14
3.3 SRAM MEMORY MAPPING .............................................................................................................................. 14
4.0 REGISTERS OPERATION............................................................................................................................. 15
4.1 COMMAND REGISTER (CR) OFFSET 00H (READ/WRITE)................................................................................... 17
4.2 INTERRUPT STATUS REGISTER (ISR) OFFSET 07H (READ/WRITE)..................................................................... 17
4.3 INTERRUPT MASK REGISTER (IMR) OFFSET 0FH (WRITE)................................................................................. 18
4.4 DATA CONFIGURATION REGISTER (DCR) OFFSET 0EH (WRITE)....................................................................... 18
4.5 TRANSMIT CONFIGURATION REGISTER (TCR) OFFSET 0DH (WRITE)................................................................ 18
4.6 TRANSMIT STATUS REGISTER (TSR) OFFSET 04H (READ)................................................................................ 19
4.7 RECEIVE CONFIGURATION (RCR) OFFSET 0CH (WRITE).................................................................................. 19
4.8 RECEIVE STATUS REGISTER (RSR) OFFSET 0CH (READ).................................................................................. 19
4.9 INTER-FRAME GAP (IFG) OFFSET 16H (READ/WRITE)...................................................................................... 20
4.10 INTER-FRAME GAP SEGMENT 1(IFGS1) OFFSET 12H (READ/WRITE)............................................................... 20
4.11 INTER-FRAME GAP SEGMENT 2(IFGS2) OFFSET 13H (READ/WRITE)............................................................... 20
4.12 MII/EEPROM MANAGEMENT REGISTER (MEMR) OFFSET 14H (READ/WRITE).............................................. 20
4.13 TEST REGISTER (TR) OFFSET 15H (WRITE)................................................................................................... 20
5.0 CPU I/O READ AND WRITE FUNCTIONS.................................................................................................. 21
5.1 ISA BUS TYPE ACCESS FUNCTIONS. ................................................................................................................... 21
5.2 80186 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................... 21
5.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS...................................................................................................... 22
5.3 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS..................................................................................................... 22
6.0 ELECTRICAL SPECIFICATION AND TIMINGS........................................................................................ 23
6.1 ABSOLUTE MAXIMUM RATINGS........................................................................................................................ 23
6.2 GENERAL OPERATION CONDITIONS................................................................................................................... 23
6.3 DC CHARACTERISTICS..................................................................................................................................... 23
6.4 A.C. TIMING CHARACTERISTICS....................................................................................................................... 24
6.4.1 XTAL / CLOCK........................................................................................................................................ 24
6.4.2 Reset Timing............................................................................................................................................ 24
6.4.3 ISA Bus Access Timing............................................................................................................................. 25
6.4.4 80186 Type I/O Access Timing................................................................................................................. 26