2011-2012 Microchip Technology Inc. DS70652E-page 1
dsPIC33FJ16(GP/MC)101/102 AND
dsPIC33FJ32(GP/MC)101/102/104
Operating Conditions
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 16 MIPS
Core: 16-bit dsPIC33F CPU
• Code-Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
Clock Management
• ±0.25% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 1 mA/MHz Dynamic Current (typical)
•30 µA I
PD Current (typical)
PWM
• Up to Three PWM Pairs
• Two Dead-Time Generators
• 31.25 ns PWM Resolution
• PWM Support for:
- Inverters, PFC, UPS
- BLDC, PMSM, ACIM, SRM
• Class B-Compliant Fault Inputs
• Possibility of ADC Synchronization with PWM Signal
Advanced Analog Features
• ADC module:
- 10-bit, 1.1 Msps with four S&H
- Four analog inputs on 18-pin devices and up to
14 analog inputs on 44-pin devices
• Flexible and Independent ADC Trigger Sources
• Three Comparator modules
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement
Timers/Output Compare/Input Capture
• Up to Five General Purpose Timers:
- One 16-bit and up to two 32-bit timers/counters
• Two Output Compare modules
• Three Input Capture modules
• Peripheral Pin Select (PPS) to allow Function Remap
Communication Interfaces
• UART module (4 Mbps)
- With support for LIN/J2602 Protocols and IrDA®
• 4-Wire SPI module (8 MHz maximum speed)
- Remappable Pins in 32-Kbyte Flash Devices
•I
2C™ module (400 kHz)
Input/Output
• Sink/Source 10 mA or 6 mA, Pin-Specific for Standard
VOH/VOL, up to 16 mA or 12 mA for Non-Standard VOH1
• 5V Tolerant Pins
• Up to 20 Selectable Open-Drain and Pull-ups
• Three External Interrupts (two are remappable)
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) Planned
• Class B Safety Library, IEC 60730, UDE Certified
Debugger Development Support
• In-Circuit and In-Application Programming
• Up to Three Complex Data Breakpoints
• Trace and Run-Time Watch
16-Bit Digital Signal Controllers
(up to 32-Kbyte Flash and 2-Kbyte SRAM)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 2 2011-2012 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND
dsPIC33FJ32(GP/MC)101/102/104
PRODUCT FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed in
Table 1. The following pages show their pinout
diagrams.
TABLE 1: dsPIC33FJ16(GP/MC)101/102 DEVICE FEATURES
Device
Pins
Program Flash (Kbyte)
RAM (Kbytes)
Remappable Peripherals
Motor Control PWM
PWM Faults
10-Bit, 1.1 Msps ADC
RTCC
I2C™
Comparators
CTMU
I/O Pins
Packages
Remappable Pins
16-bit Timer(1,2)
Input Capture
Output Compare
UART
External Interrupts(3)
SPI
dsPIC33FJ16GP101 18 16 1 8 3 3 2 1 3 1 — — 1 ADC,
4-ch
Y 1 3 Y 13 PDIP,
SOIC
20 16 1 8 3 3 2 1 3 1 — — 1 ADC,
4-ch
Y1 3 Y15SSOP
dsPIC33FJ16GP102 28 16 1 16 3 3 2 1 3 1 — — 1 ADC,
6-ch
Y1 3 Y21SPDIP,
SOIC,
SSOP,
QFN
36 16 1 16 3 3 2 1 3 1 — — 1 ADC,
6-ch
Y 1 3 Y 21 VTLA
dsPIC33FJ16MC101 20 16 1 10 3 3 2 1 3 1 6-ch 1 1 ADC,
4-ch
Y1 3 Y15PDIP,
SOIC,
SSOP
dsPIC33FJ16MC102 28 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC,
6-ch
Y1 3 Y21SPDIP,
SOIC,
SSOP,
QFN
36 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC,
6-ch
Y 1 3 Y 21 VTLA
Note 1: Two out of three timers are remappable.
2: One pair can be combined to create one 32-bit timer.
3: Two out of three interrupts are remappable.
2011-2012 Microchip Technology Inc. DS70652E-page 3
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 2: dsPIC33FJ32(GP/MC)101/102/104 DEVICE FEATURES
Device
Pins
Program Flash (Kbyte)
RAM (Kbytes)
Remappable Peripherals
Motor Control PWM
PWM Faults
10-Bit, 1.1 Msps ADC
RTCC
I2C™
Comparators
CTMU
I/O Pins
Packages
Remappable Pins
16-bit Timer(1,2)
Input Capture
Output Compare
UART
External Interrupts(3)
SPI
dsPIC33FJ32GP101 18 32 2 8 5 3 2 1 3 1 — — 1 ADC,
6-ch
Y 1 3 Y 13 PDIP,
SOIC
20 32 2 8 5 3 2 1 3 1 — — 1 ADC,
6-ch
Y 1 3 Y 15 SSOP
dsPIC33FJ32GP102 28 32 2 16 5 3 2 1 3 1 — — 1 ADC,
8-ch
Y 1 3 Y 21 SPDIP,
SOIC,
SSOP,
QFN
36 32 2 16 5 3 2 1 3 1 — — 1 ADC,
8-ch
Y 1 3 Y 21 VTLA
dsPIC33FJ32GP104 44 32 2 26 5 3 2 1 3 1 — — 1 ADC,
14-ch
Y 1 3 Y 35 TQFP,
QFN,
VTLA
dsPIC33FJ32MC101 20 32 2 10 5 3 2 1 3 1 6-ch 1 1 ADC,
6-ch
Y1 3 Y15PDIP,
SOIC,
SSOP
dsPIC33FJ32MC102 28 32 2 16 5 3 2 1 3 1 6-ch 2 1 ADC,
8-ch
Y 1 3 Y 21 SPDIP,
SOIC,
SSOP,
QFN
36 32 2 16 5 3 2 1 3 1 6-ch 2 1 ADC,
8-ch
Y 1 3 Y 21 VTLA
dsPIC33FJ32MC104 44 32 2 26 5 3 2 1 3 1 6-ch 2 1 ADC,
14-ch
Y 1 3 Y 35 TQFP,
QFN,
VTLA
Note 1: Four out of five timers are remappable.
2: Two pairs can be combined to have up to two 32-bit timers.
3: Two out of three interrupts are remappable.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 4 2011-2012 Microchip Technology Inc.
Pin Diagrams
18-Pin PDIP/SOIC
dsPIC33FJ16GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VDD
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
SCK1/INT0/RP7(1)/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4(1)/CN1/RB4
VCAP
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VSS
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
= Pins are up to 5V tolerant
dsPIC33FJ32GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VDD
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
INT0/RP7(1)/CN23/RB7
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
VCAP
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VSS
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
2011-2012 Microchip Technology Inc. DS70652E-page 5
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
dsPIC33FJ16GP101
MCLR
VSS
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AVDD
AVSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
SCK1/INT0/RP7(1)/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4(1)/CN1/RB4
VCAP
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VSS
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
VDD
20-Pin SSOP
Note 1: The RPn pins can be used by any remappable peripheral. See Ta b l e 1 for the list of available peripherals.
= Pins are up to 5V tolerant
dsPIC33FJ32GP101
MCLR
VSS
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AVDD
AVSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
INT0/RP7(1)/CN23/RB7
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
VCAP
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VSS
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
VDD
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 6 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
dsPIC33FJ16GP102
MCLR
VSS
VDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AVDD
AVSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
ASCL1/RP6(1)/CN24/RB6
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4(1)/CN1/RB4
VSS
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VCAP
SCK1/INT0/RP7(1)/CN23/RB7
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP10(1)/CN16/RB10
RP11(1)/CN15/RB11
ASDA1/RP5(1)/CN27/RB5
28-Pin SPDIP/SOIC/SSOP
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
= Pins are up to 5V tolerant
dsPIC33FJ32GP102
MCLR
VSS
VDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AVDD
AVSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
ASCL1/RP6(1)/CN24/RB6
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
VSS
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VCAP
INT0/RP7(1)/CN23/RB7
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP10(1)/CN16/RB10
RP11(1)/CN15/RB11
ASDA1/RP5(1)/CN27/RB5
2011-2012 Microchip Technology Inc. DS70652E-page 7
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
dsPIC33FJ16MC101
MCLR
VSS
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VDD
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
FLTA1(2)/SCK1/INT0/RP7(1)/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4(1)/CN1/RB4
PWM1H2/RP12(1)/CN14/RB12
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VCAP
SDA1/SDI1/PWM1L3/RP9(1)/CN21/RB9
SCL1/SDO1/PWM1H3/RP8(1)/CN22/RB8
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
20-Pin PDIP/SOIC/SSOP
Note 1: The RPn pins can be used by any remappable peripheral. See Ta b l e 1 for the list of available peripherals.
2: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
= Pins are up to 5V tolerant
dsPIC33FJ32MC101
MCLR
VSS
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VDD
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
FLTA1(2)/INT0/RP7(1)/CN23/RB7
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
PWM1H2/RP12(1)/CN14/RB12
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VCAP
SDA1/PWM1L3/RP9(1)/CN21/RB9
SCL1/PWM1H3/RP8(1)/CN22/RB8
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 8 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
Note 1: The RPn pins can be used by any remappable peripheral. See Ta b l e 1 for the list of available peripherals.
2: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
dsPIC33FJ16MC102
MCLR
VSS
VDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AVDD
AVSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
FLTA1(2)/ASCL1/RP6(1)/CN24/RB6
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4(1)/CN1/RB4
VSS
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VCAP
SCK1/INT0/RP7(1)/CN23/RB7
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1H3/RP10(1)/CN16/RB10
PWM1L3/RP11(1)/CN15/RB11
FLTB1(2)/ASDA1/RP5(1)/CN27/RB5
28-Pin SPDIP/SOIC/SSOP = Pins are up to 5V tolerant
dsPIC33FJ32MC102
MCLR
VSS
VDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AVDD
AVSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
FLTA1(2)/ASCL1/RP6(1)/CN24/RB6
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
VSS
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2 VCAP
INT0/RP7(1)/CN23/RB7
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1H3/RP10(1)/CN16/RB10
PWM1L3/RP11(1)/CN15/RB11
FLTB1(2)/ASDA1/RP5(1)/CN27/RB5
2011-2012 Microchip Technology Inc. DS70652E-page 9
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
28-Pin QFN(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
= Pins are up to 5V tolerant
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ16GP102
5
4
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VSS
VCAP
SDA1/SDI1/RP9(1)/CN21/RB9
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP10(1)/CN16/RB10
RP11(1)/CN15/RB11
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VDD
PGEC3/SOSCO/T1CK/CN0/RA4
ASDA1/RP5(1)/CN27/RB5
PGED3/SOSCI/RP4(1)/CN1/RB4
ASCL1/RP6(1)/CN24/RB6
SCK1/INT0/RP7(1)/CN23/RB7
SCL1/SDO1/RP8(1)/CN22/RB8
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 10 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin QFN(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Ta b l e 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
= Pins are up to 5V tolerant
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ32GP102
5
4
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VSS
VCAP
SDA1/RP9(1)/CN21/RB9
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP10(1)/CN16/RB10
RP11(1)/CN15/RB11
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VDD
PGEC3/SOSCOAN10//T1CK/CN0/RA4
ASDA1/RP5(1)/CN27/RB5
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
2011-2012 Microchip Technology Inc. DS70652E-page 11
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
28-Pin QFN(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Ta b l e 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ16MC102
5
4
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VSS
VCAP
SDA1/SDI1/RP9(1)/CN21/RB9
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1H3/RP10(1)/CN16/RB10
PWM1L3/RP11(1)/CN15/RB11
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VDD
PGEC3/SOSCO/T1CK/CN0/RA4
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
PGED3/SOSCI/RP4(1)/CN1/RB4
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
SCK1/INT0/RP7(1)/CN23/RB7
SCL1/SDO1/RP8(1)/CN22/RB8
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
= Pins are up to 5V tolerant
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 12 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin QFN(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM
Faults” for more information on the PWM Faults.
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ32MC102
5
4
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VSS
VCAP
SDA1/RP9(1)/CN21/RB9
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1H3/RP10(1)/CN16/RB10
PWM1L3/RP11(1)/CN15/RB11
VSS
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VDD
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
= Pins are up to 5V tolerant
2011-2012 Microchip Technology Inc. DS70652E-page 13
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
36-Pin VTLA(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
1
dsPIC33FJ16GP102
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
N/C
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
MCLR
AVDD
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
AVSS
N/C
N/C
VSS
SDA1/SDI1/RP9(1)/CN21/RB9
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP10(1)/CN16/RB10
RP11(1)/CN15/RB11
VDD
VCAP
VDD
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGED3/SOSCI/RP4(1)/CN1/RB4
OSCO/CLKO/CN29/RA3
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VSS
OSCI/CLKI/CN30/RA2
N/C (Vss)
N/C
ASDA1/RP5(1)/CN27/RB5
PGEC3/SOSCO/T1CK/CN0/RA4
ASCL1/RP6(1)/CN24/RB6
SCK1/INT0/RP7(1)/CN23/RB7
SCL1/SDO1/RP8(1)/CN22/RB8
VDD
N/C (VDD)
7
8
9
34
35
36
16 17 18
27
26
25
= Pins are up to 5V tolerant
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 14 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
36-Pin VTLA(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Ta b l e 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
1
dsPIC33FJ32GP102
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
N/C
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
MCLR
AVDD
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
AVSS
N/C
N/C
VSS
SDA1/RP9(1)/CN21/RB9
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP10(1)/CN16/RB10
RP11(1)/CN15/RB11
VDD
VCAP
VDD
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
OSCO/CLKO/CN29/RA3
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VSS
OSCI/CLKI/CN30/RA2
N/C (Vss)
N/C
ASDA1/RP5(1)/CN27/RB5
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
VDD
N/C (VDD)
7
8
9
34
35
36
16 17 18
27
26
25
= Pins are up to 5V tolerant
2011-2012 Microchip Technology Inc. DS70652E-page 15
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
36-Pin VTLA(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Ta b l e 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
N/C
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
MCLR
AVDD
PWM1L1/RP15(1)/CN11/RB15
AVSS
N/C
N/C
VSS
SDA1/SDI1/RP9(1)/CN21/RB9
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1H3/RP10(1)/CN16/RB10
PWM1L3/RP11(1)/CN15/RB11
VDD
VCAP
VDD
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGED3/SOSCI/RP4(1)/CN1/RB4
OSCO/CLKO/CN29/RA3
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VSS
OSCI/CLKI/CN30/RA2
N/C (Vss)
N/C
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
PGEC3/SOSCO/T1CK/CN0/RA4
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
SCK1/INT0/RP7(1)/CN23/RB7
SCL1/SDO1/RP8(1)/CN22/RB8
VDD
N/C (VDD)
dsPIC33FJ16MC102
= Pins are up to 5V tolerant
1
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
7
8
9
34
35
36
16 17 18
27
26
25
PWM1H1/RTCC/RP14(1)/CN12/RB14
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 16 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
36-Pin VTLA(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
N/C
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
MCLR
AVDD
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
AVSS
N/C
N/C
VSS
SDA1/RP9(1)/CN21/RB9
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1H3/RP10(1)/CN16/RB10
PWM1L3/RP11(1)/CN15/RB11
VDD
VCAP
VDD
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
OSCO/CLKO/CN29/RA3
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VSS
OSCI/CLKI/CN30/RA2
N/C (Vss)
N/C
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
VDD
N/C (VDD)
dsPIC33FJ32MC102
= Pins are up to 5V tolerant
1
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
7
8
9
34
35
36
16 17 18
27
26
25
2011-2012 Microchip Technology Inc. DS70652E-page 17
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
44 43 42 41 40 39 38 37 36 35 34
133
232
331
430
529
628
727
826
925
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
44-Pin TQFP = Pins are up to 5V tolerant
SCL1/RP8(1)/CN22/RB8RA10
RA7
RTCC/RP14(1)/CN12/RB14
RP15(1)/CN11/RB15
AVSS
AVDD
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
ASDA1/RP5(1)/CN27/RB5
VDD
VSS
AN15/RP21(1)/CN26/RC5
AN12/RP20(1)/CN25/RC4
AN11/RP19(1)/CN28/RC3
RA9
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
dsPIC33FJ32GP104
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP11(1)/CN15/RB11
RP10/CN16/RB10
VCAP
VSS
RP25(1)/CN19/RC9
RP24(1)/CN20/RC8
RP23(1)/CN17/RC7
SDA1/RP9(1)/CN21/RB9
RP22(1)/CN18/RC6
PEGED3/SOSCI/AN9/RP4(1)/CN1/RB4
RA8
OSC2/CLK0/CN29/RA3
OSC1/CLKI/CN30/RA2
VSS
VDD
AN8/RP18(1)/CN10/RC2
AN7/RP17(1)/CN9/RC1
AN6/RP16(1)/CN8/RC0
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 18 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin TQFP = Pins are up to 5V tolerant
44 43 42 41 40 39 38 37 36 35 34
133
232
331
430
529
628
727
826
925
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
SCL1/RP8(1)/CN22/RB8RA10
RA7
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L1/RP15(1)/CN11/RB15
AVSS
AVDD
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
INT0/RP7(1)/CN23/RB7
FLTA1(2)/ASCL1/RP6(1)/CN24/RB6
FLTB1(2)/ASDA1/RP5(1)/CN27/RB5
VDD
VSS
AN15/RP21(1)/CN26/RC5
AN12/RP20(1)/CN25/RC4
AN11/RP19(1)/CN28/RC3
RA9
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
dsPIC33FJ32MC104
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1L3/RP11(1)/CN15/RB11
PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
RP25(1)/CN19/RC9
RP24(1)/CN20/RC8
RP23(1)/CN17/RC7
SDA1/RP9(1)/CN21/RB9
RP22(1)/CN18/RC6
PEGED3/SOSCI/AN9/RP4(1)/CN1/RB4
RA8
OSC2/CLK0/CN29/RA3
OSC1/CLKI/CN30/RA2
VSS
VDD
AN8/RP18(1)/CN10/RC2
AN7/RP17(1)/CN9/RC1
AN6/RP16(1)/CN8/RC0
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
2011-2012 Microchip Technology Inc. DS70652E-page 19
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
dsPIC33FJ32GP104
44-Pin QFN(2)
44
12
11 23
24
25
26
27
28
29
30
31
32
33
13 14 15 16 17 18 19 20 21 22
10
9
8
7
6
5
4
3
2
1
43 42 41 40 39 38 37 36 35 34
= Pins are up to 5V tolerant
RA10
RA7
RTCC/RP14(1)/CN12/RB14
RP15(1)/CN11/RB15
AVSS
AVDD
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/RP18(1)/CN10/RC2
VDD
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
RA8
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
ASDA1/RP5(1)/CN27/RB5
VDD
VSS
AN15/RP21(1)/CN26/RC5
AN12/RP20(1)/CN25/RC4
AN11/RP19(1)/CN28/RC3
RA9
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP11(1)/CN15/RB11
RP10(1)/CN16/RB10
VCAP
VSS
RP25(1)/CN19/RC9
RP24(1)/CN20/RC8
RP23(1)/CN17/RC7
RP22(1)/CN18/RC6
SDA1/RP9(1)/CN21/RB9
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 20 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
dsPIC33FJ32MC104
44-Pin QFN(2)
44
12
11 23
24
25
26
27
28
29
30
31
32
33
13 14 15 16 17 18 19 20 21 22
10
9
8
7
6
5
4
3
2
1
43 42 41 40 39 38 37 36 35 34
= Pins are up to 5V tolerant
RA10
RA7
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L1/RP15(1)/CN11/RB15
AVSS
AVDD
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/RP18(1)/CN10/RC2
VDD
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
RA8
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
VDD
VSS
AN15/RP21(1)/CN26/RC5
AN12/RP20(1)/CN25/RC4
AN11/RP19(1)/CN28/RC3
RA9
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1L3/RP11(1)/CN15/RB11
PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
RP25(1)/CN19/RC9
RP24(1)/CN20/RC8
RP23(1)/CN17/RC7
RP22(1)/CN18/RC6
SDA1/RP9(1)/CN21/RB9
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
2011-2012 Microchip Technology Inc. DS70652E-page 21
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
dsPIC33FJ32GP104
44-Pin TLA(2) = Pins are up to 5V tolerant
RA10
RA7
RTCC/RP14(1)/CN12/RB14
RP15(1)/CN11/RB15
AVSS
AVDD
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/RP18(1)/CN10/RC2
VDD
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
RA8
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
ASDA1/RP5(1)/CN27/RB5
VDD
VSS
AN15/RP21(1)/CN26/RC5
AN12/RP20(1)/CN25/RC4
AN11/RP19(1)/CN28/RC3
RA9
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP11(1)/CN15/RB11
RP10(1)/CN16/RB10
VCAP
VSS
RP25(1)/CN19/RC9
RP24(1)/CN20/RC8
RP23(1)/CN17/RC7
RP22(1)/CN18/RC6
SDA1/RP9(1)/CN21/RB9
34 33
32
31
30
29
28
27
26
25
24
23
2221
11 12 13 14 15 16 17 18 19 20
10
9
8
7
6
5
4
3
2
1
44 43 42 41 36 3540 39 38 37
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 22 2011-2012 Microchip Technology Inc.
Pin Diagrams (Continued)
dsPIC33FJ32MC104
44-Pin TLA(2) = Pins are up to 5V tolerant
RA10
RA7
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L1/RP15(1)/CN11/RB15
AVSS
AVDD
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
VDD
VSS
AN15/RP21(1)/CN26/RC5
AN12/RP20(1)/CN25/RC4
AN11/RP19(1)/CN28/RC3
RA9
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1L3/RP11(1)/CN15/RB11
PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
RP25(1)/CN19/RC9
RP24(1)/CN20/RC8
RP23(1)/CN17/RC7
RP22(1)/CN18/RC6
SDA1/RP9(1)/CN21/RB9
34 33
32
31
30
29
28
27
26
25
24
23
2221
11 12 13 14 15 16 17 18 19 20
10
9
8
7
6
5
4
3
2
1
44 43 42 41 36 3540 39 38 37
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/RP18(1)/CN10/RC2
VDD
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
RA8
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
2011-2012 Microchip Technology Inc. DS70652E-page 23
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Table of Contents
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 Product Families .................................................................. 2
1.0 Device Overview ........................................................................................................................................................................ 27
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 33
3.0 CPU............................................................................................................................................................................................ 37
4.0 Memory Organization ................................................................................................................................................................. 49
5.0 Flash Program Memory.............................................................................................................................................................. 83
6.0 Resets ....................................................................................................................................................................................... 87
7.0 Interrupt Controller ..................................................................................................................................................................... 95
8.0 Oscillator Configuration ............................................................................................................................................................ 125
9.0 Power-Saving Features............................................................................................................................................................ 133
10.0 I/O Ports ................................................................................................................................................................................... 139
11.0 Timer1 ...................................................................................................................................................................................... 163
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................. 165
13.0 Input Capture............................................................................................................................................................................ 173
14.0 Output Compare....................................................................................................................................................................... 175
15.0 Motor Control PWM Module ..................................................................................................................................................... 179
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 195
17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 201
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 209
19.0 10-Bit Analog-to-Digital Converter (ADC)................................................................................................................................. 215
20.0 Comparator Module.................................................................................................................................................................. 229
21.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 241
22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 253
23.0 Special Features ...................................................................................................................................................................... 259
24.0 Instruction Set Summary .......................................................................................................................................................... 267
25.0 Development Support............................................................................................................................................................... 275
26.0 Electrical Characteristics .......................................................................................................................................................... 279
27.0 Packaging Information.............................................................................................................................................................. 337
Appendix A: Revision History............................................................................................................................................................. 367
Index ................................................................................................................................................................................................. 375
The Microchip Web Site ..................................................................................................................................................................... 381
Customer Change Notification Service .............................................................................................................................................. 381
Customer Support.............................................................................................................................................................................. 381
Reader Response .............................................................................................................................................................................. 382
Product Identification System ............................................................................................................................................................ 383
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 24 2011-2012 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Customer Notification System
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2011-2012 Microchip Technology Inc. DS70652E-page 25
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the primary reference for the operation
of a particular module or device feature.
•Section 2. “CPU” (DS70204)
•Section 3. “Data Memory” (DS70202)
•Section 4. “Program Memory” (DS70203)
•Section 5. “Flash Programming” (DS70191)
•Section 8. “Reset” (DS70192)
•Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)
•Section 11. “Timers” (DS70205)
•Section 12. “Input Capture” (DS70198)
•Section 13. “Output Compare” (DS70209)
•Section 14. “Motor Control PWM” (DS70187)
• Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
•Section 17. “UART” (DS70188)
• Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
• Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
•Section 23. “CodeGuard Security” (DS70199)
•Section 24. “Programming and Diagnostics” (DS70207)
•Section 25. “Device Configuration” (DS70194)
•Section 30. “I/O Ports with Peripheral Pin Select (PPS)” (DS70190)
•Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301)
•Section 51. “Introduction (Part VI)” (DS70655)
•Section 52. “Oscillator (Part VI)” (DS70644)
•Section 53. “Interrupts (Part VI)” (DS70633)
•Section 54. “Comparator with Blanking” (DS70647)
•Section 55. “Charge Time Measurement Unit (CTMU)” (DS70635)
Note 1: To access the documents listed below,
browse to the documentation section
of the dsPIC33FJ16MC102 product
page of the Microchip Web site
(www.microchip.com).
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 26 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 27
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
1.0 DEVICE OVERVIEW This data sheet contains device-specific information for
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 Digital Signal Controller (DSC)
Devices. These devices contain extensive Digital Signal
Processor (DSP) functionality with a high-performance,
16-bit microcontroller (MCU) architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
family of devices. Tab le 1 - 1 lists the functions of the
various pins shown in the pinout diagrams.
Note: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the latest family reference
sections of the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 28 2011-2012 Microchip Technology Inc.
FIGURE 1-1: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 BLOCK
DIAGRAM
16
OSC1/CLKI
OSC2/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP
IC1-IC3 I2C1
PORTA
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program Memory
Data Latch
Literal Data
16 16
16
16
Data Latch
Address
Latch
16
X RAM Y RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-5
CNx
UART1 OC/
PWM1-2 RTCC
PWM
6-ch
Remappable
Pins
SPI1
CTMU
External
Interrupts
1-3
Comparators
1-3
Note: Not all pins or features are implemented on all device pinout configurations. See the “Pin Diagrams” section for the specific pins
and features present on each device.
2011-2012 Microchip Technology Inc. DS70652E-page 29
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name Pin
Type
Buffer
Type PPS Description
AN0-AN12,
AN15(5)
I Analog No Analog input channels.
CLKI
CLKO
I
O
ST/CMOS
—
No
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
OSC1
OSC2
I
I/O
ST/CMOS
—
No
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
ST/CMOS
—
No
No
32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
CN0-CN30(5)I ST No Change Notification inputs. Can be software programmed for internal weak
pull-ups on all inputs.
IC1-IC3 I ST Yes Capture Inputs 1/2/3.
OCFA
OC1-OC2
I
O
ST
—
Yes
Yes
Compare Fault A input (for Compare Channels 1 and 2).
Compare Outputs 1 through 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
RA0-RA4,
RA7-RA10(5)
I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15(5)I/O ST No PORTB is a bidirectional I/O port.
RC0-RC9(5)I/O ST No PORTC is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK(6)
T5CK(6)
I
I
I
I
I
ST
ST
ST
ST
ST
No
Yes
Yes
Yes
Yes
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Ready-to-Send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: This pin is available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 30 2011-2012 Microchip Technology Inc.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
FLTA1(1,2,4)
FLTB1(3,4)
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
I
I
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
No
No
No
No
No
No
No
No
PWM1 Fault A input.
PWM1 Fault B input.
PWM1 Low Output 1
PWM1 High Output 1
PWM1 Low Output 2
PWM1 High Output 2
PWM1 Low Output 3
PWM1 High Output 3
RTCC O Digital No RTCC Alarm output.
CTPLS
CTED1
CTED2
O
I
I
Digital
Digital
Digital
Yes
No
No
CTMU pulse output.
CTMU External Edge Input 1.
CTMU External Edge Input 2.
CVREFIN
CVREFOUT
C1INA
C1INB
C1INC
C1IND
C1OUT
C2INA
C2INB
C2INC
C2IND
C2OUT
C3INA
C3INB
C3INC
C3IND
C3OUT
I
O
I
I
I
I
O
I
I
I
I
O
I
I
I
I
O
Analog
Analog
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
No
No
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
Comparator Voltage Positive Reference Input.
Comparator Voltage Positive Reference Output.
Comparator 1 Positive Input A.
Comparator 1 Negative Input B.
Comparator 1 Negative Input C.
Comparator 1 Negative Input D.
Comparator 1 Output.
Comparator 2 Positive Input A.
Comparator 2 Negative Input B.
Comparator 2 Negative Input C.
Comparator 2 Negative Input D.
Comparator 2 Output.
Comparator 3 Positive Input A.
Comparator 3 Negative Input B.
Comparator 3 Negative Input C.
Comparator 3 Negative Input D.
Comparator 3 Output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Type
Buffer
Type PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: This pin is available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 31
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
AVDD P P No Positive supply for analog modules. This pin must be connected at all times.
AVDD is connected to VDD in the 18-pin dsPIC33FJXXGP101 and 20-pin
dsPIC33FJXXMC101 devices. In all other devices, AVDD is separated from
VDD.
AVSS P P No Ground reference for analog modules. AVSS is connected to VSS in the
18-pin dsPIC33FJXXGP101 and 20-pin dsPIC33FJXXMC101 devices. In all
other devices, AVSS is separated from VSS.
VDD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Type
Buffer
Type PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: This pin is available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 32 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 33
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
2.1 Basic Connection Requirements
Getting started with the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104 family of 16-bit
Digital Signal Controllers (DSCs) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins, if present on the device
(regardless if ADC module is not used)
(see Section 2.2 “Decoupling Capacitors”)
•V
CAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
•MCLR
pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD, and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
•Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10V-20V. This capacitor
should be a low-ESR and have resonance
frequency in the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
•Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
•Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be
a comprehensive reference source. To
complement the information in
this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
“dsPIC33F/PIC24H Family Reference
Manual” sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 34 2011-2012 Microchip Technology Inc.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTION
2.2.1 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3 CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 26.0
“Electrical Characteristics” for additional
information.
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 23.2
“On-Chip Voltage Regulator” for details.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
dsPIC33F
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
VDD
MCLR
0.1 µF
Ceramic
VCAP
L1(1)
R1
10 µF
Tantalum
Note 1: As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
fFCNV
2
--------------=
f1
2LC
-----------------------=
L1
2fC
----------------------
2
=
(i.e., ADC conversion rate/2)
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C
R1(2)
R(1)
VDD
MCLR
dsPIC33F
JP
2011-2012 Microchip Technology Inc. DS70652E-page 35
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternately, refer to the AC/DC characteristics and
timing requirements information in the “dsPIC33F
Flash Programming Specification for Devices with Vol-
atile Configuration Bits” (DS70659) for information on
capacitive loading limits and pin Input Voltage High
(VIH) and Input Voltage Low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
•“Using MPLAB® ICD 3” (poster) (DS51765)
•“MPLAB® ICD 3 Design Advisory” (DS51764)
•“MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS51616)
•“Using MPLAB® REAL ICE™” (poster) (DS51749)
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
13
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
14
15
16
17
18
19
20
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 36 2011-2012 Microchip Technology Inc.
2.7 Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz (for MSPLL mode) or 3 MHz <
FIN < 8 MHz (for ECPLL mode) to comply with device
PLL start-up conditions. HSPLL mode is not supported.
This means that if the external oscillator frequency is
outside this range, the application must start-up in the
FRC mode first. The fixed PLL settings of 4x after a
POR with an oscillator frequency outside this range will
violate the device operating speed.
Once the device powers up, the application firmware
can enable the PLL, and then perform a clock switch to
the Oscillator + PLL clock source. Note that clock
switching must be enabled in the device Configuration
Word.
2.8 Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or MPLAB REAL ICE in-circuit
emulator is selected as a debugger, it automatically
initializes all of the Analog-to-Digital input pins (ANx) as
“digital” pins, by setting all bits in the AD1PCFGL
register.
The bits in the register that correspond to the
Analog-to-Digital pins that are initialized by MPLAB
ICD 3 or MPLAB REAL ICE in-circuit emulator, must
not be cleared by the user application firmware;
otherwise, communication errors will result between
the debugger and the device.
If your application needs to use certain
Analog-to-Digital pins as analog input pins during the
debug session, the user application must clear the
corresponding bits in the AD1PCFGL register during
initialization of the ADC module.
When MPLAB ICD 3 or MPLAB REAL ICE in-circuit
emulator is used as a programmer, the user application
firmware must correctly configure the AD1PCFGL
register. Automatic initialization of this register is only
done during debugger operation. Failure to correctly
configure the register(s) will result in all
Analog-to-Digital pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternately, connect a 1k to 10k resistor between VSS
and unused pins.
2011-2012 Microchip Technology Inc. DS70652E-page 37
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.0 CPU
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices have six-
teen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address, or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices: MCU and DSP. These two
instruction classes are seamlessly integrated into a sin-
gle CPU. The instruction set includes many addressing
modes and is designed for optimum C compiler effi-
ciency. For most instructions, dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
devices are capable of executing a data (or program
data) memory read, a working register (data) read, a
data memory write, and a program (instruction) memory
read per instruction cycle. As a result, three parameter
instructions can be supported, allowing A + B = C
operations to be executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1, and
the programmer’s model for the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
is shown in Figure 3-2.
3.1 Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.2 DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators, and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC instruction and other associated instructions
can concurrently fetch two data operands from mem-
ory, while multiplying two W registers and accumulating
and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM data
space be split for these instructions and linear for all
others. Data space partitioning is achieved in a trans-
parent and flexible manner through dedicating certain
working registers to each address space.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 38 2011-2012 Microchip Technology Inc.
3.3 Special MCU Features
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 supports 16/16
and 32/16 divide operations, both fractional and
integer. All divide instructions are iterative operations.
They must be executed within a REPEAT loop, resulting
in a total execution time of 19 instruction cycles. The
divide operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
CPU CORE BLOCK DIAGRAM
Instruction
Decode and
Control
PCH PCL
Program Counter
16-Bit ALU
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
EA MUX
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Control Signals
to Various Blocks
Literal Data
16 16
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM Y RAM
Address Generator Units
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
16
23
23
16
8
PSV and Table
Data Access
Control Block
16
16
16
16
Program Memory
Data Latch
Address Latch
2011-2012 Microchip Technology Inc. DS70652E-page 39
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 3-2: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
PROGRAMMER’S MODEL
PC22 PC0
7 0
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators
ACCA
ACCB
7 0
Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15 0
REPEAT Loop Counter
DCOUNT
15 0
DO Loop Counter
DOSTART
22 0
DO Loop Start Address
IPL2 IPL1
SPLIM Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15 0
Core Configuration Register
Legend
CORCON
DA DC RA N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 40 2011-2012 Microchip Technology Inc.
3.4 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0
OA OB SA(1)SB(1)OAB SAB DA DC
bit 15 bit 8
R/W-0(3)R/W-0(3)R/W-0(3)R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL<2:0>(2)RA N OV Z C
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
2011-2012 Microchip Technology Inc. DS70652E-page 41
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 42 2011-2012 Microchip Technology Inc.
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — —USEDT
(1)DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3(2)PSV RND IF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15-13 Unimplemented: Read as ‘0’
bit 12 US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing DO loop at end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops is active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply ops
0 = Fractional mode is enabled for DSP multiply ops
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
2011-2012 Microchip Technology Inc. DS70652E-page 43
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.5 Arithmetic Logic Unit (ALU)
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts,
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU can affect the
values of the Carry (C), Zero (Z), Negative (N), Over-
flow (OV), and Digit Carry (DC) Status bits in the SR
register. The C and DC Status bits operate as Borrow
and Digit Borrow bits, respectively, for subtraction
operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 CPU incorpo-
rates hardware support for both multiplication and
division. This includes a dedicated hardware multiplier
and support hardware for 16-bit-divisor division.
3.5.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
3.5.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.6 DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 is a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the
same instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumula-
tor-to-accumulator operations that require no additional
data. These instructions are ADD, SUB, and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or Integer DSP Multiply (IF)
• Signed or Unsigned DSP Multiply (US)
• Conventional or Convergent Rounding (RND)
• Automatic Saturation On/Off for ACCA (SATA)
• Automatic Saturation On/Off for ACCB (SATB)
• Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
• Accumulator Saturation mode Selection (ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1: DSP INSTRUCTIONS
SUMMARY
Instruction Algebraic
Operation
ACC Write
Back
CLR A = 0 Yes
ED A = (x – y)2No
EDAC A = A + (x – y)2No
MAC A = A + (x * y) Yes
MAC A = A + x2No
MOVSAC No change in AYes
MPY A = x * y No
MPY A = x 2No
MPY.N A = – x * y No
MSC A = A – x * y Yes
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 44 2011-2012 Microchip Technology Inc.
FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM
Zero Backfill
Sign-Extend
Barrel
Shifter
40-Bit Accumulator A
40-Bit Accumulator B Round
Logic
X Data Bus
To/From W Array
Adder
Saturate
Negate
32
32
33
16
16 16
16
40 40
40 40
S
a
t
u
r
a
t
e
Y Data Bus
40
Carry/Borrow Out
Carry/Borrow In
16
40
Multiplier/Scaler
17-Bit
2011-2012 Microchip Technology Inc. DS70652E-page 45
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.6.1 MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most Signifi-
cant bit (MSb) is defined as a sign bit. The range of an
N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a
1.31 product that has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
3.6.2.1 Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described previously, and the SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value, to
saturate.
Six STATUS register bits support saturation and
overflow:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and
saturated (bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and
saturated (bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when OA and OB are set and
the corresponding Overflow Trap Flag Enable bits
(OVATE, OVBTE) in the INTCON1 register are set
(refer to Section 7.0 “Interrupt Controller”). This
allows the user application to take immediate action; for
example, to correct system gain.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 46 2011-2012 Microchip Technology Inc.
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow, and therefore, indicate that a
catastrophic overflow has occurred. If the COVTE bit in
the INTCON1 register is set, the SA and SB bits will
generate an arithmetic warning trap when saturation is
disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programmers can check one bit in
the STATUS register to determine whether either
accumulator has overflowed, or one bit to determine
whether either accumulator has saturated. This is
useful for complex number arithmetic, which typically
uses both accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
value (0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator.
The SA or SB bit is set and remains set until
cleared by the user application. This condition is
referred to as ‘super saturation’ and provides pro-
tection against erroneous data or unexpected
algorithm problems (such as gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
3.6.3 ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED, and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator which is not targeted by the instruc-
tion into data space memory. The write is performed
across the X bus into combined X and Y address
space. The following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
3.6.3.1 Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit,
1.15 data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word (lsw) is simply discarded.
Conventional rounding will zero-extend bit 15 of the
accumulator and will add it to the ACCxH word (bits 16
through 31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the accu-
mulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a succes-
sion of random rounding operations, the value tends to
be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (LSb), bit 16 of the accumulator, of
ACCxH is examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
2011-2012 Microchip Technology Inc. DS70652E-page 47
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 3.6.3.2 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator write-
back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
3.6.3.2 Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit,
1.15 fractional value from the round logic block as its
input, together with overflow status from the original
source (accumulator) and the 16-bit round adder.
These inputs are combined and used to select the
appropriate 1.15 fractional value as output to write to
data space memory.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative
1.15 value, 0x8000.
The MSb of the source (bit 39) is used to determine the
sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
3.6.4 BARREL SHIFTER
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts, in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between Bit Positions 16
and 31 for right shifts, and between Bit Positions 0 and
16 for left shifts.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 48 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 49
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.0 MEMORY ORGANIZATION
The device architecture features separate program and
data memory spaces and buses. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1 Program Address Space
The program address memory space of the
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices is 4M instructions. The space
is addressable by a 24-bit value derived either from the
23-bit Program Counter (PC) during program execution,
or from table operation or data space remapping as
described in Section 4.6 “Interfacing Program and
Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps for the dsPIC33FJ16(GP/MC)101/
102 and dsPIC33FJ32(GP/MC)101/102/104 family of
devices re shown in Figure 4-1 and Figure 4-2.
FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES
Note: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 3. “Data Memory”
(DS70202) and Section 4. “Program
Memory” (DS70203) in the “dsPIC33F/
PIC24H Family Reference Manual”, which
are available from the Microchip web site
(www.microchip.com).
Reset Address
0x000000
0x0000FE
0x000002
0x000100
Device Configuration
User Program
Flash Memory
0x002BFC
0x002BFA
(5.6K instructions)
0x800000
0xF80000
Shadow Registers
0xF80017
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
0xF7FFFE
Unimplemented
(Read ‘
0
’s)
GOTO
Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
0x000104
Alternate Vector Table
Reserved
Interrupt Vector Table
Configuration Memory Space User Memory Space
Flash Configuration
Words
(1)
0x002COO
0x002BFE
Note 1: On Reset, these bits are automatically copied into the device Configuration Shadow registers.
0xF80018
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 50 2011-2012 Microchip Technology Inc.
FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33FJ32(GP/MC)101/102/104 DEVICES
0x000000
0x0000FE
0x000002
0x000100
Device Configuration
User Program
Flash Memory
0x0057FC
0x0057FA
(11.2K instructions)
0x800000
0xF80000
Shadow Registers
0xF80020
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
0xF7FFFE
Unimplemented
(Read ‘
0
’s)
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
0x000104
Alternate Vector Table
Reserved
Interrupt Vector Table
Configuration Memory Space User Memory Space
Flash Configuration
Words
(1)
0x005800
0x0057FE
Note 1: On Reset, these bits are automatically copied into the device Configuration Shadow registers.
0xF80022
GOTO
Instruction
Reset Address
2011-2012 Microchip Technology Inc. DS70652E-page 51
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.1.1 PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-3).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
4.1.2 INTERRUPT AND TRAP VECTORS
All dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices reserve
the addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user application at 0x000000, with the actual
address for the start of code at 0x000002.
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices also have two Interrupt Vec-
tor Tables (IVTs), located from 0x000004 to 0x0000FF
and 0x000100 to 0x0001FF. These vector tables allow
each of the device interrupt sources to be handled by
separate Interrupt Service Routines (ISRs). A more
detailed discussion of the Interrupt Vector Tables is
provided in Section 7.1 “Interrupt Vector Table”.
FIGURE 4-3: PROGRAM MEMORY ORGANIZATION
0816
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
least significant word (lsw)
most significant word (msw)
Instruction Width
0x000001
0x000003
0x000005
0x000007
msw
Address (lsw Address)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 52 2011-2012 Microchip Technology Inc.
4.2 Data Address Space
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 CPU has a
separate 16-bit-wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps is shown in Figure 4-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
Microchip dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices imple-
ment up to 2 Kbytes of data memory. Should an EA
point to a location outside of this area, an all-zero word
or byte will be returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2 DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 instruction set
supports both word and byte operations. As a
consequence of byte accessibility, all Effective Address
calculations are internally scaled to step through word-
aligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decoding
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in progress is completed. If the error
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternately, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3 SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 core and peripheral modules for
controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.4 NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV class of instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode with a working register
as an Address Pointer.
Note: The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
2011-2012 Microchip Technology Inc. DS70652E-page 53
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES WITH
1-KBYTE RAM
0x0000
0x07FE
0x0BFE
0xFFFE
LSB
Address
16 Bits
LSbMSb
MSB
Address
0x0001
0x07FF
0xFFFF
Optionally
Mapped
into Program
Memory
0x0801 0x0800
0x0C00
2-Kbyte
SFR Space
1-Kbyte
SRAM Space
0x8001 0x8000
X Data
Unimplemented (X)
Y Data RAM (Y)
0x09FE
0x0A00
0x09FF
0x0A01
0x0BFF
0x0C01
0x1FFF 0x1FFE
0x2001 0x2000
8-Kbyte
Near Data
Space
X Data RAM (X)
SFR Space
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 54 2011-2012 Microchip Technology Inc.
FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ32(GP/MC)101/102/104 DEVICES WITH
2-KBYTE RAM
0x0000
0x07FE
0x0FFE
0xFFFE
LSB
Address
16 Bits
LSbMSb
MSB
Address
0x0001
0x07FF
0xFFFF
Optionally
Mapped
into Program
Memory
0x0801 0x0800
0x1000
2 Kbyte
SFR Space
2 Kbyte
SRAM Space
0x8001 0x8000
SFR Space
X Data
Unimplemented (X)
Y Data RAM (Y)
0x0BFE
0x0C00
0x0BFF
0x0C01
0x0FFF
0x1001
0x1FFF 0x1FFE
0x2001 0x2000
8 Kbyte
Near Data
Space
X Data RAM (X)
2011-2012 Microchip Technology Inc. DS70652E-page 55
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.2.5 X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide
two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, although the
implemented memory locations vary by device.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 56 2011-2012 Microchip Technology Inc.
TABLE 4-1: CPU CORE REGISTER MAP
SFR Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
WREG0 0000 Working Register 0 xxxx
WREG1 0002 Working Register 1 xxxx
WREG2 0004 Working Register 2 xxxx
WREG3 0006 Working Register 3 xxxx
WREG4 0008 Working Register 4 xxxx
WREG5 000A Working Register 5 xxxx
WREG6 000C Working Register 6 xxxx
WREG7 000E Working Register 7 xxxx
WREG8 0010 Working Register 8 xxxx
WREG9 0012 Working Register 9 xxxx
WREG10 0014 Working Register 10 xxxx
WREG11 0016 Working Register 11 xxxx
WREG12 0018 Working Register 12 xxxx
WREG13 001A Working Register 13 xxxx
WREG14 001C Working Register 14 xxxx
WREG15 001E Working Register 15 0800
SPLIM 0020 Stack Pointer Limit Register xxxx
ACCAL 0022 Accumulator A Low Word Register xxxx
ACCAH 0024 Accumulator A High Word Register xxxx
ACCAU 0026 Accumulator A Upper Word Register xxxx
ACCBL 0028 Accumulator B Low Word Register xxxx
ACCBH 002A Accumulator B High Word Register xxxx
ACCBU 002C Accumulator B Upper Word Register xxxx
PCL 002E Program Counter Low Word Register 0000
PCH 0030 — — — — — — — — Program Counter High Byte Register 0000
TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000
PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000
RCOUNT 0036 Repeat Loop Counter Register xxxx
DCOUNT 0038 DCOUNT<15:0> xxxx
DOSTARTL 003A DOSTARTL<15:1> 0xxxx
DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx
DOENDL 003E DOENDL<15:1> 0xxxx
DOENDH 0040 — — — — — — — — — — DOENDH 00xx
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 — — — US EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020
MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2012 Microchip Technology Inc. DS70652E-page 57
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
XMODSRT 0048 XS<15:1> 0xxxx
XMODEND 004A XE<15:1> 1xxxx
YMODSRT 004C YS<15:1> 0xxxx
YMODEND 004E YE<15:1> 1xxxx
XBREV 0050 BREN XB<14:0> xxxx
DISICNT 0052 —— Disable Interrupts Counter Register 0000
TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)
SFR Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 58 2011-2012 Microchip Technology Inc.
TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CNEN1 0060 — — — CN12IE CN11IE — — — — — CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE — — — — — CN23IE CN22IE CN21IE — — — — — 0000
CNPU1 0068 — — — CN12PUE CN11PUE — — — — — CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE — — — — — CN23PUE CN22PUE CN21PUE — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXMC101 DEVICES
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CNEN1 0060 — CN14IE CN13IE CN12IE CN11IE — — — — — CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE — — — — — CN23IE CN22IE CN21IE — — — — — 0000
CNPU1 0068 — CN14PUE CN13PUE CN12PUE CN11PUE — — — — — CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE — — — — — CN23PUE CN22PUE CN21PUE — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE —CN27IE—— CN24IE CN23IE CN22IE CN21IE ————CN16IE0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE — CN27PUE —— CN24PUE CN23PUE CN22PUE CN21PUE ———— CN16PUE 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-5: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0All
Resets
CNEN1 0060 CN15IE CN13IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000
CNPU1 0068 CN15PUE CN13PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2012 Microchip Technology Inc. DS70652E-page 59
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000
IFS0 0084 —— AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000
IFS1 0086 ——INT2IFT5IF
(2)T4IF(2)— — — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0088 — — — — — — — — — —IC3IF — — — — — 0000
IFS3 008A FLTA1IF(1)RTCIF — — — —PWM1IF
(1)— — — — — — — — — 0000
IFS4 008C ——CTMUIF — — — — — — — — — — — U1EIF FLTB1IF(3)0000
IEC0 0094 —— AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000
IEC1 0096 —— INT2IE T5IE(2)T4IE(2)— — — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0098 — — — — — — — — — —IC3IE — — — — — 0000
IEC3 009A FLTA1IE(1)RTCIE — — — —PWM1IE
(1)— — — — — — — — — 0000
IEC4 009C ——CTMUIE — — — — — — — — — — — U1EIE FLTB1IE(3)0000
IPC0 00A4 — T1IP<2:0> —OC1IP<2:0>—IC1IP<2:0>— INT0IP<2:0> 4444
IPC1 00A6 — T2IP<2:0> —OC2IP<2:0>—IC2IP<2:0>— — — — 4440
IPC2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 00AA — — — — — — — — —AD1IP<2:0>— U1TXIP<2:0> 0044
IPC4 00AC — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 00AE — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 00B0 — T4IP<2:0>(2)— — — — — — — — — — — — 4000
IPC7 00B2 — — — — — — — — — INT2IP<2:0> — T5IP<2:0>(2)0044
IPC9 00B6 — — — — — — — — —IC3IP<2:0>— — — — 0040
IPC14 00C0 — — — — — — — — — PWM1IP<2:0>(1)— — — — 0040
IPC15 00C2 — FLTA1IP<2:0>(1)— RTCIP<2:0> — — — — — — — — 4400
IPC16 00C4 — — — — — — — — —U1EIP<2:0>— FLTB1IP<2:0>(3)0040
IPC19 00CA — — — — — — — — — CTMUIP<2:0> — — — — 0040
INTTREG 00E0 — — — —ILR<3:0> — VECNUM<6:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available in dsPIC33FJXXMC10X devices only.
2: This bit is available in dsPIC33FJ32(GP/MC)10X devices only.
3: This bit is available in dsPIC33FJ(16/32)MC102/104 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 60 2011-2012 Microchip Technology Inc.
TABLE 4-7: TIMERS REGISTER MAP FOR dsPIC33FJ16(GP/MC)10X DEVICES
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TMR1 0100 Timer1 Register 0000
PR1 0102 Period Register 1 FFFF
T1CON 0104 TON —TSIDL—————— TGATE TCKPS<1:0> —TSYNCTCS —0000
TMR2 0106 Timer2 Register 0000
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx
TMR3 010A Timer3 Register 0000
PR2 010C Period Register 2 FFFF
PR3 010E Period Register 3 FFFF
T2CON 0110 TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000
T3CON 0112 TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8: TIMERS REGISTER MAP FOR DSPIC33FJ32(GP/MC)10X DEVICES
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TMR1 0100 Timer1 Register 0000
PR1 0102 Period Register 1 FFFF
T1CON 0104 TON —TSIDL—————— TGATE TCKPS<1:0> —TSYNCTCS —0000
TMR2 0106 Timer2 Register 0000
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx
TMR3 010A Timer3 Register 0000
PR2 010C Period Register 2 FFFF
PR3 010E Period Register 3 FFFF
T2CON 0110 TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000
T3CON 0112 TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000
TMR4 0114 Timer4 Register 0000
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx
TMR5 0118 Timer5 Register 0000
PR4 011A Period Register 4 FFFF
PR5 011C Period Register 5 FFFF
T4CON 011E TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000
T5CON 0120 TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2012 Microchip Technology Inc. DS70652E-page 61
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 4-9: INPUT CAPTURE REGISTER MAP
SFR Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
IC1BUF 0140 Input 1 Capture Register xxxx
IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
IC2BUF 0144 Input 2 Capture Register xxxx
IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
IC3BUF 0148 Input 3 Capture Register xxxx
IC3CON 014A ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10: OUTPUT COMPARE REGISTER MAP
SFR Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
OC1RS 0180 Output Compare 1 Secondary Register xxxx
OC1R 0182 Output Compare 1 Register xxxx
OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000
OC2RS 0186 Output Compare 2 Secondary Register xxxx
OC2R 0188 Output Compare 2 Register xxxx
OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11: 6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJXXMC10X DEVICES
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
P1TCON 01C0 PTEN —PTSIDL ————— PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0>
0000 0000 0000 0000
P1TMR 01C2 PTDIR PWM Timer Count Value Register
0000 0000 0000 0000
P1TPER 01C4 — PWM Time Base Period Register
0111 1111 1111 1111
P1SECMP 01C6 SEVTDIR PWM Special Event Compare Register
0000 0000 0000 0000
PWM1CON1
01C8 —————PMOD3PMOD2PMOD1— PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L
0000 0000 0000 0000
PWM1CON2
01CA ————SEVOPS<3:0>— — — — — IUE OSYNC UDIS
0000 0000 0000 0000
P1DTCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0>
0000 0000 0000 0000
P1DTCON2 01CE — — — — — — — — — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I
0000 0000 0000 0000
P1FLTACON 01D0 —— FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM ———— FAEN3 FAEN2 FAEN1
0000 0000 0000 0111
P1FLTBCON 01D2 —— FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM ———— FBEN3 FBEN2 FBEN1
0000 0000 0000 0111
P1OVDCON 01D4 —— POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L —— POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L
0011 1111 0000 0000
P1DC1 01D6 PWM Duty Cycle 1 Register
0000 0000 0000 0000
P1DC2 01D8 PWM Duty Cycle 2 Register
0000 0000 0000 0000
P1DC3 01DA PWM Duty Cycle 3 Register
0000 0000 0000 0000
PWM1KEY 01DE PWMKEY <15:0>
0000 0000 0000 0000
Legend: — = unimplemented, read as ‘0’
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 62 2011-2012 Microchip Technology Inc.
TABLE 4-12: I2C1 REGISTER MAP
SFR Name SFR
Addr Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 All
Resets
I2C1RCV 0200 — ——————— Receive Register 0000
I2C1TRN 0202 — ——————— Transmit Register 00FF
I2C1BRG 0204 — —————— Baud Rate Generator Register 0000
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1STAT 0208 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000
I2C1ADD 020A — ————— Address Register 0000
I2C1MSK 020C — ————— Address Mask Register 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: UART1 REGISTER MAP
SFR Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UART Transmit Register xxxx
U1RXREG 0226 — — — — — — — UART Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14: SPI1 REGISTER MAP
SFR
Name
SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
SPI1STAT 0240 SPIEN — SPISIDL ——————SPIROV— — — —SPITBFSPIRBF0000
SPI1CON1 0242 ——— DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000
SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — —FRMDLY—0000
SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2012 Microchip Technology Inc. DS70652E-page 63
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)101 DEVICES
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
ADC1BUF0 0300 ADC Data Buffer 0 xxxx
ADC1BUF1 0302 ADC Data Buffer 1 xxxx
ADC1BUF2 0304 ADC Data Buffer 2 xxxx
ADC1BUF3 0306 ADC Data Buffer 3 xxxx
ADC1BUF4 0308 ADC Data Buffer 4 xxxx
ADC1BUF5 030A ADC Data Buffer 5 xxxx
ADC1BUF6 030C ADC Data Buffer 6 xxxx
ADC1BUF7 030E ADC Data Buffer 7 xxxx
ADC1BUF8 0310 ADC Data Buffer 8 xxxx
ADC1BUF9 0312 ADC Data Buffer 9 xxxx
ADC1BUFA 0314 ADC Data Buffer 10 xxxx
ADC1BUFB 0316 ADC Data Buffer 11 xxxx
ADC1BUFC 0318 ADC Data Buffer 12 xxxx
ADC1BUFD 031A ADC Data Buffer 13 xxxx
ADC1BUFE 031C ADC Data Buffer 14 xxxx
ADC1BUFF 031E ADC Data Buffer 15 xxxx
AD1CON1 0320 ADON —ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000
AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000
AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000
AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000
AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000
AD1PCFGL 032C — — — — —PCFG10
(1)PCFG9(1)— — — — — PCFG3 PCFG2 PCFG1 PCFG0 0000
AD1CSSL 0330 — — — — — CSS10(1)CSS9(1)— — — — — CSS3 CSS2 CSS1 CSS0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available in dsPIC33FJ32(GP/MC)101/102 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 64 2011-2012 Microchip Technology Inc.
TABLE 4-16: ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
ADC1BUF0 0300 ADC Data Buffer 0 xxxx
ADC1BUF1 0302 ADC Data Buffer 1 xxxx
ADC1BUF2 0304 ADC Data Buffer 2 xxxx
ADC1BUF3 0306 ADC Data Buffer 3 xxxx
ADC1BUF4 0308 ADC Data Buffer 4 xxxx
ADC1BUF5 030A ADC Data Buffer 5 xxxx
ADC1BUF6 030C ADC Data Buffer 6 xxxx
ADC1BUF7 030E ADC Data Buffer 7 xxxx
ADC1BUF8 0310 ADC Data Buffer 8 xxxx
ADC1BUF9 0312 ADC Data Buffer 9 xxxx
ADC1BUFA 0314 ADC Data Buffer 10 xxxx
ADC1BUFB 0316 ADC Data Buffer 11 xxxx
ADC1BUFC 0318 ADC Data Buffer 12 xxxx
ADC1BUFD 031A ADC Data Buffer 13 xxxx
ADC1BUFE 031C ADC Data Buffer 14 xxxx
ADC1BUFF 031E ADC Data Buffer 15 xxxx
AD1CON1 0320 ADON —ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000
AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000
AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000
AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000
AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000
AD1PCFGL 032C — — — — —PCFG10
(1)PCFG9(1)— — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
AD1CSSL 0330 — — — — — CSS10(1)CSS9(1)— — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available in dsPIC33FJ32(GP/MC)101/102 devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 65
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 4-17: ADC1 REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
ADC1BUF0 0300 ADC Data Buffer 0 xxxx
ADC1BUF1 0302 ADC Data Buffer 1 xxxx
ADC1BUF2 0304 ADC Data Buffer 2 xxxx
ADC1BUF3 0306 ADC Data Buffer 3 xxxx
ADC1BUF4 0308 ADC Data Buffer 4 xxxx
ADC1BUF5 030A ADC Data Buffer 5 xxxx
ADC1BUF6 030C ADC Data Buffer 6 xxxx
ADC1BUF7 030E ADC Data Buffer 7 xxxx
ADC1BUF8 0310 ADC Data Buffer 8 xxxx
ADC1BUF9 0312 ADC Data Buffer 9 xxxx
ADC1BUFA 0314 ADC Data Buffer 10 xxxx
ADC1BUFB 0316 ADC Data Buffer 11 xxxx
ADC1BUFC 0318 ADC Data Buffer 12 xxxx
ADC1BUFD 031A ADC Data Buffer 13 xxxx
ADC1BUFE 031C ADC Data Buffer 14 xxxx
ADC1BUFF 031E ADC Data Buffer 15 xxxx
AD1CON1 0320 ADON —ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000
AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS —SMPI<3:0>BUFMALTS0000
AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000
AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000
AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000
AD1PCFGL 032C PCFG15 —— PCFG12 PCFG11 PCFG10(1)PCFG9(1)PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
AD1CSSL 0330 CSS15 —— CSS12 CSS11 CSS10(1)CSS9(1)CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available in dsPIC33FJ32(GP/MC)104 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 66 2011-2012 Microchip Technology Inc.
TABLE 4-18: CTMU REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CTMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000
CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000
CTMUICON 033E ITRIM<5:0> IRNG<1:0> — — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
ALRMVAL 0620 Alarm Value Register Window based on APTR<1:0> xxxx
ALCFGRPT 0622 ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0> ARPT<7:0> 0000
RTCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0> xxxx
RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR<1:0> CAL<7:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: PAD CONFIGURATION REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PADCFG1 02FC — — — — — — — — — — — — — — RTSECSEL —0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2012 Microchip Technology Inc. DS70652E-page 67
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 4-21: COMPARATOR REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CMSTAT 0650 CMSIDL — — — — C3EVT C2EVT C1EVT ———— — C3OUT C2OUT C1OUT 0000
CVRCON 0652 — — — — — VREFSEL BGSEL<1:0> CVREN CVROE CVRR —CVR<3:0>0000
CM1CON 0654 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF —— CCH<1:0> 0000
CM1MSKSRC 0656 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM1MSKCON 0658 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM1FLTR 065A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM2CON 065C CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF —— CCH<1:0> 0000
CM2MSKSRC 065E — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM2MSKCON 0660 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM2FLTR 0662 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM3CON 0664 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF —— CCH<1:0> 0000
CM3MSKSRC 0666 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM3MSKCON 0668 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM3FLTR 066A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPINR0 0680 — — — INT1R<4:0> — — — — — — — — 1F00
RPINR1 0682 — — — — — — — — — — —INT2R<4:0>001F
RPINR3 0686 — — —T3CKR<4:0>— — —T2CKR<4:0>1F1F
RPINR4 0688 — — —T5CKR<4:0>
(1)— — —T4CKR<4:0>
(1)1F1F
RPINR7 068E — — — IC2R<4:0> — — — IC1R<4:0> 1F1F
RPINR8 0690 — — — — — — — — — — — IC3R<4:0> 001F
RPINR11 0696 — — — — — — — — — — —OCFAR<4:0>001F
RPINR18 06A4 — — — U1CTSR<4:0> — — —U1RXR<4:0>1F1F
RPINR20 06A8 — — —SCK1R<4:0>
(1)— — —SDI1R<4:0>
(1)1F1F
RPINR21 06AA — — — — — — — — — — — SS1R<4:0> 001F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 68 2011-2012 Microchip Technology Inc.
TABLE 4-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000
RPOR2 06C4 — — — — — — — — — — — RP4R<4:0> 0000
RPOR3 06C6 — — —RP7R<4:0>— — — — — — — — 0000
RPOR4 06C8 — — —RP9R<4:0>— — — RP8R<4:0> 0000
RPOR7 06CE — — — RP15R<4:0> — — —RP14R<4:0>0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXXMC101 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000
RPOR2 06C4 — — — — — — — — — — — RP4R<4:0> 0000
RPOR3 06C6 — — —RP7R<4:0>— — — — — — — — 0000
RPOR4 06C8 — — —RP9R<4:0>— — — RP8R<4:0> 0000
RPOR6 06CC — — — RP13R<4:0> — — —RP12R<4:0>0000
RPOR7 06CE — — — RP15R<4:0> — — —RP14R<4:0>0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 06C0 — — — RP1R<4:0> ——— RP0R<4:0> 0000
RPOR1 06C2 — — — RP3R<4:0> ——— RP2R<4:0> 0000
RPOR2 06C4 — — — RP5R<4:0> ——— RP4R<4:0> 0000
RPOR3 06C6 — — — RP7R<4:0> ——— RP6R<4:0> 0000
RPOR4 06C8 — — — RP9R<4:0> ——— RP8R<4:0> 0000
RPOR5 06CA — — —RP11R<4:0>——— RP10R<4:0> 0000
RPOR6 06CC — — —RP13R<4:0>——— RP12R<4:0> 0000
RPOR7 06CE — — —RP15R<4:0>——— RP14R<4:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2012 Microchip Technology Inc. DS70652E-page 69
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 06C0 — — — RP1R<4:0> ——— RP0R<4:0> 0000
RPOR1 06C2 — — — RP3R<4:0> ——— RP2R<4:0> 0000
RPOR2 06C4 — — — RP5R<4:0> ——— RP4R<4:0> 0000
RPOR3 06C6 — — — RP7R<4:0> ——— RP6R<4:0> 0000
RPOR4 06C8 — — — RP9R<4:0> ——— RP8R<4:0> 0000
RPOR5 06CA — — —RP11R<4:0>——— RP10R<4:0> 0000
RPOR6 06CC — — —RP13R<4:0>——— RP12R<4:0> 0000
RPOR7 06CE — — —RP15R<4:0>——— RP14R<4:0> 0000
RPOR8 06D0 — — — RP17R<4:0> ——— RP16R<4:0> 0000
RPOR9 06D2 — — —RP19R<4:0>——— RP18R<4:0> 0000
RPOR10 06D4 — — —RP21R<4:0>——— RP20R<4:0> 0000
RPOR11 06D6 — — —RP23R<4:0>——— RP22R<4:0> 0000
RPOR12 06D8 — — —RP25R<4:0>——— RP24R<4:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-27: PORTA REGISTER MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F
PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx
LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
ODCA 02C6 — — — — — — — — — — — ODCA4 ODCA3 ODCA2 — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-28: PORTA REGISTER MAP FOR dsPIC33FJ32(GP/MC)101/102 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F
PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx
LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
ODCA 02C6 — — — — — — — — — — — — ODCA3 ODCA2 — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 70 2011-2012 Microchip Technology Inc.
TABLE 4-29: PORTA REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 —— TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F
PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 —— RA4 RA3 RA2 RA1 RA0 xxxx
LATA 02C4 — — — — — LATA10 LATA9 LATA8 LATA7 —— LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
ODCA 02C6 — — — — — ODCA10 ODCA9 ODCBA ODCA7 — — — ODCA3 ODCA2 — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-30: PORTB REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB15 TRISB14 ———— TRISB9 TRISB8 TRISB7 —— TRISB4 —— TRISB1 TRISB0 C393
PORTB 02CA RB15 RB14 ———— RB9 RB8 RB7 ——RB4——RB1RB0xxxx
LATB 02CC LATB15 LATB14 ———— LATB9 LATB8 LATB7 ——LATB4——LATB1LATB0xxxx
ODCB 02CE ODCB15 ODCB14 ———— ODCB9 ODCB8 ODCB7 —— ODCB4 — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
TABLE 4-31: PORTB REGISTER MAP FOR dsPIC33FJ16MC101 DEVICES
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 —— TRISB9 TRISB8 TRISB7 —— TRISB4 —— TRISB1 TRISB0 F393
PORTB 02CA RB15 RB14 RB13 RB12 —— RB9 RB8 RB7 ——RB4——RB1RB0xxxx
LATB 02CC LATB15 LATB14 LATB13 LATB12 —— LATB9 LATB8 LATB7 ——LATB4 ——LATB1LATB0xxxx
ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 —— ODCB9 ODCB8 ODCB7 —— ODCB4 — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
TABLE 4-32: PORTB REGISTER MAP FOR dsPIC33FJ16(GP/MC)102 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2012 Microchip Technology Inc. DS70652E-page 71
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 4-33: PORTB REGISTER MAP FOR dsPIC33FJ32GP101 DEVICES
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB15 TRISB14 ———— TRISB9 TRISB8 TRISB7 —— TRISB4 —— TRISB1 TRISB0 C393
PORTB 02CA RB15 RB14 ———— RB9 RB8 RB7 ——RB4——RB1RB0xxxx
LATB 02CC LATB15 LATB14 ———— LATB9 LATB8 LATB7 ——LATB4——LATB1LATB0xxxx
ODCB 02CE ODCB15 ODCB14 ———— ODCB9 ODCB8 ODCB7 — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
TABLE 4-34: PORTB REGISTER MAP FOR dsPIC33FJ32MC101 DEVICES
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 —— TRISB9 TRISB8 TRISB7 —— TRISB4 —— TRISB1 TRISB0 F393
PORTB 02CA RB15 RB14 RB13 RB12 —— RB9 RB8 RB7 ——RB4——RB1RB0xxxx
LATB 02CC LATB15 LATB14 LATB13 LATB12 —— LATB9 LATB8 LATB7 ——LATB4 ——LATB1LATB0xxxx
ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 —— ODCB9 ODCB8 ODCB7 — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
TABLE 4-35: PORTB REGISTER MAP FOR dsPIC33FJ32(GP/MC)102 AND dsPIC33FJ32(GP/MC)104 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-36: PORTC REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISC 02D8 —————— TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 FFFF
PORTC 02DA —————— RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx
LATC 02DC —————— LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx
ODCC 02DE —————— ODCC9 ODCC8 ODCC7 ODCC6 — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 72 2011-2012 Microchip Technology Inc.
TABLE 4-37: SYSTEM CONTROL REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1)
OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK —CF— LPOSCEN OSWEN 0300(2)
CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> — — — — — — — — 3040
OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-38: NVM REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
NVMCON 0760 WR WREN WRERR —————— ERASE —— NVMOP<3:0> 0000(1)
NVMKEY 0766 ———————— NVMKEY<7:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-39: PMD REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0770 T5MD(2)T4MD(2)T3MD T2MD T1MD —PWM1MD
(1)— I2C1MD —U1MD— SPI1MD ——AD1MD0000
PMD2 0772 — — — — — IC3MD IC2MD IC1MD — — — — — —OC2MDOC1MD0000
PMD3 0774 — — — — — CMPMD RTCCMD — — — — — — — — — 0000
PMD4 0776 — — — — — — — — — — — — —CTMUMD— — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available in dsPIC33FJXXMC10X devices only.
2: This bit is available in dsPIC33FJ32(GP/MC)10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 73
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.2.6 SOFTWARE STACK
In addition to its use as a working register, the W15
register in the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices is also
used as a software Stack Pointer. The Stack Pointer
always points to the first available free word and grows
from lower to higher addresses. It pre-decrements for
stack pops and post-increments for stack pushes, as
shown in Figure 4-6. For a PC push during any CALL
instruction, the MSb of the PC is zero-extended before
the push, ensuring that the MSb is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. However, the stack error trap will
occur on a subsequent push operation. For example, to
cause a stack error trap when the stack grows beyond
address 0x0C00 in RAM, initialize the SPLIM with the
value 0x0BFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the SFR space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6: CALL STACK FRAME
4.2.7 DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
Segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM Segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
4.3 Instruction Addressing Modes
The addressing modes shown in Table 4-40 form the
basis of the addressing modes that are optimized to
support the specific features of individual instructions.
The addressing modes provided in the MAC class of
instructions differ from those provided in other
instruction types.
4.3.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
Note: A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Toward
Higher Address
0x0000
PC<22:16>
POP : [--W15]
PUSH : [W15++]
Note: Not all instructions support all of the
addressing modes given above.
Individual instructions can support
different subsets of these addressing
modes.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 74 2011-2012 Microchip Technology Inc.
TABLE 4-40: FUNDAMENTAL ADDRESSING MODES SUPPORTED
4.3.3 MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
In summary, the following addressing modes are
supported by move and accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-Bit Literal
• 16-Bit Literal
4.3.4 MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC, and MSC), also
referred to as MAC instructions, use a simplified set of
addressing modes to allow the user application to
effectively manipulate the Data Pointers through
register indirect tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
4.3.5 OTHER INSTRUCTIONS
In addition to the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the Effective Address (EA).
Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset
(Register Indexed)
The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
Note: For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared by both source and destination
(but typically only used by one).
Note: Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
Note: Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
2011-2012 Microchip Technology Inc. DS70652E-page 75
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.4 Modulo Addressing
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the Data Pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W Register Pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be config-
ured to operate in only one direction as there are
certain restrictions on the buffer start address (for incre-
menting buffers), or end address (for decrementing
buffers), based upon the direction of the circular buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
4.4.1 START AND END ADDRESS
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT, and YMODEND
(see Tab le 4 -1 ).
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.4.2 W ADDRESS REGISTER
SELECTION
• The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags
as well as a W register field to specify the W
Address registers. The XWM and YWM fields
select which registers will operate with Modulo
Addressing.
• If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled.
• If YWM = 15, Y AGU Modulo Addressing is
disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
Note: Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 76 2011-2012 Microchip Technology Inc.
FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE
0x1100
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 Words
Byte
Address
MOV #0x1100, W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163, W0
MOV W0, MODEND ;set modulo end address
MOV #0x8001, W0
MOV W0, MODCON ;enable W1, X AGU for modulo
MOV #0x0000, W0 ;W0 holds buffer fill value
MOV #0x1110, W1 ;point W1 to buffer
DO AGAIN, #0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0, W0 ;increment the fill value
2011-2012 Microchip Technology Inc. DS70652E-page 77
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.4.3 MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
4.5 Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1 BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
will not function for any other addressing mode or for
byte-sized data and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB) and the offset associated with the
Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.
Note: The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (such
as [W7 + W2]) is used, Modulo Address
correction is performed, but the contents
of the register remain unchanged.
Note: All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note: Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority, when active, for the X WAGU, and
X WAGU, Modulo Addressing will be
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 78 2011-2012 Microchip Technology Inc.
FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE
TABLE 4-41: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0000 00000 0
0001 11000 8
0010 20100 4
0011 31100 12
0100 40010 2
0101 51010 10
0110 60110 6
0111 71110 14
1000 80001 1
1001 91001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15
b3 b2 b1 0
b2 b3 b4 0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
Bit-Reversed Address
XB = 0x0008 for a 16-Word, Bit-Reversed Buffer
b7 b6 b5 b1
b7 b6 b5 b4
b11 b10 b9 b8
b11 b10 b9 b8
b15 b14 b13 b12
b15 b14 b13 b12
Sequential Address
Pivot Point
2011-2012 Microchip Technology Inc. DS70652E-page 79
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.6 Interfacing Program and Data
Memory Spaces
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 architecture uses
a 24-bit-wide program space and a 16-bit-wide data
space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
Aside from normal execution, the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
architecture provides two methods by which program
space can be accessed during operation:
• Using table instructions to access individual
bytes, or words, anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for lookups
from a large table of static data. The application can
only access the lsw of the program word.
4.6.1 ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the MSb of TBLPAG is used to determine if
the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the MSb
of the EA is ‘1’, PSVPAG is concatenated with the lower
15 bits of the EA to form a 23-bit program space
address. Unlike table operations, this limits remapping
operations strictly to the user memory area.
Table 4-42 and Figure 4-9 show how the program EA is
created for table operations and remapping accesses
from the data EA.
TABLE 4-42: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Type Access
Space
Program Space Address
<23> <22:16> <15> <14:1> <0>
Instruction Access
(Code Execution)
User 0PC<22:1> 0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
User TBLPAG<7:0> Data EA<15:0>
0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
Program Space Visibility
(Block Remap/Read)
User 0PSVPAG<7:0> Data EA<14:0>(1)
0 xxxx xxxx xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 80 2011-2012 Microchip Technology Inc.
FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
0
Program Counter
23 Bits
1
PSVPAG
8 Bits
EA
15 Bits
Program Counter(1)
Select
TBLPAG
8 Bits
EA
16 Bits
Byte Select
0
0
1/0
User/Configuration
Table Operations(2)
Program Space Visibility(1)
Space Select
24 Bits
23 Bits
(Remapping)
1/0
0
Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.6.2 DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses. Pro-
gram memory can thus be regarded as two 16-bit-wide
word address spaces, residing side by side, each with
the same address range. TBLRDL and TBLWTL access
the space that contains the least significant data word.
TBLRDH and TBLWTH access the space that contains the
upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
•TBLRDL (Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space location
(P<15:0>) to a data address (D<15:0>).
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
•TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. Note that D<15:8>, the
‘phantom byte’, will always be ‘0’.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL instruc-
tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and
configuration spaces. When TBLPAG<7> = 0, the table
page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
081623
00000000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
23 15 0
TBLPAG
02
0x000000
0x800000
0x020000
0x030000
Program Space
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 82 2011-2012 Microchip Technology Inc.
4.6.3 READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL and
TBLRDH).
Program space access through the data space occurs
if the MSb of the data space EA is ‘1’ and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON<2>). The location of
the program memory space to be mapped into the data
space is determined by the Program Space Visibility
Page register (PSVPAG). This 8-bit register defines
any one of 256 possible pages of 16K words in
program space. In effect, PSVPAG functions as the
upper 8 bits of the program memory address, with the
15 bits of the EA functioning as the lower bits. By
incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 4-11), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data, to execute in a
single cycle.
FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION
Note: PSV access is temporarily disabled during
table reads/writes.
23 15 0
PSVPAG
Data Space
Program Space
0x0000
0x8000
0xFFFF
02 0x000000
0x800000
0x010000
0x018000
When CORCON<2> = 1 and EA<15> = 1:
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
Data EA<14:0>
...while the lower 15 bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
PSV Area
2011-2012 Microchip Technology Inc. DS70652E-page 83
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
5.0 FLASH PROGRAM MEMORY
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices contain
internal Flash program memory for storing and
executing application code. The memory is readable,
writable, and erasable during normal operation over the
entire VDD range.
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
ICSP allows a device to be serially programmed while
in the end application circuit. This is done with two lines
for programming clock and programming data (one of
the alternate programming pin pairs: PGECx/PGEDx),
and three other lines for power (VDD), ground (VSS) and
Master Clear (MCLR). This allows users to manufac-
ture boards with unprogrammed devices, and then
program the Digital Signal Controller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data in a single
program memory word, and erase program memory in
blocks or ‘pages’ of 512 instructions (1536 bytes).
5.1 Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space, from the data
memory, while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash
Programming” (DS70191) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
0
Program Counter
24 Bits
Program Counter
TBLPAG Reg
8 Bits
Working Reg EA
16 Bits
Byte
24-Bit EA
0
1/0
Select
Using
Table Instruction
Using
User/Configuration
Space Select
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 84 2011-2012 Microchip Technology Inc.
5.2 RTSP Operation
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 Flash program
memory array is organized into rows of 64 instructions or
192 bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows
(512 instructions); and to program one word. Table 26-12
shows typical erase and programming times. The 8-row
erase pages are edge-aligned from the beginning of
program memory, on boundaries of 1536 bytes.
5.3 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the operation is
finished.
The programming time depends on the FRC accuracy
(see Table 26-18) and the value of the FRC Oscillator
Tuning register (see Register 8-3). Use the following
formula to calculate the minimum and maximum values
for the Word Write Time and Page Erase Time (see
Table 26-12).
EQUATION 5-1: PROGRAMMING TIME
For example, if the device is operating at +125°C, the
FRC accuracy will be ±2%. If the TUN<5:0> bits (see
Register 8-3) are set to ‘b000000, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2: MINIMUM ROW WRITE
TIME
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3: MAXIMUM ROW WRITE
TIME
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.3.1 PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
Programmers can program one word (24 bits) of
program Flash memory at a time. To do this, it is
necessary to erase the 8-row erase page that contains
the desired address of the location the user wants to
change.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs.
Refer to Section 5. “Flash Programming” (DS70191)
in the “dsPIC33F/PIC24H Family Reference Manual”
for details and codes examples on programming using
RTSP.
5.4 Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed, and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.3
“Programming Operations” for further details.
T
7.37 MHz FRC Accuracy%FRC Tuning%
--------------------------------------------------------------------------------------------------------------------------
TRW
355 Cycles
7.37 MHz 10.02+1 0.00375–
---------------------------------------------------------------------------------------------- 47.4s==
TRW
355 Cycles
7.37 MHz 10.02–1 0.00375–
----------------------------------------------------------------------------------------------49.3s==
Note: Performing a page erase operation on the
last page of program memory will clear the
Flash Configuration Words, thereby
enabling code protection as a result.
Therefore, users should avoid performing
page erase operations on the last page of
program memory.
2011-2012 Microchip Technology Inc. DS70652E-page 85
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)R/W-0(1)R/W-0(1)U-0 U-0 U-0 U-0 U-0
WR WREN WRERR — — — — —
bit 15 bit 8
U-0 R/W-0(1)U-0 U-0 R/W-0(1)R/W-0(1)R/W-0(1)R/W-0(1)
— ERASE ——NVMOP<3:0>
(2)
bit 7 bit 0
Legend: SO = Settable Only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7 Unimplemented: Read as ‘0’
bit 6 ERASE: Erase/Program Enable bit(1)
1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command
0 = Performs the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2)
If ERASE = 1:
1111 = No operation
1101 = Erase General Segment
1100 = No operation
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = No operation
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = No operation
0000 = No operation
Note 1: These bits can only be reset on a POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 86 2011-2012 Microchip Technology Inc.
REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 NVMKEY<7:0>: Key Register bits (write-only)
2011-2012 Microchip Technology Inc. DS70652E-page 87
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
6.0 RESETS
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST
. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
•MCLR
: Master Clear Pin Reset
•SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of Reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state, and some are unaffected.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 6-1).
All bits that are set, with the exception of the POR bit
(RCON<0>), are cleared during a POR event. The user
application can set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software
does not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Reset”
(DS70192) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Refer to the specific peripheral section or
Section 3.0 “CPU” of this data sheet for
register Reset states.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
MCLR
VDD
BOR
Sleep or Idle
RESET Instruction
WDT
Module
Glitch Filter
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
VDD Rise
Detect
POR
Configuration Mismatch
Internal
Regulator
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 88 2011-2012 Microchip Technology Inc.
6.1 Reset Control Register
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR — — — —CMVREGS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
EXTR SWR SWDTEN(2)WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An Illegal Opcode or Uninitialized W Reset has not occurred
bit 13-10 Unimplemented: Read as ‘0’
bit 9 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Stand-by During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Stand-by mode during Sleep
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
2011-2012 Microchip Technology Inc. DS70652E-page 89
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 90 2011-2012 Microchip Technology Inc.
6.2 System Reset
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
A Cold Reset is the result of a POR or a BOR. On a
Cold Reset, the FNOSC Configuration bits in the FOSC
Configuration register selects the device clock source.
A Warm Reset is the result of all other Reset sources,
including the RESET instruction. On Warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selec-
tion (COSC<2:0>) bits in the Oscillator Control
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is shown in Figure 6-2.
TABLE 6-1: OSCILLATOR DELAY
Oscillator Mode Oscillator
Start-up Delay
Oscillator Start-up
Timer PLL Lock Time Total Delay
FRC, FRCDIV16,
FRCDIVN
TOSCD(1)—— TOSCD
FRCPLL TOSCD(1)—TLOCK(3)TOSCD(1) + TLOCK(3)
MS TOSCD(1)TOST(2)—TOSCD(1) + TOST(2)
HS TOSCD(1)TOST(2)—TOSCD(1) + TOST(2)
EC — — — —
MSPLL TOSCD(1)TOST(2)TLOCK(3)TOSCD(1) + TOST(2) + TLOCK(3)
ECPLL — — TLOCK(3)TLOCK(3)
SOSC TOSCD(1)TOST(2)—TOSCD(1) + TOST(2)
LPRC TOSCD(1)—— TOSCD(1)
Note 1: TOSCD = Oscillator Start-up Delay (1.1 s max. for FRC, 70 s max. for LPRC). Crystal oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 s for a
10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
3: TLOCK = PLL Lock time (1.5 ms nominal) if PLL is enabled.
2011-2012 Microchip Technology Inc. DS70652E-page 91
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 6-2: SYSTEM RESET TIMING
Reset Run
Device Status
VDD
VPOR
VBOR
POR
BOR
SYSRST
TPWRT
TPOR
TBOR
Oscillator Clock
TOSCD TOST TLOCK
Time
FSCM
TFSCM
1
2
3
4
5
6
1. POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the
VPOR threshold and the delay, TPOR, has elapsed.
2. BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the
delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable.
3. PWRT Timer: The Power-up Timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The
delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay,
TPWRT, has elapsed, the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles.
4. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to
Section 8.0 “Oscillator Configuration” for more information.
5. When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO
instruction at the Reset address, which redirects program execution to the appropriate start-up routine.
6. The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay,
TFSCM, has elapsed.
TABLE 6-2: OSCILLATOR PARAMETERS
Symbol Parameter Value
VPOR POR Threshold 1.8V nominal
TPOR POR Extension Time 30 s maximum
VBOR BOR Threshold 2.5V nominal
TBOR BOR Extension Time 100 s maximum
TPWRT Power-up Time
Delay
64 ms nominal
TFSCM Fail-Safe Clock
Monitor Delay
900 s maximum
Note: When the device exits the Reset condition
(begins normal operation), the device
operating parameters (voltage, frequency,
temperature, etc.) must be within their
operating ranges; otherwise, the device
may not function correctly. The user appli-
cation must ensure that the delay between
the time power is first applied, and the time
SYSRST becomes inactive, is long
enough to get all operating parameters
within specification.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 92 2011-2012 Microchip Technology Inc.
6.3 POR
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until VDD crosses the
VPOR threshold and the delay, TPOR, has elapsed. The
delay, TPOR, ensures that the internal device bias
circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR. Refer to Section 26.0
“Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
6.4 BOR and PWRT
The on-chip regulator has a BOR circuit that resets the
device when the VDD is too low (VDD < VBOR) for proper
device operation. The BOR circuit keeps the device in
Reset until VDD crosses the VBOR threshold and the
delay, TBOR, has elapsed. The delay, TBOR, ensures
the voltage regulator output becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The Power-up Timer (PWRT) provides
power-up time delay (TPWRT) to ensure that the system
power supplies have stabilized at the appropriate levels
for full-speed operation before the SYSRST is
released.
Refer to Section 23.0 “Special Features” for further
details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3: BROWN-OUT RESET SITUATIONS
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
T
BOR
+ T
PWRT
VDD Dips Before PWRT Expires
T
BOR
+ T
PWRT
T
BOR
+ T
PWRT
2011-2012 Microchip Technology Inc. DS70652E-page 93
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
6.5 External Reset (EXTR)
The External Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 26.0 “Electrical Characteristics” for
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.5.1 EXTERNAL SUPERVISORY
CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This External Reset signal can be directly con-
nected to the MCLR pin to reset the device when the
rest of the system is reset.
6.5.2 INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
reset the device, the External Reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
External Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.6 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the device
will assert SYSRST, placing the device in a special
Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain as the source. SYSRST is
released at the next instruction cycle and the Reset
vector fetch will commence.
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate the
Software Reset.
6.7 Watchdog Timer Time-out Reset
(WDTO)
Whenever a Watchdog Timer Time-out Reset occurs,
the device will asynchronously assert SYSRST. The
clock source will remain unchanged. A WDT time-out
during Sleep or Idle mode will wake-up the processor,
but will not reset the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate the
Watchdog Reset. Refer to Section 23.4 “Watchdog
Timer (WDT)” for more information on Watchdog
Reset.
6.8 Trap Conflict Reset
If a lower priority hard trap occurs while a higher priority
trap is being processed, a hard Trap Conflict Reset
occurs. The hard traps include exceptions of Priority
Level 13 through Level 15, inclusive. The address error
(Level 13) and oscillator error (Level 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on Trap Conflict Resets.
6.9 Configuration Mismatch Reset
To maintain the integrity of the Peripheral Pin Select
Control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occurs (such as cell
disturbances caused by ESD or other external events),
a Configuration Mismatch Reset occurs.
The Configuration Mismatch Flag (CM) bit in the Reset
Control (RCON<9>) register is set to indicate the
Configuration Mismatch Reset. Refer to Section 10.0
“I/O Ports” for more information on the Configuration
Mismatch Reset.
6.10 Illegal Condition Device Reset
An Illegal Condition Device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to indicate the Illegal Condition Device
Reset.
6.10.1 ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The Illegal Opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the Illegal Opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 0x3F,
which is an illegal opcode value.
Note: The Configuration Mismatch feature and
associated Reset flag is not available on
all devices.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 94 2011-2012 Microchip Technology Inc.
6.10.2 UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
Address Pointer will reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.10.3 SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a Security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine or other form of branch
instruction.
The VFC occurs when the Program Counter is
reloaded with an interrupt or trap vector.
6.11 Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Table 6-3 provides a summary of Reset flag bit
operation.
TABLE 6-3: RESET FLAG BIT OPERATION
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Flag Bit Set by: Cleared by:
TRAPR (RCON<15>) Trap conflict event POR, BOR
IOPWR (RCON<14>) Illegal opcode or uninitialized
W register access or Security Reset
POR, BOR
CM (RCON<9>) Configuration Mismatch POR, BOR
EXTR (RCON<7>) MCLR Reset POR
SWR (RCON<6>) RESET instruction POR, BOR
WDTO (RCON<4>) WDT Time-out PWRSAV instruction,
CLRWDT instruction, POR, BOR
SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR
IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR —
Note: All Reset flag bits can be set or cleared by user software.
2011-2012 Microchip Technology Inc. DS70652E-page 95
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
7.0 INTERRUPT CONTROLLER
The interrupt controller reduces the numerous periph-
eral interrupt request signals to a single interrupt
request signal to the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104 CPU. It has
the following features:
• Up to eight processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1 Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location,
000004h. The IVT contains 126 vectors consisting of
eight non-maskable trap vectors, plus up to 118 sources
of interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit-wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 will take priority over interrupts at any
other vector address.
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices implement up to 26 unique
interrupts and 4 nonmaskable traps. These are
summarized in Tab le 7 -1 and Table 7-2.
7.1.1 ALTERNATE INTERRUPT VECTOR
TA B L E
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a way to
switch between an application and a support environ-
ment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
between applications to facilitate evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2 Reset Sequence
A device Reset is not a true exception because the inter-
rupt controller is not involved in the Reset process. The
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices clear their registers in
response to a Reset, forcing the PC to zero. The Digital
Signal Controller then begins program execution at
location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 41. “Interrupts
(Part IV)” (DS70300) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 96 2011-2012 Microchip Technology Inc.
FIGURE 7-1: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
INTERRUPT VECTOR TABLE
Reset – GOTO Instruction 0x000000
Reset – GOTO Address 0x000002
Reserved 0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 0x000014
Interrupt Vector 1
~
~
~
Interrupt Vector 52 0x00007C
Interrupt Vector 53 0x00007E
Interrupt Vector 54 0x000080
~
~
~
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
Reserved 0x000100
Reserved 0x000102
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 0x000114
Interrupt Vector 1
~
~
~
Interrupt Vector 52 0x00017C
Interrupt Vector 53 0x00017E
Interrupt Vector 54 0x000180
~
~
~
Interrupt Vector 116
Interrupt Vector 117 0x0001FE
Start of Code 0x000200
Decreasing Natural Order Priority
Interrupt Vector Table (IVT)(1)
Alternate Interrupt Vector Table (AIVT)(1)
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
2011-2012 Microchip Technology Inc. DS70652E-page 97
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 7-1: INTERRUPT VECTORS
Vector
Number
Interrupt
Request (IRQ)
Number
IVT Address AIVT Address Interrupt Source
8 0 0x000014 0x000114 INT0 – External Interrupt 0
9 1 0x000016 0x000116 IC1 – Input Capture 1
10 2 0x000018 0x000118 OC1 – Output Compare 1
11 3 0x00001A 0x00011A T1 – Timer1
12 40x00001C 0x00011C Reserved
13 5 0x00001E 0x00011E IC2 – Input Capture 2
14 6 0x000020 0x000120 OC2 – Output Compare 2
15 7 0x000022 0x000122 T2 – Timer2
16 8 0x000024 0x000124 T3 – Timer3
17 9 0x000026 0x000126 SPI1E – SPI1 Error
18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done
19 11 0x00002A 0x00012A U1RX – UART1 Receiver
20 12 0x00002C 0x00012C U1TX – UART1 Transmitter
21 13 0x00002E 0x00012E ADC1 – ADC1
22-23 14-15 0x000030-0x000032 0x000130-0x000132 Reserved
24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events
25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events
26 18 0x000038 0x000138 CMP – Comparator Interrupt
27 19 0x00003A 0x00013A Change Notification Interrupt
28 20 0x00003C 0x00013C INT1 – External Interrupt 1
29-34 21-26 0x00003E-0x000038 0x00013E-0x000138 Reserved
35 27 0x00004A 0x00014A T4 – Timer4(2)
36 28 0x00004C 0x00014C T5 – Timer4(2)
37 29 0x00004E 0x00014E INT2 – External Interrupt 2
38-44 30-36 0x000050-0x00005C 0x000150-0x00015C Reserved
45 37 0x00005E 0x00015E IC3 – Input Capture 3
46-64 38-56 0x000060-0x000084 0x000160-0x000184 Reserved
65 57 0x000086 0x000186 PWM1 – PWM1 Period Match(1)
66-69 58-61 0x000088-0x00008E 0x000188-0x00018E Reserved
70 62 0x000090 0x000190 RTCC – Real-Time Clock and Calendar
71 63 0x000092 0x000192 FLTA1 – PWM1 Fault A(1)
72 64 0x000094 0x000194 FLTB1 – PWM1 Fault B(3)
73 65 0x000096 0x000196 U1E – UART1 Error
74-84 66-76 0x000098-0x0000AC 0x000198-0x0001AC Reserved
85 77 0x0000AE 0x0001AE CTMU – Charge Time Measurement Unit
86-125 78-117 0x0000B0-0x0000FE 0x0001B0-0x0001FE Reserved
Note 1: This interrupt vector is available in dsPIC33FJ(16/32)MC10X devices only.
2: This interrupt vector is available in dsPIC33FJ32(GP/MC)10X devices only.
3: This interrupt vector is available in dsPIC33FJ(16/32)MC102/104 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 98 2011-2012 Microchip Technology Inc.
TABLE 7-2: TRAP VECTORS
7.3 Interrupt Control and Status
Registers
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices implement
a total of 22 registers for the interrupt controller:
• INTCON1
• INTCON2
•IFSx
•IECx
•IPCx
•INTTREG
7.3.1 INTCON1 AND INTCON2
Global interrupt functions are controlled from INTCON1
and INTCON2. INTCON1 contains the Interrupt Nest-
ing Disable (NSTDIS) bit as well as the control and
status flags for the processor trap sources. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2 IFSx Registers
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3 IECx Registers
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.3.4 IPCx Registers
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
7.3.5 INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into Vector Number
(VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Tab l e 7- 1. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IPx
bits in the first positions of IPC0 (IPC0<2:0>).
7.3.6 STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user
application can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU Interrupt Priority Level. IPL3 is a
read-only bit so that trap events cannot be
masked by the user software.
All Interrupt registers are described in Register 7-1
through Register 7-28 in the following pages.
Vector Number IVT Address AIVT Address Trap Source
0 0x000004 0x000104 Reserved
1 0x000006 0x000106 Oscillator Failure
2 0x000008 0x000108 Address Error
3 0x00000A 0x00010A Stack Error
4 0x00000C 0x00010C Math Error
5 0x00000E 0x00010E Reserved
6 0x000010 0x000110 Reserved
7 0x000012 0x000112 Reserved
2011-2012 Microchip Technology Inc. DS70652E-page 99
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-1: SR: CPU STATUS REGISTER(1)
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0(3)R/W-0(3)R/W-0(3)R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2(2)IPL1(2)IPL0(2)RA N OV Z C
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — —USEDT DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3(2)PSV RND IF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 100 2011-2012 Microchip Technology Inc.
REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap is disabled
bit 7 SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6 DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 5 Unimplemented: Read as ‘0’
bit 4 MATHERR: Arithmetic Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
2011-2012 Microchip Technology Inc. DS70652E-page 101
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’
REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 102 2011-2012 Microchip Technology Inc.
REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
ALTIVT DISI — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Uses Alternate Interrupt Vector Table
0 = Uses standard Interrupt Vector Table (default)
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3 Unimplemented: Read as ‘0’
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
2011-2012 Microchip Technology Inc. DS70652E-page 103
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 Unimplemented: Read as ‘0’
bit 3 T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 104 2011-2012 Microchip Technology Inc.
bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
2011-2012 Microchip Technology Inc. DS70652E-page 105
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
——INT2IFT5IF
(1)T4IF(1)— — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT1IF CNIF CMIF MI2C1IF SI2C1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 T5IF: Timer5 Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 T4IF: Timer4 Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10-5 Unimplemented: Read as ‘0’
bit 4 INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 CMIF: Comparator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note 1: This bit is available in dsPIC33FJ32(GP/MC)10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 106 2011-2012 Microchip Technology Inc.
REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——IC3IF— — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0
FLTA1IF(1)RTCIF — — — —PWM1IF
(1)—
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 RTCIF: RTCC Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-10 Unimplemented: Read as ‘0’
bit 9 PWM1IF: PWM1 Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-0 Unimplemented: Read as ‘0’
Note 1: This bit is available in dsPIC(16/32)MC10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 107
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——CTMUIF— — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — U1EIF FLTB1IF(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CTMUIF: CTMU Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-2 Unimplemented: Read as ‘0’
bit 1 U1EIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 FLTB1IF: PWM1 Fault B Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note 1: This bit is available in dsPIC(16/32)MC102/104 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 108 2011-2012 Microchip Technology Inc.
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10 SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8 T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7 T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4 Unimplemented: Read as ‘0’
bit 3 T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
2011-2012 Microchip Technology Inc. DS70652E-page 109
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
——INT2IET5IE
(1)T4IE(1)— — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — INT1IE CNIE CMIE MI2C1IE SI2C1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12 T5IE: Timer5 Interrupt Enable bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 T4IE: Timer4 Interrupt Enable bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10-5 Unimplemented: Read as ‘0’
bit 4 INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3 CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 CMIE: Comparator Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1: This bit is available in dsPIC33FJ32(GP/MC)10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 110 2011-2012 Microchip Technology Inc.
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——IC3IE— — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0
FLTA1IE(1)RTCIE — — — —PWM1IE
(1)—
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 RTCIE: RTCC Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-10 Unimplemented: Read as ‘0’
bit 9 PWM1IE: PWM1 Interrupt Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8-0 Unimplemented: Read as ‘0’
Note 1: This bit is available in dsPIC(16/32)MC10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 111
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——CTMUIE— — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — U1EIE FLTB1IE(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CTMUIE: CTMU Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-2 Unimplemented: Read as ‘0’
bit 1 U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note 1: This bit is available in dsPIC(16/32)MC102/104 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 112 2011-2012 Microchip Technology Inc.
REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— T1IP<2:0> —OC1IP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
—IC1IP<2:0>— INT0IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2011-2012 Microchip Technology Inc. DS70652E-page 113
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— T2IP<2:0> —OC2IP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
—IC2IP<2:0>— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 114 2011-2012 Microchip Technology Inc.
REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— U1RXIP<2:0> — SPI1IP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— SPI1EIP<2:0> — T3IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2011-2012 Microchip Technology Inc. DS70652E-page 115
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
—AD1IP<2:0>— U1TXIP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 116 2011-2012 Microchip Technology Inc.
REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CNIP<2:0> — CMIP<2:0>
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— MI2C1IP<2:0> — SI2C1IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2011-2012 Microchip Technology Inc. DS70652E-page 117
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — INT1IP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— T4IP<2:0>(1)— — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11-0 Unimplemented: Read as ‘0’
Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 118 2011-2012 Microchip Technology Inc.
REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— INT2IP<2:0> — T5IP<2:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 119
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-23: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
—IC3IP<2:0>— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 IC3IP<2:0>: External Interrupt 3 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 7-24: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— PWM1IP<2:0>(1)— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
Note 1: These bits are available in dsPIC(16/32)MC10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 120 2011-2012 Microchip Technology Inc.
REGISTER 7-25: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
—FLTA1IP<2:0>
(1)— RTCIP<2:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 RTCIP<2:0>: RTCC Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0 Unimplemented: Read as ‘0’
Note 1: These bits are available in dsPIC(16/32)MC10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 121
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-26: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
—U1EIP<2:0>—FLTB1IP<2:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 FLTB1IP<2:0>: PWM1 Fault B Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
Note 1: These bits are available in dsPIC(16/32)MC102/104 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 122 2011-2012 Microchip Technology Inc.
REGISTER 7-27: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— CTMUIP<2:0> — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
2011-2012 Microchip Technology Inc. DS70652E-page 123
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-28: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — —ILR<3:0>
bit 15 bit 8
U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
— VECNUM<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111 = Interrupt Vector pending is Number 135
•
•
•
0000001 = Interrupt Vector pending is Number 9
0000000 = Interrupt Vector pending is Number 8
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 124 2011-2012 Microchip Technology Inc.
7.4 Interrupt Setup Procedures
7.4.1 INITIALIZATION
To configure an interrupt source at initialization:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
2. Select the user-assigned priority level for the
interrupt source by writing the control bits into
the appropriate IPCx register. The priority level
will depend on the specific application and type
of interrupt source. If multiple priority levels are
not desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
4. Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2 INTERRUPT SERVICE ROUTINE
The method used to declare an ISR and initialize the
IVT with the correct vector address depends on the
programming language (C or assembler) and the
language development toolsuite used to develop the
application.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, program will
re-enter the ISR immediately after exiting the routine. If
the ISR is coded in assembly language, it must be
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
7.4.3 TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4 INTERRUPT DISABLE
All user interrupts can be disabled using this
procedure:
1. Push the current SR value onto the software
stack using the PUSH instruction.
2. Force the CPU to Priority Level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction can be
used to restore the previous SR value.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period of time. Level 7 interrupt sources are not
disabled by the DISI instruction.
Note: At a device Reset, the IPCx registers
are initialized such that all user
interrupt sources are assigned to
Priority Level 4.
Note: Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(Level 8-Level 15) cannot be disabled.
2011-2012 Microchip Technology Inc. DS70652E-page 125
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
8.0 OSCILLATOR
CONFIGURATION
The oscillator system for dsPIC33FJ16(GP/MC)101/
102 and dsPIC33FJ32(GP/MC)101/102/104 devices
provides:
• External and internal oscillator options as clock
sources
• An on-chip, 4x Phase Lock Loop (PLL) to scale the
internal operating frequency to the required system
clock frequency
• An internal FRC oscillator that can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and takes fail-safe measures
• A Clock Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1: OSCILLATOR SYSTEM DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 52. “Oscillator
(Part VI)” (DS70644) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note 1: If the oscillator is used with MS or HS modes, an extended parallel resistor with the value of 1 M must be connected.
2: The term, FP, refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this docu-
ment, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is
used with a Doze ratio of 1:2 or lower.
Secondary Oscillator (SOSC)
LPOSCEN
SOSCO
SOSCI
Timer 1
MSPLL, ECPLL,
MS, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FSCM
FRCDIVN
SOSC
FRCDIV16
FRCPLL
NOSC<2:0> FNOSC<2:0>
Reset
FRC
Oscillator
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
S4
÷ 16
Clock Switch
S7
Clock Fail
÷ 2
TUN<5:0>
4x PLL
FCY(2)
FRCDIV
DOZE
OSC2
OSC1 Primary Oscillator (POSC)
R(1)
POSCMD<1:0>
FP(2)
FOSC
(To Peripherals)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 126 2011-2012 Microchip Technology Inc.
8.1 CPU Clocking System
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices provide
seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with 4x PLL
• Primary (MS, HS or EC) Oscillator
• Primary Oscillator with 4x PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
8.1.1 SYSTEM CLOCK SOURCES
8.1.1.1 Fast RC
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The FRC frequency depends on the FRC accuracy
(see Table 26-18) and the value of the FRC Oscillator
Tuning register (see Register 8-3).
8.1.1.2 Primary
The primary oscillator can use one of the following as
its clock source:
• MS (Crystal): Crystals and ceramic resonators in
the range of 4 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 32 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
• EC (External Clock): The external clock signal is
directly applied to the OSC1 pin.
8.1.1.3 Secondary
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
8.1.1.4 Low-Power RC
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
8.1.1.5 PLL
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip, 4x
Phase Lock Loop (PLL) to provide faster output
frequencies for device operation. PLL configuration is
described in Section 8.1.3 “PLL Configuration”.
8.1.2 SYSTEM CLOCK SELECTION
The oscillator source used at a device Power-on
Reset event is selected using Configuration bit
settings. The Oscillator Configuration bit settings are
located in the Configuration registers in the program
memory. (Refer to Section 23.1 “Configuration
Bits” for further details.) The initial Oscillator
Selection Configuration bits, FNOSC<2:0>
(FOSCSEL<2:0>), and the Primary Oscillator Mode
Select Configuration bits, POSCMD<1:0>
(FOSC<1:0>), select the oscillator source that is used
at a Power-on Reset. The FRC primary oscillator is
the default (unprogrammed) selection.
The Configuration bits allow users to choose among
12 different clock modes, shown in Table 8-1.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) FOSC is divided by 2 to
generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device, and speeds up to
16 MHz are supported by the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
architecture.
Instruction execution speed or device operating
frequency, FCY, is given by:
EQUATION 8-1: DEVICE OPERATING
FREQUENCY
FCY FOSC
2
-------------=
2011-2012 Microchip Technology Inc. DS70652E-page 127
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
8.1.3 PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip, 4x PLL to obtain higher
speeds of operation.
For example, suppose an 8 MHz crystal is being used
with the selected oscillator mode of MS with PLL. This
provides a FOSC of 8 MHz * 4 = 32 MHz. The resultant
device operating speed is 32/2 = 16 MIPS.
EQUATION 8-2: MS WITH PLL MODE
EXAMPLE
TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
FCY FOSC
2
------------- 1
2
---8000000 416 MIPS== =
Oscillator Mode Oscillator
Source POSCMD<1:0> FNOSC<2:0> See
Note
Fast RC Oscillator with Divide-by-n (FRCDIVN) Internal xx 111 1, 2
Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal xx 101 1
Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1
Primary Oscillator (MS) with PLL (MSPLL) Primary 01 011 —
Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1
Primary Oscillator (HS) Primary 10 010 —
Primary Oscillator (MS) Primary 01 010 —
Primary Oscillator (EC) Primary 00 010 1
Fast RC Oscillator (FRC) with Divide-by-n and
PLL (FRCPLL)
Internal xx 001 1
Fast RC Oscillator (FRC) Internal xx 000 1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 128 2011-2012 Microchip Technology Inc.
8.2 Oscillator Control Registers
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
— COSC<2:0> — NOSC<2:0>(2)
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0
CLKLOCK IOLOCK LOCK —CF — LPOSCEN OSWEN
bit 7 bit 0
Legend: C = Clearable bit y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (MS, EC) with PLL
010 = Primary Oscillator (MS, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (MS, EC) with PLL
010 = Primary Oscillator (MS, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7 CLKLOCK: Clock Lock Enable bit
If Clock Switching is Enabled and FSCM is Disabled (FCKSM<1:0> (FOSC<7:6>) = 0b01):
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
bit 6 IOLOCK: Peripheral Pin Select Lock bit
1 = Peripherial Pin Select is locked, write to Peripheral Pin Select registers is not allowed
0 = Peripherial Pin Select is not locked, write to Peripheral Pin Select registers is allowed
bit 5 LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4 Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
2011-2012 Microchip Technology Inc. DS70652E-page 129
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 3 CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
bit 2 Unimplemented: Read as ‘0’
bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit
1 = Enables secondary oscillator
0 = Disables secondary oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
Note 1: Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 130 2011-2012 Microchip Technology Inc.
REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
ROI DOZE<2:0>(2,3)DOZEN(1,2,3)FRCDIV<2:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(2,3)
111 = FCY/128
110 = FCY/64
101 = FCY/32
100 = FCY/16
011 = FCY/8 (default)
010 = FCY/4
001 = FCY/2
000 = FCY/1
bit 11 DOZEN: DOZE Mode Enable bit(1,2,3)
1 = DOZE<2:0> bits field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio is forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide-by-256
110 = FRC divide-by-64
101 = FRC divide-by-32
100 = FRC divide-by-16
011 = FRC divide-by-8
010 = FRC divide-by-4
001 = FRC divide-by-2
000 = FRC divide-by-1 (default)
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: If DOZEN = 1, writes to DOZE<2:0> are ignored.
3: If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored.
2011-2012 Microchip Technology Inc. DS70652E-page 131
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN<5:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)
011111 = Center frequency +11.625% (8.23 MHz)
011110 = Center frequency +11.25% (8.20 MHz)
•
•
•
000001 = Center frequency +0.375% (7.40 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency -0.375% (7.345 MHz)
•
•
•
100001 = Center frequency -11.625% (6.52 MHz)
100000 = Center frequency -12% (6.49 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 132 2011-2012 Microchip Technology Inc.
8.3 Clock Switching Operation
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104 devices have
a safeguard lock built into the switch process.
8.3.1 ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit
in the FOSC Configuration register must be programmed
to ‘0’. (Refer to Section 23.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is unpro-
grammed (‘1’), the clock switching function and Fail-Safe
Clock Monitor function are disabled. This is the default
setting.
The NOSCx control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is dis-
abled. However, the COSCx bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSCx
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
8.3.2 OSCILLATOR SWITCHING SEQUENCE
Performing a clock switch requires this basic
sequence:
1. If desired, read the COSC bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSCx con-
trol bits (OSCCON<10:8>) for the new oscillator
source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit (OSCCON<0>) to initiate
the oscillator switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSCx status bits with the new value of the
NOSCx control bits. If they are the same, the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2. If a valid clock switch has been initiated, the LOCK
and CF (OSCCON<5,3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSCx bit values are transferred to the COSCx
status bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM is
enabled) or LP (if LPOSCEN remains set).
8.4 Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then, the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a Warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Note: Primary Oscillator mode has three different
submodes (MS, HS, and EC), which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any Pri-
mary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to Section 52. “Oscillator (Part
VI)” (DS70644) in the “dsPIC33F/PIC24H
Family Reference Manual” for details.
2011-2012 Microchip Technology Inc. DS70652E-page 133
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
9.0 POWER-SAVING FEATURES
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. Devices can manage power
consumption in four different ways:
• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software-Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
9.1 Clock Frequency and Clock
Switching
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices allow a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by
simply changing the NOSCx bits (OSCCON<10:8>).
The process of changing a system clock during
operation, as well as limitations to the process, are
discussed in more detail in Section 8.0 “Oscillator
Configuration”.
9.2 Instruction-Based Power-Saving
Modes
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices have two special power-
saving modes that are entered through the execution of
a special PWRSAV instruction. Sleep mode stops clock
operation and halts all code execution. Idle mode halts
the CPU and code execution, but allows peripheral
modules to continue operation. The assembler syntax
of the PWRSAV instruction is shown in Example 9-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
9.2.1 SLEEP MODE
The following occur in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode
• Some device features or peripherals may continue
to operate. This includes items such as the Input
Change Notification (ICN) on the I/O ports, or
peripherals that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled
The device will wake-up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog
Timer and Power-Saving Modes”
(DS70196) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode
PWRSAV #IDLE_MODE ; Put the device into IDLE mode
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 134 2011-2012 Microchip Technology Inc.
9.2.2 IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Peripheral Module Disable”).
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAV instruction, or the first instruction in the ISR.
9.2.3 INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
9.3 Doze Mode
The preferred strategies for reducing power
consumption are changing clock speed and invoking
one of the power-saving modes. In some
circumstances, this may not be practical. For example,
it may be necessary for an application to maintain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving mode can stop communications
completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the UART module has been configured
for 500 kbps based on this device operating speed. If
the device is placed in Doze mode with a clock
frequency ratio of 1:4, the UART module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
9.4 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC® DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note: If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable
module operation).
2011-2012 Microchip Technology Inc. DS70652E-page 135
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
9.5 PMD Control Registers
REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
T5MD(1)T4MD(1)T3MD T2MD T1MD —PWM1MD—
bit 15 bit 8
R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0
I2C1MD —U1MD—SPI1MD——AD1MD
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 T5MD: Timer5 Module Disable bit(1)
1 = Timer5 module is disabled
0 = Timer5 module is enabled
bit 14 T4MD: Timer4 Module Disable bit(1)
1 = Timer4 module is disabled
0 = Timer4 module is enabled
bit 13 T3MD: Timer3 Module Disable bit
1 = Timer3 module is disabled
0 = Timer3 module is enabled
bit 12 T2MD: Timer2 Module Disable bit
1 = Timer2 module is disabled
0 = Timer2 module is enabled
bit 11 T1MD: Timer1 Module Disable bit
1 = Timer1 module is disabled
0 = Timer1 module is enabled
bit 10 Unimplemented: Read as ‘0’
bit 9 PWM1MD: PWM1 Module Disable bit
1 = PWM1 module is disabled
0 = PWM1 module is enabled
bit 18 Unimplemented: Read as ‘0’
bit 7 I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6 Unimplemented: Read as ‘0’
bit 5 U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4 Unimplemented: Read as ‘0’
Note 1: This bit is available in dsPIC33FJ32(GP/MC)10X devices only.
2: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port
pins that have been multiplexed with ANx will be in Digital mode.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 136 2011-2012 Microchip Technology Inc.
REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
bit 3 SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
bit 2-1 Unimplemented: Read as ‘0’
bit 0 AD1MD: ADC1 Module Disable bit(2)
1 = ADC1 module is disabled
0 = ADC1 module is enabled
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
————— IC3MD IC2MD IC1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
——————OC2MDOC1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 IC3MD: Input Capture 3 Module Disable bit
1 = Input Capture 3 module is disabled
0 = Input Capture 3 module is enabled
bit 9 IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled
0 = Input Capture 2 module is enabled
bit 8 IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
bit 7-2 Unimplemented: Read as ‘0’
bit 1 OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
bit 0 OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
Note 1: This bit is available in dsPIC33FJ32(GP/MC)10X devices only.
2: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port
pins that have been multiplexed with ANx will be in Digital mode.
2011-2012 Microchip Technology Inc. DS70652E-page 137
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
REGISTER 9-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0
————— CMPMD RTCCMD —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled
bit 9 RTCCMD: RTCC Module Disable bit
1 = RTCC module is disabled
0 = RTCC module is enabled
bit 8-0 Unimplemented: Read as ‘0’
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
—————CTMUMD— —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2 CTMUMD: CTMU Module Disable bit
1 = CTMU module is disabled
0 = CTMU module is enabled
bit 1-0 Unimplemented: Read as ‘0’
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 138 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 139
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
10.0 I/O PORTS
All of the device pins (except VDD, VSS, MCLR, and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
10.1 Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 10-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, the pin is
an input. All port pins are defined as inputs after a
Reset. Reads from the Output Latch (LATx) register
read the latch. Writes to the Output Latch register write
the latch. Reads from the port (PORTx) read the port
pins, while writes to the port pins write the latch.
Any bit and its associated data and control registers
that is not valid for a particular device will be disabled.
This means the corresponding LATx and TRISx
registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 10. “I/O Ports”
(DS70193) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 140 2011-2012 Microchip Technology Inc.
FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
QD
CK
WR LAT +
TRIS Latch
I/O Pin
WR PORT
Data Bus
QD
CK
Data Latch
Read PORT
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data
Output Enable
Peripheral Input Data
I/O
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LAT
2011-2012 Microchip Technology Inc. DS70652E-page 141
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
10.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired 5V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See “Pin Diagrams” for the available pins and their
functionality.
10.2 Configuring Analog Port Pins
The AD1PCFGL and TRIS registers control the opera-
tion of the Analog-to-Digital port pins. The port pins that
are to function as analog inputs must have their corre-
sponding TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP. An demonstration is shown in
Example 10-1.
10.3 Input Change Notification (ICN)
The Input Change Notification function of the I/O
ports allows the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices to gener-
ate interrupt requests to the processor in response to a
Change-of-State (COS) on selected input pins. This
feature can detect input Change-of-States even in
Sleep mode when the clocks are disabled. Depending
on the device pin count, up to 21 external signals (CNx
pin) can be selected (enabled) for generating an
interrupt request on a Change-of-State.
Four control registers are associated with the CN mod-
ule. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
EXAMPLE 10-1: PORT WRITE/READ EXAMPLE
Note: Pull-ups on Input Change Notification pins
should always be disabled when the port
pin is configured as a digital output.
MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs
MOV W0, TRISBB ; and PORTB<7:0> as outputs
NOP ; Delay 1 cycle
btss PORTB, #13 ; Next Instruction
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 142 2011-2012 Microchip Technology Inc.
10.4 Peripheral Pin Select (PPS)
Peripheral Pin Select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The Peripheral Pin Select configuration feature oper-
ates over a fixed subset of digital I/O pins. Program-
mers can independently map the input and/or output
of most digital peripherals to any one of these I/O
pins. Peripheral Pin Select is performed in software,
and generally does not require the device to be
reprogrammed. Hardware safeguards are included
that prevent accidental or spurious changes to the
peripheral mapping, once it has been established.
10.4.1 AVAILABLE PINS
The Peripheral Pin Select feature is used with a range
of up to 16 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the Peripheral Pin Select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
10.4.2 CONTROLLING PERIPHERAL PIN
SELECT
Peripheral Pin Select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
10.4.2.1 Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. A control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 10-1
through Register 10-10). Each register contains sets
of 5-bit fields, with each set associated with one of the
remappable peripherals. Programming a given
peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral.
For any given device, the valid range of values for any
bit field corresponds to the maximum number of
Peripheral Pin Selections supported by the device.
Figure 10-2 Illustrates remappable pin selection for
U1RX input.
FIGURE 10-2: REMAPPABLE MUX
INPUT FOR U1RX
Note: For input mapping only, the Peripheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. There-
fore, when configuring the RPx pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to ‘1’).
RP0
RP1
RP2
RP
25
0
25
1
2
U1RX Input
U1RXR<4:0>
to Peripheral
2011-2012 Microchip Technology Inc. DS70652E-page 143
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
10.4.2.2 Output Mapping
In contrast to the inputs, the outputs of the Peripheral
Pin Select options are mapped on the basis of the pin.
In this case, a control register associated with a
particular pin dictates the peripheral output to be
mapped. The RPORx registers are used to control out-
put mapping. Like the RPINRx registers, each register
contains sets of 5-bit fields, with each set associated
with one RPn pin (see Register 10-11 through
Register 10-18). The value of the bit field corresponds
to one of the peripherals, and that peripheral’s output is
mapped to the pin (see Table 10-2 and Figure 10-3).
The list of peripherals for output mapping also includes
a null value of ‘00000’ because of the mapping
technique. This permits any given pin to remain
unconnected from the output of any of the pin
selectable peripherals.
FIGURE 10-3: MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
Input Name Function Name Register Configuration
Bits
External Interrupt 1 INT1 RPINR0 INT1R<4:0>
External Interrupt 2 INT2 RPINR1 INT2R<4:0>
Timer2 External Clock T2CK RPINR3 T2CKR<4:0>
Timer3 External Clock T3CK RPINR3 T3CKR<4:0>
Timer4 External Clock T4CK RPINR4 T4CKR<4:0>(2)
Timer5 External Clock T5CK RPINR4 T5CKR<4:0>(2)
Input Capture 1 IC1 RPINR7 IC1R<4:0>
Input Capture 2 IC2 RPINR7 IC2R<4:0>
Input Capture 3 IC3 RPINR8 IC3R<4:0>
Output Compare Fault A OCFA RPINR11 OCFAR<4:0>
UART1 Receive U1RX RPINR18 U1RXR<4:0>
UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<4:0>
SDI1 SPI Data Input 1 SDI1 RPINR20 SDI1R<4:0>(2)
SCK1 SPI Clock Input 1 SCK1 RPINR20 SCK1R<4:0>(2)
SPI1 Slave Select Input SS1 RPINR21 SS1R<4:0>(2)
Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers.
2: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
0
3
RPnR<4:0>
Default
U1TX Output Enable
U1RTS Output Enable 4
19
OC2 Output Enable
0
3
Default
U1TX Output
U1RTS Output 4
19
OC2 Output
Output Enable
Output Data
RPn
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 144 2011-2012 Microchip Technology Inc.
TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
10.4.3 CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices include
three features to prevent alterations to the peripheral
map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.4.3.1 Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these regis-
ters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
10.4.3.2 Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
10.4.3.3 Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<5>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute, and the Peripheral Pin Select Control
registers cannot be written to. The only way to clear the
bit and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
Peripheral Pin Select registers.
Function RPnR<4:0> Output Name
NULL 00000 RPn tied to Default Port Pin
C1OUT 00001 RPn tied to Comparator 1 Output
C2OUT 00010 RPn tied to Comparator 2 Output
U1TX 00011 RPn tied to UART1 Transmit
U1RTS 00100 RPn tied to UART1 Ready-to-Send
SCK1 01000 RPn tied to SPI Clock(1)
SDO1 00111 RPn tied to SPI Data Output(1)
SS1 01001 RPn tied to SPI1 Slave Select Output(1)
OC1 10010 RPn tied to Output Compare 1
OC2 10011 RPn tied to Output Compare 2
CTPLS 11101 RPn tied to CTMU Pulse Output
C3OUT 11110 RPn tied to Comparator 3 Output
Note 1: This function is available in dsPIC33FJ32(GP/MC)10X devices only.
Note: MPLAB® C30 provides built-in C language
functions for unlocking the OSCCON
register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB IDE Help for more
information.
2011-2012 Microchip Technology Inc. DS70652E-page 145
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
10.5 I/O Helpful Tips
1. In some cases, certain pins, as defined in
Section 26.0 “Electrical Characteristics”,
Table 26-11 under “Injection Current”, have
internal protection diodes to VDD and VSS. The
term, “Injection Current”, is also referred to as
“Clamp Current”. On designated pins, with suffi-
cient external current limiting precautions by the
user, I/O pin input voltages are allowed to be
greater or less than the data sheet absolute
maximum ratings with nominal VDD, with respect
to the VSS and VDD supplies. Note that when the
user application forward biases either of the high
or low side internal input clamp diodes, that the
resulting current being injected into the device,
that is clamped internally by the VDD and VSS
power rails, may affect the ADC accuracy by
four to six counts.
2. I/O pins that are shared with any analog input pin,
(i.e., ANx), are always analog pins by default after
any Reset. Consequently, any pin(s) configured
as an analog input pin, automatically disables the
digital input pin buffer. As such, any attempt to
read a digital input pin will always return a ‘0’
regardless of the digital logic level on the pin if the
analog pin is configured. To use a pin as a digital
I/O pin on a shared ANx pin, the user application
needs to configure the Analog Pin Configuration
register in the ADC module (AD1PCFGL), by
setting the appropriate bit that corresponds to that
I/O port pin, to a ‘1’. On devices with more than
one ADC, both analog pin configurations for both
ADC modules must be configured as a digital I/O
pin for that pin to function as a digital I/O pin.
3. Most I/O pins have multiple functions. Referring to
the device pin diagrams in the data sheet, the pri-
orities of the functions allocated to any pins are
indicated by reading the pin name from left-to-
right. The left most function name takes prece-
dence over any function to its right in the naming
convention. For example: AN16/T2CK/T7CK/RC1.
This indicates that AN16 is the highest priority in
this example and will supersede all other functions
to its right in the list. Those other functions to its
right, even if enabled, would not work as long as
any other function to its left was enabled. This rule
applies to all of the functions listed for a given pin.
4. Each CN pin has a configurable internal weak
pull-up resistor. The pull-ups act as a current
source connected to the pin, and eliminates the
need for external resistors in certain applica-
tions. The internal pull-up is to ~(VDD-0.8), not
VDD. This is still above the minimum VIH of
CMOS and TTL devices.
5. When driving LEDs directly, the I/O pin can
source or sink more current than what is specified
in the VOH/IOH and VOL/IOL DC characteristic
specification. The respective IOH and IOL current
rating only applies to maintaining the correspond-
ing output at or above the VOH and at or below the
VOL levels. However, for LEDs unlike digital
inputs of an externally connected device, they are
not governed by the same minimum VIH/VIL
levels. An I/O pin output can safely sink or source
any current less than that listed in the absolute
maximum rating section of the data sheet. For
example:
VOH = 2.4v @ IOH = -6 mA and VDD = 3.3V
The maximum output current sourced by any 6 mA
I/O pin = 15 mA.
LED source current < 15 mA is technically
permitted. Refer to the VOH/IOH specifications in
Section 26.0 “Electrical Characteristics” for
additional information.
10.6 I/O Resources
Many useful resources are provided on the main
product page of the Microchip web site for the devices
listed in this data sheet. This product page, which can
be accessed using this link, contains the latest updates
and additional information.
10.6.1 KEY RESOURCES
•“dsPIC33F/PIC24H Family Reference Manual”,
Section 10. “I/O Ports” (DS70193)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33F/PIC24H Family Reference
Manual” Sections
• Development Tools
Note: Although it is not possible to use a digital
input pin when its analog function is
enabled, it is possible to use the digital I/O
output function, TRISx = 0x0, while the
analog function is also enabled. However,
this is not recommended, particularly if the
analog input is connected to an external
analog voltage source, which would
create signal contention between the
analog signal and the output pin driver.
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554109
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 146 2011-2012 Microchip Technology Inc.
10.7 Peripheral Pin Select Registers
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family of devices
implements up to 23 registers for remappable
peripheral configuration.
Note: Input and Output Register values can only
be changed if IOLOCK (OSCCON<6>) = 0.
See Section 10.4.3.1 “Control Register
Lock” for a specific command sequence.
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —INT1R<4:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-0 Unimplemented: Read as ‘0’
2011-2012 Microchip Technology Inc. DS70652E-page 147
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —INT2R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 148 2011-2012 Microchip Technology Inc.
REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —T3CKR<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —T2CKR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
2011-2012 Microchip Technology Inc. DS70652E-page 149
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —T5CKR<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —T4CKR<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to the Corresponding RPn Pin bits(1)
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to the Corresponding RPn Pin bits(1)
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 150 2011-2012 Microchip Technology Inc.
REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — IC2R<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — IC1R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
2011-2012 Microchip Technology Inc. DS70652E-page 151
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-6: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — IC3R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4-0 IC3R<4:0>: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 152 2011-2012 Microchip Technology Inc.
REGISTER 10-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —OCFAR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4-0 OCFAR<4:0>: Assign Output Capture A (OCFA) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
2011-2012 Microchip Technology Inc. DS70652E-page 153
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — U1CTSR<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —U1RXR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 U1CTSR<4:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 154 2011-2012 Microchip Technology Inc.
REGISTER 10-9: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —SCK1R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —SDI1R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits(1)
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits(1)
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 155
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-10: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — SS1R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits
11111 = Input tied to VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 156 2011-2012 Microchip Technology Inc.
REGISTER 10-11: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP1R<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP0R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-12: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP3R<4:0>(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP2R<4:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not available in dsPIC33FJXX(GP/MC)101 devices.
2011-2012 Microchip Technology Inc. DS70652E-page 157
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-13: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP5R<4:0>(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP4R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not available in dsPIC33FJ(16/32)(GP/MC)101 devices.
REGISTER 10-14: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP7R<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP6R<4:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not available in dsPIC33FJ(16/32)(GP/MC)101 devices.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 158 2011-2012 Microchip Technology Inc.
REGISTER 10-15: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP9R<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP8R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-16: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP11R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP10R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not available in dsPIC33FJXX(GP/MC)101 devices.
2011-2012 Microchip Technology Inc. DS70652E-page 159
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-17: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP13R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP12R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not available in dsPIC33FJXXGP101 devices.
REGISTER 10-18: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP15R<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP14R<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits
(see Table 10-2 for peripheral function numbers)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 160 2011-2012 Microchip Technology Inc.
REGISTER 10-19: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP17R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP16R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only.
REGISTER 10-20: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP19R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP18R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 161
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 10-21: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP21R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP20R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only.
REGISTER 10-22: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP23R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP22R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 162 2011-2012 Microchip Technology Inc.
\
REGISTER 10-23: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP25R<4:0>
(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —RP24R<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 163
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
11.0 TIMER1
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the Real-Time Clock (RTC) or
operate as a free-running interval timer/counter. Timer1
can operate in three modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Timer1 also supports these features:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep modes
• Interrupt on 16-bit Period register match or falling
edge of external gate signal
Figure 11-1 presents a block diagram of the 16-bit timer
module.
To configure Timer1 for operation:
1. Load the timer value into the TMR1 register.
2. Load the timer period value into the PR1
register.
3. Select the timer prescaler ratio using the
TCKPS<1:0> bits in the T1CON register.
4. Set the Clock and Gating modes using the TCS
and TGATE bits in the T1CON register.
5. Set or clear the TSYNC bit in T1CON to select
synchronous or asynchronous operation.
6. If interrupts are required, set the Timer1 Inter-
rupt Enable bit, T1IE. Use the Timer1 Interrupt
Priority bits, T1IP<2:0>, to set the interrupt
priority.
7. Set the TON bit (= 1) in the T1CON register.
FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
TON
SOSCI
SOSCO/
PR1
Set T1IF
Equal
Comparator
TMR1
Reset
SOSCEN
1
0
TSYNC
Q
QD
CK
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TCS
TGATE
Sync
Gate
Sync
1x
01
00
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 164 2011-2012 Microchip Technology Inc.
11.1 Timer1 Control Register
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1)—TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
— TGATE TCKPS<1:0> —TSYNCTCS
(1)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer1 On bit(1)
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0> Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer1 Clock Source Select bit(1)
1 = External clock from pin, T1CK (on the rising edge)
0 = Internal clock (FCY)
bit 0 Unimplemented: Read as ‘0’
Note 1: When TCS = 1 and TON = 1, writes to the TMR1 register are inhibited from the CPU.
2011-2012 Microchip Technology Inc. DS70652E-page 165
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
12.0 TIMER2/3 AND TIMER4/5
Timer2/3 and Timer4/5 have three 2-bit timers that can
also be configured as two independent 16-bit timers
with selectable operating modes.
As a 32-bit timer, Timer2/3 and Timer4/5 permit
operation in three modes:
• Two independent 16-bit timers (e.g., Timer2 and
Timer3 or Timer4 and Timer5) with all 16-bit
operating modes (except Asynchronous Counter
mode)
• Single 32-bit timer (Timer2/3 and Timer4/5)
• Single 32-bit synchronous counter (Timer2/3 and
Timer4/5)
Timer2/3 and Timer4/5 also support:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during Idle and Sleep modes
• Interrupt on a 32-bit Period register match
• Time base for input capture and output compare
modules (Timer2 and Timer3 only)
• ADC1 event trigger (Timer2/3 only)
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the event trigger. The
operating modes and enabled features are determined
by setting the appropriate bit(s) in the T2CON, T3CON,
T4CON and T5CON registers (see Register 12-1
through Register 12-2).
For 32-bit timer/counter operation, Timer2/4 is the least
significant word (lsw) and Timer3/5 is the most
significant word (msw) of the 32-bit timers.
12.1 32-Bit Operation
To configure Timer2/3 and Timer4/5 for 32-bit
operation:
1. Set the T32 control bit.
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
4. Load the timer period value. PR3/PR5 contains
the msw of the value, while PR2/PR4 contains
the least significant word (lsw).
5. If interrupts are required, set the interrupt enable
bit, T3IE or T5IE. Use the priority bits,
T3IP<2:0> or T5IP<2:0>, to set the interrupt pri-
ority. While Timer2/Timer4 controls the timer, the
interrupt appears as a Timer3/Timer5 interrupt.
6. Set the corresponding TON bit.
The timer value at any point is stored in the register
pair, TMR3:TMR2 or TMR5:TMR4, which always
contains the msw of the count, while TMR2 or TMR4
contains the lsw.
12.2 16-Bit Operation
To configure any of the timers for individual 16-bit
operation:
1. Clear the T32 bit corresponding to that timer.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx
register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the TON bit.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note 1: Timer4 and Timer5 are available in
dsPIC33FJ32(GP/MC10X) devices only.
Note: For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are used for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 166 2011-2012 Microchip Technology Inc.
FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM(1,3,4)
Set TxIF
Equal Comparator
PRx PRy
Reset
LSbMSb
Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective
to the TxCON register.
2: The ADC event trigger is available only on Timer2/3.
3: Timer4/5 is available in dsPIC33FJ32(GP/MC)10X devices only.
4: Where ‘x’ or ‘y’ are present, x = 2 or 4; y = 3 or 5.
Data Bus<15:0>
TMRxHLD
Read TMRx/TMRy
Write TMRx/TMRy 16
16
16
Q
QD
CK
TGATE
0
1
TON
TCKPS<1:0>
2
TCY
TCS
1x
01
TGATE
00
TxCK
ADC Event Trigger(2)
Gate
Sync
Prescaler
1, 8, 64, 256
Sync
TMRx TMRy
16
To CTMU Filter
2011-2012 Microchip Technology Inc. DS70652E-page 167
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT) BLOCK DIAGRAM(1)
FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT) BLOCK DIAGRAM(1)
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TCY TCS
TGATE
TxCK
PRx
Set TxIF
Equal
Comparator
TMRx
Reset
Q
QD
CK
TGATE
1
0
Gate
Sync
1x
01
00
Sync
To C T M U F i lt e r
Note 1: Timer4 is available in dsPIC33FJ32(GP/MC)10X devices only.
Prescaler
(/n)
Gate
Sync
TGATE
TCS
00
10
x1
TMRx
PRx
FCY
TGATE
Set TxIF Flag
0
1
Sync
TCKPS<1:0>
Equal
Reset
TxCK
ADC SOC Trigger
Prescaler
(/n)
TCKPS<1:0>
To CTMU F i lter
Note 1: Timer5 is available in dsPIC33FJ32(GP/MC)10X devices only.
Falling Edge
Detect
Comparator
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 168 2011-2012 Microchip Technology Inc.
12.3 Timer2/3 and Timer4/5 Control
Registers
REGISTER 12-1: T2CON CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON —TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
— TGATE TCKPS<1:0> T32 —TCS—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer2 On bit
When T32 = 1:
1 = Starts 32-bit Timer2/3
0 = Stops 32-bit Timer2/3
When T32 = 0:
1 = Starts 16-bit Timer2
0 = Stops 16-bit Timer2
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer2 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer2 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit
1 = Timer2 and Timer3 form a single 32-bit timer
0 = Timer2 and Timer3 act as two 16-bit timers
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer2 Clock Source Select bit
1 = External clock from pin, T2CK (on the rising edge)
0 = Internal clock (FCY)
bit 0 Unimplemented: Read as ‘0’
2011-2012 Microchip Technology Inc. DS70652E-page 169
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 12-2: T3CON CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(2) —TSIDL
(1)— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
— TGATE
(2)TCKPS<1:0>(2)——TCS
(2)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer3 On bit(2)
1 = Starts 16-bit Timer3
0 = Stops 16-bit Timer3
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer3 Stop in Idle Mode bit(1)
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer3 Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(2)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer3 Clock Source Select bit(2)
1 = External clock from T3CK pin
0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer2 Control register (T2CON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer2 Control register (T2CON<3>), these
bits have no effect.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 170 2011-2012 Microchip Technology Inc.
REGISTER 12-3: T4CON CONTROL REGISTER(1)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON —TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
— TGATE TCKPS<1:0> T32 —TCS—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer4 On bit
When T32 = 1:
1 = Starts 32-bit Timer4/5
0 = Stops 32-bit Timer4/5
When T32 = 0:
1 = Starts 16-bit Timer4
0 = Stops 16-bit Timer4
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer4 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer4 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer4 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit
1 = Timer4 and Timer5 form a single 32-bit timer
0 = Timer4 and Timer5 act as two 16-bit timers
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer4 Clock Source Select bit
1 = External clock from pin, T4CK (on the rising edge)
0 = Internal clock (FCY)
bit 0 Unimplemented: Read as ‘0’
Note 1: This register is available in dsPIC33FJ32(GP/MC)10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 171
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 12-4: T5CON CONTROL REGISTER(1)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(3) —TSIDL
(2)— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
— TGATE
(3)TCKPS<1:0>(3)——TCS
(3)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer5 On bit(3)
1 = Starts 16-bit Timer3
0 = Stops 16-bit Timer3
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer5 Stop in Idle Mode bit(2)
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer5 Gated Time Accumulation Enable bit(3)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer5 Input Clock Prescale Select bits(3)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer5 Clock Source Select bit(3)
1 = External clock from T5CK pin
0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: This register is available in dsPIC33FJ32(GP/MC)10X devices only.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timer4 Control register (T4CON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: When the 32-bit timer operation is enabled (T32 = 1) in the Timer4 Control register (T4CON<3>), these
bits have no effect.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 172 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 173
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
13.0 INPUT CAPTURE
The input capture module is useful in applications
requiring frequency (period) and pulse
measurement. The dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104 devices
support up to three input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1. Simple Capture Event modes:
• Capture timer value on every falling edge of
input at ICx pin
• Capture timer value on every rising edge of
input at ICx pin
2. Capture timer value on every edge (rising and
falling)
3. Prescaler Capture Event modes:
• Capture timer value on every 4th rising edge
of input at ICx pin
• Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values:
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Use of input capture to provide additional sources
of external interrupts
FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “Input
Capture” (DS70198) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
ICxBUF
ICx Pin
ICM<2:0> (ICxCON<2:0>)
Mode Select
3
Set Flag ICxIF
(in IFSn Register)
TMR2 TMR3
Edge Detection Logic
16 16
ICI<1:0>
ICOV, ICBNE (ICxCON<4:3>)
ICxCON Interrupt
Logic
System Bus
From 16-Bit Timers
ICTMR
(ICxCON<7>)
FIFO
Prescaler
Counter
(1, 4, 16) and
Clock Synchronizer
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
FIFO
R/W Logic
10
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 174 2011-2012 Microchip Technology Inc.
13.1 Input Capture Register
REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——ICSIDL— — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 ICSIDL: Input Capture Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 ICTMR: Input Capture Timer Select bits
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture Mode Select bits
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling)
(ICI<1:0> bits do not control interrupt generation for this mode.)
000 = Input capture module turned off
2011-2012 Microchip Technology Inc. DS70652E-page 175
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
14.0 OUTPUT COMPARE The output compare module can select either Timer2 or
Timer3 for its time base. The module compares the
value of the timer with the value of one or two compare
registers depending on the operating mode selected.
The state of the output pin changes when the timer
value matches the Compare register value. The output
compare module generates either a single output
pulse, or a sequence of output pulses, by changing the
state of the output pin on the compare match events.
The output compare module can also generate
interrupts on compare match events.
The output compare module has multiple operating
modes:
• Active-Low One-Shot mode
• Active-High One-Shot mode
• Toggle mode
• Delayed One-Shot mode
• Continuous Pulse mode
• PWM mode without Fault protection
• PWM mode with Fault protection
FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Output
Compare” (DS70209) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
OCxR
Comparator
Output
Logic
OCM<2:0>
OCx
Set Flag bit,
OCxIF
OCxRS
Mode Select
3
01OCTSEL 01
1616
OCFA
TMR2
TMR2
QS
R
TMR3
TMR3
Rollover Rollover
Output
Logic
Output
Enable Enable
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 176 2011-2012 Microchip Technology Inc.
14.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare x Control (OCxCON<2:0>)
register. Table 14-1 lists the different bit settings for the
Output Compare modes. Figure 14-2 illustrates the
output compare operation for various modes. The user
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
TABLE 14-1: OUTPUT COMPARE MODES
FIGURE 14-2: OUTPUT COMPARE OPERATION
Note: See Section 13. “Output Compare” in
the “dsPIC33F/PIC24H Family Reference
Manual” (DS70209) for OCxR and
OCxRS register restrictions.
OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation
000 Module Disabled Controlled by GPIO register —
001 Active-Low One-Shot 0OCx Rising Edge
010 Active-High One-Shot 1OCx Falling Edge
011 Toggle Mode Current output is maintained OCx Rising and Falling Edge
100 Delayed One-Shot 0OCx Falling Edge
101 Continuous Pulse 0OCx Falling Edge
110 PWM Mode without Fault
Protection
0, if OCxR is zero
1, if OCxR is non-zero
No Interrupt
111 PWM Mode with Fault
Protection
0, if OCxR is zero
1, if OCxR is non-zero
OCFA Falling Edge for OC1 to OC4
OCxRS
TMRy
OCxR
Timer is Reset on
Period Match
Continuous Pulse Mode
(OCM<2:0> = 101)
PWM Mode
(OCM<2:0> =
110
or
111
)
Active-Low One-Shot
(OCM<2:0> = 001)
Active-High One-Shot
(OCM<2:0> = 010)
Toggle Mode
(OCM<2:0> = 011)
Delayed One-Shot
(OCM<2:0> = 100)
Output Compare
Mode Enabled
2011-2012 Microchip Technology Inc. DS70652E-page 177
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
14.2 Output Compare Control Register
REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——OCSIDL — — — — —
bit 15 bit 8
U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0
— — — OCFLT OCTSEL OCM<2:0>
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit
1 = Output Compare x will halt in CPU Idle mode
0 = Output Compare x will continue to operate in CPU Idle mode
bit 12-5 Unimplemented: Read as ‘0’
bit 4 OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in hardware only)
0 = No PWM Fault condition has occurred
(This bit is only used when OCM<2:0> = 111.)
bit 3 OCTSEL: Output Compare Timer Selection bit
1 = Timer3 is the clock source for Output Compare x
0 = Timer2 is the clock source for Output Compare x
bit 2-0 OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx, Fault pin is enabled
110 = PWM mode on OCx, Fault pin is disabled
101 = Initializes OCx pin low, generates continuous output pulses on OCx pin
100 = Initializes OCx pin low, generates single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initializes OCx pin high, compare event forces OCx pin low
001 = Initializes OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 178 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 179
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
15.0 MOTOR CONTROL PWM
MODULE
The dsPIC33FJ16MC10X devices have a 6-channel
Pulse-Width Modulation (PWM) module.
The PWM module has the following features:
• Up to 16-bit resolution
• On-the-fly PWM frequency changes
• Edge-Aligned and Center-Aligned Output modes
• Single Pulse Generation mode
• Interrupt support for asymmetrical updates in
Center-Aligned mode
• Output override control for Electrically
Commutative Motor (ECM) operation or BLDC
• Special Event comparator for scheduling other
peripheral events
• Fault pins to optionally drive each of the PWM
output pins to a defined state
• Duty cycle updates configurable to be immediate
or synchronized to the PWM time base
15.1 PWM1: 6-Channel PWM Module
This module simplifies the task of generating multiple
synchronized PWM outputs. The following power and
motion control applications are supported by the PWM
module:
• 3-Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
• Uninterruptible Power Supply (UPS)
This module contains three duty cycle generators,
numbered 1 through 3. The module has six PWM
output pins, numbered PWM1H1/PWM1L1 through
PWM1H3/PWM1L3. The six I/O pins are grouped into
high/low numbered pairs, denoted by the suffix H or L,
respectively. For complementary loads, the low PWM
pins are always the complement of the corresponding
high I/O pin.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Motor Con-
trol PWM” (DS70187), in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 180 2011-2012 Microchip Technology Inc.
FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1)
P1DC3
P1DC3 Buffer
PWM1CON1
PWM1CON2
P1TPER
Comparator
Comparator
Channel 3 Dead-Time
Generator and
P1TCON
P1SECMP
Special Event Trigger
P1OVDCON
PWM Enable and Mode SFRs
PWM Manual Control SFR
Channel 2 Dead-Time
Generator and
Channel 1 Dead-Time
Generator and
PWM
Generator 2(1)
PWM
Generator 1(1)
PWM Generator 3
SEVTDIR
PTDIR
P1DTCON1
Dead-Time Control SFRs
PWM1L1
PWM1H1
PWM1L2
PWM1H2
Note 1: The details of PWM Generator 1 and 2 are not shown for clarity.
2: On dsPIC33FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for
correct functionality.
3: On dsPIC33FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external
pull-down resistor.
PWM1L3
PWM1H3
P1DTCON2
P1FLTACON Fault A Pin Control SFRs
PWM Time Base
Output
Driver
Block
FLTA1
(2,3)
Override Logic
Override Logic
Override Logic
Special Event
Postscaler
P1TPER Buffer
P1TMR
P1FLTBCON Fault B Pin Control SFRs
FLTB1
(3)
Comparator
16-Bit Data Bus
2011-2012 Microchip Technology Inc. DS70652E-page 181
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
15.2 PWM Faults
The Motor Control PWM module incorporates up to two
Fault inputs, FLTA1 and FLTB1. These Fault inputs are
implemented with Class B safety features. These
features ensure that the PWM outputs enter a safe
state when either of the Fault inputs is asserted.
The FLTA1 and FLTB1 pins, when enabled and having
ownership of a pin, also enable a soft internal pull-down
resistor. The soft pull-down provides a safety feature by
automatically asserting the Fault should a break occur
in the Fault signal connection.
The implementation of internal pull-down resistors is
dependent on the device variant. Tab le 1 5- 1 describes
which devices and pins implement the internal pull-down
resistors.
TABLE 15-1: INTERNAL PULL-DOWN
RESISTORS ON PWM FAULT
PINS
On devices without internal pull-downs on the Fault pin,
it is recommended to connect an external pull-down
resistor for Class B safety features.
15.2.1 PWM FAULTS AT RESET
During any Reset event, the PWM module maintains
ownership of both PWM Fault pins. At Reset, both
Faults are enabled in latched mode to guarantee the
fail-safe power-up of the application. The application
software must clear both of the PWM Faults before
enabling the Motor Control PWM module.
The Fault condition must be cleared by the external cir-
cuitry driving the Fault input pin high and clearing the
Fault interrupt flag. After the Fault pin condition has been
cleared, the PWM module restores the PWM output
signals on the next PWM period or half-period boundary.
Refer to Section 14. “Motor Control PWM”
(DS70187), in the “dsPIC33F/PIC24H Family
Reference Manual” for more information on the PWM
Faults.
15.3 Write-Protected Registers
On dsPIC33FJ(16/32)MC10X devices, write protection
is implemented for the PWMxCON1, PxFLTACON and
PxFLTBCON registers. The write protection feature
prevents any inadvertent writes to these registers. The
write protection feature can be controlled by the
PWMLOCK Configuration bit in the FOSCSEL Config-
uration register. The default state of the write protection
feature is enabled (PWMLOCK = 1). The write protec-
tion feature can be disabled by configuring PWMLOCK
(FOSCSEL<6>) = 0.
The user application can gain access to these locked
registers either by configuring the PWMLOCK bit
(FOSCSEL<6>) = 0 or by performing the unlock
sequence. To perform the unlock sequence, the user
application must write two consecutive values
(0xABCD and 0x4321) to the PWMxKEY register to
perform the unlock operation. The write access to the
PWMxCON1, PxFLTACON or PxFLTBCON registers
must be the next SFR access following the unlock
process. There can be no other SFR accesses during
the unlock process and subsequent write access.
To write to all registers, the PWMxCON1, PxFLTACON
and PxFLTBCON registers require three unlock
operations.
The correct unlocking sequence is described in
Example 15-1 and Example 15-2.
Device Fault Pin
Internal
Pull-Down
Implemented?
dsPIC33FJXXMC101 FLTA1 No
dsPIC33FJXXMC102 FLTA1 Yes
FLTB1 Yes
dsPIC33FJ32MC104 FLTA1 Yes
FLTB1 Yes
Note: The number of PWM Faults mapped to
the device pins depend on the specific
variant. Regardless of the variant, both
Faults will be enabled during any Reset
event. The application must clear both
FLTA1 and FLTB1 before enabling the
Motor Control PWM module. Refer to the
specific device pin diagrams to see which
Fault pins are mapped to the device pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 182 2011-2012 Microchip Technology Inc.
EXAMPLE 15-1: ASSEMBLY CODE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT
CLEARING SEQUENCE
EXAMPLE 15-2: C CODE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT CLEARING
SEQUENCE
; FLTA1 pin must be pulled high externally in order to clear and disable the Fault
; Writing to P1FLTBCON register requires unlock sequence
mov #0xabcd,w10 ; Load first unlock key to w10 register
mov #0x4321,w11 ; Load second unlock key to w11 register
mov #0x0000,w0 ; Load desired value of P1FLTACON register in w0
mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register
mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register
mov w0,P1FLTACON ; Write desired value to P1FLTACON register
; FLTB1 pin must be pulled high externally in order to clear and disable the Fault
; Writing to P1FLTBCON register requires unlock sequence
mov #0xabcd,w10 ; Load first unlock key to w10 register
mov #0x4321,w11 ; Load second unlock key to w11 register
mov #0x0000,w0 ; Load desired value of P1FLTBCON register in w0
mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register
mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register
mov w0,P1FLTBCON ; Write desired value to P1FLTBCON register
; Enable all PWMs using PWM1CON1 register
; Writing to PWM1CON1 register requires unlock sequence
mov #0xabcd,w10 ; Load first unlock key to w10 register
mov #0x4321,w11 ; Load second unlock key to w11 register
mov #0x0077,w0 ; Load desired value of PWM1CON1 register in w0
mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register
mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register
mov w0,PWM1CON1 ; Write desired value to PWM1CON1 register
// FLTA1 pin must be pulled high externally in order to clear and disable the Fault
// Writing to P1FLTACON register requires unlock sequence
// Use builtin function to write 0x0000 to P1FLTACON register
__builtin_write_PWMSFR(&P1FLTACON, 0x0000, &PWM1KEY);
// FLTB1 pin must be pulled high externally in order to clear and disable the Fault
// Writing to P1FLTBCON register requires unlock sequence
// Use builtin function to write 0x0000 to P1FLTBCON register
__builtin_write_PWMSFR(&P1FLTBCON, 0x0000, &PWM1KEY);
// Enable all PWMs using PWM1CON1 register
// Writing to PWM1CON1 register requires unlock sequence
// Use builtin function to write 0x0077 to PWM1CON1 register
__builtin_write_PWMSFR(&PWM1CON1, 0x0077, &PWM1KEY);
2011-2012 Microchip Technology Inc. DS70652E-page 183
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
15.4 PWM Control Registers
REGISTER 15-1: PxTCON: PWMx TIME BASE CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
PTEN —PTSIDL— — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTEN: PWM Time Base Timer Enable bit
1 = PWM time base is on
0 = PWM time base is off
bit 14 Unimplemented: Read as ‘0’
bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7-4 PTOPS<3:0>: PWM Time Base Output Postscale Select bits
1111 = 1:16 postscale
•
•
•
0001 = 1:2 postscale
0000 = 1:1 postscale
bit 3-2 PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits
11 = PWM time base input clock period is 64 TCY (1:64 prescale)
10 = PWM time base input clock period is 16 TCY (1:16 prescale)
01 = PWM time base input clock period is 4 TCY (1:4 prescale)
00 = PWM time base input clock period is TCY (1:1 prescale)
bit 1-0 PTMOD<1:0>: PWM Time Base Mode Select bits
11 = PWM time base operates in a Continuous Up/Down Count mode with interrupts for double
PWM updates
10 = PWM time base operates in a Continuous Up/Down Count mode
01 = PWM time base operates in Single Pulse mode
00 = PWM time base operates in a Free-Running mode
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 184 2011-2012 Microchip Technology Inc.
REGISTER 15-2: PxTMR: PWMx TIMER COUNT VALUE REGISTER
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTDIR PTMR<14:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTMR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only)
1 = PWM time base is counting down
0 = PWM time base is counting up
bit 14-0 PTMR <14:0>: PWM Time Base Register Count Value bits
REGISTER 15-3: PxTPER: PWMx TIME BASE PERIOD REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— PTPER<14:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTPER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits
2011-2012 Microchip Technology Inc. DS70652E-page 185
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 15-4: PxSECMP: PWMx SPECIAL EVENT COMPARE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTDIR(1)SEVTCMP<14:8>(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<7:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit(1)
1 = A Special Event Trigger will occur when the PWM time base is counting down
0 = A Special Event Trigger will occur when the PWM time base is counting up
bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits(2)
Note 1: SEVTDIR is compared with PTDIR (PxTMR<15>) to generate the Special Event Trigger.
2: PxSECMP<14:0> is compared with PxTMR<14:0> to generate the Special Event Trigger.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 186 2011-2012 Microchip Technology Inc.
REGISTER 15-5: PWMxCON1: PWMx CONTROL REGISTER 1(1)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PMOD3 PMOD2 PMOD1
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— PEN3H(2)PEN2H(2)PEN1H(2)— PEN3L(2)PEN2L(2)PEN1L(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 PMOD<3:1>: PWM I/O Pair Mode bits
1 = PWM I/O pin pair is in the Independent PWM Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
bit 7 Unimplemented: Read as ‘0’
bit 6-4 PEN3H:PEN1H: PWMxH I/O Enable bits(2)
1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin is disabled, I/O pin becomes a general purpose I/O
bit 3 Unimplemented: Read as ‘0’
bit 2-0 PEN3L:PEN1L: PWMxL I/O Enable bits(2)
1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin is disabled, I/O pin becomes a general purpose I/O
Note 1: The PWMxCON1 register is a write-protected register. Refer to Section 15.3 “Write-Protected
Registers” for more information on the unlock sequence.
2: The Reset status for this bit depends on the setting of the PWMPIN Configuration bit (FPOR<7>):
• If PWMPIN = 1 (default), the PWM pins are controlled by the PORT register at Reset, meaning they
are initially programmed as inputs (i.e., tri-stated).
• If PWMPIN = 0, the PWM pins are controlled by the PWM module at Reset and are therefore, initially
programmed as output pins.
2011-2012 Microchip Technology Inc. DS70652E-page 187
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 15-6: PWMxCON2: PWMx CONTROL REGISTER 2
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — SEVOPS<3:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — IUE OSYNC UDIS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 postscale
•
•
•
0001 = 1:2 postscale
0000 = 1:1 postscale
bit 7-3 Unimplemented: Read as ‘0’
bit 2 IUE: Immediate Update Enable bit
1 = Updates to the active PxDC registers are immediate
0 = Updates to the active PxDC registers are synchronized to the PWM time base
bit 1 OSYNC: Output Override Synchronization bit
1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on the next TCY boundary
bit 0 UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 188 2011-2012 Microchip Technology Inc.
REGISTER 15-7: PxDTCON1: PWMx DEAD-TIME CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTBPS<1:0> DTB<5:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTAPS<1:0> DTA<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits
11 = Clock period for Dead-Time Unit B is 8 TCY
10 = Clock period for Dead-Time Unit B is 4 TCY
01 = Clock period for Dead-Time Unit B is 2 TCY
00 = Clock period for Dead-Time Unit B is TCY
bit 13-8 DTB<5:0>: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit B bits
bit 7-6 DTAPS<1:0>: Dead-Time Unit A Prescale Select bits
11 = Clock period for Dead-Time Unit A is 8 TCY
10 = Clock period for Dead-Time Unit A is 4 TCY
01 = Clock period for Dead-Time Unit A is 2 TCY
00 = Clock period for Dead-Time Unit A is TCY
bit 5-0 DTA<5:0>: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit A bits
2011-2012 Microchip Technology Inc. DS70652E-page 189
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 15-8: PxDTCON2: PWMx DEAD-TIME CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5 DTS3A: Dead-Time Select for PWM3 Signal Going Active bit
1 = Dead time provided from Unit B
0 = Dead time provided from Unit A
bit 4 DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit
1 = Dead time provided from Unit B
0 = Dead time provided from Unit A
bit 3 DTS2A: Dead-Time Select for PWM2 Signal Going Active bit
1 = Dead time provided from Unit B
0 = Dead time provided from Unit A
bit 2 DTS2I: Dead-Time Select for PWM2 Signal Going Inactive bit
1 = Dead time provided from Unit B
0 = Dead time provided from Unit A
bit 1 DTS1A: Dead-Time Select for PWM1 Signal Going Active bit
1 = Dead time provided from Unit B
0 = Dead time provided from Unit A
bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit
1 = Dead time provided from Unit B
0 = Dead time provided from Unit A
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 190 2011-2012 Microchip Technology Inc.
REGISTER 15-9: PxFLTACON: PWMx FAULT A CONTROL REGISTER(1,2,3,4)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
FLTAM — — — — FAEN3 FAEN2 FAEN1
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 FAOVxH<3:1>:FAOVxL<3:1>: Fault Input A PWM Override Value bits
1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
bit 7 FLTAM: Fault A Mode bit
1 = The Fault A input pin functions in the Cycle-by-Cycle mode
0 = The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8>
bit 6-3 Unimplemented: Read as ‘0’
bit 2 FAEN3: Fault Input A Enable bit
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A
bit 1 FAEN2: Fault Input A Enable bit
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input A
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A
bit 0 FAEN1: Fault Input A Enable bit
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input A
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A
Note 1: Comparator outputs are not internally connected to the PWM Fault control logic. If using the comparator
modules for Fault generation, the user must externally connect the desired comparator output pin to the
dedicated FLTA1 or FLTB1 input pin.
2: Refer to Table 15-1 for FLTA1 implementation details.
3: The PxFLTACON register is a write-protected register. Refer to Section 15.3 “Write-Protected Registers”
for more information on the unlock sequence.
4: During any Reset event, FLTA1 is enabled by default and must be cleared as described in Section 15.2
“PWM Faults”.
2011-2012 Microchip Technology Inc. DS70652E-page 191
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 15-10: PxFLTBCON: PWMx FAULT B CONTROL REGISTER(1,2,3,4)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
FLTBM — — — — FBEN3 FBEN2 FBEN1
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 FBOVxH<3:1>:FBOVxL<3:1>: Fault Input B PWM Override Value bits
1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
bit 7 FLTBM: Fault B Mode bit
1 = The Fault B input pin functions in the Cycle-by-Cycle mode
0 = The Fault B input pin latches all control pins to the programmed states in PxFLTBCON<13:8>
bit 6-3 Unimplemented: Read as ‘0’
bit 2 FBEN3: Fault Input B Enable bit
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input B
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input B
bit 1 FBEN2: Fault Input B Enable bit
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input B
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input B
bit 0 FBEN1: Fault Input B Enable bit
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input B
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B
Note 1: Comparator outputs are not internally connected to the PWM Fault control logic. If using the Comparator
modules for Fault generation, the user must externally connect the desired comparator output pin to the
dedicated FLTA1 or FLTB1 input pin.
2: Refer to Table 15-1 for FLTB1 implementation details.
3: The PxFLTACON register is a write-protected register. Refer to Section 15.3 “Write-Protected Registers”
for more information on the unlock sequence.
4: During any Reset event, FLTB1 is enabled by default and must be cleared as described in Section 15.2
“PWM Faults”.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 192 2011-2012 Microchip Technology Inc.
REGISTER 15-11: PxOVDCON: PWMx OVERRIDE CONTROL REGISTER
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits
1 = Output on PWMx I/O pin is controlled by the PWM generator
0 = Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bits
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 POUTxH<3:1>:POUTxL<3:1>: PWM Manual Output bits
1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bits are cleared
0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bits are cleared
2011-2012 Microchip Technology Inc. DS70652E-page 193
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 15-12: PxDC1: PWMx DUTY CYCLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDC1<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDC1<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PDC1<15:0>: PWM Duty Cycle 1 Value bits
REGISTER 15-13: PxDC2: PWMx DUTY CYCLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDC2<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDC2<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PDC2<15:0>: PWM Duty Cycle 2 Value bits
REGISTER 15-14: PxDC3: PWMx DUTY CYCLE REGISTER 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDC3<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDC3<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 194 2011-2012 Microchip Technology Inc.
REGISTER 15-15: PWMxKEY: PWMx UNLOCK REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PWMKEY<15:0>: PWMx Unlock bits
If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and
PxFLTBCON registers are writable only after the proper sequence is written to the PWMxKEY register. If the
PWMLOCK Configuration bit is deasserted (PWMLOCK = 0), the PWMxCON1, PxFLTACON and
PxFLTBCON registers are writable at all times. Refer to Section 14. “Motor Control PWM” (DS70187) in
the “dsPIC33F/PIC24H Family Reference Manual” for details on the unlock sequence.
2011-2012 Microchip Technology Inc. DS70652E-page 195
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift regis-
ters, display drivers, Analog-to-Digital Converters, etc.
The SPI module is compatible with SPI and SIOP from
Motorola®.
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of four pins:
• SDIx (serial data input)
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active-low slave select).
In Master mode operation, SCKx is a clock output. In
Slave mode, it is a clock input.
FIGURE 16-1: SPIx MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 18. “Serial
Peripheral Interface (SPI)” (DS70206)
in the “dsPIC33F/PIC24H Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Internal Data Bus
SDIx
SDOx
SSx
SCKx
SPIxSR
bit 0
Shift Control
Edge
Select
FCY
Primary
1:1/4/16/64
Enable
Prescaler
SPIxBUF
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Clock
Control
Secondary
Prescaler
1:1 to 1:8
SPIxRXB SPIxTXB
Control
Sync
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 196 2011-2012 Microchip Technology Inc.
16.1 SPI Helpful Tips
1. In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2<13>) = 1, use a
pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on SSx.
2. In Non-Framed 3-Wire mode, (i.e., not using
SSx from a master):
a) If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx.
b) If CKP = 0, always place a pull-down
resistor on SSx.
3. FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
4. In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit (SPIxCON1<5>)
is set.
5. To avoid invalid slave read data to the master,
the user’s master software must ensure enough
time for slave software to fill its write buffer
before the user application initiates a master
write/read cycle. It is always advisable to pre-
load the SPIxBUF Transmit register in advance
of the next master transaction cycle. SPIxBUF is
transferred to the SPIx Shift register and is
empty once the data transmission begins.
6. The SPI related pins (SDI1, SDO1, SCK1) are
located at fixed positions in the dsPIC33FJ16(GP/
MC)10X devices. The same pins are remappable
in the dsPIC33FJ32(GP/MC)10X devices.
16.2 SPI Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
16.2.1 KEY RESOURCES
•Section 18. “Serial Peripheral Interface (SPI)”
(DS70206) in the “dsPIC33F/PIC24H Family
Reference Manual”.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33F/PIC24H Family Reference
Manual” sections
• Development Tools
Note: This insures that the first frame transmission
after initialization is not shifted or corrupted.
Note: This will insure that during power-up and
initialization, the master/slave will not lose
sync due to an errant SCK transition that
would cause the slave to accumulate data
shift errors for both transmit and receive,
appearing as corrupted data.
Note: Not all third-party devices support Frame
mode timing. Refer to the SPI electrical
characteristics for details.
Note: In the event you are not able to access
the product page using the link above,
enter this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554109
2011-2012 Microchip Technology Inc. DS70652E-page 197
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
16.3 SPI Control Registers
REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
SPIEN — SPISIDL — — — — —
bit 15 bit 8
U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0
— SPIROV — — — — SPITBF SPIRBF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user software has not read the
previous data in the SPIxBUF register
0 = No overflow has occurred.
bit 5-2 Unimplemented: Read as ‘0’
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit has started, SPIxTXB is empty
Automatically set in hardware when the CPU writes the SPIxBUF location, loading SPIxTXB. Automatically
cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared
in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 198 2011-2012 Microchip Technology Inc.
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK DISSDO MODE16 SMP CKE(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN(2)CKP MSTEN SPRE<2:0>(3)PPRE<1:0>(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
bit 11 DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7 SSEN: SPIx Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by module, pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to a value of 1:1.
2011-2012 Microchip Technology Inc. DS70652E-page 199
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
.
.
.
000 = Secondary prescale 8:1
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to a value of 1:1.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 200 2011-2012 Microchip Technology Inc.
REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD FRMPOL — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — — FRMDLY —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin used as Frame Sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14 SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
bit 13 FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame Sync pulse is active-high
0 = Frame Sync pulse is active-low
bit 12-2 Unimplemented: Read as ‘0’
bit 1 FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with first bit clock
0 = Frame Sync pulse precedes first bit clock
bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application
2011-2012 Microchip Technology Inc. DS70652E-page 201
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
17.0 INTER-INTEGRATED CIRCUIT™
(I2C™)
The Inter-Integrated Circuit™ (I2C™) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
The I2C module has a 2-pin interface:
• The SCLx pin is clock
• The SDAx pin is data
The I2C module offers the following key features:
•I
2C interface supporting both Master and Slave
modes of operation.
•I
2C Slave mode supports 7-bit and 10-bit addresses
•I
2C Master mode supports 7-bit and 10-bit addresses
•I
2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
•I
2C supports multi-master operation, detects bus
collision and arbitrates accordingly
17.1 Operating Modes
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7-bit and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
The following types of I2C operation are supported:
•I
2C slave operation with 7-bit address
•I
2C slave operation with 10-bit address
•I
2C master operation with 7-bit or 10-bit address
For details about the communication sequence in each
of these modes, refer to the Microchip web site
(www.microchip.com) for the latest “dsPIC33F/PIC24H
Family Reference Manual” sections.
17.2 I2C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CxSTAT are
read/write:
• I2CxRSR is the shift register used for shifting data
• I2CxRCV is the receive buffer and the register to
which data bytes are written or from which data
bytes are read
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation
• I2CxADD register holds the slave address
• ADD10 status bit indicates 10-Bit Addressing
mode
• I2CxBRG acts as the Baud Rate Generator (BRG)
reload value
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 19. “Inter-Integrated
Circuit™ (I2C™)” (DS70195) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 202 2011-2012 Microchip Technology Inc.
FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1)
Internal
Data Bus
SCLx
SDAx
Shift
Match Detect
I2CxADD
Clock
Address Match
Clock
Stretching
I2CxTRN
LSb
Shift Clock
BRG Down Counter
Reload
Control
TCY/2
Acknowledge
Generation
I2CxCON
I2CxSTAT
Control Logic
Read
LSb
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
I2CxRCV
Collision
Detect
Start and Stop
Bit Generation
Start and Stop
Bit Detect
I2CxMSK
2011-2012 Microchip Technology Inc. DS70652E-page 203
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
17.3 I2C Control Registers
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C pins are controlled by port functions
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clears at
beginning of every slave data byte transmission. Hardware clears at end of every slave address byte
reception. Hardware clears at every slave data byte reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clears at beginning of every slave
data byte transmission. Hardware clears at end of every slave address byte reception.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode is disabled
bit 10 A10M: I2Cx 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0 = General call address is disabled
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 204 2011-2012 Microchip Technology Inc.
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; hardware
clears at end of master Acknowledge sequence
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C; hardware clears at end of eighth bit of the master receive data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins; hardware clears at end of the master Stop sequence
0 = Stop condition not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware clears at end of the master
Repeated Start sequence
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins; hardware clears at end of master Start sequence
0 = Start condition is not in progress
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
2011-2012 Microchip Technology Inc. DS70652E-page 205
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC
R/C-0, HSC R/C-0, HSC
R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit HS = Hardware Settable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware sets or clears at end of slave Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware sets at beginning of master transmission. Hardware clears at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware sets at detection of bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware sets when address matches general call address. Hardware clears at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware sets at match of 2nd byte of matched 10-bit address. Hardware clears at Stop detection.
bit 7 IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware sets at occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware sets at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5 D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clears at device address match. Hardware sets by reception of a slave byte.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware sets or clears when Start, Repeated Start or Stop is detected.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 206 2011-2012 Microchip Technology Inc.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware sets or clears when Start, Repeated Start or Stop is detected.
bit 2 R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware sets or clears after reception of an I2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware sets when I2CxRCV is written with received byte. Hardware clears when software reads
I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware sets when software writes to I2CxTRN. Hardware clears at completion of data transmission.
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
2011-2012 Microchip Technology Inc. DS70652E-page 207
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK9 AMSK8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0 AMSKx: Mask for Address Bit x Select bits
1 = Enables masking for Bit x of incoming message address; bit match not required in this position
0 = Disables masking for Bit x; bit match required in this position
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 208 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 209
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 device family. The
UART is a full-duplex asynchronous system that can
communicate with peripheral devices, such as
personal computers, LIN/J2602, RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins, and
also includes an IrDA® encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
through the UxTX and UxRX Pins
• Even, Odd or No Parity options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with
16-Bit Prescaler
• Baud Rates Ranging from 1 Mbps to 6 bps at
16x mode at 16 MIPS
• Baud Rates Ranging from 4 Mbps to 24.4 bps at
4x mode at 16 MIPS
• 4-Deep First-In First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Support for Automatic Baud Rate Detection
•IrDA
® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA® Support
A simplified block diagram of the UART module is
shown in Figure 18-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “UART”
(DS70188) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
UxRX
Hardware Flow Control
UART Receiver
UART Transmitter UxTX
Baud Rate Generator
UxRTS/BCLK
UxCTS
IrDA®
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 210 2011-2012 Microchip Technology Inc.
18.1 UART Helpful Tips
1. In multi-node direct connect UART networks,
UART receive inputs react to the complementary
logic level, defined by the URXINV bit
(UxMODE<4>) which defines the Idle state, the
default of which is logic high (i.e., URXINV = 0).
Because remote devices do not initialize at the
same time, it is likely that one of the devices,
because the RX line is floating, will trigger a Start
bit detection and will cause the first byte received
after the device has been initialized to be invalid.
To avoid this situation, the user should use a
pull-up or pull-down resistor on the RX pin
depending on the value of the URXINV bit.
a) If URXINV = 0, use a pull-up resistor on the
RX pin.
b) If URXINV = 1, use a pull-down resistor on
the RX pin.
2. The first character received on a wake-up from
Sleep mode, caused by activity on the UxRX pin
of the UART module, will be invalid. In Sleep
mode, peripheral clocks are disabled. By the
time the oscillator system has restarted and
stabilized from Sleep mode, the baud rate bit
sampling clock, relative to the incoming UxRX
bit timing, is no longer synchronized, resulting in
the first character being invalid. This is to be
expected.
18.2 UART Resources
Many useful resources are provided on the main
product page of the Microchip web site for the devices
listed in this data sheet. This product page, which can
be accessed using this link, contains the latest updates
and additional information.
18.2.1 KEY RESOURCES
•Section 17. “UART” (DS70188) in the
“dsPIC33F/PIC24H Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33F/PIC24H Family Reference
Manual” sections
• Development Tools
Note: In the event you are not able to access
the product page using the link above,
enter this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554109
2011-2012 Microchip Technology Inc. DS70652E-page 211
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
18.3 UART Control Registers
REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
UARTEN(1)— USIDL IREN(2)RTSMD —UEN<1:0>
bit 15 bit 8
R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by the UEN<1:0> bits
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is
minimal
bit 14 Unimplemented: Read as ‘0’
bit 13 USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: UARTx Mode Selection for UxRTS Pin bit
1 =UxRTS
pin in Simplex mode
0 =UxRTS pin in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins are controlled by
port latches
bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt is generated on falling edge; bit is cleared
in hardware on following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
2: This feature is available for 16x BRG mode (BRGH = 0) only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 212 2011-2012 Microchip Technology Inc.
bit 4 URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
2: This feature is available for 16x BRG mode (BRGH = 0) only.
2011-2012 Microchip Technology Inc. DS70652E-page 213
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1)UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0
URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14 UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA encoded, UxTX Idle state is ‘1’
0 = IrDA encoded, UxTX Idle state is ‘0’
bit 12 Unimplemented: Read as ‘0’
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by port
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 214 2011-2012 Microchip Technology Inc.
bit 5 ADDEN: Address Character Detect bit (Bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (read-only/clear only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1 0 transition) will reset
the receiver buffer and the UxRSR to the empty state
bit 0 URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
2011-2012 Microchip Technology Inc. DS70652E-page 215
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
19.0 10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices have up
to 14 ADC module input channels.
19.1 Key Features
The 10-bit ADC configuration has the following key
features:
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 14 analog input pins
• Four Sample-and-Hold (S&H) circuits for
simultaneous sampling of up to four analog input
pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• Four result alignment options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle modes
• 16-word conversion result buffer
Depending on the particular device pinout, the ADC
can have up to 14 analog input pins.
Block diagrams of the ADC module are shown in
Figure 19-1 through Figure 19-3.
19.2 ADC Initialization
To configure the ADC module:
1. Select port pins as analog inputs
(AD1PCFGL<15:0>).
2. Select the analog conversion clock to match the
desired data rate with the processor clock
(ADxCON3<7:0>).
3. Determine how many Sample-and-Hold
channels will be used (ADxCON2<9:8>).
4. Select the appropriate sample/conversion
sequence (ADxCON1<7:5> and
ADxCON3<12:8>).
5. Select the way conversion results are presented
in the buffer (ADxCON1<9:8>).
6. Turn on the ADC module (ADxCON1<15>).
7. Configure ADC interrupt (if required):
a) Clear the ADxIF bit.
b) Select the ADC interrupt priority.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer
to Section 16. “Analog-to-Digital
Converter (ADC)” (DS70183) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 216 2011-2012 Microchip Technology Inc.
FIGURE 19-1: ADC1 BLOCK DIAGRAM FOR dsPIC33FJXX(GP/MC)101 DEVICES
S&H0
S&H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0-AN3
AN10(3)
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
S&H2
AN1
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
S&H3
AN2
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
CH1
CH0
CH2
CH3
CH0SA<4:0>
Channel
Scan
CSCNA
Alternate Input Selection
CTMU TEMP(1)
Note 1: Internally connected to the CTMU module.
2: This selection is only used with CTMU capacitive and time measurement.
3: This pin is available in dsPIC33FJ32(GP/MC)101 devices only.
Open(2)
CTMUI(1)
AVDD AVSS
VCFG<2:0>
AN9(3)
AN10(3)
AN9(3)
SAR ADC
VREFH VREFL
2011-2012 Microchip Technology Inc. DS70652E-page 217
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 19-2: ADC1 BLOCK DIAGRAM FOR dsPIC33FJXX(GP/MC)102 DEVICES
SAR ADC
S&H0
S&H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0-AN5
AN10(3)
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
S&H2
AN1
AN4
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
S&H3
AN2
AN5
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
CH1
CH0
CH2
CH3
CH0SA<4:0>
Channel
Scan
CSCNA
Alternate Input Selection
VREFH VREFL
CTMU TEMP(1)
Note 1: Internally connected to the CTMU module.
2: This selection is only used with CTMU capacitive and time measurement.
3: This pin is available in dsPIC33FJ32(GP/MC)102 devices only.
Open(2) CTMUI(1)
AN9
(3)
AN10
(3)
AN9(3)
AVDD AVSS
VCFG<2:0>
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 218 2011-2012 Microchip Technology Inc.
FIGURE 19-3: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ32(GP/MC)104 DEVICES
SAR ADC
S&H0
S&H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0-AN12
AN15
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
S&H2
AN1
AN4
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
S&H3
AN2
AN5
CH123SA
VREFL
CH123SB
CH123NA CH123NB
+
-
CH1
CH0
CH2
CH3
CH0SA<4:0>
Channel
Scan
CSCNA
Alternate Input Selection
VREFH VREFL
CTMU TEMP(1)
Note 1: Internally connected to the CTMU module.
2: This selection is only used with CTMU capacitive and time measurement.
Open(2)
CTMUI(1)
AN6
AN10
AN9
AN7
AN11
AN8
AVDD AVSS
VCFG<2:0>
2011-2012 Microchip Technology Inc. DS70652E-page 219
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 19-4: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
19.3 ADC Helpful Tips
1. The SMPI<3:0> (AD1CON2<5:2>) control bits:
a) Determine when the ADC interrupt flag is
set and an interrupt is generated if enabled.
b) When the CSCNA bit (AD1CON2<10>) is
set to ‘1’, determine when the ADC analog
scan channel list, defined in the AD1CSSL
register, starts over from the beginning.
2. The ADC has 16 result buffers. ADC conversion
results are stored sequentially in ADC1BUF0-
ADC1BUFF regardless of which analog inputs
are being used, subject to the SMPI<3:0> bits
(AD1CON2<5:2>). There is no relationship
between the ANx input being measured and
which ADC buffer (ADC1BUF0-ADC1BUFF)
that the conversion results will be placed in.
3. The DONE bit (AD1CON1<0>) is only cleared at
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely, even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this
behavior because the CPU code execution is
faster than the ADC. As a result, in Manual
Sample mode, particularly where the user’s
code is setting the SAMP bit (AD1CON1<1>),
the DONE bit should also be cleared by the user
application just before setting the SAMP bit.
19.4 ADC Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
19.4.1 KEY RESOURCES
•Section 16. “Analog-to-Digital Converter
(ADC)” (DS70183) in the “dsPIC33F/PIC24H
Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33F/PIC24H Family Reference
Manual” sections
• Development Tools
1
0
ADC Internal
RC Clock(1)
TOSC(1) X2
ADC Conversion
Clock Multiplier
1, 2, 3, 4, 5,..., 64
ADxCON3<15>
TCY
TAD
6
ADxCON3<5:0>
Note 1: See the ADC specifications in Section 26.0 “Electrical Characteristics” for the exact RC clock value.
Note: In the event you are not able to access
the product page using the link above,
enter this URL in your browser: http://
www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554109
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 220 2011-2012 Microchip Technology Inc.
19.5 ADC Control Registers
REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ADON —ADSIDL — — — FORM<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0,
HC, HS
R/C-0,
HC, HS
SSRC<2:0> — SIMSAM ASAM SAMP DONE
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: ADC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)
00 = Integer (DOUT = 0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 =CTMU
101 = Reserved
100 = Reserved
011 = Motor control PWM interval ends sampling and starts conversion(1)
010 = GP Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing SAMP bit ends sampling and starts conversion
bit 4 Unimplemented: Read as ‘0’
bit 3 SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x)
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or samples CH0 and
CH1 simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set
0 = Sampling begins when the SAMP bit is set
Note 1: This feature is available in dsPIC33FJ(16/32)MC10X devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 221
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 1 SAMP: ADC Sample Enable bit
1 = ADC Sample-and-Hold amplifiers are sampling
0 = ADC Sample-and-Hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling; automatically set by hardware if ASAM = 1.
If SSRC<2:0> = 000, software can write ‘0’ to end sampling and start conversion. If SSRC<2:0> 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADC Conversion Status bit
1 = ADC conversion cycle is completed
0 = ADC conversion has not started or is in progress
Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear the
DONE bit status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
Note 1: This feature is available in dsPIC33FJ(16/32)MC10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 222 2011-2012 Microchip Technology Inc.
REGISTER 19-2: AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
VCFG<2:0> —— CSCNA CHPS<1:0>
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS — SMPI<3:0> BUFM ALTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits
bit 12-11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Scan Input Selections for CH0+ During Sample A bit
1 = Scans inputs
0 = Does not scan inputs
bit 9-8 CHPS<1:0>: Select Channels Utilized bits
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = ADC is currently filling second half of buffer, user should access data in the first half
0 = ADC is currently filling first half of buffer, user application should access data in the second half
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Fill Mode Select bit
1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0 = Always starts filling buffer from the beginning
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
ADREF+ ADREF-
xxx AVDD AVSS
2011-2012 Microchip Technology Inc. DS70652E-page 223
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 19-3: AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC —— SAMC<4:0>(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS<7:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: ADC Conversion Clock Source bit
1 = ADC internal RC clock
0 = Clock derived from system clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111 = Reserved
•
•
•
•
01000000 = Reserved
00111111 = TCY • (ADCS<7:0> + 1) = 64 • TCY = TAD
•
•
•
00000010 = TCY • (ADCS<7:0> + 1) = 3 • TCY = TAD
00000001 = TCY • (ADCS<7:0> + 1) = 2 • TCY = TAD
00000000 = TCY • (ADCS<7:0> + 1) = 1 • TCY = TAD
Note 1: This bit is only used if SSRC<2:0> (AD1CON1<7:5>) = 1.
2: This bit is not used if ADRC (AD1CON3<15>) = 1.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 224 2011-2012 Microchip Technology Inc.
REGISTER 19-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NB<1:0> CH123SB
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NA<1:0> CH123SA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
dsPIC33FJ16(GP/MC)101/102 Devices Only:
11 = Reserved
10 = Reserved
0x = CH1, CH2, CH3 negative input is AVSS
dsPIC33FJ32(GP/MC)101/102 Devices Only:
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is not connected
10 = Reserved
0x = CH1, CH2, CH3 negative input is AVSS
dsPIC33FJ32(GP/MC)104 Devices Only:
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is AVSS
bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
dsPIC33FJXX(GP/MC)101 Devices Only:
1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
All Other Devices:
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3 Unimplemented: Read as ‘0’
bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
Refer to bits<10-9> for the available settings.
bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
Refer to bit 8 for the available settings.
2011-2012 Microchip Technology Inc. DS70652E-page 225
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 19-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB —— CH0SB<4:0>
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA —— CH0SA<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is AVSS
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
11111-10000 = Reserved; do not use
01111 = Channel 0 positive input is AN15(2)
01110 = No channels connected, all inputs floating (used for CTMU)
01101 = Channel 0 positive input is connected to CTMU temperature sensor
01100 = Channel 0 positive input is AN12(2)
01011 = Channel 0 positive input is AN11(2)
01010 = Channel 0 positive input is AN10(3)
01001 = Channel 0 positive input is AN9(3)
01000 = Channel 0 positive input is AN8(2)
00111 = Channel 0 positive input is AN7(2)
00110 = Channel 0 positive input is AN6(2)
00101 = Channel 0 positive input is AN5(1)
00100 = Channel 0 positive input is AN4(1)
00011 = Channel 0 positive input is AN3
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is AVSS
bit 6-5 Unimplemented: Read as ‘0’
bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
Refer to bits<12-8> for the available settings.
Note 1: This setting is available on all devices, excluding the dsPIC33FJXX(GP/MC)101, where it is reserved.
2: This setting is available in the dsPIC33FJ32(GP/MC)104 devices only and is reserved in all other devices.
3: This setting is available on all devices, excluding the dsPIC33FJ16(GP/MC)101/102, where it is reserved.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 226 2011-2012 Microchip Technology Inc.
,2
REGISTER 19-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2,3)
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS15(4)—— CSS12(4)CSS11(4)CSS10(6)CSS9(6)CSS8(4)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS7(4)CSS6(4)CSS5(5)CSS4(5)CSS3 CSS2 CSS1 CSS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CSS15: ADC Input Scan Selection bit(4)
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 14-13 Unimplemented: Read as ‘0’
bit 12-0 CSS<12:0>: ADC Input Scan Selection bits(4,5,6)
1 = Selects ANx for input scan
0 = Skips ANx for input scan
Note 1: On devices without 14 analog inputs, all AD1CSSL bits can be selected by the user application. However,
inputs selected for scan without a corresponding input on the device converts VREFL.
2: CSSx = ANx, where x = 0 through 12 and 15.
3: CTMU temperature sensor input cannot be scanned.
4: The CSS<15,12:11,8:6> bits are available in the dsPIC33FJ32(GP/MC)104 devices only and are reserved
in all other devices.
5: The CSS<5:4> bits are available on all devices, excluding the dsPIC33FJXX(GP/MC)101 devices, where
they are reserved.
6: The CSS<10:9> bits are available on all devices, excluding the dsPIC33FJ16(GP/MC)101/102 devices,
where they are reserved.
2011-2012 Microchip Technology Inc. DS70652E-page 227
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 19-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3)
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG15(4,5)——PCFG12
(4,5)PCFG11(4,5)PCFG10(4,7)PCFG9(4,7)PCFG8(4,5)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG7(4,5)PCFG6(4,5)PCFG5(4,6)PCFG4(4,6)PCFG3(4)PCFG2(4)PCFG1(4)PCFG0(4)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PCFG15: ADC Port Configuration Control bit(4,5)
1 = Port pin is in Digital mode, port read input is enabled, ADC input multiplexer is connected to AVSS
0 = Port pin is in Analog mode, port read input is disabled, ADC samples pin voltage
bit 14-13 Unimplemented: Read as ‘0’
bit 12-0 PCFG<12:0>: ADC Port Configuration Control bits(4,5,6,7)
1 = Port pin is in Digital mode, port read input is enabled, ADC input multiplexer is connected to AVSS
0 = Port pin is in Analog mode, port read input is disabled, ADC samples pin voltage
Note 1: On devices without 14 analog inputs, all PCFG bits are R/W by user. However, PCFGx bits are ignored on
ports without a corresponding input on the device.
2: PCFGx = ANx, where x = 0 through 12, and 15.
3: The PCFGx bits have no effect if the ADC module is disabled by setting the AD1MD bit in the PMD1 register.
When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.
4: Pins shared with analog functions (i.e., ANx) are analog by default and therefore, must be set by the user
to enable any digital function on that pin. Reading any port pin with the analog function enabled will return
a ‘0’, regardless of the signal input level.
5: The PCFG<15,12:11,8:6> bits are available in the dsPIC33FJ32(GP/MC)104 devices only and are
reserved in all other devices.
6: The PCFG<5:4> bits are available on all devices, excluding the dsPIC33FJXX(GP/MC)101 devices, where
they are reserved.
7: The PCFG<10:9> bits are available on all devices, excluding the dsPIC33FJ16(GP/MC)101/102 devices,
where they are reserved.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 228 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 229
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
20.0 COMPARATOR MODULE The comparator module provides three comparators
that can be configured in different ways. As shown in
Figure 20-1, individual comparator options are
specified by the comparator module’s Special Function
Register (SFR) control bits.
These options allow users to:
• Select the edge for trigger and interrupt generation
• Select low-power control
• Configure the comparator voltage reference and
band gap
• Configure output blanking and masking
The comparator operating mode is determined by the
input selections (i.e., whether the input voltage is
compared to a second input voltage) to an internal
voltage reference.
FIGURE 20-1: COMPARATOR I/O OPERATING MODES
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
device families. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 54. “Comparator with
Blanking” (DS70647) of the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
C3
C1
Blanking
Function
Digital
Filter
C2
CVREF
(Figure 20-3)(Figure 20-4)
–
+
VIN-
VIN+
–
+
VIN-
VIN+
–
+
VIN-
VIN+
BGSEL<1:0>
AVDD AVSS
IVREF(1)
C1INB
C1INC
C1IND
MUX
C1INA
INTREF
MUX
C2INB
C2INC
C2IND
C2INA
INTREF
CVREFIN
MUX
C3INB
C3INC
C3IND
MUX
C3INA
INTREF
CVREFIN
CVREFIN
C1OUT
CPOL
Interrupt
Logic
EVPOL<1:0>
COE
COUT
Blanking
Function
Digital
Filter
(Figure 20-3)(Figure 20-4)
C2OUT
CPOL
Interrupt
Logic
EVPOL<1:0>
COE
COUT
Digital
Filter
(Figure 20-4)
C3OUT
CPOL
Interrupt
Logic
EVPOL<1:0>
COE
COUT
Note 1: This reference voltage is generated internally on the device. Refer to Section 26.0 “Electrical
Characteristics” for the specified voltage range.
MUX
MUX
Function
(Figure 20-3)
Blanking
Reference
(Figure 20-2)
Comparator Voltage
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 230 2011-2012 Microchip Technology Inc.
FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
FIGURE 20-3: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM
8R
R
CVREN
AVDD(1)
8R
R
R
R
R
R
R
16 Steps
CVRR
CVREF
CVR3
CVR2
CVR1
CVR0
CVRCON<3:0>
AVSS(1)
CVRSRC
CVRCON<CVROE>
CVREFIN
VREFSEL
Note 1: This pin is VDD and VSS on devices that have no AVDD or AVSS pins.
16-to-1 MUX
SELSRCA<3:0>
SELSRCB<3:0>
SELSRCC<3:0>
AND
CMxMSKCON
MUX A
MAI
MBI
MCI
Comparator Output To D i g ita l
Signals
Filter
OR
Blanking
Blanking
Blanking
Signals
Signals
ANDI
MASK
“AND-OR” Function
HLMS
MUX C
Blanking
Logic
(CMxMSKCON<15)
(CMxMSKSRC<11:8)
(CMxMSKSRC<7:4)
(CMxMSKSRC<3:0>)
MBI
MCI
MAI
MBI
MCI
MAI
MUX B
2011-2012 Microchip Technology Inc. DS70652E-page 231
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 20-4: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM
CXOUT
CFLTREN
Digital Filter
Timer2
FOSC
FCY
CFSEL<2:0>
CFDIV
From Blanking Logic
Timer3
PWM Special Event Trigger
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 232 2011-2012 Microchip Technology Inc.
20.1 Comparator Control Registers
REGISTER 20-1: CMSTAT: COMPARATOR STATUS REGISTER
R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
CMSIDL — — — — C3EVT C2EVT C1EVT
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — C3OUT C2OUT C1OUT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CMSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues operation of all comparators when device enters Idle mode
0 = Continues operation of all comparators in Idle mode
bit 14-11 Unimplemented: Read as ‘0’
bit 10 C3EVT: Comparator 3 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 9 C2EVT: Comparator 2 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 8 C1EVT: Comparator 1 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 7-3 Unimplemented: Read as ‘0’
bit 2 C3OUT: Comparator 3 Output Status bit
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 1 C2OUT: Comparator 2 Output Status bit
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 0 C1OUT: Comparator 1 Output Status bit
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
2011-2012 Microchip Technology Inc. DS70652E-page 233
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-2: CMxCON: COMPARATOR x CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
CON COE CPOL — — — CEVT COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
EVPOL<1:0> —CREF—— CCH<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-10 Unimplemented: Read as ‘0’
bit 9 CEVT: Comparator Event bit
1 = Comparator event according to EVPOL<1:0> settings occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8 COUT: Comparator Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1 (inverted polarity):
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated only on high-to-low transition of the polarity selected
comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt is generated only on low-to-high transition of the polarity-selected
comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 234 2011-2012 Microchip Technology Inc.
bit 4 CREF: Comparator Reference Select bit (VIN+ input)
1 = VIN+ input connects to internal CVREFIN voltage
0 = VIN+ input connects to CxINA pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Channel Select bits
11 = VIN- input of comparator connects to INTREF
10 = VIN- input of comparator connects to CXIND pin
01 = VIN- input of comparator connects to CXINC pin
00 = VIN- input of comparator connects to CXINB pin
REGISTER 20-2: CMxCON: COMPARATOR x CONTROL REGISTER (CONTINUED)
2011-2012 Microchip Technology Inc. DS70652E-page 235
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0
— — — — SELSRCC<3:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SELSRCB<3:0> SELSRCA<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 SELSRCC<3:0>: Mask C Input Select bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM1H3
0100 = PWM1L3
0011 = PWM1H2
0010 = PWM1L2
0001 = PWM1H1
0000 = PWM1L1
bit 7-4 SELSRCB<3:0>: Mask B Input Select bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM1H3
0100 = PWM1L3
0011 = PWM1H2
0010 = PWM1L2
0001 = PWM1H1
0000 = PWM1L1
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 236 2011-2012 Microchip Technology Inc.
bit 3-0 SELSRCA<3:0>: Mask A Input Select bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM1H3
0100 = PWM1L3
0011 = PWM1H2
0010 = PWM1L2
0001 = PWM1H1
0000 = PWM1L1
REGISTER 20-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT REGISTER (CONTINUED)
2011-2012 Microchip Technology Inc. DS70652E-page 237
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-4: CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 HLMS: High or Low Level Masking Select bits
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 14 Unimplemented: Read as ‘0’
bit 13 OCEN: OR Gate C Input Inverted Enable bit
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
bit 12 OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
bit 11 OBEN: OR Gate B Input Inverted Enable bit
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
bit 10 OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
bit 9 OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
bit 8 OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
bit 7 NAGS: Negative AND Gate Output Select
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
bit 6 PAGS: Positive AND Gate Output Select
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
bit 5 ACEN: AND Gate A1 C Input Inverted Enable bit
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
bit 4 ACNEN: AND Gate A1 C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 238 2011-2012 Microchip Technology Inc.
bit 3 ABEN: AND Gate A1 B Input Inverted Enable bit
1 = MBI is connected to AND gate
0 = MBI is not connected to AND gate
bit 2 ABNEN: AND Gate A1 B Input Inverted Enable bit
1 = Inverted MBI is connected to AND gate
0 = Inverted MBI is not connected to AND gate
bit 1 AAEN: AND Gate A1 A Input Enable bit
1 = MAI is connected to AND gate
0 = MAI is not connected to AND gate
bit 0 AANEN: AND Gate A1 A Input Inverted Enable bit
1 = Inverted MAI is connected to AND gate
0 = Inverted MAI is not connected to AND gate
REGISTER 20-4: CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER (CONTINUED)
2011-2012 Microchip Technology Inc. DS70652E-page 239
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-5: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CFSEL<2:0> CFLTREN CFDIV<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = Reserved
110 = Reserved
101 = Timer3
100 = Timer2
011 = Reserved
010 = PWM Special Event Trigger
001 = FOSC
000 = FCY
bit 3 CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 240 2011-2012 Microchip Technology Inc.
REGISTER 20-6: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — VREFSEL BGSEL<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE(1)CVRR —CVR<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 VREFSEL: Voltage Reference Select bit
1 = CVREFIN = CVREF pin
0 = CVREFIN is generated by the resistor network
bit 9-8 BGSEL<1:0>: Band Gap Reference Source Select bits
11 = INTREF = CVREF pin
10 = INTREF = 1.2V (nominal)(2)
0x = Reserved
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6 CVROE: Comparator Voltage Reference Output Enable bit(1)
1 = Voltage level is output on CVREF pin
0 = Voltage level is disconnected from CVREF pin
bit 5 CVRR: Comparator Voltage Reference Range Selection bit
1 = CVRSRC/24 step-size
0 = CVRSRC/32 step-size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR<3:0>: Comparator Voltage Reference Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1:
CVREFIN = (CVR<3:0>/24) • (CVRSRC)
When CVRR = 0:
CVREFIN = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)
Note 1: CVROE overrides the TRIS bit setting.
2: This reference voltage is generated internally on the device. Refer to Section 26.0 “Electrical Characteristics”
for the specified voltage range.
2011-2012 Microchip Technology Inc. DS70652E-page 241
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
21.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
This chapter discusses the Real-Time Clock and
Calendar (RTCC) module, available
on dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices, and
its operation.
Some of the key features of the RTCC module are:
• Time: hours, minutes and seconds
• 24-hour format (military time)
• Calendar: weekday, date, month and year
• Alarm configurable
• Year range: 2000 to 2099
• Leap year correction
• BCD format for compact firmware
• Optimized for low-power operation
• User calibration with auto-adjust
• Calibration range: ±2.64 seconds error per month
• Requirements: external 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on RTCC pin
The RTCC module is intended for applications where
accurate time must be maintained for extended periods
of time with minimum to no intervention from the CPU.
The RTCC module is optimized for low-power usage to
provide extended battery lifetime while keeping track of
time.
The RTCC module is a 100-year clock and calendar
with automatic leap year detection. The range of the
clock is from 00:00:00 (midnight) on January 1, 2000 to
23:59:59 on December 31, 2099.
The hours are available in 24-hour (military time)
format. The clock provides a granularity of one second
with half-second visibility to the user.
FIGURE 21-1: RTCC BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
device families of devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 37.
“Real-Time Clock and Calendar
(RTCC)” (DS70310) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
RTCC Prescalers
RTCC Timer
Comparator
Compare Registers
Repeat Counter
with Masks
RTCC Interrupt Logic
RCFGCAL
ALCFGRPT
Alarm
Event
32.768 kHz Input
from SOSC Oscillator
0.5s
RTCC Clock Domain
Alarm Pulse
RTCC Interrupt
CPU Clock Domain
RTCVAL
ALRMVAL
RTCC Pin
RTCOE
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 242 2011-2012 Microchip Technology Inc.
21.1 RTCC Module Registers
The RTCC module registers are organized into three
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
21.1.1 REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RCFGCAL<9:8>) to select the desired
Timer register pair (see Table 21-1).
By writing the RTCVALH byte, the RTCC Pointer value
(RTCPTR<1:0> bits) decrements by one until it
reaches ‘00’. Once it reaches ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
TABLE 21-1: RTCVAL REGISTER MAPPING
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits
(ALCFGRPT<9:8>) to select the desired Alarm register
pair (see Table 21-2).
By writing the ALRMVALH byte, the Alarm Pointer
value (ALRMPTR<1:0> bits) decrements by one until it
reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and
ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
TABLE 21-2: ALRMVAL REGISTER
MAPPING
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL, bytes will decrement the ALRMPTR<1:0>
value. The same applies to the RTCVALH or RTCVALL
bytes with the RTCPTR<1:0> being decremented.
21.1.2 WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
set (refer to Example 21-1).
EXAMPLE 21-1: SETTING THE RTCWREN BIT
RTCPTR
<1:0>
RTCC Value Register Window
RTCVAL<15:8> RTCVAL<7:0>
00 MINUTES SECONDS
01 WEEKDAY HOURS
10 MONTH DAY
11 — YEAR
ALRMPTR
<1:0>
Alarm Value Register Window
ALRMVAL<15:8> ALRMVAL<7:0>
00 ALRMMIN ALRMSEC
01 ALRMWD ALRMHR
10 ALRMMNTH ALRMDAY
11 ——
Note: This only applies to read operations and
not write operations.
Note: To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only 1 instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 21-1.
MOV #NVMKEY, W1 ;move the address of NVMKEY into W1
MOV #0x55, W2
MOV #0xAA, W3
MOV W2, [W1] ;start 55/AA sequence
MOV W3, [W1]
BSET RCFGCAL, #13 ;set the RTCWREN bit
2011-2012 Microchip Technology Inc. DS70652E-page 243
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
21.2 RTCC Control Registers
REGISTER 21-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
(1)
R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
RTCEN(2)— RTCWREN RTCSYNC HALFSEC(3)RTCOE RTCPTR<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CAL<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 RTCEN: RTCC Enable bit(2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading, due to a rollover ripple,
resulting in an invalid data read. If the register is read twice and the results are the same data, the
data can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11 HALFSEC: Half-Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 10 RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers;
the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00 = MINUTES
01 = WEEKDAY
10 = MONTH
11 = Reserved
RTCVAL<7:0>:
00 = SECONDS
01 = HOURS
10 = DAY
11 = YEAR
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 244 2011-2012 Microchip Technology Inc.
bit 7-0 CAL<7:0>: RTC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute
•
•
•
00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
•
•
•
10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
REGISTER 21-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
(1)
(CONTINUED)
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
2011-2012 Microchip Technology Inc. DS70652E-page 245
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — — RTSECSEL(1)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as ‘0’
bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1 = RTCC seconds clock is selected for the RTCC pin
0 = RTCC alarm pulse is selected for the RTCC pin
bit 0 Unimplemented: Read as ‘0’
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 246 2011-2012 Microchip Technology Inc.
REGISTER 21-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ARPT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 0x00 and
CHIME = 0)
0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit
1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 0x00 to 0xFF
0 = Chime is disabled; ARPT<7:0> bits stop once they reach 0x00
bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved – do not use
11xx = Reserved – do not use
bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;
the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVAL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
•
•
•
00000000 = Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to
0xFF unless CHIME = 1.
2011-2012 Microchip Technology Inc. DS70652E-page 247
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
YRTEN<3:0> YRONE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 21-5: RTCVAL (WHEN RTCPTR<1:0> = 10): MONTH AND DAY VALUE REGISTER(1)
U-0 U-0 U-0 R-x R-x R-x R-x R-x
— — — MTHTEN0 MTHONE<3:0>
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— DAYTEN<1:0> DAYONE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 248 2011-2012 Microchip Technology Inc.
REGISTER 21-6: RTCVAL (WHEN RTCPTR<1:0> = 01): WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY<2:0>
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— HRTEN<1:0> HRONE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
2011-2012 Microchip Technology Inc. DS70652E-page 249
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-7: RTCVAL (WHEN RTCPTR<1:0> = 00): MINUTES AND SECONDS VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— MINTEN<2:0> MINONE<3:0>
bit 15 bit 8
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— SECTEN<2:0> SECONE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 250 2011-2012 Microchip Technology Inc.
REGISTER 21-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE
REGISTER(1)
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — MTHTEN0 MTHONE<3:0>
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— DAYTEN<1:0> DAYONE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
2011-2012 Microchip Technology Inc. DS70652E-page 251
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS
VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— HRTEN<1:0> HRONE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 252 2011-2012 Microchip Technology Inc.
REGISTER 21-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS
VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— MINTEN<2:0> MINONE<3:0>
bit 15 bit 8
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— SECTEN<2:0> SECONE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
2011-2012 Microchip Technology Inc. DS70652E-page 253
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
22.0 CHARGE TIME
MEASUREMENT UNIT (CTMU)
The Charge Time Measurement Unit (CTMU) is a flex-
ible analog module that provides accurate differential
time measurement between pulse sources, as well as
asynchronous pulse generation. Its key features
include:
• Four edge input trigger sources
• Polarity control for each edge source
• Control of edge sequence
• Control of response to edges
• Precise time measurement resolution of 200 ps
• Accurate current source suitable for capacitive
measurement
• On-chip temperature measurement using a
built-in diode
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance
or generate output pulses that are independent of the
system clock.
The CTMU module is ideal for interfacing with
capacitive-based sensors. The CTMU is controlled
through three registers: CTMUCON1, CTMUCON2
and CTMUICON. CTMUCON1 enables the module,
the edge delay generation, sequencing of edges, and
controls the current source and the output trigger.
CTMUCON2 controls the edge source selection, edge
source polarity selection and edge sampling mode. The
CTMUICON register controls the selection and trim of
the current source.
Figure 22-1 shows the CTMU block diagram.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
device families of devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 55.
“Charge Time Measurement Unit
(CTMU)” (DS70635) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 254 2011-2012 Microchip Technology Inc.
FIGURE 22-1: CTMU BLOCK DIAGRAM
CTED1
CTED2
Current Source
Edge
Control
Logic
CTMUCON1 or CTMUCON2
Pulse
Generator
CTMUI to ADC
Comparator 2
Timer1
OC1
Current
Control
ITRIM<5:0>
IRNG<1:0>
CTMUICON
CTMU
Control
Logic
EDG1STAT
EDG2STAT Analog-to-Digital
CTPLS
IC1
CMP2
C2INA
CDelay
CTMU TEMP
CTMU
Temperature
Sensor
Current Control Selection TGEN EDG1STAT, EDG2STAT
CTMU TEMP 0EDG1STAT = EDG2STAT
CTMUI 0EDG1STAT EDG2STAT
CTMUP 1EDG1STAT EDG2STAT
No Connect 1EDG1STAT = EDG2STAT
Trigger
TGEN
CTMUP
External Capacitor
for Pulse Generation
2011-2012 Microchip Technology Inc. DS70652E-page 255
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
22.1 CTMU Control Registers
REGISTER 22-1: CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN(2)CTTRIG
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 TGEN: Time Generation Enable bit(1)
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11 EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10 EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9 IDISSEN: Analog Current Source Control bit(2)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8 CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7-0 Unimplemented: Read as ‘0’
Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more
information, see Section 10.4 “Peripheral Pin Select (PPS)”.
2: The ADC module S&H capacitor is not automatically discharged between sample/conversion cycles.
Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor before
conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC must be
sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 256 2011-2012 Microchip Technology Inc.
REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
EDG2MOD EDG2POL EDG2SEL<3:0> — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 EDG1MOD: Edge 1 Edge Sampling Selection bit
1 = Edge 1 is edge-sensitive
0 = Edge 1 is level-sensitive
bit 14 EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bits
1xxx = Reserved
01xx = Reserved
0011 = CTED1 pin
0010 = CTED2 pin
0001 = OC1 module
0000 = Timer1 module
bit 9 EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the edge source.
1 = Edge 2 has occurred
0 = Edge 2 has not occurred
bit 8 EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the edge source.
1 = Edge 1 has occurred
0 = Edge 1 has not occurred
bit 7 EDG2MOD: Edge 2 Edge Sampling Selection bit
1 = Edge 2 is edge-sensitive
0 = Edge 2 is level-sensitive
bit 6 EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits
1xxx = Reserved
01xx = Reserved
0011 = CTED2 pin
0010 = CTED1 pin
0001 = Comparator 2 module
0000 = IC1 module
bit 1-0 Unimplemented: Read as ‘0’
2011-2012 Microchip Technology Inc. DS70652E-page 257
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 22-3: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ITRIM<5:0> IRNG<1:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 ITRIM<5:0>: Current Source Trim bits
011111 = Nominal current output specified by IRNG<1:0> + 62%
011110 = Nominal current output specified by IRNG<1:0> + 60%
•
•
•
000001 = Nominal current output specified by IRNG<1:0> + 2%
000000 = Nominal current output specified by IRNG<1:0>
111111 = Nominal current output specified by IRNG<1:0> – 2%
•
•
•
100010 = Nominal current output specified by IRNG<1:0> – 62%
100001 = Nominal current output specified by IRNG<1:0> – 64%
bit 9-8 IRNG<1:0>: Current Source Range Select bits
11 = 100 Base Current(1)
10 = 10 Base Current
01 = Base current level (0.55 A nominal)
00 = Reserved
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This setting must be used for the CTMU temperature sensor.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 258 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 259
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
23.0 SPECIAL FEATURES
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices include several features
intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
23.1 Configuration Bits
The Configuration Shadow register bits can be config-
ured (read as ‘0’) or left unprogrammed (read as ‘1’) to
select various device configurations. These read-only
bits are mapped starting at program memory location,
0xF80000. A detailed explanation of the various bit
functions is provided in Table 23-4.
Note that address 0xF80000 is beyond the user pro-
gram memory space and belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads.
In dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices, the
configuration bytes are implemented as volatile memory.
This means that configuration data must be
programmed each time the device is powered up. Con-
figuration data is stored in the two words at the top of the
on-chip program memory space, known as the Flash
Configuration Words. Their specific locations are shown
in Table 23-2. These are packed representations of the
actual device Configuration bits, whose actual locations
are distributed among several locations in configuration
space. The configuration data is automatically loaded
from the Flash Configuration Words to the proper
Configuration registers during device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in pro-
gram memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
Note 1: This data sheet summarizes the
features of the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 24. “Pro-
gramming and Diagnostics” (DS70207)
and Section 25. “Device Configuration”
(DS70194) in the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Configuration data is reloaded on all types
of device Resets.
Note: Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 260 Preliminary 2011-2012 Microchip Technology Inc.
The Configuration Shadow register map is shown in Tab l e 2 3 - 1.
The Configuration Flash Word maps are shown in Tabl e 2 3 - 2 and Table 23-3.
TABLE 23-2: CONFIGURATION FLASH WORDS FOR dsPIC33FJ16(GP/MC)10X DEVICES(1)
TABLE 23-3: CONFIGURATION FLASH WORDS FOR dsPIC33FJ32(GP/MC)10X DEVICES(1)
TABLE 23-1: CONFIGURATION SHADOW REGISTER MAP
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
F80004 FGS —————— GCP GWRP
F80006 FOSCSEL IESO PWMLOCK(1)— WDTWIN<1:0> FNOSC<2:0>
F80008 FOSC FCKSM<1:0> IOL1WAY ——OSCIOFNC POSCMD<1:0>
F8000A FWDT FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
F8000C FPOR PWMPIN(1)HPOL(1)LPOL(1)ALTI2C1 — — — —
F8000E FICD Reserved(2)— Reserved(3)Reserved(3)——ICS<1:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: These bits are available in dsPIC33FJ(16/32)MC10X devices only.
2: This bit is reserved for use by development tools.
3: These bits are reserved, program as ‘0’.
File
Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2 002BFC —IESOPWMLOCK
(2)PWMPIN(2)WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC IOL1WAY LPOL(2)ALTI2C1 POSCMD<1:0>
CONFIG1 002BFE — Reserved(3)Reserved(3)GCP GWRP Reserved(4)HPOL(2)ICS<1:0> FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
2: These bits are reserved on dsPIC33FJ16GP10X devices and read as ‘1’.
3: These bits are reserved, program as ‘0’.
4: This bit is reserved for use by development tools and must be programmed as ‘1’.
File
Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2 0057FC —IESOPWMLOCK
(2)PWMPIN(2)WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC IOL1WAY LPOL(2)ALTI2C1 POSCMD<1:0>
CONFIG1 0057FE — Reserved(3)Reserved(3)GCP GWRP Reserved(4)HPOL(2)ICS<1:0> FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
2: These bits are reserved in dsPIC33FJ32GP10X devices and read as ‘1’.
3: These bits are reserved, program as ‘0’.
4: This bit is reserved for use by development tools and must be programmed as ‘1’.
2011-2012 Microchip Technology Inc. DS70652E-page 261
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 23-4: dsPIC33F CONFIGURATION BITS DESCRIPTION
Bit Field Description
GCP General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = Code protection is enabled for the entire program memory space
GWRP General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO Two-Speed Oscillator Start-up Enable bit
1 = Starts up device with FRC, then automatically switches to the user-selected oscillator source
when ready
0 = Starts up device with user-selected oscillator source
PWMLOCK PWM Lock Enable bit
1 = Certain PWM registers may only be written after key sequence
0 = PWM registers may be written without a key sequence
WDTWIN<1:0> Watchdog Timer Window Select bits
11 = WDT window is 24% of WDT period
10 = WDT window is 37.5% of WDT period
01 = WDT window is 50% of WDT period
00 = WDT window is 75% of WDT period
FNOSC<2:0> Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Reserved; do not use
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (MS + PLL, EC + PLL)
010 = Primary Oscillator (MS, HS, EC)
001 = Fast RC Oscillator with Divide-by-N and PLL module (FRCDIVN + PLL)
000 = Fast RC Oscillator (FRC)
FCKSM<1:0> Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSCIOFNC OSC2 Pin Function bit (except in MS and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
POSCMD<1:0> Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode (10 MHz-32 MHz)
01 = MS Crystal Oscillator mode (3 MHz-10 MHz)
00 = EC (External Clock) mode (DC-32 MHz)
FWDTEN Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN
bit in the RCON register will have no effect)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the
SWDTEN bit in the RCON register)
WINDIS Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 262 2011-2012 Microchip Technology Inc.
WDTPRE Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0> Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
PLLKEN PLL Lock Enable bit
1 = Clock switch to PLL will wait until the PLL lock signal is valid
0 = Clock switch will not wait for the PLL lock signal
ALTI2C Alternate I2C™ Pins bit
1 = I2C is mapped to SDA1/SCL1 pins
0 = I2C is mapped to ASDA1/ASCL1 pins
ICS<1:0> ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
PWMPIN Motor Control PWM Module Pin Mode bit
1 = PWM module pins controlled by PORT register at device Reset (tri-stated)
0 = PWM module pins controlled by PWM module at device Reset (configured as output pins)
HPOL Motor Control PWM High Side Polarity bit
1 = PWM module high side output pins have active-high output polarity
0 = PWM module high side output pins have active-low output polarity
LPOL Motor Control PWM Low Side Polarity bit
1 = PWM module low side output pins have active-high output polarity
0 = PWM module low side output pins have active-low output polarity
TABLE 23-4: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Description
2011-2012 Microchip Technology Inc. DS70652E-page 263
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 23-1: DEVID: DEVICE ID REGISTER
RRRRRRRR
DEVID<23:16>(1)
bit 23 bit 16
RRRRRRRR
DEVID<15:8>(1)
bit 15 bit 8
RRRRRRRR
DEVID<7:0>(1)
bit 7 bit 0
Legend: R = Read-Only bit U = Unimplemented bit
bit 23-0 DEIDV<23:0>: Device Identifier bits(1)
Note 1: Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits”
(DS70659) for the list of device ID values.
REGISTER 23-2: DEVREV: DEVICE REVISION REGISTER
RRRRRRRR
DEVREV<23:16>(1)
bit 23 bit 16
RRRRRRRR
DEVREV<15:8>(1)
bit 15 bit 8
RRRRRRRR
DEVREV<7:0>(1)
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-0 DEVREV<23:0>: Device Revision bits(1)
Note 1: Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits”
(DS70659) for the list of device revision values.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 264 2011-2012 Microchip Technology Inc.
23.2 On-Chip Voltage Regulator
All of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices power
their core digital logic at a nominal 2.5V. This can
create a conflict for designs that are required to operate
at a higher typical voltage, such as 3.3V. To simplify
system design, all devices in the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 23-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 26-14 located in Section 26.1
“DC Characteristics”.
On a POR, it takes approximately 20 s for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 23-1: CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
23.3 BOR: Brown-out Reset
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the
regulated supply voltage, VCAP. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an Oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT Time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
Note: It is important for low-ESR capacitors to
be placed as close as possible to the VCAP
pin.
Note 1: These are typical operating voltages. Refer to
Table 26-14 located in Section 26.1 “DC
Characteristics” for the full operating ranges
of VDD and VCAP.
2: It is important for low-ESR capacitors to be
placed as close as possible to the VCAP pin.
3: Typical VCAP pin voltage = 2.5V when
VDD VDDMIN.
VDD
VCAP
VSS
dsPIC33F
CEFC
3.3V
10
µF
Tantalum
2011-2012 Microchip Technology Inc. DS70652E-page 265
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
23.4 Watchdog Timer (WDT)
For dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices, the
WDT is driven by the LPRC oscillator. When the WDT
is enabled, the clock source is also enabled.
23.4.1 PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT Time-out (TWDT) period of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
•By a CLRWDT instruction during normal execution
23.4.2 SLEEP AND IDLE MODES
If the WDT is enabled, it will continue to run during Sleep
or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after the
device wakes up.
23.4.3 ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed to
‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN control
bit is cleared on any device Reset. The software WDT
option allows the user application to enable the WDT for
critical code segments and disables the WDT during
non-critical segments for maximum power savings.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
FIGURE 23-2: WDT BLOCK DIAGRAM
Note: The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
Note: If the WINDIS bit (FWDT<6>) is cleared,
the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
0
1
WDTPRE WDTPOST<3:0>
Watchdog Timer
Prescaler
(divide-by-N1)
Postscaler
(divide-by-N2)
Sleep/Idle
WDT
WDT Window Select
WINDIS
WDT
CLRWDT Instruction
SWDTEN
FWDTEN
LPRC Clock
RS RS
Wake-up
Reset
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 266 2011-2012 Microchip Technology Inc.
23.5 In-Circuit Serial Programming™
(ICSP™)
Devices can be serially programmed while in the end
application circuit. This is done with two lines for clock
and data and three other lines for power, ground and
the programming sequence. Serial programming
allows customers to manufacture boards with
unprogrammed devices and then program the Digital
Signal Controller just before shipping the product.
Serial programming also allows the most recent
firmware or a custom firmware to be programmed.
Refer to the “dsPIC33F Flash Programming
Specification for Devices with Volatile Configuration
Bits” (DS70659) for details about In-Circuit Serial
Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
23.6 In-Circuit Debugger
When MPLAB® ICD 3 is selected as a debugger, the in-
circuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
2011-2012 Microchip Technology Inc. DS70652E-page 267
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
24.0 INSTRUCTION SET SUMMARY
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• DSP operations
• Control operations
Table 24-1 shows the general symbols used in
describing the instructions.
The dsPIC33F instruction set summary in Ta b l e 2 4 - 2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write-back destination
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
Note: This data sheet summarizes the
features of the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices. However, it is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
latest family reference sections of the
“dsPIC33F/PIC24H Family Reference
Manual”, which are available from the
Microchip web site (www.microchip.com).
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 268 2011-2012 Microchip Technology Inc.
Most instructions are a single word. Certain double-
word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles.
Note: For more details on the instruction set, refer
to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70157).
TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text Means literal defined by “text”
(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator write-back destination address register {W13, [W13]+ = 2}
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit5 5-bit unsigned literal {0...31}
lit8 8-bit unsigned literal {0...255}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14 14-bit unsigned literal {0...16384}
lit16 16-bit unsigned literal {0...65535}
lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None Field does not require an entry, can be blank
OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Slit16 16-bit signed literal {-32768...32767}
Slit6 6-bit signed literal {-16...16}
Wb Base W register {W0..W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor working register pair (direct addressing)
2011-2012 Microchip Technology Inc. DS70652E-page 269
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Wm*Wm Multiplicand and Multiplier working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn One of 16 working registers {W0..W15}
Wnd One of 16 destination working registers {W0..W15}
Wns One of 16 source working registers {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X data space prefetch address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd X data space prefetch destination register for DSP instructions {W4..W7}
Wy Y data space prefetch address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd Y data space prefetch destination register for DSP instructions {W4..W7}
TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 270 2011-2012 Microchip Technology Inc.
TABLE 24-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
1ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB
ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if greater than or equal 1 1 (2) None
BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None
BRA GT,Expr Branch if greater than 1 1 (2) None
BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None
BRA LE,Expr Branch if less than or equal 1 1 (2) None
BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None
BRA LT,Expr Branch if less than 1 1 (2) None
BRA LTU,Expr Branch if unsigned less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None
BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None
BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
7BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
8BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
2011-2012 Microchip Technology Inc. DS70652E-page 271
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
9BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1
(2 or 3)
None
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1
(2 or 3)
None
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1
(2 or 3)
None
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1
(2 or 3)
None
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call subroutine 2 2 None
CALL Wn Call indirect subroutine 1 2 None
15 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
17 COM COM f f = f 11 N,Z
COM f,WREG WREG = f 11 N,Z
COM Ws,Wd Wd = Ws 11 N,Z
18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1 1 C,DC,N,OV,Z
21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1
(2 or 3)
None
22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1
(2 or 3)
None
23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1
(2 or 3)
None
24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if 11
(2 or 3)
None
25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C
26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 272 2011-2012 Microchip Technology Inc.
29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV
30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None
DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None
32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
38 GOTO GOTO Expr Go to address 2 2 None
GOTO Wn Go to indirect 1 2 None
39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
41 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
43 LNK LNK #lit14 Link Frame Pointer 1 1 None
44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,
AWB
Multiply and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
46 MOV MOV f,Wn Move f to Wn 1 1 None
MOV f Move f to f 1 1 N,Z
MOV f,WREG Move f to WREG 1 1 None
MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 None
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
2011-2012 Microchip Technology Inc. DS70652E-page 273
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
48 MPY MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
49 MPY.N MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
(Multiply Wm by Wn) to Accumulator 1 1 None
50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1 1 None
MUL f W3:W2 = f * WREG 1 1 None
52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
NEG f f = f + 1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
53 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1 2 None
POP.S Pop Shadow Registers 1 1 All
55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
57 RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
59 RESET RESET Software device Reset 1 1 None
60 RETFIE RETFIE Return from interrupt 1 3 (2) None
61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None
62 RETURN RETURN Return from Subroutine 1 3 (2) None
63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 274 2011-2012 Microchip Technology Inc.
66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z
69 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB
71 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z
76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None
SWAP Wn Wn = byte swap Wn 1 1 None
77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None
78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
81 ULNK ULNK Unlink Frame Pointer 1 1 None
82 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
2011-2012 Microchip Technology Inc. DS70652E-page 275
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
25.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® Digital Signal
Controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
25.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 276 2011-2012 Microchip Technology Inc.
25.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of Digital Signal Con-
trollers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
25.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of
Digital Signal Controllers. These compilers provide
powerful integration capabilities, omniscient code
generation and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
25.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
25.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
2011-2012 Microchip Technology Inc. DS70652E-page 277
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
25.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
25.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
25.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip’s
most cost effective high-speed hardware debugger/pro-
grammer for Microchip Flash Digital Signal Controller
(DSC) and microcontroller (MCU) devices. It debugs
and programs PIC® Flash microcontrollers and dsPIC®
DSCs with the powerful, yet easy-to-use graphical user
interface of MPLAB Integrated Development
Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer’s PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB REAL ICE systems
(RJ-11).
25.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer’s PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the Reset line to
implement in-circuit debugging and In-Circuit Serial
Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 278 2011-2012 Microchip Technology Inc.
25.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
25.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
25.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2011-2012 Microchip Technology Inc. DS70652E-page 279
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
26.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 electrical
characteristics. Additional information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family are
listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this
specification, is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) .................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) ....................................... -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum output current sourced and sunk by any I/O pin excluding OSCO .........................................................15 mA
Maximum output current sourced and sunk by OSCO............................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of the device maximum power dissipation (see Table 26-2).
3: See the “Pin Diagrams” section for 5V tolerant pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 280 2011-2012 Microchip Technology Inc.
26.1 DC Characteristics
TABLE 26-1: OPERATING MIPS vs. VOLTAGE
Characteristic VDD Range
(in Volts)
Temp Range
(in °C)
Max MIPS
dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104
DC5 VBOR-3.6V(1)-40°C to +85°C 16
VBOR-3.6V(1)-40°C to +125°C 16
Note 1: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
TABLE 26-2: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ-40 — +125 °C
Operating Ambient Temperature Range TA-40 — +85 °C
Extended Temperature Devices
Operating Junction Temperature Range TJ-40 — +140 °C
Operating Ambient Temperature Range TA-40 — +125 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH) PDPINT + PIO W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 18-pin PDIP JA 50 — °C/W 1
Package Thermal Resistance, 20-pin PDIP JA 50 — °C/W 1
Package Thermal Resistance, 28-pin SPDIP JA 50 — °C/W 1
Package Thermal Resistance, 18-pin SOIC JA 63 — °C/W 1
Package Thermal Resistance, 20-pin SOIC JA 63 — °C/W 1
Package Thermal Resistance, 28-pin SOIC JA 55 — °C/W 1
Package Thermal Resistance, 20-pin SSOP JA 90 — °C/W 1
Package Thermal Resistance, 28-pin SSOP JA 71 — °C/W 1
Package Thermal Resistance, 28-pin QFN (6x6 mm) JA 37 — °C/W 1
Package Thermal Resistance, 36-pin VTLA (5x5 mm) JA 31.1 — °C/W 1
Package Thermal Resistance, 44-pin TQFP JA 45 — °C/W 1, 2
Package Thermal Resistance, 44-pin QFN JA 32 — °C/W 1, 2
Package Thermal Resistance, 44-pin VTLA JA 30 — °C/W 1, 2
Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.
2: This package is available in dsPIC33FJ32(GP/MC)104 devices only.
2011-2012 Microchip Technology Inc. DS70652E-page 281
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
Operating Voltage
DC10 Supply Voltage(3)
VDD —VBOR — 3.6 V Industrial and Extended
DC12 VDR RAM Data Retention Voltage(2)1.8 — — V
DC16 VPOR VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—1.75VSS V
DC17 SVDD VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.024 — — V/ms 0-2.4V in 0.1s
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: This is the limit to which VDD may be lowered without losing RAM data.
3: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
TABLE 26-5: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1)Typ Max Units Conditions
BO10 VBOR BOR Event on VDD Transition
High-to-Low
2.40 2.48 2.55 V See Note 2
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 282 2011-2012 Microchip Technology Inc.
TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Operating Current (IDD)(2) – dsPIC33FJ16(GP/MC)10X Devices
DC20d 0.7 1.7 mA -40°C
3.3V LPRC
(32.768 kHz)(3)
DC20a 0.7 1.7 mA +25°C
DC20b 1.0 1.7 mA +85°C
DC20c 1.3 1.7 mA +125°C
DC21d 1.9 2.6 mA -40°C
3.3V 1 MIPS(3)
DC21a 1.9 2.6 mA +25°C
DC21b 1.9 2.6 mA +85°C
DC21c 2.0 2.6 mA +125°C
DC22d 6.5 8.5 mA -40°C
3.3V 4 MIPS(3)
DC22a 6.5 8.5 mA +25°C
DC22b 6.5 8.5 mA +85°C
DC22c 6.5 8.5 mA +125°C
DC23d 12.2 16 mA -40°C
3.3V 10 MIPS(3)
DC23a 12.2 16 mA +25°C
DC23b 12.2 16 mA +85°C
DC23c 12.2 16 mA +125°C
DC24d 16 21 mA -40°C
3.3V 16 MIPS
DC24a 16 21 mA +25°C
DC24b 16 21 mA +85°C
DC24c 16 21 mA +125°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
• CPU executing while(1) statement
3: These parameters are characterized, but not tested in manufacturing.
2011-2012 Microchip Technology Inc. DS70652E-page 283
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Operating Current (IDD)(2) – dsPIC33FJ32(GP/MC)10X Devices
DC20d 1 2 mA -40°C
3.3V LPRC
(32.768 kHz)(3)
DC20a 1 2 mA +25°C
DC20b 1.1 2 mA +85°C
DC20c 1.3 2 mA +125°C
DC21d 1.7 3 mA -40°C
3.3V 1 MIPS(3)
DC21a 2.3 mA +25°C3
DC21b 2.3 3 mA +85°C
DC21c 2.4 3 mA +125°C
DC22d 7 8.5 mA -40°C
3.3V 4 MIPS(3)
DC22a 7 8.5 mA +25°C
DC22b 7 mA +85°C8.5
8.5DC22c 7 mA +125°C
DC23d 13.2 17 mA -40°C
3.3V 10 MIPS(3)
DC23a 13.2 17 mA +25°C
DC23b 13.2 17 mA +85°C
DC23c 13.2 17 mA +125°C
DC24d 17 22 mA -40°C
3.3V 16 MIPS
DC24a 17 mA +25°C22
DC24b 17 22 mA +85°C
DC24c 17 22 mA +125°C
TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
• CPU executing while(1) statement
3: These parameters are characterized, but not tested in manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 284 2011-2012 Microchip Technology Inc.
TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Idle Current (IIDLE): Core OFF, Clock ON Base Current(2) – dsPIC33FJ16(GP/MC)10X Devices
DC40d 0.4 1.0 mA -40°C
3.3V
LPRC
(32.768 kHz)(3)
DC40a 0.4 1.0 mA +25°C
DC40b 0.4 1.0 mA +85°C
DC40c 0.5 1.0 mA +125°C
DC41d 0.5 1.1 mA -40°C
3.3V 1 MIPS(3)
DC41a 0.5 1.1 mA +25°C
DC41b 0.5 1.1 mA +85°C
DC41c 0.8 1.1 mA +125°C
DC42d 0.9 1.6 mA -40°C
3.3V 4 MIPS(3)
DC42a 0.9 1.6 mA +25°C
DC42b 1.0 1.6 mA +85°C
DC42c 1.2 1.6 mA +125°C
DC43a 1.6 2.6 mA +25°C
3.3V 10 MIPS(3)
2.6DC43d 1.6 mA -40°C
DC43b 1.7 2.6 mA +85°C
DC43c 2 2.6 mA +125°C
DC44d 2.4 3.8 mA -40°C
3.3V 16 MIPS(3)
DC44a 2.4 3.8 mA +25°C
DC44b 2.6 3.8 mA +85°C
DC44c 2.9 3.8 mA +125°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: Base Idle current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as
digital I/O inputs)
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
3: These parameters are characterized, but not tested in manufacturing.
2011-2012 Microchip Technology Inc. DS70652E-page 285
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Idle Current (IIDLE): Core OFF, Clock ON Base Current(2) – dsPIC33FJ32(GP/MC)10X Devices
DC40d 0.4 1.0 mA -40°C
3.3V
LPRC
(32.768 kHz)(3)
DC40a 0.4 1.0 mA +25°C
DC40b 0.4 1.0 mA +85°C
DC40c 0.5 1.0 mA +125°C
DC41d 0.5 1.1 mA -40°C
3.3V 1 MIPS(3)
DC41a 0.5 1.1 mA +25°C
DC41b 0.5 1.1 mA +85°C
DC41c 0.8 1.1 mA +125°C
DC42d 0.9 1.6 mA -40°C
3.3V 4 MIPS(3)
DC42a 0.9 1.6 mA +25°C
DC42b 1.0 1.6 mA +85°C
DC42c 1.2 1.6 mA +125°C
DC43a 1.6 2.6 mA +25°C
3.3V 10 MIPS(3)
1.6 2.6DC43d mA -40°C
DC43b 1.7 2.6 mA +85°C
DC43c 2.0 2.6 mA +125°C
DC44d 2.4 3.8 mA -40°C
3.3V 16 MIPS(3)
DC44a 2.4 3.8 mA +25°C
DC44b 2.6 3.8 mA +85°C
DC44c 2.9 3.8 mA +125°C
TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: Base Idle current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as
digital I/O inputs)
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
3: These parameters are characterized, but not tested in manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 286 2011-2012 Microchip Technology Inc.
TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Power-Down Current (IPD)(2) – dsPIC33FJ16(GP/MC)10X Devices
DC60d 27 250 µA -40°C
3.3V Base Power-Down Current(3,4)
DC60a 32 250 µA +25°C
DC60b 43 250 µA +85°C
DC60c 150 500 µA +125°C
DC61d 420 600 µA -40°C
3.3V Watchdog Timer Current: IWDT(3,5)
DC61a 420 600 µA +25°C
DC61b 530 750 µA +85°C
DC61c 620 900 µA +125°C
Power-Down Current (IPD)(2) – dsPIC33FJ32(GP/MC)10X Devices
DC60d 27 250 µA -40°C
3.3V Base Power-Down Current(3,4)
DC60a 32 250 µA +25°C
DC60b 43 250 µA +85°C
DC60c 150 500 µA +125°C
DC61d 420 600 µA -40°C
3.3V Watchdog Timer Current: IWDT(3,5)
DC61a 420 600 µA +25°C
DC61b 530 750 µA +85°C
DC61c 620 900 µA +125°C
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
2: IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as
digital I/O inputs)
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (PMDx bits are all ones)
• VREGS bit (RCON<8>) = 1 (i.e., core regulator is set to stand-by while the device is in Sleep mode)
• On applicable devices, RTCC is disabled, plus the VREGS bit (RCON<8>) = 1
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: These currents are measured on the device containing the most memory in this family.
5: These parameters are characterized, but not tested in manufacturing.
2011-2012 Microchip Technology Inc. DS70652E-page 287
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-9: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No. Typical(1)Max Doze
Ratio(2)Units Conditions
Doze Current (IDOZE)(2) – dsPIC33FJ16(GP/MC)10X Devices
DC73a 13.2 17.2 1:2 mA
-40°C 3.3V 16 MIPSDC73f 4.7 6.2 1:64 mA
DC73g 4.7 6.2 1:128 mA
DC70a 13.2 17.2 1:2 mA
+25°C 3.3V 16 MIPSDC70f 4.7 6.2 1:64 mA
DC70g 4.7 6.2 1:128 mA
DC71a 13.2 17.2 1:2 mA
+85°C 3.3V 16 MIPSDC71f 4.7 6.2 1:64 mA
DC71g 4.7 6.2 1:128 mA
DC72a 13.2 17.2 1:2 mA
+125°C 3.3V 16 MIPSDC72f 4.7 6.2 1:64 mA
DC72g 4.7 6.2 1:128 mA
Doze Current (IDOZE)(2) – dsPIC33FJ32(GP/MC)10X Devices
DC73a 13.2 17.2 1:2 mA
-40°C 3.3V 16 MIPSDC73f 4.7 6.2 1:64 mA
DC73g 4.7 6.2 1:128 mA
DC70a 13.2 17.2 1:2 mA
+25°C 3.3V 16 MIPSDC70f 4.7 6.2 1:64 mA
DC70g 4.7 6.2 1:128 mA
DC71a 13.2 17.2 1:2 mA
+85°C 3.3V 16 MIPSDC71f 4.7 6.2 1:64 mA
DC71g 4.7 6.2 1:128 mA
DC72a 13.2 17.2 1:2 mA
+125°C 3.3V 16 MIPSDC72f 4.7 6.2 1:64 mA
DC72g 4.7 6.2 1:128 mA
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
2: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroes)
• CPU executing while(1) statement
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 288 2011-2012 Microchip Technology Inc.
TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
VIL Input Low Voltage
DI10 I/O Pins VSS —0.2VDD V
DI15 MCLR VSS —0.2VDD V
DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled
DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled
VIH Input High Voltage
DI20 I/O Pins Not 5V Tolerant(4)
I/O Pins 5V Tolerant(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
DI28 SDAx, SCLx 0.7 VDD — 5.5 V SMBus disabled
DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled
ICNPU CNx Pull-up Current
DI30 50 250 450 AVDD = 3.3V, VPIN = VSS
IIL Input Leakage Current(2,3)
DI50 I/O Pins 5V Tolerant(4)——±2AVSS VPIN VDD,
Pin at high-impedance
DI51 I/O Pins Not 5V Tolerant(4)——±1AVSS VPIN VDD,
Pin at high-impedance,
-40°C TA +85°C
DI51a I/O Pins Not 5V Tolerant(4)——±2A Shared with external
reference pins,
-40°C TA +85°C
DI51b I/O Pins Not 5V Tolerant(4)——±3.5AVSS VPIN VDD,
Pin at high-impedance,
-40°C TA +125°C
DI51c I/O Pins Not 5V Tolerant(4)——±8A Analog pins shared with
external
reference pins,
-40°C TA +125°C
DI55 MCLR ——±2AVSS VPIN VDD
DI56 OSC1 — — ±2 AVSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for the 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins, VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2011-2012 Microchip Technology Inc. DS70652E-page 289
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
IICL Input Low Injection Current
DI60a 0 -5(5,8)— mA All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, SOSCI, SOSCO
and RB14
IICH Input High Injection Current
DI60b 0 +5(6,7,8)— mA All pins except VDD,
VSS, AVDD, AVSS,
MCLR, VCAP, SOSCI,
SOSCO, RB14 and
digital 5V-tolerant
designated pins
IICT Total Input Injection Current
(sum of all I/O and control
pins)
DI60c -20(9)+20(9)— mA Absolute instantaneous
sum of all ± input
injection currents from
all I/O pins,
(| I
ICL + | IICH |) IICT
TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for the 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins, VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 290 2011-2012 Microchip Technology Inc.
TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA+125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
DO10 VOL
Output Low Voltage
I/O Pins:
4x Sink Driver Pins – All pins
excluding OSCO
——0.4V
IOL 6 mA, VDD = 3.3V
See Note 1
Output Low Voltage
I/O Pins:
8x Sink Driver Pins – OSCO
——0.4V
IOL 10 mA, VDD = 3.3V
See Note 1
DO20 VOH
Output High Voltage
I/O Pins:
4x Source Driver Pins – All
pins excluding OSCO
2.4 — — V IOL -6 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
8x Source Driver Pins – OSCO
2.4 — — V IOL -10 mA, VDD = 3.3V
See Note 1
DO20A VOH1
Output High Voltage
I/O Pins:
4x Source Driver Pins – All
pins excluding OSCO
1.5 — —
V
IOH -12 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -11 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -3 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
8x Source Driver Pins – OSCO
1.5 — —
V
IOH -16 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -12 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -4 mA, VDD = 3.3V
See Note 1
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2011-2012 Microchip Technology Inc. DS70652E-page 291
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(3)Min Typ(1)Max Units Conditions
Program Flash Memory
D130a EPCell Endurance 10,000 — — E/W -40C to +125C
D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating
voltage
D132B VPEW VDD for Self-Timed Write VMIN —3.6VVMIN = Minimum operating
voltage
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated
D135 IDDP Supply Current during
Programming
—10—mA
D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles,
TA = +85°C, See Note 2
D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles,
TA = +125°C, See Note 2
D138a TWW Word Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles,
TA = +85°C, See Note 2
D138b TWW Word Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles,
TA = +125°C, See Note 2
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 26-18) and the value of the FRC Oscillator
Tuning register (see Register 8-3). For complete details on calculating the Minimum and Maximum time,
see Section 5.3 “Programming Operations”.
3: These parameters are ensured by design, but are not characterized or tested in manufacturing.
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA+125°C for Extended
Param
No. Symbol Characteristics Min Typ Max Units Comments
—C
EFC External Filter Capacitor
Value(1)
4.7 10 — µF Capacitor must be low
series resistance
(< 5 ohms)
Note 1: Typical VCAP voltage = 2.5V when VDD VDDMIN.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 292 2011-2012 Microchip Technology Inc.
26.2 AC Characteristics and Timing
Parameters
This section defines dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 AC characteristics
and timing parameters.
TABLE 26-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 26-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 26-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 26.1 “DC
Characteristics”.
Param
No. Symbol Characteristic Min Typ Max Units Conditions
DO50 COSC2 OSC2/SOSC2 Pin — — 15 pF In MS and HS modes when external
clock is used to drive OSC1
DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode
DO58 CBSCLx, SDAx — — 400 pF In I2C™ mode
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
2011-2012 Microchip Technology Inc. DS70652E-page 293
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-2: EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4
OSC1
CLKO
Q1 Q2 Q3 Q4
OS20
OS25
OS30 OS30
OS40
OS41
OS31 OS31
TABLE 26-16: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symb Characteristic Min Typ(1)Max Units Conditions
OS10 FIN External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC — 32 MHz EC
Oscillator Crystal Frequency 3.0
10
31
—
—
—
10
32
33
MHz
MHz
kHz
MS
HS
SOSC
OS20 TOSC TOSC = 1/FOSC 31.25 — DC ns
OS25 TCY Instruction Cycle Time(2,4)62.5 — DC ns
OS30 TosL,
Tos H
External Clock in (OSC1)(5)
High or Low Time
0.45 x TOSC ——nsEC
OS31 TosR,
Tos F
External Clock in (OSC1)(5)
Rise or Fall Time
——20nsEC
OS40 TckR CLKO Rise Time(3,5) —610ns
OS41 TckF CLKO Fall Time(3,5)—610ns
OS42 GMExternal Oscillator
Transconductance(4)
14 16 18 mA/V VDD = 3.3V,
TA = +25ºC
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: These parameters are characterized by similarity, but are tested in manufacturing at FIN = 32 MHz only.
5: These parameters are characterized by similarity, but are not tested in manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 294 2011-2012 Microchip Technology Inc.
TABLE 26-17: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
OS50 FPLLI PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range(2)
3.0 — 8 MHz ECPLL and MSPLL
modes
OS51 FSYS On-Chip VCO System
Frequency(3)
12 — 32 MHz
OS52 TLOCK PLL Start-up Time (Lock Time)(3)—— 2mS
OS53 DCLK CLKO Stability (Jitter)(3)-2 1 +2 %
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: These parameters are characterized by similarity, but are tested in manufacturing at 7.7 MHz input only.
3: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. The effective jitter for individual time bases, or communi-
cation clocks used by the user application, are derived from dividing the CLKO stability specification by the
square root of “N” (where “N” is equal to FOSC, divided by the peripheral data rate clock). For example, if
FOSC = 32 MHz and the SPI bit rate is 5 MHz, the effective jitter of the SPI clock is equal to:
TABLE 26-18: AC CHARACTERISTICS: INTERNAL FAST RC (FRC) ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min Typ Max Units Conditions
Internal FRC Accuracy @ 7.3728 MHz(1)
F20a FRC -1.5 ±0.25 +1.5 % -40°C TA -10°C
F20b FRC -1 ±0.25 +1 % -10°C T
A +85°C
F20c FRC -2 ±0.25 +2 % +125°C
Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits may be used to compensate for temperature drift.
DCLK
32
5
------
--------------2%
2.53
---------- 0 . 7 9 %==
TABLE 26-19: INTERNAL LOW-POWER RC (LPRC) ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Characteristic Min Typ Max Units Conditions
LPRC @ 32.768 kHz(1,2)
F21a LPRC -20 ±10 +20 % -40°C TA +85°C
F21b LPRC -30 ±10 +30 % -40°C TA +125°C
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 23.4 “Watchdog
Timer (WDT)” for more information.
2011-2012 Microchip Technology Inc. DS70652E-page 295
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-3: CLKO AND I/O TIMING CHARACTERISTICS
Note: Refer to Figure 26-1 for load conditions.
I/O Pin
(Input)
I/O Pin
(Output)
DI35
Old Value New Value
DI40
DO31
DO32
TABLE 26-20: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(2)Min Typ(1)Max Units Conditions
DO31 TIOR Port Output Rise Time — 10 25 ns
DO32 TIOF Port Output Fall Time — 10 25 ns
DI35 TINP INTx Pin High or Low Time (input) 25 — — ns
DI40 TRBP CNx High or Low Time (input) 2 — — TCY
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: These parameters are characterized, but are not tested in manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 296 2011-2012 Microchip Technology Inc.
FIGURE 26-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY11
SY10
SY20
SY13
I/O Pins
SY13
Note: Refer to Figure 26-1 for load conditions.
FSCM
Delay
SY35
SY30
SY12
TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symb Characteristic(1)Min Typ(2)Max Units Conditions
SY10 TMCLMCLR Pulse Width (low) 2 — — s
SY11 TPWRT Power-up Timer Period — 64 — ms
SY12 TPOR Power-on Reset Delay 3 10 30 s
SY13 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
——1.2s
SY20 TWDT1 Watchdog Timer Time-out
Period
———msSee Section 23.4 “Watchdog
Timer (WDT)” and LPRC
Parameter F21a (Table 26-19).
SY30 TOST Oscillator Start-up Time — 1024 * TOSC ——TOSC = OSC1 period
SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 s
Note 1: These parameters are characterized but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2011-2012 Microchip Technology Inc. DS70652E-page 297
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS
Note: Refer to Figure 26-1 for load conditions.
Tx11
Tx15
Tx10
Tx20
TMRx
OS60
TxCK
TABLE 26-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(2)Min Typ Max Units Conditions
TA10 TTXH T1CK High
Time
Synchronous
mode
Greater of:
20 or
(T
CY + 20)/N
— — ns Must also meet
Parameter TA15,
N = prescaler
value (1, 8, 64,
256)
Asynchronous 35 — — ns
TA11 TTXL T1CK Low
Time
Synchronous
mode
Greater of:
20 ns or
(T
CY + 20)/N
— — ns Must also meet
Parameter TA15,
N = prescaler
value (1, 8, 64,
256)
Asynchronous 10 — — ns
TA15 TTXP T1CK Input
Period
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
— — ns N = prescale
value
(1, 8, 64, 256)
OS60 Ft1 SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
bit, TCS (T1CON<1>))
DC — 50 kHz
TA20 TCKEXTMRL Delay from External T1CK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 ns
Note 1: Timer1 is a Type A.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 298 2011-2012 Microchip Technology Inc.
TABLE 26-23: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
TB10 TtxH TxCK High
Time
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
— — ns Must also meet
Parameter TB15,
N = prescale
value
(1, 8, 64, 256)
TB11 TtxL TxCK Low
Time
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
— — ns Must also meet
Parameter TB15,
N = prescale
value
(1, 8, 64, 256)
TB15 TtxP TxCK Input
Period
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
— — ns N = prescale
value
(1, 8, 64, 256)
TB20 TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
TABLE 26-24: TIMER3/5 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
TC10 TtxH TxCK High
Time
Synchronous TCY + 20 — — ns Must also meet
Parameter TC15
TC11 TtxL TxCK Low
Time
Synchronous TCY + 20 — — ns Must also meet
Parameter TC15
TC15 TtxP TxCK Input
Period
Synchronous,
with prescaler
2 TCY + 40 — — ns N = prescale
value
(1, 8, 64, 256)
TC20 TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2011-2012 Microchip Technology Inc. DS70652E-page 299
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10 IC11
IC15
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-25: INPUT CAPTURE x (ICx) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Max Units Conditions
IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
IC15 TccP ICx Input Period (TCY + 40)/N — ns N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 300 2011-2012 Microchip Technology Inc.
FIGURE 26-7: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
FIGURE 26-8: OCx/PWM MODULE TIMING CHARACTERISTICS
OCx
OC11 OC10
(Output Compare
Note: Refer to Figure 26-1 for load conditions.
or PWM Mode)
TABLE 26-26: OUTPUT COMPARE x (OCx) MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32
OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
OCFA
OCx
OC20
OC15
Active Tri-State
TABLE 26-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
OC15 TFD Fault Input to PWM I/O
Change
——TCY + 20 ns ns
OC20 TFLT Fault Input Pulse Width TCY + 20 ns — — ns
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
2011-2012 Microchip Technology Inc. DS70652E-page 301
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-9: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS
FIGURE 26-10: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS
FLTA1
PWMx
MP30
MP20
See Note 1
Note 1: For the logic state after a Fault, refer to the FAOVxH:FAOVxL bits in the PxFLTACON register.
PWMx
MP11 MP10
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
MP10 TFPWM PWM Output Fall Time — — — ns See Parameter DO32
MP11 TRPWM PWM Output Rise Time — — — ns See Parameter DO31
MP20 TFD Fault Input to PWM
I/O Change
——50ns
MP30 TFH Minimum Pulse Width 50 — — ns
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 302 2011-2012 Microchip Technology Inc.
TABLE 26-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR dsPIC33FJ16(GP/MC)10X
FIGURE 26-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE CKP SMP
15 MHz Table 26-30 ——0,10,10,1
10 MHz — Table 26-31 —10,11
10 MHz — Table 26-32 —00,11
15 MHz — — Table 26-33 100
11 MHz — — Table 26-34 110
15 MHz — — Table 26-35 010
11 MHz — — Table 26-36 000
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
2011-2012 Microchip Technology Inc. DS70652E-page 303
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
TABLE 26-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
SP36
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 304 2011-2012 Microchip Technology Inc.
FIGURE 26-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
TABLE 26-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 10 MHz See Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— 6 20 ns
SP36 TdoV2sc,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
SP36
SP41
MSb In LSb In
Bit 14 - - - -1
SDIx
SP40
2011-2012 Microchip Technology Inc. DS70652E-page 305
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
TABLE 26-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 10 MHz -40ºC to +125ºC and
see Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP10
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
MSb In LSb In
Bit 14 - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 306 2011-2012 Microchip Technology Inc.
FIGURE 26-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP60
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 26-1 for load conditions.
SP50
SP35
2011-2012 Microchip Technology Inc. DS70652E-page 307
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
SP60 TssL2doV SDOx Data Output Valid after
SSx Edge
——50ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 308 2011-2012 Microchip Technology Inc.
FIGURE 26-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP60
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 26-1 for load conditions.
SP50
2011-2012 Microchip Technology Inc. DS70652E-page 309
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
SP60 TssL2doV SDOx Data Output Valid after
SSx Edge
——50ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 310 2011-2012 Microchip Technology Inc.
FIGURE 26-17: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SSX
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOX
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 26-1 for load conditions.
SDIXMSb In
2011-2012 Microchip Technology Inc. DS70652E-page 311
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 312 2011-2012 Microchip Technology Inc.
FIGURE 26-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SSX
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOX
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 26-1 for load conditions.
SDIXMSb In
2011-2012 Microchip Technology Inc. DS70652E-page 313
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 314 2011-2012 Microchip Technology Inc.
TABLE 26-37: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR dsPIC33FJ32(GP/MC)10X
FIGURE 26-19: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE CKP SMP
15 MHz Table 26-30 ——0,10,10,1
9 MHz — Table 26-31 —10,11
9 MHz — Table 26-32 —00,11
15 MHz — — Table 26-33 100
11 Mhz — — Table 26-34 110
15 MHz — — Table 26-35 010
11 MHz — — Table 26-36 000
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
2011-2012 Microchip Technology Inc. DS70652E-page 315
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-20: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
TABLE 26-38: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
SP36
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 316 2011-2012 Microchip Technology Inc.
FIGURE 26-21: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
TABLE 26-39: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 9 MHz See Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— 6 20 ns
SP36 TdoV2sc,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
SP36
SP41
LSb In
Bit 14 - - - -1
SDIx
SP40
MSb In
2011-2012 Microchip Technology Inc. DS70652E-page 317
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-22: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
TABLE 26-40: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 9 MHz -40ºC to +125ºC and
See Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP10
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
MSb In LSb In
Bit 14 - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 318 2011-2012 Microchip Technology Inc.
FIGURE 26-23: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP60
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 26-1 for load conditions.
SP50
2011-2012 Microchip Technology Inc. DS70652E-page 319
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-41: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
SP60 TssL2doV SDOx Data Output Valid after
SSx Edge
——50ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 320 2011-2012 Microchip Technology Inc.
FIGURE 26-24: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP60
SDIx
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 26-1 for load conditions.
SP50
2011-2012 Microchip Technology Inc. DS70652E-page 321
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-42: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
SP60 TssL2doV SDOx Data Output Valid after
SSx Edge
——50ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 322 2011-2012 Microchip Technology Inc.
FIGURE 26-25: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SSX
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOX
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 26-1 for load conditions.
SDIXMSb In
2011-2012 Microchip Technology Inc. DS70652E-page 323
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-43: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — —w ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 324 2011-2012 Microchip Technology Inc.
FIGURE 26-26: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SSX
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOX
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 26-1 for load conditions.
SDIXMSb In
2011-2012 Microchip Technology Inc. DS70652E-page 325
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-44: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance
10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 326 2011-2012 Microchip Technology Inc.
FIGURE 26-27: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
FIGURE 26-28: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
SCLx
SDAx
Start
Condition
Stop
Condition
IM30
Note: Refer to Figure 26-1 for load conditions.
IM31
IM33
IM34
IM11 IM10 IM33
IM11
IM10
IM20
IM26 IM25
IM40 IM40 IM45
IM21
SCLx
SDAx
In
SDAx
Out
Note: Refer to Figure 26-1 for load conditions.
2011-2012 Microchip Technology Inc. DS70652E-page 327
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-45: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1)Max Units Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM20 TF:SCL SDAx and SCLx
Fall Time
100 kHz mode — 300 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)— 100 ns
IM21 TR:SCL SDAx and SCLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)— 300 ns
IM25 TSU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(2)40 — ns
IM26 THD:DAT Data Input
Hold Time
100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode(2)0.2 — s
IM30 TSU:STA Start Condition
Setup Time
100 kHz mode TCY/2 (BRG + 1) — s Only relevant for
Repeated Start
condition
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM31 THD:STA Start Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1) — s After this period the first
clock pulse is generated
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM33 TSU:STO Stop Condition
Setup Time
100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns
Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns
1 MHz mode(2)TCY/2 (BRG + 1) — ns
IM40 TAA:SCL Output Valid
from Clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(2)— 400 ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode(2)0.5 — s
IM50 CBBus Capacitive Loading — 400 pF
IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)”
(DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site for the
latest “dsPIC33F/PIC24H Family Reference Manual” sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 328 2011-2012 Microchip Technology Inc.
FIGURE 26-29: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
FIGURE 26-30: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
SDAx
Start
Condition
Stop
Condition
IS34
IS33
IS31
IS30
IS30 IS31 IS33
IS11
IS10
IS20
IS26 IS25
IS40 IS40 IS45
IS21
SCLx
SDAx
In
SDAx
Out
2011-2012 Microchip Technology Inc. DS70652E-page 329
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-46: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic Min Max Units Conditions
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1)0.5 — s
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1)0.5 — s
IS20 TF:SCL SDAx and SCLx
Fall Time
100 kHz mode — 300 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)— 100 ns
IS21 TR:SCL SDAx and SCLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)— 300 ns
IS25 TSU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(1)100 — ns
IS26 THD:DAT Data Input
Hold Time
100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode(1)00.3s
IS30 TSU:STA Start Condition
Setup Time
100 kHz mode 4.7 — s Only relevant for Repeated
Start condition
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS31 THD:STA Start Condition
Hold Time
100 kHz mode 4.0 — s After this period, the first
clock pulse is generated
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS33 TSU:STO Stop Condition
Setup Time
100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
1 MHz mode(1)0.6 — s
IS34 THD:STO Stop Condition
Hold Time
100 kHz mode 4000 — ns
400 kHz mode 600 — ns
1 MHz mode(1)250 ns
IS40 TAA:SCL Output Valid
from Clock
100 kHz mode 0 3500 ns
400 kHz mode 0 1000 ns
1 MHz mode(1)0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
1 MHz mode(1)0.5 — s
IS50 CBBus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 330 2011-2012 Microchip Technology Inc.
TABLE 26-47: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V(6)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
Device Supply
AD01 AVDD Module VDD Supply(2,4)Greater of
VDD – 0.3
or 2.9
— Lesser of
VDD + 0.3
or 3.6
V
AD02 AVSS Module VSS Supply(2,5)VSS – 0.3 — VSS + 0.3 V
AD09 IAD Operating Current — 7.0 9.0 mA See Note 1
Analog Input
AD12 VINH Input Voltage Range
VINH(2)
VINL —AVDD V This voltage reflects S&H
Channels 0, 1, 2 and 3
(CH0-CH3), positive input
AD13 VINL Input Voltage Range
VINL(2)
AVSS —AVSS + 1V V This voltage reflects S&H
Channels 0, 1, 2 and 3
(CH0-CH3), negative input
AD17 RIN Recommended
Impedance of Analog
Voltage Source(3)
——200
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized, but are not tested in manufacturing.
3: These parameters are assured by design, but are not characterized or tested in manufacturing.
4: This pin may not be available on all devices; in which case, this pin will be connected to VDD internally.
See the “Pin Diagrams” section for availability.
5: This pin may not be available on all devices; in which case, this pin will be connected to VSS internally. See
the “Pin Diagrams” section for availability.
6: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
2011-2012 Microchip Technology Inc. DS70652E-page 331
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-48: 10-BIT ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V(4)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
10-Bit ADC Accuracy – Measurements with AVDD/AVSS(3)
AD20b Nr Resolution 10 Data Bits bits
AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = 0V, AVDD = 3.6V
AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23b GERR Gain Error 3 7 15 LSb VINL = AVSS = 0V, AVDD = 3.6V
AD24b EOFF Offset Error 1.5 3 7 LSb VINL = AVSS = 0V, AVDD = 3.6V
AD25b — Monotonicity — — — — Guaranteed(1)
Dynamic Performance (10-Bit Mode)(2)
AD30b THD Total Harmonic Distortion — — -64 dB
AD31b SINAD Signal to Noise and
Distortion
57 58.5 — dB
AD32b SFDR Spurious Free Dynamic
Range
72 — — dB
AD33b FNYQ Input Signal Bandwidth — — 550 kHz
AD34b ENOB Effective Number of Bits 9.16 9.4 — bits
Note 1: The Analog-to-Digital conversion result never decreases with an increase in the input voltage and has no
missing codes.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
3: These parameters are characterized, but are tested at 20 ksps only.
4: Overall functional device operation at VBOR < VDD < VDDMIN is guaranteed but not characterized. All
device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 332 2011-2012 Microchip Technology Inc.
FIGURE 26-31: ADC CONVERSION TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
FIGURE 26-32: ADC CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
TSAMP
Set SAMP
AD61
ADCLK
Instruction
SAMP
AD60
DONE
ADxIF
1 2 3 4 5 6 8 5 6 7
1– Software sets ADxCON. SAMP to start sampling.
2– Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)”
3– Software clears ADxCON. SAMP to start conversion.
4– Sampling ends, conversion sequence starts.
5– Convert bit 9.
8– One TAD for end of conversion.
AD50
7 8
6– Convert bit 8.
7– Convert bit 0.
Execution
(DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”.
Clear SAMP
AD55 AD55
– Convert bit 9.
1 2 3 4 5 6 4 5 6 8
1– Software sets ADxCON. ADON to start AD operation.
2– Sampling starts after discharge period. TSAMP is described in
3– Convert bit 9.
4– Convert bit 8.
5– Convert bit 0.
7 3
6– One TAD for end of conversion.
7– Begin conversion of next channel.
8– Sample for time specified by SAMC<4:0>.
ADCLK
Instruction Set ADON
Execution
SAMP
TSAMP
ADxIF
DONE
AD55 AD55 TSAMP AD55
AD50
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
in the “dsPIC33F/PIC24H Family Reference Manual”.
2011-2012 Microchip Technology Inc. DS70652E-page 333
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-49: 10-BIT ADC CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ(1)Max. Units Conditions
Clock Parameters(2)
AD50 TAD ADC Clock Period 76 — — ns
AD51 tRC ADC Internal RC Oscillator Period — 250 — ns
Conversion Rates
AD55 tCONV Conversion Time — 12 TAD ——
AD56 FCNV Throughput Rate — — 1.1 Msps
AD57 TSAMP Sample Time 2.0 TAD ———
Timing Parameters
AD60 tPCS Conversion Start from Sample
Trigger(1)
2.0 TAD — 3.0 TAD — Auto-Convert Trigger
(SSRC<2:0> = 111) not
selected
AD61 tPSS Sample Start from Setting
Sample (SAMP) bit(1)
2.0 TAD — 3.0 TAD —
AD62 tCSS Conversion Completion to
Sample Start (ASAM = 1)(1)
— 0.5 TAD ——
AD63 tDPU Time to Stabilize Analog Stage
from ADC Off to ADC On(1)
——20s
Note 1: These parameters are characterized but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 334 2011-2012 Microchip Technology Inc.
TABLE 26-50: COMPARATOR TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
300 TRESP Response Time(1,2)— 150 400 ns
301 TMC2OV Comparator Mode Change
to Output Valid(1)
——10s
302 TON2OV Comparator Enabled to
Output Valid(1)
——10µs
Note 1: Parameters are characterized but not tested.
2: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 26-51: COMPARATOR MODULE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
D300 VIOFF Input Offset Voltage(1)-20 ±10 20 mV
D301 VICM Input Common-Mode Voltage(1)0—AVDD – 1.5V V
D302 CMRR Common-Mode Rejection Ratio(1)-54 — — dB
D305 IVREF Internal Voltage Reference(1)1.116 1.24 1.364 V
Note 1: Parameters are characterized but not tested.
TABLE 26-52: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
VR310 TSET Settling Time(1)——10s
Note 1: Setting time measured while CVRR = 1 and the CVR<3:0> bits transition from ‘0000’ to ‘1111’.
2011-2012 Microchip Technology Inc. DS70652E-page 335
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-53: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions:3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb
VRD311 CVRAA Absolute Accuracy — — 0.5 LSb
VRD312 CVRUR Unit Resistor Value (R) — 2k —
TABLE 26-54: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions:3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
CTMU Current Source
CTMUI1 IOUT1 Base Range(1)320 550 980 na IRNG<1:0> bits (CTMUICON<9:8>) = 0b01
CTMUI2 IOUT2 10x Range(1)3.2 5.5 9.8 µA IRNG<1:0> bits (CTMUICON<9:8>) = 0b10
CTMUI3 IOUT3 100x Range(1)32 55 98 µA IRNG<1:0> bits (CTMUICON<9:8>) = 0b11
Internal Diode
CTMUFV1 VFForward Voltage(2)— 0.77 — V IRNG<1:0> bits (CTMUICON<9:8>) = 0b11
@ +25ºC
CTMUFV2 VFVR Forward Voltage
Rate(2)
— -1.38 — mV/ºC IRNG<1:0> bits (CTMUICON<9:8>) = 0b11
Note 1: Nominal value at center point of current trim range (ITRIM<5:0> bits (CTMUICON<15:10>) = 0b000000).
2: ADC module configured for conversion speed of 500 ksps. Parameters are characterized but not tested in
manufacturing.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 336 2011-2012 Microchip Technology Inc.
FIGURE 26-33: FORWARD VOLTAGE VERSUS TEMPERATURE
0.700
0.750
0.800
0.850
Forward Voltage @ +25ºC
VF= 0.77
Forward Voltage Rate
VFVR = -1.38 mV/ºC
0.500
0.550
0.600
0.650
0.700
0.750
0.800
0.850
0.900
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
Forward Voltage (V)
Temperature (ºC)
VF @ IOUT = 55 µA
Note: This graph is a statistical summary based on a limited number of samples and this data is characterized but not
tested in manufacturing.
2011-2012 Microchip Technology Inc. DS70652E-page 337
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
3
e
3
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20-Lead PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ16MC
1230235
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ16
MC101-I/SS
1230235
101-E/P
20-Lead SOIC
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ16
MC101-I/SO
1210017
18-Lead PDIP
XXXXXXXXXXXXXXXXX
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YYWWNNN
Example
dsPIC33FJ16GP
1230235
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18-Lead SOIC
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Example
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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 338 2011-2012 Microchip Technology Inc.
27.1 Package Marking Information (Continued)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
3
e
3
e
Example
33FJ16MC
102-EML
1230235
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
33FJ16MC
102-E/SS
1230235
36-Lead VTLA
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
33FJ16MC
102-ETL
1230235
28-Lead SPDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ16MC
1230235
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ16MC
1230235
102-E/SP
102-E/SO
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
3
e
3
e
3
e
3
e
3
e
2011-2012 Microchip Technology Inc. DS70652E-page 339
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
27.1 Package Marking Information (Continued)
44-Lead VTLA
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
33FJ32MC
104-ETL
1230235
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC33FJ
Example
32MC104
1230235
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ
32MC104
1230235
-E/PT
3
e
3
e
3
e
-E/ML
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 340 2011-2012 Microchip Technology Inc.
27.2 Package Details
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2011-2012 Microchip Technology Inc. DS70652E-page 341
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 342 2011-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc. DS70652E-page 343
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 344 2011-2012 Microchip Technology Inc.
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2011-2012 Microchip Technology Inc. DS70652E-page 345
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 346 2011-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc. DS70652E-page 347
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 348 2011-2012 Microchip Technology Inc.
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2011-2012 Microchip Technology Inc. DS70652E-page 349
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 350 2011-2012 Microchip Technology Inc.
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e .100 BSC
Top to Seating Plane A – – .200
Molded Package Thickness A2 .120 .135 .150
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .335
Molded Package Width E1 .240 .285 .295
Overall Length D 1.345 1.365 1.400
Tip to Seating Plane L .110 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .050 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
NOTE 1
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Microchip Technology Drawing C04-070B
2011-2012 Microchip Technology Inc. DS70652E-page 351
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 352 2011-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc. DS70652E-page 353
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 354 2011-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc. DS70652E-page 355
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 356 2011-2012 Microchip Technology Inc.
2011-2012 Microchip Technology Inc. DS70652E-page 357
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 358 2011-2012 Microchip Technology Inc.
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2011-2012 Microchip Technology Inc. DS70652E-page 359
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 360 2011-2012 Microchip Technology Inc.
2011-2012 Microchip Technology Inc. DS70652E-page 361
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 364 2011-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc. DS70652E-page 365
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 366 2011-2012 Microchip Technology Inc.
2011-2012 Microchip Technology Inc. DS70652E-page 367
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
APPENDIX A: REVISION HISTORY
Revision A (January 2011)
This is the initial released version of the document.
Revision B (February 2011)
All major changes are referenced by their respective
section in Tab le A - 1 .
In addition, minor text and formatting changes were
incorporated throughout the document.
TABLE A-1: MAJOR SECTION UPDATES
Section Name Update Description
High-Performance, Ultra Low Cost 16-bit
Digital Signal Controllers
Pin diagram updates (see “Pin Diagrams”):
• 20-pin PDIP/SOIC/SSOP (dsPIC33FJ16MC101):
Removed the FLTB1 pin from pin 10
• 28-pin SPDIP/SOIC/SSOP (dsPIC33FJ16MC102):
Relocated the FLTB1 pin from pin 12 to pin 14;
relocated the FLTA1 pin from pin 16 to pin 15
• 28-pin QFN (dsPIC33FJ16MC102):
Relocated the FLTA1 pin from pin 13 to pin 12;
relocated the FLTB1 pin from pin 9 to pin 11
• 36-pin TLA (dsPIC33FJ16MC102):
Relocated the FLTA1 pin from pin 17 to pin 16;
relocated the FLTB1 pin from pin 10 to pin 15
Section 1.0 “Device Overview” Added Notes 1, 2, and 3 regarding the FLTA1 and FLTB1 pins to the
Pinout I/O Descriptions (see Table 1-1).
Added Section “”.
Section 4.0 “Memory Organization” Updated All Resets value for PxFLTACON and PxFLTABCON to the
6-Output PWM1 Register Map (see Table 4-9).
Added Note 1 to the PMD Register Map (see Table 4-29).
Section 6.0 “Resets” Removed Reset timing sequence information from Section 6.2
“System Reset”, as this information is provided in Figure 6-2.
Section 15.0 “Motor Control PWM Module” Added Note 2 and Note 3 regarding the FLTA1 and FLTB1 pins to the
6-channel PWM Module Block Diagram (see Figure 15-1).
Added Section 15.2 “PWM Faults” and Section 15.3 “Write-
protected Registers”.
Added Note 2 and Note 3 regarding the FLTA1 and FLTB1 pins to the
note boxes located below the PxFLTACON and PxFLTBCON
registers (see Register 15-9 and Register 15-10).
Section 17.0 “Inter-Integrated Circuit™
(I2C™)”
Updated the descriptions for the conditional If STREN = 1 and If
STREN = 0 statements for the SCLREL bit in the I2Cx Control
Register (see Register 17-1).
Section 23.0 “Special Features” Added the RTSP Effect column to the dsPIC33F Configuration Bits
Description (see Table 23-3).
Section 26.0 “Electrical Characteristics” Added Parameters 300 and D305 (see Table 26-42 and Table 26-43).
Section 27.0 “Packaging Information” Modified the pending TLA packaging page.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 368 2011-2012 Microchip Technology Inc.
Revision C (June 2011)
This revision includes the following global update:
• All JTAG references have been removed
All other major changes are referenced by their
respective section in Tabl e A- 2 .
In addition, minor text and formatting changes were
incorporated throughout the document.
TABLE A-2: MAJOR SECTION UPDATES
Section Name Update Description
High-Performance, Ultra Low Cost
16-bit Digital Signal Controllers
The TMS, TDI, TDO, and TCK pin names were removed from these pin
diagrams:
• 28-pin SPDIP/SOIC/SSOP
• 28-pin QFN
• 36-pin TLA
Section 1.0 “Device Overview” Updated the Buffer Type to Digital for the CTED1 and CTED2 pins (see
Table 1-1).
Section 4.0 “Memory Organization” Updated the SFR Address for IC2CON, IC3BUF, and IC3CON in the Input
Capture Register Map (see Table 4-7).
Added the VREGS bit to the RCON register in the System Control Register
Map (see Table 4-27).
Section 6.0 “Resets” Added the VREGS bit to the RCON register (see Register 6-1).
Section 8.0 “Oscillator Configuration” Updated the definition for COSC<2:0> = 001 and NOSC<2:0> = 001 in
the OSCCON register (see Register 8-1).
Section 15.0 “Motor Control PWM
Module”
Updated the title for Example 15-1 to include a reference to the Assembly
language.
Added Example 15-2, which provides a C code version of the write-
protected register unlock and Fault clearing sequence.
Section 19.0 “10-bit Analog-to-Digital
Converter (ADC)”
Updated the CH0 section and added Note 2 in both ADC block diagrams
(see Figure 19-1 and Figure 19-2).
Updated the multiplexer values in the ADC Conversion Clock Period Block
Diagram (see Figure 19-3.
Added the 01110 bit definitions and updated the 01101 bit definitions for
the CH0SB<4:0> and CH0SA<4:0> bits in the AD1CHS0 register (see
Register 19-5).
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Removed Section 22.1 “Measuring Capacitance”, Section 22.2 “Measuring
Time”, and Section 22.3 “Pulse Generation and Delay”
Updated the key features.
Added the CTMU Block Diagram (see Figure 22-1).
Updated the ITRIM<5:0> bit definitions and added Note 1 to the CTMU
Current Control register (see Register 22-3).
2011-2012 Microchip Technology Inc. DS70652E-page 369
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Section 23.0 “Special Features” Updated bits 5 and 4 of FPOR, modified Note 2, and removed Note 3 from
the Configuration Shadow Register Map (see Table 23-1).
Updated bit 14 of CONFIG1 and removed Note 5 from the Configuration
Flash Words (see Table 23-2).
Updated the PLLKEN Configuration bit description (see Table 23-3).
Added Note 3 to Connections for the On-Chip Voltage Regulator (see
Figure 23-1).
Section 26.0 “Electrical
Characteristics”
Updated the Standard Operating Conditions to: 3.0V to 3.6V in all tables.
Removed the Voltage on VCAP with respect to VSS entry in Absolute
Maximum Ratings(1).
Updated the VDD Range (in Volts) in Operating MIPS vs. Voltage (see
Table 26-1).
Removed Parameter DC18 and updated the minimum value for
Parameter DC 10 in the DC Temperature and Voltage Specifications (see
Table 26-4).
Updated the Characteristic definition and the Typical value for
Parameter BO10 in Electrical Characteristics: BOR (see Table 26-5).
Updated Note 2 in the DC Characteristics: Operating Current (IDD) (see
Table 26-6).
Updated Note 2 in the DC Characteristics: Idle Current (IIDLE) (see
Table 26-7).
Updated Note 2 and Parameters DC60C and DC61a-DC61d in the DC
Characteristics: Power-Down Current (IPD) (see Table 26-8).
Updated Note 2 in the DC Characteristics: Doze Current (IDOZE) (see
Table 26-9).
Added Note 1 to the Internal Voltage Regulator Specifications (see
Table 26-13).
Updated the Minimum and Maximum values for Parameter F20a and the
Typical value for Parameter F20b in AC Characteristics: Internal Fast RC
(FRC) Accuracy (see Table 26-18).
Updated the Minimum, Typical, and Maximum values for Parameter F21a
and F21b in Internal Low-Power RC (LPRC) Accuracy (see Table 26-19).
Updated the Minimum, Typical, and Maximum values for Parameter D305
in the Comparator Module Specifications (see Table 26-43).
Added Parameters CTMUFV1 and CTMUFV2 and updated Note 1 and the
Conditions for all parameters in the CTMU Current Source Specifications
(see Table 26-46).
Added Forward Voltage Versus Temperature (see Figure 26-25).
TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 370 2011-2012 Microchip Technology Inc.
Revision D (April 2012)
This revision includes updates in support of the
following new devices:
• dsPIC33FJ32GP101
• dsPIC33FJ32GP102
• dsPIC33FJ32GP104
• dsPIC33FJ32MC101
• dsPIC33FJ32MC102
• dsPIC33FJ32MC104
Also, where applicable, new sections were added to
peripheral chapters that provide information and links
to the related resources, as well as helpful tips. For
examples, see Section 18.1 “UART Helpful Tips”
and Section 18.2 “UART Resources”.
This revision includes text and formatting changes that
were incorporated throughout the document.
All other major changes are referenced by their
respective section in Table A-3.
TABLE A-3: MAJOR SECTION UPDATES
Section Name Update Description
“16-Bit Digital Signal
Controllers (up to 32-
Kbyte Flash and 2-Kbyte
SRAM)”
The content on the first page of this section was extensively reworked to provide the
reader with the key features and functionality of this device family in an “at-a-glance”
format.
TABLE 2: “dsPIC33FJ32(GP/MC)101/102/104 Device Features” was added, which
provides a feature overview of the new devices.
All pin diagrams were updated (see “Pin Diagrams”).
Section 1.0 “Device
Overview”
Updated the notes in the device family block diagram (see Figure 1-1).
Updated the following pinout I/O descriptions (Ta bl e 1- 1):
•ANx
• CNx
•RAx
• RCx
•C
VREFIN (formerly CVREF)
Relocated 1.1 “Referenced Sources” to the previous chapter (see “Referenced
Sources”).
Section 2.0 “Guidelines
for Getting Started with
16-bit Digital Signal
Controllers”
Updated the Recommended Minimum Connection diagram (see Figure 2-1).
Section 4.0 “Memory
Organization”
Updated the existing Program Memory Map (see Figure 4-1) and added the Program
Memory Map for dsPIC33FJ16(GP/MC)101/102 Devices (see Figure 4-1).
Updated the existing Data Memory Map (see Figure 4-4) and added the Data Memory
Map for dsPIC33FJ32(GP/MC)101/102/104 Devices with 2-Kbyte RAM (see Figure 4-5).
The following Special Function Register maps were updated or added:
•TABLE 4-5: Change Notification Register Map for dsPIC33FJ32(GP/MC)104
Devices
•TABLE 4-6: Interrupt Controller Register Map
•TABLE 4-8: Timers Register Map for dsPIC33FJ32(GP/MC)10X Devices
•TABLE 4-15: ADC1 Register Map for dsPIC33FJXX(GP/MC)101 Devices
•TABLE 4-17: ADC1 Register Map for dsPIC33FJ32(GP/MC)104 Devices
•TABLE 4-22: Peripheral Pin Select Input Register Map
•TABLE 4-26: Peripheral Pin Select Output Register Map for dsPIC33FJ32(GP/
MC)104 Devices
•TABLE 4-28: PORTA Register Map for dsPIC33FJ32(GP/MC)101/102 Devices
•TABLE 4-29: PORTA Register Map for dsPIC33FJ32(GP/MC)104 Devices
•TABLE 4-36: PORTC Register Map for dsPIC33FJ32(GP/MC)104 Devices
•TABLE 4-39: PMD Register Map
2011-2012 Microchip Technology Inc. DS70652E-page 371
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Section 7.0 “Interrupt
Controller”
Updated the Interrupt Vectors (see Table 7-1).
The following registers were updated or added:
•Register 7-5: IFS0: Interrupt Flag Status Register 0
•Register 7-11: IEC1: Interrupt Enable Control Register 1
•Register 7-21: IPC6: Interrupt Priority Control Register 6
Section 9.0 “Power-
Saving Features”
Updated 9.5 PMD Control Registers.
Section 10.0 “I/O Ports” Updated TABLE 10-1: Selectable Input Sources (Maps Input to Function)(1).
Updated TABLE 10-2: Output Selection for Remappable Pin (RPn)
The following registers were updated or added:
•Register 10-4: RPINR4: Peripheral Pin Select Input Register 4
•Register 10-6: RPINR8: Peripheral Pin Select Input Register 8
•Register 10-19: RPOR8: Peripheral Pin Select Output Register 8
•Register 10-20: RPOR9: Peripheral Pin Select Output Register 9
•Register 10-21: RPOR10: Peripheral Pin Select Output Register 10
•Register 10-22: RPOR11: Peripheral Pin Select Output Register 11
•Register 10-23: RPOR12: Peripheral Pin Select Output Register 12
Section 12.0 “Timer2/3
and Timer4/5”
The features and operation information was extensively updated in support of Timer4/5
(see Section 12.1 “32-Bit Operation” and Section 12.2 “16-Bit Operation”).
The block diagrams were updated in support of the new timers (see Figure 12-1,
Figure 12-2, and Figure 12-3).
The following registers were added:
•Register 12-3: T4CON Control Register(1)
•Register 12-4: T5CON Control Register(1)
Section 15.0 “Motor
Control PWM Module”
Updated TABLE 15-1: Internal Pull-down resistors on PWM Fault pins.
Note 2 was added to Register 15-5: PWMXCON1: PWMx Control Register 1(1).
Section 19.0 “10-Bit
Analog-to-Digital
Converter (ADC)”
The number of available input pins and channels were updated from six to 14.
Updated FIGURE 19-1: ADC1 Block Diagram for dsPIC33FJXX(GP/MC)101 Devices.
Updated FIGURE 19-2: ADC1 Block Diagram for dsPIC33FJXX(GP/MC)102 Devices.
Added FIGURE 19-3: ADC1 Block Diagram for dsPIC33FJ32(GP/MC)104 Devices.
The following registers were updated:
•Register 19-4: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register
•Register 19-5: AD1CHS0: ADC1 INPUT Channel 0 select Register
•Register 19-6: AD1CSSL: ADC1 Input Scan Select Register Low(1,2,3)
•Register 19-7: AD1PCFGL: ADC1 Port Configuration Register Low(1,2,3)
TABLE A-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 372 2011-2012 Microchip Technology Inc.
Section 26.0 “Electrical
Characteristics”
Updated the Absolute Maximum Ratings.
Updated TABLE 26-3: Thermal Packaging Characteristics.
Updated TABLE 26-6: DC Characteristics: Operating Current (Idd).
Updated TABLE 26-7: DC Characteristics: Idle Current (Iidle).
Updated TABLE 26-8: DC Characteristics: Power-Down Current (Ipd).
Updated TABLE 26-9: DC Characteristics: Doze Current (Idoze).
Updated TABLE 26-10: DC Characteristics: I/O Pin Input Specifications.
Replaced all SPI specifications and figures (see Table 26-29 through Table 26-44 and
Figure 26-11 through Figure 26-26).
Section 27.0 “Packaging
Information”
Added the following Package Marking Information and Package Drawings:
• 44-Lead TQFP
• 44-Lead QFN
• 44-Lead VTLA (referred to as TLA in the package drawings)
TABLE A-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
2011-2012 Microchip Technology Inc. DS70652E-page 373
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Revision E (September 2012)
This revision includes updates to the values in
Section 26.0 “Electrical Characteristics” and
updated packaging diagrams in Section 27.0
“Packaging Information”. There are minor text edits
throughout the document.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 374 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 375
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
INDEX
A
Absolute Maximum Ratings .............................................. 279
AC Characteristics ............................................................ 292
10-Bit ADC Specifications......................................... 331
ADC Specifications ................................................... 330
Internal Fast RC (FRC) Accuracy ............................. 294
Internal Low-Power RC (LPRC) Accuracy ................ 294
Load Conditions ........................................................ 292
Temperature and Voltage Specifications .................. 292
ADC
Control Registers ...................................................... 220
Helpful Tips ............................................................... 219
Initialization ............................................................... 215
Key Features............................................................. 215
Resources................................................................. 219
Alternate Interrupt Vector Table (AIVT) .............................. 95
Analog-to-Digital Converter (ADC).................................... 215
Arithmetic Logic Unit (ALU)................................................. 43
Assembler
MPASM Assembler................................................... 276
B
Bit-Reversed Addressing .................................................... 77
Example ...................................................................... 78
Implementation ........................................................... 77
Sequence Table (16-Entry)......................................... 78
Block Diagrams
16-Bit Timer1 Module................................................ 163
6-Channel PWM Module (PWM1)............................. 180
ADC Conversion Clock Period.................................. 219
ADC1 for dsPIC33FJ32(GP/MC)104 Devices .......... 218
ADC1 for dsPIC33FJXX(GP/MC)101 Devices.......... 216
ADC1 for dsPIC33FJXX(GP/MC)102 Devices.......... 217
Comparator I/O Operating Modes............................. 229
Comparator Voltage Reference ................................ 230
Connections for On-Chip Voltage Regulator............. 264
CTMU Module........................................................... 254
Digital Filter Interconnect .......................................... 231
DSP Engine ................................................................ 44
dsPIC33FJXX(GP/MC)10X......................................... 28
dsPIC33FJXX(GP/MC)10X CPU Core ....................... 38
I2C Module ................................................................ 202
Input Capture ............................................................ 173
Multiplexing of Remappable Output for RPn............. 143
Oscillator System ...................................................... 125
Output Compare Module........................................... 175
Real-Time Clock and Calendar (RTCC) Module....... 241
Remappable MUX Input for U1RX............................ 142
Reset System.............................................................. 87
Shared Port Structure ............................................... 140
SPIx Module.............................................................. 195
Timer2 and Timer4 (16-Bit)....................................... 167
Timer2/3 and Timer4/5 (32-Bit)................................. 166
Timer3 and Timer5 (16-Bit)....................................... 167
UART Simplified........................................................ 209
User-Programmable Blanking Function .................... 230
Watchdog Timer (WDT) ............................................ 265
Brown-out Reset (BOR) .................................................... 264
C
C Compilers
MPLAB C18.............................................................. 276
Charge Time Measurement Unit. See CTMU.
Clock Switching ................................................................ 132
Enabling.................................................................... 132
Sequence ................................................................. 132
Code Examples
Assembly Code for Write-Protected Register
Unlock, Fault Clearing Sequence ..................... 182
C Code for Write-Protected Register Unlock,
Fault Clearing Sequence .................................. 182
Port Write/Read ........................................................ 141
PWRSAV Instruction Syntax .................................... 133
Setting the RTCWREN Bit........................................ 242
Comparator....................................................................... 229
Control Registers...................................................... 232
Configuration Bits ............................................................. 259
CPU
Barrel Shifter............................................................... 47
Control Registers........................................................ 40
CPU Clocking System ...................................................... 126
Clock Selection......................................................... 126
Clock Sources .......................................................... 126
Configuration Bit Values for Clock Selection ............ 127
PLL Configuration..................................................... 127
CTMU
Control Registers...................................................... 255
Customer Change Notification Service............................. 380
Customer Notification Service .......................................... 380
Customer Support............................................................. 380
D
Data Accumulators and Adder/Subtracter .......................... 45
Data Space Write Saturation ...................................... 47
Overflow and Saturation ............................................. 45
Round Logic ............................................................... 46
Write Back .................................................................. 46
Data Address Space........................................................... 52
Alignment.................................................................... 52
Memory Map for dsPIC33FJ16(GP/MC)101/102
Devices with 1-Kbyte RAM .................................... 53
Memory Map for dsPIC33FJ32(GP/MC)101/102/104
Devices with 1-Kbyte RAM .................................... 54
Near Data Space ........................................................ 52
Software Stack ........................................................... 73
Width .......................................................................... 52
DC Characteristics............................................................ 280
Brown-out Reset (BOR)............................................ 281
Doze Current (IDOZE)................................................ 287
I/O Pin Input Specifications ...................................... 288
I/O Pin Output Specifications.................................... 290
Idle Current (IIDLE) .................................................... 284
Operating Current (IDD) ............................................ 282
Operating MIPS vs. Voltage ..................................... 280
Power-Down Current (IPD)........................................ 286
Program Memory...................................................... 291
Temperature and Voltage Specifications.................. 281
Thermal Operating Conditions.................................. 280
Thermal Packaging................................................... 280
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 376 2011-2012 Microchip Technology Inc.
Development Support ....................................................... 275
Doze Mode........................................................................ 134
DSP Engine......................................................................... 43
Multiplier...................................................................... 45
dsPIC33FJ16(GP/MC)101/102
Device Features............................................................ 2
dsPIC33FJ32(GP/MC)101/102/104
Device Features............................................................ 3
E
Electrical Characteristics................................................... 279
AC ............................................................................. 292
Equations
Device Operating Frequency .................................... 126
MS with PLL Mode.................................................... 127
Errata .................................................................................. 24
F
Flash Program Memory....................................................... 83
Control Registers ........................................................ 85
Operations .................................................................. 84
Programming Algorithm .............................................. 84
RTSP Operation.......................................................... 84
Table Instructions........................................................ 83
I
I/O Ports ............................................................................ 139
Configuring Analog Port Pins.................................... 141
Open-Drain Configuration ......................................... 141
Parallel I/O (PIO)....................................................... 139
Write/Read Timing .................................................... 141
I2C
Control Registers ...................................................... 203
Operating Modes ...................................................... 201
Registers................................................................... 201
In-Circuit Debugger ........................................................... 266
In-Circuit Serial Programming (ICSP) ............................... 266
Input Capture .................................................................... 173
Registers................................................................... 174
Input Change Notification (ICN) ........................................ 141
Instruction Addressing Modes............................................. 73
File Register Instructions ............................................ 73
Fundamental Modes Supported.................................. 74
MAC Instructions......................................................... 74
MCU Instructions ........................................................ 73
Move and Accumulator Instructions............................ 74
Other Instructions........................................................ 74
Instruction Set
Summary........................................................... 267
Overview ................................................................... 270
Symbols Used in Opcode Descriptions..................... 268
Instruction-Based Power-Saving Modes ........................... 133
Idle ............................................................................ 134
Sleep......................................................................... 133
Internet Address................................................................ 380
Interrupt Controller
Interrupt Registers
IECx .................................................................... 98
IFSx..................................................................... 98
INTCON1 ............................................................ 98
INTCON2 ............................................................ 98
INTTREG ............................................................ 98
IPCx .................................................................... 98
Reset Sequence ......................................................... 95
Interrupt Setup Procedures............................................... 124
Initialization............................................................... 124
Interrupt Disable ....................................................... 124
Interrupt Service Routine (ISR)................................. 124
Trap Service Routine (TSR) ..................................... 124
Interrupt Vector Table (IVT) ................................................ 95
Interrupts Coincident with Power Save Instructions ......... 134
L
LPRC Oscillator
Use with WDT........................................................... 265
M
Memory Organization ......................................................... 49
Microchip Internet Web Site.............................................. 380
Modulo Addressing ............................................................. 75
Applicability................................................................. 77
Operation Example..................................................... 76
Start and End Address ............................................... 75
W Address Register Selection .................................... 75
Motor Control PWM .......................................................... 179
Control Registers...................................................... 183
Faults........................................................................ 181
At Reset............................................................ 181
PWM1 6-Channel Module......................................... 179
Write-Protected Registers......................................... 181
MPLAB ASM30 Assembler, Linker, Librarian ................... 276
MPLAB Integrated Development Environment
Software ................................................................... 275
MPLAB PM3 Device Programmer .................................... 278
MPLAB REAL ICE In-Circuit Emulator System ................ 277
MPLINK Object Linker/MPLIB Object Librarian ................ 276
O
Output Compare ............................................................... 175
Modes....................................................................... 176
Active-High One-Shot....................................... 176
Active-Low One-Shot........................................ 176
Continuous Pulse ............................................. 176
Delayed One-Shot ............................................ 176
Module Disabled............................................... 176
PWM with Fault Protection ............................... 176
PWM without Fault Protection .......................... 176
Toggle............................................................... 176
P
Packaging ......................................................................... 337
Details....................................................................... 340
Marking..................................................... 337, 338, 339
Peripheral Module Disable (PMD) .................................... 134
Peripheral Pin Select (PPS).............................................. 142
Available Pins ........................................................... 142
Controlling ................................................................ 142
Controlling Configuration Changes........................... 144
Helpful Tips............................................................... 145
I/O Resources........................................................... 145
Input Selection Sources for Remappable
Pin (RPn) .......................................................... 143
Output Selection Sources for Remappable
Pin (RPn) .......................................................... 144
Registers .................................................................. 146
Pin Diagrams ........................................................................ 4
Pinout I/O Descriptions (table)............................................ 29
2011-2012 Microchip Technology Inc. DS70652E-page 377
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
PORTA
Register Map............................................................... 70
Power-Saving Features .................................................... 133
Clock Frequency and Switching................................ 133
Program Address Space..................................................... 49
Construction................................................................ 79
Data Access from Program Memory Using
Program Space Visibility..................................... 82
Data Access from Program Memory Using
Table Instructions ............................................... 81
Data Access from, Address Generation...................... 80
Memory Map
dsPIC33FJ16(GP/MC)101/102 Devices ............. 49
dsPIC33FJ32(GP/MC)101/102/104 Devices ...... 50
Table Read Instructions
TBLRDH ............................................................. 81
TBLRDL .............................................................. 81
Visibility Operation ...................................................... 82
Program Memory
Interrupt Vector ........................................................... 51
Organization................................................................ 51
Reset Vector ............................................................... 51
Programmer’s Model........................................................... 39
R
Reader Response ............................................................. 381
Real-Time Clock and Calendar (RTCC)............................ 241
Register Maps
6-Output PWM1, dsPIC33FJXXMC10X Devices........ 61
ADC1, dsPIC33FJ32(GP/MC)104 Devices................. 65
ADC1, dsPIC33FJXX(GP/MC)101 Devices................ 63
ADC1, dsPIC33FJXX(GP/MC)102 Devices................ 64
Change Notification, dsPIC33FJ32(GP/MC)104
Devices ............................................................... 58
Change Notification, dsPIC33FJXX(GP/MC)102
Devices ............................................................... 58
Change Notification, dsPIC33FJXXGP101
Devices ............................................................... 58
Change Notification, dsPIC33FJXXMC101
Devices ............................................................... 58
Comparator ................................................................. 67
Configuration Flash Words
dsPIC33FJ16(GP/MC)10X Devices.................. 260
dsPIC33FJ32(GP/MC)10X Devices.................. 260
Configuration Shadow Registers .............................. 260
CPU Core.................................................................... 56
CTMU.......................................................................... 66
I2C1 ............................................................................ 62
Input Capture .............................................................. 61
Interrupt Controller ...................................................... 59
NVM ............................................................................ 72
Output Compare ......................................................... 61
PAD Configuration ...................................................... 66
PMD ............................................................................ 72
PORTA, dsPIC33FJ32(GP/MC)104 Devices.............. 70
PORTA, dsPIC33FJXX(GP/MC)101/102 Devices ...... 69
PORTB, dsPIC33FJXX(GP/MC)102 and
dsPIC33FJ32(GP/MC)104 Devices .................... 70
PORTB, dsPIC33FJXXGP101 Devices ...................... 71
PORTB, dsPIC33FJXXMC101 Devices................ 70, 71
PORTC, dsPIC33FJ32(GP/MC)104 Devices.............. 71
PPS Input.................................................................... 67
PPS Output, dsPIC33FJ32(GP/MC)104 Devices ....... 69
PPS Output, dsPIC33FJXX(GP/MC)102 Devices ...... 68
PPS Output, dsPIC33FJXXGP101 Devices ............... 68
PPS Output, dsPIC33FJXXMC101 Devices ............... 68
Real-Time Clock and Calendar .................................. 66
SPI1............................................................................ 62
System Control ........................................................... 72
Timers, dsPIC33FJ16(GP/MC)10X Devices .............. 60
Timers, dsPIC33FJ32(GP/MC)10X Devices .............. 60
UART1........................................................................ 62
Registers
AD1CHS0 (ADC1 Input Channel 0 Select)............... 225
AD1CHS123 (ADC1 Input Channel 1, 2, 3
Select) .............................................................. 224
AD1CON1 (ADC1 Control 1) .................................... 220
AD1CON2 (ADC1 Control 2) .................................... 222
AD1CON3 (ADC1 Control 3) .................................... 223
AD1CSSL (ADC1 Input Scan Select Low) ............... 226
AD1PCFGL (ADC1 Port Configuration Low) ............ 227
ALCFGRPT (Alarm Configuration) ........................... 246
ALRMVAL (Alarm Minutes and Seconds Value,
ALRMPTR Bits = 00) ........................................ 252
ALRMVAL (Alarm Month and Day Value,
ALRMPTR Bits = 10) ................................ 250, 251
ALRMVAL (Alarm Weekday and Hours Value,
ALRMPTR Bits = 01) ........................................ 251
CLKDIV (Clock Divisor) ............................................ 130
CMSTAT (Comparator Status) ................................. 232
CMxCON (Comparator x Control) ............................ 233
CMxFLTR (Comparator x Filter Control) .................. 239
CMxMSKCON (Comparator x Mask
Gating Control) ................................................. 237
CMxMSKSRC (Comparator x Mask
Source Select).................................................. 235
CORCON (Core Control)...................................... 42, 99
CTMUCON1 (CTMU Control 1)................................ 255
CTMUCON2 (CTMU Control 2)................................ 256
CTMUICON (CTMU Current Control) ....................... 257
CVRCON (Comparator Voltage Reference
Control)............................................................. 240
DEVID (Device ID).................................................... 263
DEVREV (Device Revision)...................................... 263
I2CxCON (I2Cx Control)........................................... 203
I2CxMSK (I2Cx Slave Mode Address Mask)............ 207
I2CxSTAT (I2Cx Status) ........................................... 205
ICxCON (Input Capture x Control)............................ 174
IEC0 (Interrupt Enable Control 0) ............................. 108
IEC1 (Interrupt Enable Control 1) ............................. 109
IEC2 (Interrupt Enable Control 2) ............................. 110
IEC3 (Interrupt Enable Control 3) ............................. 110
IEC4 (Interrupt Enable Control 4) ............................. 111
IFS0 (Interrupt Flag Status 0) ................................... 103
IFS1 (Interrupt Flag Status 1) ................................... 105
IFS2 (Interrupt Flag Status 2) ................................... 106
IFS3 (Interrupt Flag Status 3) ................................... 106
IFS4 (Interrupt Flag Status 4) ................................... 107
INTCON1 (Interrupt Control 1) ................................. 100
INTCON2 (Interrupt Control 2) ................................. 102
INTTREG (Interrupt Control and Status) .................. 123
IPC0 (Interrupt Priority Control 0) ............................. 112
IPC1 (Interrupt Priority Control 1) ............................. 113
IPC14 (Interrupt Priority Control 14) ......................... 119
IPC15 (Interrupt Priority Control 15) ......................... 120
IPC16 (Interrupt Priority Control 16) ......................... 121
IPC19 (Interrupt Priority Control 19) ......................... 122
IPC2 (Interrupt Priority Control 2) ............................. 114
IPC3 (Interrupt Priority Control 3) ............................. 115
IPC4 (Interrupt Priority Control 4) ............................. 116
IPC5 (Interrupt Priority Control 5) ............................. 117
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 378 2011-2012 Microchip Technology Inc.
IPC6 (Interrupt Priority Control 6) ............................. 117
IPC7 (Interrupt Priority Control 7) ............................. 118
IPC9 (Interrupt Priority Control 9) ............................. 119
NVMCON (Flash Memory Control) ............................. 85
NVMKEY (Nonvolatile Memory Key) .......................... 86
OCxCON (Output Compare x Control) ..................... 177
OSCCON (Oscillator Control) ................................... 128
OSCTUN (FRC Oscillator Tuning) ............................ 131
PADCFG1 (Pad Configuration Control) .................... 245
PMD1 (Peripheral Module Disable Control 1) ........... 135
PMD2 (Peripheral Module Disable Control 2) ........... 136
PMD3 (Peripheral Module Disable Control 3) ........... 137
PMD4 (Peripheral Module Disable Control 4) ........... 137
PWMxCON1 (PWMx Control 1) ................................ 186
PWMxCON2 (PWMx Control 2) ................................ 187
PWMxKEY (PWMx Unlock) ...................................... 194
PxDC1 (PWMx Duty Cycle 1) ................................... 193
PxDC2 (PWMx Duty Cycle 2) ................................... 193
PxDC3 (PWMx Duty Cycle 3) ................................... 193
PxDTCON1 (PWMx Dead-Time Control 1)............... 188
PxDTCON2 (PWMx Dead-Time Control 2)............... 189
PxFLTACON (PWMx Fault A Control) ...................... 190
PxFLTBCON (PWMx Fault B Control) ...................... 191
PxOVDCON (PWMx Override Control)..................... 192
PxSECMP (PWMx Special Event Compare) ............ 185
PxTCON (PWMx Time Base Control) ....................... 183
PxTMR (PWMx Timer Count Value) ......................... 184
PxTPER (PWMx Time Base Period)......................... 184
RCFGCAL (RTCC Calibration
and Configuration) ............................................ 243
RCON (Reset Control) ................................................ 88
RPINR0 (Peripheral Pin Select Input 0) .................... 146
RPINR1 (Peripheral Pin Select Input 1) .................... 147
RPINR11 (Peripheral Pin Select Input 11) ................ 152
RPINR18 (Peripheral Pin Select Input 18) ................ 153
RPINR20 (Peripheral Pin Select Input 20) ................ 154
RPINR21 (Peripheral Pin Select Input 21) ................ 155
RPINR3 (Peripheral Pin Select Input 3) .................... 148
RPINR4 (Peripheral Pin Select Input 4) .................... 149
RPINR7 (Peripheral Pin Select Input 7) .................... 150
RPINR8 (Peripheral Pin Select Input 8) .................... 151
RPOR0 (Peripheral Pin Select Output 0) .................. 156
RPOR1 (Peripheral Pin Select Output 1) .................. 156
RPOR10 (Peripheral Pin Select Output 10) .............. 161
RPOR11 (Peripheral Pin Select Output 11) .............. 161
RPOR12 (Peripheral Pin Select Output 12) .............. 162
RPOR2 (Peripheral Pin Select Output 2) .................. 157
RPOR3 (Peripheral Pin Select Output 3) .................. 157
RPOR4 (Peripheral Pin Select Output 4) .................. 158
RPOR5 (Peripheral Pin Select Output 5) .................. 158
RPOR6 (Peripheral Pin Select Output 6) .................. 159
RPOR7 (Peripheral Pin Select Output 7) .................. 159
RPOR8 (Peripheral Pin Select Output 8) .................. 160
RPOR9 (Peripheral Pin Select Output 9) .................. 160
RTCVAL (Minutes and Seconds Value,
RTCPTR Bits = 00) ........................................... 249
RTCVAL (Year Value, RTCPTR Bits = 11) ............... 247
RTCVAL Month and Day Value,
RTCPTR Bits = 10) ........................................... 247
RTCVAL Weekdays and Hours Value,
RTCPTR Bits = 01) ........................................... 248
SPIxCON1 (SPIx Control 1) ...................................... 198
SPIxCON2 (SPIx Control 2) ...................................... 200
SPIxSTAT (SPIx Status and Control) ....................... 197
SR (CPU STATUS) ............................................... 40, 99
T1CON (Timer1 Control) .......................................... 164
T2CON Control ......................................................... 168
T3CON Control ......................................................... 169
T4CON Control ......................................................... 170
T5CON Control ......................................................... 171
UxMODE (UARTx Mode).......................................... 211
UxSTA (UARTx Status and Control)......................... 213
Resets................................................................................. 87
BOR (Brown-out Reset).............................................. 87
BOR and Power-up Timer (PWRT) ............................ 92
CM (Configuration Mismatch Reset)........................... 87
Configuration Mismatch (CM) ..................................... 93
External (EXTR).......................................................... 93
Illegal Condition .......................................................... 93
Illegal Opcode..................................................... 93
Security......................................................... 93, 94
Uninitialized W Register ............................... 93, 94
IOPUWR (Illegal Condition Reset).............................. 87
Illegal Opcode..................................................... 87
Security............................................................... 87
Uninitialized W Register ..................................... 87
MCLR (Master Clear Pin) ........................................... 87
Oscillator Delays......................................................... 90
POR (Power-on Reset)............................................... 87
Power-on Reset (POR)............................................... 92
Software RESET Instruction (SWR) ........................... 93
SWR (RESET Instruction) .......................................... 87
System
Cold Reset.......................................................... 90
Warm Reset........................................................ 90
Trap Conflict ............................................................... 93
TRAPR (Trap Conflict Reset) ..................................... 87
Watchdog Timer Time-out (WDTR) ............................ 93
WDTO (Watchdog Timer Reset)................................. 87
Revision History................................................................ 367
RTCC
Control Registers...................................................... 243
Module Registers...................................................... 242
S
Serial Peripheral Interface (SPI) ....................................... 195
Control Registers...................................................... 197
Helpful Tips............................................................... 196
Resources ................................................................ 196
Software Simulator (MPLAB SIM) .................................... 277
Software Stack Pointer, Frame Pointer
CALL Stack Frame ..................................................... 73
Special Features............................................................... 259
Code Protection........................................................ 259
Flexible Configuration ............................................... 259
In-Circuit Emulation .................................................. 259
In-Circuit Serial Programming (ICSP)....................... 259
Watchdog Timer (WDT)............................................ 259
T
Timer1............................................................................... 163
Timer2/3 and Timer4/5 ..................................................... 165
16-Bit Operation ....................................................... 165
32-Bit Operation ....................................................... 165
Control Registers...................................................... 168
Timing Diagrams
ADC Conversion Characteristics (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)... 332
ADC Conversion Characteristics (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111,
SAMC<4:0> = 00001)....................................... 332
2011-2012 Microchip Technology Inc. DS70652E-page 379
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Brown-out Reset Situations ........................................ 92
CLKO and I/O ........................................................... 295
External Clock........................................................... 293
I2Cx Bus Data (Master Mode) .................................. 326
I2Cx Bus Data (Slave Mode) .................................... 328
I2Cx Bus Start/Stop Bits (Master Mode) ................... 326
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 328
Input Capture x (ICx)................................................. 299
Motor Control PWM .................................................. 301
Motor Control PWM Fault ......................................... 301
OCx/PWM ................................................................. 300
Output Compare x (OCx) .......................................... 300
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ................................................ 296
SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP
= 1) for dsPIC33FJ16(GP/MC)10X ................... 305
SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP
= 1) for dsPIC33FJ32(GP/MC)10X ................... 317
SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP
= 1) for dsPIC33FJ16(GP/MC)10X ................... 304
SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP
= 1) for dsPIC33FJ32(GP/MC)10X ................... 316
SPIx Master Transmit Mode (Half-Duplex, CKE = 0) for
dsPIC33FJ16(GP/MC)10X ............................... 302
SPIx Master Transmit Mode (Half-Duplex, CKE = 0) for
dsPIC33FJ32(GP/MC)10X ............................... 314
SPIx Master Transmit Mode (Half-Duplex, CKE = 1) for
dsPIC33FJ16(GP/MC)10X ............................... 303
SPIx Master Transmit Mode (Half-Duplex, CKE = 1) for
dsPIC33FJ32(GP/MC)10X ............................... 315
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP
= 0) for dsPIC33FJ16(GP/MC)10X ................... 312
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP
= 0) for dsPIC33FJ32(GP/MC)10X ................... 324
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP
= 0) for dsPIC33FJ16(GP/MC)10X ................... 310
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP
= 0) for dsPIC33FJ32(GP/MC)10X ................... 322
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP
= 0) for dsPIC33FJ16(GP/MC)10X ................... 306
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP
= 0) for dsPIC33FJ32(GP/MC)10X ................... 318
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP
= 0) for dsPIC33FJ16(GP/MC)10X ................... 308
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP
= 0) for dsPIC33FJ32(GP/MC)10X ................... 320
System Reset.............................................................. 91
Timer1, 2 and 3 External Clock................................. 297
Timing Requirements
10-Bit ADC Conversion............................................. 333
Capacitive Loading on Output Pins........................... 292
CLKO and I/O ........................................................... 295
External Clock........................................................... 293
I2Cx Bus Data (Master Mode) .................................. 327
I2Cx Bus Data (Slave Mode) .................................... 329
Input Capture x (ICx)................................................. 299
Motor Control PWM .................................................. 301
Output Compare x (OCx) .......................................... 300
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset................296
Simple OCx/PWM Mode..............................................300
SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x,
SMP = 1) for dsPIC33FJ16(GP/MC)10X.............305
SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x,
SMP = 1) for dsPIC33FJ32(GP/MC)10X.............317
SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x,
SMP = 1) for dsPIC33FJ16(GP/MC)10X.......... 304
SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x,
SMP = 1) for dsPIC33FJ32(GP/MC)10X.......... 316
SPIx Master Transmit Mode (Half-Duplex) for
dsPIC33FJ16(GP/MC)10X ............................... 303
SPIx Master Transmit Mode (Half-Duplex) for
dsPIC33FJ32(GP/MC)10X ............................... 315
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0,
SMP = 0) for dsPIC33FJ16(GP/MC)10X............. 313
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0,
SMP = 0) for dsPIC33FJ32(GP/MC)10X............. 325
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1,
SMP = 0) for dsPIC33FJ16(GP/MC)10X............. 311
SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1,
SMP = 0) for dsPIC33FJ32(GP/MC)10X............. 323
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0,
SMP = 0) for dsPIC33FJ16(GP/MC)10X............. 307
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0,
SMP = 0) for dsPIC33FJ32(GP/MC)10X............. 319
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1,
SMP = 0) for dsPIC33FJ16(GP/MC)10X............. 309
SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1,
SMP = 0) for dsPIC33FJ32(GP/MC)10X............. 321
Timer1 External Clock .............................................. 297
Timer2/4 External Clock ........................................... 298
Timer3/5 External Clock ........................................... 298
Timing Specifications
Comparator Module.................................................. 334
Comparator Timing................................................... 334
Comparator Voltage Reference................................ 335
Comparator Voltage Reference Settling Time.......... 334
CTMU Current Source.............................................. 335
PLL Clock ................................................................. 294
U
UART
Control Registers...................................................... 211
Helpful Tips............................................................... 210
Resources ................................................................ 210
Universal Asynchronous Receiver
Transmitter (UART) .................................................. 209
Using the RCON Status Bits............................................... 94
V
Voltage Regulator (On-Chip) ............................................ 264
W
Watchdog Timer (WDT).................................................... 265
Programming Considerations ................................... 265
WWW Address ................................................................. 380
WWW, On-Line Support ..................................................... 24
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 380 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 381
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 382 2011-2012 Microchip Technology Inc.
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(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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DS70652EdsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2011-2012 Microchip Technology Inc. DS70652E-page 383
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Architecture: 33 = 16-bit Digital Signal Controller
Flash Memory Family: FJ = Flash program memory, 3.3V
Product Group: GP1 = General Purpose family
MC1 = Motor Control family
Pin Count: 01 = 18-pin and 20-pin
02 = 28-pin and 32-pin
Temperature Range: I = -40C to+85C (Industrial)
E=-40C to+125C (Extended)
Package: P = Plastic Dual In-Line - 300 mil body (PDIP)
SS = Plastic Shrink Small Outline -5.3 mm body (SSOP)
SP = Skinny Plastic Dual In-Line - 300 mil body (SPDIP)
SO = Plastic Small Outline - Wide, 7.50 mil body (SOIC)
ML = Plastic Quad, No Lead - (28-pin) 6x6 mm body (QFN)
PT = Plastic Thin Quad Flatpack - (44-pin) 10x10 mm body (TQFP)
TL = Very Thin Leadless Array - (36-pin) 5x5 mm body (VTLA)
Examples:
a) dsPIC33FJ16MC102-E/SP:
Motor Control dsPIC33,
16-Kbyte program memory,
28-pin, Extended temperature,
SPDIP package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (Kbyte)
Product Group
Pin Count
Temperature Range
Package
Pattern
dsPIC 33 FJ 16 MC1 02 T E / SP - XXX
Tape and Reel Flag (if applicable)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 384 2011-2012 Microchip Technology Inc.
NOTES:
2011-2012 Microchip Technology Inc. DS70652E-page 385
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-602-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS70652E-page 386 2011-2012 Microchip Technology Inc.
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11/29/11
