ADA49382ACPZRL - ANALOG DEVICES

10-Bit, 210 MSPS TxDAC

Digital-to-Analog Converter

AD9740W

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

High performance member of pin-compatible

TxDAC product family

Excellent spurious-free dynamic range performance

SNR at 5 MHz output, 125 MSPS: 65 dB

Twos complement or straight binary data format

Differential current outputs: 2 mA to 20 mA

Power dissipation: 135 mW at 3.3 V

Power-down mode: 15 mW at 3.3 V

On-chip 1.2 V reference

CMOS-compatible digital interface

28-lead TSSOP package

Edge-triggered latches

Qualified for automotive applications

APPLICATIONS

Wideband communication transmit channel

Direct IF

Base stations

Wireless local loops

Digital radio links

Direct digital synthesis (DDS)

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

1.2V RE F

REFLO

3.3V

CLOCK

SLEEP

REFIO

FS ADJ

DVDD

DCOM

CLOCK

DIG ITAL DATA INPUTS (DB9 TO DB0)

150pF

3.3

AVDD ACOM

AD9740W

CURRENT

SOURCE

ARRAY

IOUTA

IOUTB

MODE

SEGMENTED

SWITCHES

LATCHES

09489-001

LSB

SWITCHES

SET

0.1µF

Figure 1.

GENERAL DESCRIPTION

The AD9740W1 is a 10-bit resolution, wideband, third

generation member of the TxDAC® series of high performance,

low power CMOS digital-to-analog converters (DACs). The

TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and

14-bit DACs, is specifically optimized for the transmit signal

path of communication systems. All of the devices share the

same interface options, small outline package, and pinout,

providing an upward or downward component selection path

based on performance, resolution, and cost. The AD9740W

offers exceptional ac and dc performance while supporting

update rates up to 210 MSPS.

The AD9740W’s low power dissipation makes it well suited for

portable and low power applications. Its power dissipation can

be further reduced to 60 mW with a slight degradation in

performance by lowering the full-scale current output. In

addition, a power-down mode reduces the standby power

dissipation to approximately 15 mW. A segmented current

source architecture is combined with a proprietary switching

technique to reduce spurious components and enhance

dynamic performance.

Edge-triggered input latches and a 1.2 V temperature-compensated

band gap reference have been integrated to provide a complete

monolithic DAC solution. The digital inputs support 3 V CMOS

logic families.

PRODUCT HIGHLIGHTS

1. The AD9740W is the 10-bit member of the pin-compatible

TxDAC family, which offers excellent INL and DNL

performance.

2. Data input supports twos complement or straight binary

data coding.

3. High speed, single-ended CMOS clock input supports

210 MSPS conversion rate.

4. Low power: Complete CMOS DAC function operates on

135 mW from a 2.7 V to 3.6 V single supply. The DAC full-

scale current can be reduced for lower power operation,

and a sleep mode is provided for low power idle periods.

5. On-chip voltage reference: The AD9740W includes a 1.2 V

temperature-compensated band gap voltage reference.

6. Industry-standard 28-lead TSSOP package.

1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.

AD9740W

Rev. 0 | Page 2 of 20

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

Dynamic Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Terminology ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

Functional Description .................................................................. 12

Reference Operation .................................................................. 12

Reference Control Amplifier .................................................... 13

DAC Transfer Function ............................................................. 13

Analog Outputs .......................................................................... 13

Digital Inputs .............................................................................. 14

Clock Input.................................................................................. 14

DAC Timing................................................................................ 14

Power Dissipation....................................................................... 15

Applying the AD9740W............................................................ 15

Differential Coupling Using a Transformer............................... 15

Differential Coupling Using an Op Amp................................ 15

Single-Ended, Unbuffered Voltage Output............................. 16

Single-Ended, Buffered Voltage Output Configuration........ 16

Power and Grounding Considerations, Power Supply

Rejection...................................................................................... 16

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 18

Automotive Products................................................................. 18

REVISION HISTORY

12/10—Revision 0: Initial Version

AD9740W

Rev. 0 | Page 3 of 20

SPECIFICATIONS

DC SPECIFICATIONS

TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 10 Bits

DC ACCURACY1

Integral Linearity Error (INL) −0.75 ±0.15 +0.75 LSB

Differential Nonlinearity (DNL) −0.5 ±0.12 +0.5 LSB

ANALOG OUTPUT

Offset Error −0.02 +0.02 % of FSR

Gain Error (Without Internal Reference) −2 ±0.1 +2 % of FSR

Gain Error (With Internal Reference) −2 ±0.1 +2 % of FSR

Full-Scale Output Current2 2 20 mA

Output Compliance Range −1 +1.25 V

Output Resistance 100 kΩ

Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V

Reference Output Current3 100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance (External Reference) 7 kΩ

Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C

Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C

Gain Drift (With Internal Reference) ±100 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD 2.7 3.3 3.6 V

DVDD 2.7 3.3 3.6 V

Analog Supply Current (IAVDD) 33 36 mA

Digital Supply Current (IDVDD)4 8 9 mA

Supply Current Sleep Mode (IAVDD) 5 6 mA

Power Dissipation4 135 145 mW

Power Dissipation5 145 mW

Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V

Power Supply Rejection Ratio—DVDD6 −0.04 +0.04 % of FSR/V

OPERATING RANGE −40 +105 °C

1 Measured at IOUTA, driving a virtual ground.

2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.

3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz.

5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz.

6 ±5% power supply variation.

AD9740W

Rev. 0 | Page 4 of 20

DYNAMIC SPECIFICATIONS

TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated, unless

otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (fCLOCK) 210 MSPS

Output Settling Time (tST) (to 0.1%)1 11 ns

Output Propagation Delay (tPD) 1 ns

Glitch Impulse 5 pV-s

Output Rise Time (10% to 90%)1 2.5 ns

Output Fall Time (10% to 90%)1 2.5 ns

Output Noise (IOUTFS = 20 mA)2 50 pA/√Hz

Output Noise (IOUTFS = 2 mA)2 30 pA/√Hz

Noise Spectral Density3 −143 dBm/Hz

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

fCLOCK = 25 MSPS; fOUT = 1.00 MHz

0 dBFS Output 66 79 dBc

−6 dBFS Output 75 dBc

−12 dBFS Output 67 dBc

−18 dBFS Output 61 dBc

fCLOCK = 65 MSPS; fOUT = 1.00 MHz 84 dBc

fCLOCK = 65 MSPS; fOUT = 2.51 MHz 80 dBc

fCLOCK = 65 MSPS; fOUT = 10 MHz 78 dBc

fCLOCK = 65 MSPS; fOUT = 15 MHz 76 dBc

fCLOCK = 65 MSPS; fOUT = 25 MHz 75 dBc

fCLOCK = 165 MSPS; fOUT = 21 MHz 70 dBc

fCLOCK = 165 MSPS; fOUT = 41 MHz 60 dBc

fCLOCK = 210 MSPS; fOUT = 40 MHz 67 dBc

fCLOCK = 210 MSPS; fOUT = 69 MHz 63 dBc

Spurious-Free Dynamic Range within a Window

fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span 79 dBc

fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span 90 dBc

fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 2.5 MHz Span 90 dBc

fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 4 MHz Span 90 dBc

Total Harmonic Distortion

fCLOCK = 25 MSPS; fOUT = 1.00 MHz −79 −65 dBc

fCLOCK = 50 MSPS; fOUT = 2.00 MHz −77 dBc

fCLOCK = 65 MSPS; fOUT = 2.00 MHz −77 dBc

fCLOCK = 125 MSPS; fOUT = 2.00 MHz −77 dBc

Signal-to-Noise Ratio

fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 68 dB

fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 64 dB

fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 64 dB

fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 62 dB

fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 64 dB

fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 62 dB

fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 63 dB

fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 60 dB

AD9740W

Rev. 0 | Page 5 of 20

Parameter Min Typ Max Unit

Multitone Power Ratio (8 Tones at 400 kHz Spacing)

fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz

0 dBFS Output 65 dBc

−6 dBFS Output 66 dBc

−12 dBFS Output 60 dBc

−18 dBFS Output 55 dBc

1 Measured single-ended into 50 Ω load.

2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.

3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS1

Logic 1 Voltage 2.1 3 V

Logic 0 Voltage 0 0.9 V

Logic 1 Current −10 +10 μA

Logic 0 Current −10 +10 μA

Input Capacitance 5 pF

Input Setup Time (tS) 2.0 ns

Input Hold Time (tH) 1.5 ns

Latch Pulse Width (tLPW) 1.5 ns

1 Includes CLOCK pin in single-ended clock input mode.

0.1% 0.1%

DB0 TO DB9

CLOCK

IOUTA

IOUTB

LPW

09489-002

Figure 2. Timing Diagram

AD9740W

Rev. 0 | Page 6 of 20

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

With

Respect to Min Max Unit

AVDD ACOM −0.3 +3.9 V

DVDD DCOM −0.3 +3.9 V

ACOM DCOM −0.3 +0.3 V

AVDD DVDD −3.9 +3.9 V

CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V

Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V

IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V

REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V

Junction

Temperature

150 °C

Storage

Temperature

Range

−65 +150 °C

Lead Temperature

(10 sec)

300 °C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to

absolute maximum ratings for extended periods may affect

device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

Table 5. Thermal Resistance1

Package Type θJA Unit

28-Lead TSSOP 67.7 °C/W

1 Thermal impedance measurements were taken on a 4-layer board in still air,

in accordance with EIA/JESD51-7.

ESD CAUTION

AD9740W

Rev. 0 | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC = NO CONNECT. DO NOT

CONNE CT TO T HI S PIN.

DB8

DB7

DB6

DB3

DB4

DB5

(

MSB) DB9

DVDD

DCOM

MODE

IOUTA

RESERVED

AVDD

DB2

DB1

DB0

IOUTB

ACOM

SLEEP

NC REFLO

REFIO

FS ADJ

CLOCK

AD9740W

TOP VIEW

(No t to S cale)

09489-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 DB9 (MSB) Most Significant Data Bit (MSB).

2 to 9 DB8 to DB1 Data Bits 8 to 1.

10 DB0 (LSB) Least Significant Data Bit (LSB).

11 to 14, 19 NC No Internal Connection.

15 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it can be

left unterminated if not used.

16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both

internal and external reference operation modes.

17 REFIO Reference Input/Output. Serves as reference input when using external reference.

Serves as 1.2 V reference output when using internal reference. Requires 0.1 μF capacitor

to ACOM when using internal reference.

18 FS ADJ Full-Scale Current Output Adjust.

20 ACOM Analog Common.

21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.

22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.

23 RESERVED Reserved. Do Not Connect to Common or Supply.

24 AVDD Analog Supply Voltage (3.3 V).

25 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.

26 DCOM Digital Common.

27 DVDD Digital Supply Voltage (3.3 V).

28 CLOCK Clock Input. Data latched on positive edge of clock.

AD9740W

Rev. 0 | Page 8 of 20

TERMINOLOGY

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the

actual analog output from the ideal output, determined by a

straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output either increases or remains

constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is

called the offset error. For IOUTA, 0 mA output is expected

when the inputs are all 0s. For IOUTB, 0 mA output is expected

when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current output

DAC. Operation beyond the maximum compliance limits can

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either TMIN or TMAX. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per °C. For reference drift, the drift is reported in

ppm per °C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies

are varied from nominal to minimum and maximum specified

voltages.

Settling Time

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal. It is

expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range containing multiple carrier

tones of equal amplitude. It is measured as the difference

between the rms amplitude of a carrier tone to the peak

spurious signal in the region of a removed tone.

150pF

1.2V RE F AVDD ACOM

REFLO

REFIO

FS ADJ

DVDD

DCOM

CLOCK

3.3V

DVDD

DCOM

IOUTA

IOUTB

AD9740W

SLEEP LATCHES

3.3V

MODE

09489-005

PMOS

CURRENT S OURCE

ARRAY

LSB

SWITCHES

SEG M E NT E D SWI T CHE S

FOR DB11 TO DB3

DIGITAL

DATA

TEKTRONIX AWG-2021

WITH OPTION 4

CLOCK

OUTPUT

LECROY 9210

PULS E G E NE RATOR

RETIMED

CLOCK

OUTPUT*

SET

2kΩ

50Ω

0.1µF

ROHDE AND SCHWARZ

FSEA30

SPECTRUM

ANALYZER

MINI-CIRCUITS

T1-1T

*AWG2021 CL OCK RET IME D

SO T HAT THE DI G ITAL DATA

TRANSIT I ONS O N FALLING EDG E

OF 50% DUT Y CYCL E CL OCK.

Figure 4. Basic AC Characterization Test Setup

AD9740W

Rev. 0 | Page 9 of 20

100

TYPICAL PERFORMANCE CHARACTERISTICS

OUT

(MHz)

SF DR (dBc)

110

210MSPS

09489-006

65MSPS

125MSPS

165MSPS

Figure 5. SFDR vs. fOUT at 0 dBFS

OUT

(MHz)

SFDR (dBc)

0 5 10 15 20 25

–12dBFS

–6dBFS

0dBFS

09489-007

Figure 6. SFDR vs. fOUT at 65 MSPS

OUT

(MHz)

SFDR ( dBc)

01052015 3025 4035 45

0dBFS

–6dBFS

–12dBFS

09489-008

Figure 7. SFDR vs. fOUT at 125 MSPS

OUT

(MHz)

SFDR ( dBc)

02010 30 40 50 60

–12dBFS

–6dBFS

0dBFS

09489-009

Figure 8. SFDR vs. fOUT at 165 MSPS

OUT

(MHz)

SFDR ( dBc)

0105152025

20mA

10mA

5mA

09489-010

Figure 9. SFDR vs. fOUT and IOUTFS at 65 MSPS and 0 dBFS

fOUT

(MHz)

SF DR (dBc)

02010 30 40 50 60 70 80

–12dBFS –6dBFS

0dBFS

09489-054

Figure 10. SFDR vs. fOUT at 210 MSPS

AD9740W

Rev. 0 | Page 10 of 20

210MSPS

09489-011

165MSPS

65MSPS

OUT

(dBFS)

SF DR (d Bc)

–25 –15–20 –10 –5 0

125MSPS

Figure 11. Single-Tone SFDR vs. AOUT at fOUT = fCLOCK/11

AOUT (d BFS)

SF DR ( dBc)

–25 –15–20 –10 –5 0

210MSPS

09489-012

165MSPS

125MSPS

65MSPS

Figure 12. Single-Tone SFDR vs. AOUT at fOUT = fCLOCK/5

CLOCK

(MSPS)

SNR (dB)

0609030 150

120 180 210

5mA

10mA

20mA

09489-013

Figure 13. SNR vs. fCLOCK and IOUTFS at fOUT = 5 MHz and 0 dBFS

OUT

(dBFS)

SFDR (dBc)

–25 –15–20 –10 –5 0

210MSPS ( 29, 31)

09489-014

78MSPS

165MSPS

125MSPS

65MSPS

Figure 14. Dual-Tone IMD vs. AOUT at fOUT = fCLOCK/7

CODE

ERROR (LSB)

0.25

–0.25

–0.15

–0.05

0.05

0.15

0512256 768 1024

09489-015

Figure 15. Typical INL

CODE

ERRO R (LS B )

0.25

–0.25

–0.15

–0.05

0.05

0.15

0512256 768 1024

09489-016

Figure 16. Typical DNL

AD9740W

Rev. 0 | Page 11 of 20

TE MPE RATURE (°C)

SF DR (dBc)

–40 0 20–20 40 60 80

4MHz

19MHz

34MHz

49MHz

09489-017

Figure 17. SFDR vs. Temperature at 165 MSPS, 0 dBFS

FRE Q UE NC Y ( M Hz)

MAG NIT UDE (d Bm)

–40

–30

–20

–10

–100

–90

–80

–60

–70

–50

111166213126 36

CLOCK

= 78MSPS

OUT

= 15.0MHz

SF DR = 77d Bc

AMPL IT UDE = 0d BF S

09489-018

Figure 18. Single-Tone SFDR

FRE QUE N CY (MHz)

MAGNIT UDE (d Bm)

–40

–30

–20

–10

–100

–90

–80

–60

–70

–50

111166213126 36

CLOCK

= 78MSPS

OUT1

= 15.0MHz

OUT2

= 15.4MHz

SF DR = 77 d Bc

AMPLI TUDE = 0d B FS

09489-019

Figure 19. Dual-Tone SFDR

FREQ UE NC Y (M Hz)

MAGNITUDE (dBm)

–40

–30

–20

–10

–100

–90

–80

–60

–70

–50

111166213126 36

CLOCK

= 78MSPS

OUT1

= 15.0M Hz

OUT2

= 15.4M Hz

OUT3

= 15.8M Hz

OUT4

= 16.2M Hz

SFDR = 72dBc

AMP LI TUDE = 0dBFS

09489-020

Figure 20. Four-Tone SFDR

DIGITAL DATA INPUTS ( DB11 TO DB0)

150pF

1.2V REF

AVDD ACOM

REFLO

PMOS

CURRENT S OURCE

ARRAY

3.3

REFIO

FS ADJ

DVDD

DCOM

CLOCK

3.3V IOUTA

IOUTB

AD9740W

SLEEP LATCHES

CLOCK

IOUTB

IOUTA

MODE

09489-021

DIFF

= V

OUTA

– V

OUTB

OUTA

LOAD

50Ω

LOAD

50Ω

LSB

SWITCHES

SEGMENTED SWITCHES

FO R DB11 TO DB3

SET

2kΩ

REF

REFIO

0.1µF

Figure 21. Simplified Block Diagram

AD9740W

Rev. 0 | Page 12 of 20

FUNCTIONAL DESCRIPTION

Figure 21 shows a simplified block diagram of the AD9740W.

The AD9740W consists of a DAC, digital control logic, and full-

scale output current control. The DAC contains a PMOS

current source array capable of providing up to 20 mA of full-

scale current (IOUTFS). The array is divided into 31 equal currents

that make up the five most significant bits (MSBs). The next

four bits, or middle bits, consist of 15 equal current sources

whose value is 1/16 of an MSB current source. The remaining

LSBs are binary weighted fractions of the middle bits current

sources. Implementing the middle and lower bits with current

sources, instead of an R-2R ladder, enhances its dynamic

performance for multitone or low amplitude signals and helps

maintain the DAC’s high output impedance (that is, >100 kΩ).

All of these current sources are switched to one or the other of

the two output nodes (that is, IOUTA or IOUTB) via PMOS

differential current switches. The switches are based on the

architecture that was pioneered in the AD9764 family, with

further refinements to reduce distortion contributed by the

switching transient. This switch architecture also reduces

various timing errors and provides matching complementary

drive signals to the inputs of the differential current switches.

The analog and digital sections of the AD9740W have separate

power supply inputs (that is, AVDD and DVDD) that can

operate independently over a 2.7 V to 3.6 V range. The digital

section, which is capable of operating at a clock rate of up to

210 MSPS, consists of edge-triggered latches and segment

decoding logic circuitry. The analog section includes the PMOS

current sources, the associated differential switches, a 1.2 V

band gap voltage reference, and a reference control amplifier.

The DAC full-scale output current is regulated by the reference

control amplifier and can be set from 2 mA to 20 mA via an

external resistor, RSET, connected to the full-scale adjust (FS ADJ)

pin. The external resistor, in combination with both the refer-

ence control amplifier and voltage reference, VREFIO, sets the

reference current, IREF, which is replicated to the segmented

current sources with the proper scaling factor. The full-scale

current, IOUTFS, is 32 times IREF.

REFERENCE OPERATION

The AD9740W contains an internal 1.2 V band gap reference.

The internal reference cannot be disabled, but can be easily

overridden by an external reference with no effect on perfor-

mance. Figure 22 shows an equivalent circuit of the band gap

reference. REFIO serves as either an output or an input depend-

ing on whether the internal or an external reference is used. To

use the internal reference, simply decouple the REFIO pin to

ACOM with a 0.1 μF capacitor and connect REFLO to ACOM

via a resistance less than 5 Ω. The internal reference voltage is

present at REFIO. If the voltage at REFIO is to be used any-

where else in the circuit, then an external buffer amplifier with

an input bias current of less than 100 nA should be used. An

example of the use of the internal reference is shown in Figure 24.

7kΩ

84µA

REFLO

REFIO

09489-057

Figure 22. Equivalent Circuit of Internal Reference

An external reference can be applied to REFIO, as shown in

Figure 23. The external reference can provide either a fixed

reference voltage to enhance accuracy and drift performance

or a varying reference voltage for gain control. Note that the

0.1 μF compensation capacitor is not required because the

internal reference is overridden, and the relatively high input

impedance of REFIO minimizes any loading of the external

reference.

150pF

1.2V REF

AVDD

REFLO

REFIO

FS ADJ

AD9740W

3.3

09489-023

CURRENT

SOURCE

ARRAY

Figure 23. External Reference Configuration

150pF

1.2V REF

AVDD

REFLO

3.3V

REFIO

FS ADJ

2kΩ

0.1µF

AD9740W

09489-022

CURRENT

SOURCE

ARRAY

OPTIONAL

EXTERNAL

REF BUFFER

DDITION

LOAD

Figure 24. Internal Reference Configuration

AD9740W

Rev. 0 | Page 13 of 20

REFERENCE CONTROL AMPLIFIER

The AD9740W contains a control amplifier that is used to regu-

late the full-scale output current, IOUTFS. The control amplifier is

configured as a V-I converter, as shown in Figure 24, so that its

current output, IREF, is determined by the ratio of the VREFIO and

an external resistor, RSET, as stated in Equation 4. IREF is copied

to the segmented current sources with the proper scale factor to

set IOUTFS, as stated in Equation 3.

The control amplifier allows a wide (10:1) adjustment span of IOUTFS

over a 2 mA to 20 mA range by setting IREF between 62.5 μA and

625 μA. The wide adjustment span of IOUTFS provides several

benefits. The first relates directly to the power dissipation of

the AD9740W, which is proportional to IOUTFS (see the Power

Dissipation section). The second relates to a 20 dB adjustment,

which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 500 kHz and can be used for low frequency small

signal multiplying applications.

DAC TRANSFER FUNCTION

The AD9740W provides complementary current outputs,

IOUTA and IOUTB. IOUTA provides a near full-scale current

output, IOUTFS, when all bits are high (that is, DAC CODE =

1023), while IOUTB, the complementary output, provides no

current. The current output appearing at IOUTA and IOUTB is

a function of both the input code and IOUTFS and can be

expressed as:

IOUTA = (DAC CODE/1023) × IOUTFS (1)

IOUTB = (1023 − DAC CODE)/1024 × IOUTFS (2)

where DAC CODE = 0 to 1023 (that is, decimal representation).

As mentioned previously, IOUTFS is a function of the reference

current IREF, which is nominally set by a reference voltage,

VREFIO, and external resistor, RSET. It can be expressed as:

IOUTFS = 32 × IREF (3)

where

IREF = VREFIO/RSET (4)

The two current outputs typically drive a resistive load directly

or via a transformer. If dc coupling is required, then IOUTA

and IOUTB should be directly connected to matching resistive

loads, RLOAD, that are tied to analog common, ACOM. Note that

RLOAD can represent the equivalent load resistance seen by

IOUTA or IOUTB, as would be the case in a doubly terminated

50 Ω or 75 Ω cable. The single-ended voltage output appearing

at the IOUTA and IOUTB nodes is simply

VOUTA = IOUTA × RLOAD (5)

VOUTB = IOUTB × RLOAD (6)

Note that the full-scale value of VOUTA and VOUTB should not

exceed the specified output compliance range to maintain

specified distortion and linearity performance.

VDIFF = (IOUTA − IOUTB) × RLOAD (7)

Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be

expressed as:

VDIFF = {(2 × DAC CODE − 1023)/1024}

(32 × RLOAD/RSET) × VREFIO (8)

Equation 7 and Equation 8 highlight some of the advantages of

operating the AD9740W differentially. First, the differential

operation helps cancel common-mode error sources associated

with IOUTA and IOUTB, such as noise, distortion, and dc

offsets. Second, the differential code-dependent current and

subsequent voltage, VDIFF, is twice the value of the single-ended

voltage output (that is, VOUTA or VOUTB), thus providing twice the

signal power to the load.

Note that the gain drift temperature performance for a single-

ended (VOUTA and VOUTB) or differential output (VDIFF) of the

AD9740W can be enhanced by selecting temperature tracking

resistors for RLOAD and RSET due to their ratiometric relationship,

as shown in Equation 8.

ANALOG OUTPUTS

The complementary current outputs in each DAC, IOUTA,

and IOUTB can be configured for single-ended or differential

operation. IOUTA and IOUTB can be converted into complemen-

tary single-ended voltage outputs, VOUTA and VOUTB, via a load

resistor, RLOAD, as described in the DAC Transfer Function

section by Equation 5 through Equation 8. The differential

voltage, VDIFF, existing between VOUTA and VOUTB, can also be

converted to a single-ended voltage via a transformer or

differential amplifier configuration. The ac performance of

the AD9740W is optimum and specified using a differential

transformer-coupled output in which the voltage swing at

IOUTA and IOUTB is limited to ±0.5 V.

The distortion and noise performance of the AD9740W can be

enhanced when it is configured for differential operation. The

common-mode error sources of both IOUTA and IOUTB can

be significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode

error sources include even-order distortion products and noise.

The enhancement in distortion performance becomes more

significant as the frequency content of the reconstructed

waveform increases and/or its amplitude decreases. This is due

to the first-order cancellation of various dynamic common-

mode distortion mechanisms, digital feedthrough, and noise.

Performing a differential-to-single-ended conversion via a

transformer also provides the ability to deliver twice the

reconstructed signal power to the load (assuming no source

termination). Because the output currents of IOUTA and

IOUTB are complementary, they become additive when pro-

cessed differentially. A properly selected transformer allows

the AD9740W to provide the required power and voltage levels

to different loads.

The output impedance of IOUTA and IOUTB is determined by

the equivalent parallel combination of the PMOS switches

associated with the current sources and is typically 100 kΩ in

AD9740W

Rev. 0 | Page 14 of 20

parallel with 5 pF. It is also slightly dependent on the output

voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS

device. As a result, maintaining IOUTA and/or IOUTB at a

virtual ground via an I-V op amp configuration results in the

optimum dc linearity. Note that the INL/DNL specifications for

the AD9740W are measured with IOUTA maintained at a

virtual ground via an op amp.

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The negative output compliance range

of −1 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit can result in a

breakdown of the output stage and affect the reliability of the

AD9740W.

The positive output compliance range is slightly dependent on

the full-scale output current, IOUTFS. It degrades slightly from its

nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA.

The optimum distortion performance for a single-ended or

differential output is achieved when the maximum full-scale

signal at IOUTA and IOUTB does not exceed 0.5 V.

DIGITAL INPUTS

The AD9740W digital section consists of 10 input bit channels

and a clock input. The 10-bit parallel data inputs follow stand-

ard positive binary coding, where DB9 is the most significant

bit (MSB) and DB0 is the least significant bit (LSB). IOUTA

produces a full-scale output current when all data bits are at

Logic 1. IOUTB produces a complementary output with the

full-scale current split between the two outputs as a function of

the input code.

DVDD

09489-024

DIGITAL

INPUT

Figure 25. Equivalent Digital Input

The digital interface is implemented using an edge-triggered

master/slave latch. The DAC output updates on the rising edge

of the clock and is designed to support a clock rate as high as

210 MSPS. The clock can be operated at any duty cycle that

meets the specified latch pulse width. The setup and hold times

can also be varied within the clock cycle as long as the specified

minimum times are met, although the location of these transition

edges can affect digital feedthrough and distortion performance.

Best performance is typically achieved when the input data

transitions on the falling edge of a 50% duty cycle clock.

CLOCK INPUT

The 28-lead TSSOP package option has a single-ended clock

input (CLOCK) that must be driven to rail-to-rail CMOS levels.

The quality of the DAC output is directly related to the clock

quality, and jitter is a key concern. Any noise or jitter in the

clock translates directly into the DAC output. Optimal perfor-

mance is achieved if the CLOCK input has a sharp rising edge,

because the DAC latches are positive edge triggered.

DAC TIMING

Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the relation-

ship between the position of the clock edges and the time at

which the input data changes. The AD9740W is rising edge

triggered, and so exhibits dynamic performance sensitivity

when the data transition is close to this edge. In general, the

goal when applying the AD9740W is to make the data transition

close to the falling clock edge. This becomes more important as

the sample rate increases. Figure 26 shows the relationship of

SFDR to clock placement with different sample rates. Note that

at the lower sample rates, more tolerance is allowed in clock

placement, while at higher rates, more care must be taken.

–3 –2 2–1 0 1

CLOCK PL ACE MENT ( ns)

SFDR (dB)

40 50MHz S FDR

20MHz S FDR

50MHz S FDR

02911

026

09489-026

Figure 26. SFDR vs. Clock Placement @

fOUT = 20 MHz and 50 MHz (fCLOCK = 165 MSPS)

Sleep Mode Operation

The AD9740W has a power-down function that turns off the

output current and reduces the supply current to less than 6 mA

over the specified supply range of 2.7 V to 3.6 V and the tempera-

ture range. This mode can be activated by applying a Logic

Level 1 to the SLEEP pin. The SLEEP pin logic threshold is

equal to 0.5 Ω AVDD. This digital input also contains an active

pull-down circuit that ensures that the AD9740W remains

enabled if this input is left disconnected. The AD9740W takes

less than 50 ns to power down and approximately 5 μs to power

back up.

AD9740W

Rev. 0 | Page 15 of 20

POWER DISSIPATION

The power dissipation, PD, of the AD9740W is dependent on

several factors that include:

• The power supply voltages (AVDD and DVDD)

• The full-scale current output (IOUTFS)

• The update rate (fCLOCK)

• The reconstructed digital input waveform

The power dissipation is directly proportional to the analog

supply current, IAVDD, and the digital supply current, IDVDD. IAV DD

is directly proportional to IOUTFS, as shown in Figure 27, and is

insensitive to fCLOCK. Conversely, IDVDD is dependent on both the

digital input waveform, fCLOCK, and digital supply DVDD. Figure 28

shows IDVDD as a function of full-scale sine wave output ratios

(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.

OUTFS

(mA)

AVDD

(mA)

4 6 8 101214161820

09489-027

Figure 27. IAVDD vs. IOUTFS

0.01 10.1

165MSPS

210MSPS

65MSPS

125MSPS

DVDD

(mA)

RATIO (

OUT

CLOCK

)

09489-055

Figure 28. IDVDD vs. Ratio at DVDD = 3.3 V

APPLYING THE AD9740W

Output Configurations

The following sections illustrate some typical output configura-

tions for the AD9740W. Unless otherwise noted, it is assumed

that IOUTFS is set to a nominal 20 mA. For applications requiring

the optimum dynamic performance, a differential output

configuration is suggested. A differential output configuration

can consist of either an RF transformer or a differential op amp

configuration. The transformer configuration provides the

optimum high frequency performance and is recommended for

any application that allows ac coupling. The differential op amp

configuration is suitable for applications requiring dc coupling,

bipolar output, signal gain, and/or level shifting within the

bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage

results if IOUTA and/or IOUTB is connected to an appropriately

sized load resistor, RLOAD, referred to ACOM. This configuration

can be more suitable for a single-supply system requiring a dc-

coupled, ground referred output voltage. Alternatively, an amplifier

could be configured as an I-V converter, thus converting IOUTA

or IOUTB into a negative unipolar voltage. This configuration

provides the best dc linearity because IOUTA or IOUTB is main-

tained at a virtual ground.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-single-

ended signal conversion, as shown in Figure 29. A differentially

coupled transformer output provides the optimum distortion

performance for output signals whose spectral content lies

within the transformer’s pass band. An RF transformer, such

as the Mini-Circuits® T1–1T, provides excellent rejection of

common-mode distortion (that is, even-order harmonics) and

noise over a wide frequency range. It also provides electrical

isolation and the ability to deliver twice the power to the load.

Transformers with different impedance ratios can also be used

for impedance matching purposes. Note that the transformer

provides ac coupling only.

LOAD

AD9740W

OPTIONAL RDIFF

IOUTA

IOUTB

09489-030

MINI-CIRCUITS

T1-1T

Figure 29. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be

connected to ACOM to provide the necessary dc current path

for both IOUTA and IOUTB. The complementary voltages

appearing at IOUTA and IOUTB (that is, VOUTA and VOUTB)

swing symmetrically around ACOM and should be maintained

with the specified output compliance range of the AD9740W. A

differential resistor, RDIFF, can be inserted in applications where

the output of the transformer is connected to the load, RLOAD,

via a passive reconstruction filter or cable. RDIFF is determined

by the transformer’s impedance ratio and provides the proper

source termination that results in a low VSWR. Note that approxi-

mately half the signal power is dissipated across RDIFF.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-single-

ended conversion, as shown in Figure 30. The AD9740W is

configured with two equal load resistors, RLOAD, of 25 Ω. The

AD9740W

Rev. 0 | Page 16 of 20

differential voltage developed across IOUTA and IOUTB is

converted to a single-ended signal via the differential op amp

configuration. An optional capacitor can be installed across

IOUTA and IOUTB, forming a real pole in a low-pass filter. The

addition of this capacitor also enhances the op amp’s distortion

performance by preventing the DAC’s high slewing output from

overloading the op amp’s input.

AD9740W

IOUTA

IOUTB C

OPT

500Ω

225Ω

500Ω

25Ω25Ω

AD8047

09489-031

Figure 30. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically

determined by the resistor matching. In this circuit, the differential

op amp circuit using the AD8047 is configured to provide some

additional signal gain. The op amp must operate off a dual

supply because its output is approximately ±1 V. A high speed

amplifier capable of preserving the differential performance of the

AD9740W while meeting other system level objectives (that is,

cost or power) should be selected. The op amp’s differential

gain, gain setting resistor values, and full-scale output swing

capabilities should all be considered when optimizing this

circuit.

The differential circuit shown in Figure 31 provides the

necessary level shifting required in a single-supply system. In

this case, AVDD, which is the positive analog supply for both

the AD9740W and the op amp, is also used to level shift the

differential output of the AD9740W to midsupply (that is,

AVDD/2). The AD8041 is a suitable op amp for this application.

AD9740W

IOUTA

IOUTB C

OPT

500

Ω

225Ω

1kΩ25Ω25Ω

AD8041

1kΩAVDD

09489-032

Figure 31. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

Figure 32 shows the AD9740W configured to provide a unipo-

lar output range of approximately 0 V to 0.5 V for a doubly

terminated 50 Ω cable because the nominal full-scale current,

IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 Ω. In

this case, RLOAD represents the equivalent load resistance seen by

IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can

be connected to ACOM directly or via a matching RLOAD. Different

values of IOUTFS and RLOAD can be selected as long as the positive

compliance range is adhered to. One additional consideration

in this mode is the integral nonlinearity (INL), discussed in the

Analog Outputs section. For optimum INL performance, the

single-ended, buffered voltage output configuration is suggested.

AD9740W

IOUTA

IOUTB

50Ω

25Ω

OUTA

=0VTO0.5V

OUTFS

= 20mA

50Ω

09489-033

Figure 32. 0 V to 0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

CONFIGURATION

Figure 33 shows a buffered single-ended output configuration

in which the op amp U1 performs an I-V conversion on the

AD9740W output current. U1 maintains IOUTA (or IOUTB) at

a virtual ground, minimizing the nonlinear output impedance

effect on the DAC’s INL performance as described in the Analog

Outputs section. Although this single-ended configuration typi-

cally provides the best dc linearity performance, its ac distortion

performance at higher DAC update rates can be limited by U1’s

slew rate capabilities. U1 provides a negative unipolar output

voltage, and its full-scale output voltage is simply the product of

RFB and IOUTFS. The full-scale output should be set within U1’s

voltage output swing capabilities by scaling IOUTFS and/or RFB.

An improvement in ac distortion performance can result with a

reduced IOUTFS because U1 is required to sink less signal current.

AD9740W

IOUTA

IOUTB

OPT

200Ω

OUT

= I

OUTFS

× R

OUTFS

=10mA

09489-034

200Ω

Figure 33. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS,

POWER SUPPLY REJECTION

Many applications seek high speed and high performance

under less than ideal operating conditions. In these application

circuits, the implementation and construction of the printed

circuit board is as important as the circuit design. Proper RF

techniques must be used for device selection, placement, and

routing as well as power supply bypassing and grounding to

ensure optimum performance.

One factor that can measurably affect system performance is

the ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution.

This is referred to as the power supply rejection ratio (PSRR).

For dc variations of the power supply, the resulting performance

of the DAC directly corresponds to a gain error associated with

the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies

is common in applications where the power distribution is

AD9740W

Rev. 0 | Page 17 of 20

generated by a switching power supply. Typically, switching

power supply noise occurs over the spectrum from tens of

kilohertz to several megahertz. The PSRR vs. frequency of the

AD9740W AVDD supply over this frequency range is shown in

Figure 34.

FRE QUENCY (MHz)

40 1268100

PSRR (d B)

09489-035

Figure 34. Power Supply Rejection Ratio (PSRR)

Note that the ratio in Figure 34 is calculated as amps out/volts

in. Noise on the analog power supply has the effect of modulating

the internal switches, and therefore the output current. The

voltage noise on AVDD, therefore, is added in a nonlinear

manner to the desired IOUT. Due to the relative different size of

these switches, the PSRR is very code dependent. This can produce

a mixing effect that can modulate low frequency power supply

noise to higher frequencies. Worst-case PSRR for either one of

the differential DAC outputs occur when the full-scale current

is directed toward that output.

As a result, the PSRR measurement in Figure 34 represents a

worst-case condition in which the digital inputs remain static

and the full-scale output current of 20 mA is directed to the

DAC output being measured.

The following illustrates the effect of supply noise on the analog

supply. Suppose a switching regulator with a switching frequency

of 250 kHz produces 10 mV of noise and, for simplicity’s sake

(ignoring harmonics), all of this noise is concentrated at 250 kHz.

To calculate how much of this undesired noise appears as current

noise superimposed on the DAC’s full-scale current, IOUTFS, users

must determine the PSRR in dB using Figure 34 at 250 kHz. To

calculate the PSRR for a given RLOAD, such that the units of PSRR

are converted from A/V to V/V, adjust the curve in Figure 34 by

the scaling factor 20 Ω log (RLOAD). For instance, if RLOAD is 50 Ω,

then the PSRR is reduced by 34 dB (that is, PSRR of the DAC at

250 kHz, which is 85 dB in Figure 34, becomes 51 dB VOUT/VIN).

Proper grounding and decoupling should be a primary objec-

tive in any high speed, high resolution system. The AD9740W

features separate analog and digital supplies and ground pins to

optimize the management of analog and digital ground currents

in a system. In general, AVDD, the analog supply, should be

decoupled to ACOM, the analog common, as close to the chip

as physically possible. Similarly, DVDD, the digital supply,

should be decoupled to DCOM as close to the chip as physically

possible.

For those applications that require a single 3.3 V supply for both

the analog and digital supplies, a clean analog supply can be

generated using the circuit shown in Figure 35. The circuit

consists of a differential LC filter with separate power supply

and return lines. Lower noise can be attained by using low ESR

type electrolytic and tantalum capacitors.

FERRITE

BEADS AVDD

ACOM

09489-036

TTL/CMOS

LOGIC

CIRCUITS

3.3V

POWER SUPPLY

100µF

ELECT. 0.1µF

CER.

10µF TO

22µF

TANT.

Figure 35. Differential LC Filter for Single 3.3 V Applications

AD9740W

Rev. 0 | Page 18 of 20

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-153-AE

28 15

141

8°

0°

SEATING

PLANE

OPLANARIT

0.10

1.20 MAX

6.40 BSC

0.65

BSC

PIN 1

0.30

0.19 0.20

0.09

4.50

4.40

4.30

0.75

0.60

0.45

9.80

9.70

9.60

0.15

0.05

Figure 36. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2 Temperature Range Package Description Package Option

AD9740WARUZ −40°C to +105°C 28-Lead TSSOP RU-28

AD9740WARUZRL7 −40°C to +105°C 28-Lead TSSOP RU-28

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The AD9740W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

AD9740W

Rev. 0 | Page 19 of 20

NOTES

AD9740W

Rev. 0 | Page 20 of 20

NOTES

registered trademarks are the property of their respective owners.

D09489-0-12/10(0)