Standard Products UT8CR512K32 16 Megabit SRAM Advanced Data Sheet March 2005 www.aeroflex.com/4MSRAM FEATURES 17ns maximum access time Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volts, 1.8 volt core Radiation performance - Intrinsic total-dose: 300 Krad(Si) INTRODUCTION The UT8CR512K32 is a high-performance CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 words by 8 bit SRAMs with common output enable. Easy memory expansion is provided by active LOW chip enables (E), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. - SEL Immune >100 MeV-cm2/mg - LETth (0.25): 53.0 MeV-cm2/mg - Memory Cell Saturated Cross Section 1.67E-7cm2/bit - Neutron Fluence: 3.0E14n/cm2 - Dose Rate - Upset 1.0E9 rad(Si)/sec - Latchup 1.0E11 rad(Si)/sec Packaging options: - 68-lead ceramic quad flatpack (20.238 grams with lead frame) Standard Microcircuit Drawing 5962-04227 - QML compliant part E3 W3 E2 Writing to each memory is accomplished by taking the corresponding chip enable (E) input LOW and write enable (W) input LOW. Data on the I/O pins is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking the chip enable (E) and output enable (G) LOW while forcing write enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The input/output pins are placed in a high impedance state when the device is deselected (E HIGH), the outputs are disabled (G HIGH), or during a write operation (E LOW and W LOW). Perform 8, 16, 24 or 32 bit accesses by making W along with E a common input to any combination of the discrete memory die. W2 E1 W1 W0 E0 A(18:0) G 512K x 8 512K x 8 DQ(31:24) or DQ3(7:0) DQ(23:16) or DQ2(7:0) 512K x 8 DQ(15:8) or DQ1(7:0) Figure 1. UT8CR512K32 SRAM Block Diagram 1 512K x 8 DQ(7:0) or DQ0(7:0) VDD1 A0 A1 A2 A3 A4 A5 E2 VSS E3 W0 A6 A7 A8 A9 A10 VDD2 DEVICE OPERATION 68 67 66 65 64 63 62 61 60 59 58 57 56 555453 52 1 51 2 50 3 49 4 48 5 47 Top View 6 46 7 45 8 44 9 43 10 42 11 41 12 40 13 39 14 38 15 37 16 36 17 35 1819 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Each die in the UT8CR512K32 has three control inputs called Enable (E), Write Enable (W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The device enable (E) controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to each memory die by selecting the 2,048,000 byte of memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) VSS DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3) Table 1. Device Operation Truth Table VDD2 A11 A12 A13 A14 A15 A16 E0 G E1 A17 W1 W2 W3 A18 VDD1 VSS DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) VSS DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1) Figure 2. 17ns SRAM Pinout 68) Address DQ(7:0) Data Input/Output E Enable W Write Enable G Output Enable VDD1 Power (1.8V) VDD2 Power (3.3V) VSS W E I/O Mode Mode X X 1 3-state Standby X 0 0 Data in Write 1 1 0 3-state Read2 0 1 0 Data out Read Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. PIN NAMES A(18:0) G READ CYCLE A combination of W greater than VIH (min) with E and G less than VIL (max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. SRAM read Cycle 1, the Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQn(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). Ground SRAM read Cycle 2, the Chip Enable-controlled Access is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQn(7:0). SRAM read Cycle 3, the Output Enable-controlled Access is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. 2 WRITE CYCLE The UT8CR512K32 SRAM incorporates special design and layout features which allows operation in a limited radiation environment. A combination of W less than VIL(max) and E less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than VIH(min), or when W is less than VIL(max). Table 2. Radiation Hardness Design Specifications1 Write Cycle 1, the Write Enable-controlled Access is defined by a write terminated by W going high, with E still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by tETWH when the write is initiated by E. Unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQn(7:0) to avoid bus contention. Total Dose 300K rad(Si) Heavy Ion Error Rate2 8.9x10-10 Errors/Bit-Day Notes: 1. The SRAM is immune to latchup to particles >100MeV-cm2/mg. 2. 10% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum. Write Cycle 2, the Chip Enable-controlled Access is defined by a write terminated by the former of E or W going inactive. The write pulse width is defined by tWLEF when the write is initiated Supply Sequencing No supply voltage sequencing is required between VDD1 and VDD2. by W, and by tETEF when the write is initiated by the E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQn (7:0) to avoid bus contention. RADIATION HARDNESS 3 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD1 DC supply voltage -0.3 to 2.0V VDD2 DC supply voltage -0.3 to 3.8V VI/O Voltage on any pin -0.3 to 3.8V TSTG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature2 +150C Thermal resistance, junction-to-case3 5C/W DC input current 5 mA JC II 1.2W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD1 Positive supply voltage 1.7 to 1.9V VDD2 Positive supply voltage 3.0 to 3.6V TC Case temperature range (C) Screening: -55 to +125C (W) Screening: -40 to +125C VIN DC input voltage 0V to VDD2 4 DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)* (-55C to +125C for (C) screening and -40C to 125C for (W) screening) SYMBOL PARAMETER CONDITION MIN MAX VIH High-level input voltage VIL Low-level input voltage VOL1 Low-level output voltage IOL = 8mA,VDD2 =VDD2 (min) VOH1 High-level output voltage IOH = -4mA,VDD2 =VDD2 (min) CIN1 Input capacitance = 1MHz @ 0V 44 pF CIO1 Bidirectional I/O capacitance = 1MHz @ 0V 21 pF IIN Input leakage current VIN = VDD2 and VSS -2 2 A IOZ Three-state output leakage current VO = VDD2 and VSS, VDD2 = VDD2 (max) G = VDD2 (max) -2 2 A IOS2, 3 Short-circuit output current VDD2 = VDD2 (max), VO = VDD2 VDD2 = VDD2 (max), VO = VSS -100 +100 mA IDD1(OP1) Supply current operating @ 1MHz Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 40 mA IDD1(OP2) Supply current operating @58.8MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 100 mA IDD2(OP1) Supply current operating @ 1MHz Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) .35 mA IDD2(OP2) Supply current operating @58.8MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 11 mA IDD1(SB)4 Supply current standby @ 0Hz CMOS inputs , IOUT = 0 E = VDD2 -0.2 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 35 m 5 A CMOS inputs , IOUT = 0 E = VDD2 - 0.2 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 35 m 5 A IDD2(SB)4 IDD1(SB)4 IDD2(SB)4 Supply current standby A(18:0) @ 58.8MHz .7*VDD2 UNIT Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si). 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. VIH = VDD2 (max), VIL = 0V. 5 V .3*VDD2 V .2*VDD2 V .8*VDD2 V AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)* (-55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min)) SYMBOL PARAMETER UNIT 8CR512-155 MIN MAX tAVAV1 Read cycle time 17 ns tAVQV Read access time tAXQX2 Output hold time 3 ns tGLQX1,2 G-controlled output enable time 0 ns 17 ns tGLQV G-controlled read access time 7 ns tGHQZ2 G-controlled output three-state time 7 ns tETQX2,3 E-controlled output enable time 5 ns tETQV3 E-controlled access time 17 ns tEFQZ4 E-controlled output three-state time2 10 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Guaranteed, but not tested. 2. Three-state is defined as a 200mV change from steady-state output voltage. 3. The ET (enable true) notation refers to the latter falling edge of E. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the latter rising edge of E. SEU immunity does not affect the read parameters. 6 tAVAV A(18:0) DQn(7:0) Previous Valid Data Valid Data tAVQV tAXQX Assumptions: 1. E and G < VIL (max) and W > VIH (min) Figure 3a. SRAM Read Cycle 1: Address Access A(18:0) E tETQV DQn(7:0) tEFQZ tETQX DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Figure 3b. SRAM Read Cycle 2: Chip Enable-Controlled Access tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQn(7:0) Assumptions: 1. E < VIL (max) and W > VIH (min) tGLQV Figure 3c. SRAM Read Cycle 3: Output Enable-Controlled Access 7 AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)* (-55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min)) SYMBOL PARAMETER UNIT 8CR512-15 MIN MAX tAVAV1 Write cycle time 17 ns tETWH Device enable to end of write 12 ns tAVET Address setup time for write (E- controlled) 0 ns tAVWL Address setup time for write (W - controlled) 0 ns tWLWH Write pulse width 12 ns tWHAX Address hold time for write (W - controlled) 2 ns tEFAX Address hold time for device enable (E- controlled) 0 ns tWLQZ2 W - controlled three-state time 5 tWHQX2 W - controlled output enable time 4 ns tETEF Device enable pulse width (E - controlled) 12 ns tDVWH Data setup time 7 ns tWHDX Data hold time 2 ns tWLEF Device enable controlled write pulse width 12 ns tDVEF Data setup time 12 ns tEFDX Data hold time 0 ns tAVWH Address valid to end of write 12 ns tWHWL1 Write disable time 3 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Test with G high. 2. Three-state is defined as 200mV change from steady-state output voltage. 8 ns A(18:0) E tAVWH tETWH tWHWL W tAVWL tWLWH tWHAX Qn(7:0) tWLQZ Dn(7:0) tWHQX APPLIED DATA Assumptions: 1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be in three-state for the entire cycle. tDVWH tWHDX Figure 4a. SRAM Write Cycle 1: Write Enable - Controlled Access 9 A(18:0) tETEF tAVET tEFAX E or tAVET E W tETEF tEFAX tWLEF Dn(7:0) APPLIED DATA tWLQZ tDVEF Qn(7:0) tEFDX Assumptions & Notes: 1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle. 2. Either E scenario above can occur. Figure 4b. SRAM Write Cycle 2: Chip Enable - Controlled Access 10 DATA RETENTION CHARACTERISTICS (Pre-Radiation)* (VDD2 = VDD2 (min), 1 Sec DR Pulse) SYMBOL PARAMETER VDR MINIMUM MAXIMUM UNIT 1.0 1.0 -- V Data retention current -55C 25C 125C -- 500 500 30 A A mA Data retention current -40C 25 125C -- 500 500 30 A A mA 0 0 ns tAVAV tAVAV ns VDD1 for data retention IDDR 1 Device Type 1 IDDR 1 Device Type 2 tEFR1,2 tR1,2 Chip deselect to data retention time Operation recovery time Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. E = VDD2 all other inputs = VDD2 or VSS 2. VDD2 = 0 volts to VDD2 (max) DATA RETENTION MODE 1.7V 1.7V VDR > 1.0V VDD1 VIN >0.7VDD2 CMOS tR tEFR VSS E VDD2 VIN <0.3VDD2 CMOS Figure 5. Low VDD Data Retention Waveform CMOS 90% VDD2-0.05V 188 ohms 1.4V 10% 0.0V < 2ns 50pF < 2ns Input Pulses Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD2/2). Figure 6. AC Test Loads and Input Waveforms 11 PACKAGING Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF38535. 4. Ceramic shall be dark alumina. 5. Letter designations are to cross reference to MIL-STD-1835. 6. Dogleg geometries are optional within dimensions shown. 7. These areas may have notches and tabs different than shown. 8. Lead true position tolerances and coplanarity are not measured. 9. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in the repaired area. 10. Numbering and lettering on the ceramic are not subject to visual or marking criteria. Figure 7. 68-pin Ceramic FLATPACK 12 ORDERING INFORMATION 512K32 SRAM: UT **** * - * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (-55C to +125C) (P) = Prototype flow (W) = Extended industrial temperature range flow (-40C to +125C) Package Type: (V) = 68-lead ceramic FP Access Time: (17) = 17ns access time Device Type: (8CR512K32) = 512K x 32SRAM Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither tested nor guaranteed. 13 512K x 32 SRAM: SMD 5962 - 04227 *** * * ** * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 68-lead ceramic flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type (01) = 17ns access time, CMOS I/O, 68-lead flatpack package (-55C to +125C) (02) = 17ns access time, CMOS I/O, 68-lead flatpack package (-40C to +125C) (02TBD)=15ns access time, CMOS I/O, 40-lead flatpack package, dual chip enable (not available) Drawing Number: 04227 Total Dose: (R) = 100K rad(Si) (F) = 300K rad(Si) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 14 NOTES 15 COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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