2009-2014 Microchip Technology Inc. DS20002197C-page 1
MCP631/2/3/4/5/9
Features:
• Gain-Bandwidth Product: 24 MHz
• Slew Rate: 10 V/µs
• Noise: 10 nV/Hz at 1 MHz)
• Low Input Bias Current: 4 pA (typical)
• Ease of Use:
- Unity-Gain Stable
- Rail-to-Rail Output
- Input Range including Negative Rail
- No Phase Reversal
• Supply Voltage Range: +2.5V to +5.5V
• High Output Current: ±70 mA
• Supply Current: 2.5 mA/ch (typical)
• Low-Power Mode: 1 µA/ch
• Small Packages: SOT23-5, DFN
• Extended Temperature Range: -40°C to +125°C
Typical Applications:
• Fast Low-Side Current Sensing
• Point-of-Load Control Loops
• Power Amplifier Control Loops
• Barcode Scanners
• Optical Detector Amplifier
• Multi-Pole Active Filter
Design Aids:
• SPICE Macro Models
•FilterLab
® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Description:
The Microchip Technology Inc. MCP631/2/3/4/5/9
family of operational amplifiers features high gain
bandwidth product (24 MHz, typical) and high output
short-circuit current (70 mA, typical). Some also
provide a Chip Select (CS) pin that supports a
low-power mode of operation. These amplifiers are
optimized for high speed, low noise and distortion,
single-supply operation with rail-to-rail output and an
input that includes the negative rail.
This family is offered in single (MCP631), single with
CS pin (MCP633), dual (MCP632), dual with two CS
pins (MCP635), quad (MCP634) and quad with two
Chip Select pins (MCP639). All devices are fully
specified from -40°C to +125°C.
Typical Application Circuit
VOUT
0A – 20 A
MCP63X
0.005
51.1
51.12.0 k
+5V
0V – 4V
+
-
High Gain-Bandwidth Op Amp Portfolio
Model Family Channels/Package Gain-Bandwidth VOS (max.) IQ/Ch (typ.)
MCP621/1S/2/3/4/5/9 1, 2, 4 20 MHz 0.2 mV 2.5 mA
MCP631/2/3/4/5/9 1, 2, 4 24 MHz 8.0 mV 2.5 mA
MCP651/1S/2/3/4/5/9 1, 2, 4 50 MHz 0.2 mV 6.0 mA
MCP660/1/2/3/4/5/9 1, 2, 3, 4 60 MHz 8.0 mV 6.0 mA
24 MHz, 2.5 mA Rail-to-Rail Output (RRO) Op Amps
MCP631/2/3/4/5/9
DS20002197C-page 2 2009-2014 Microchip Technology Inc.
Package Types
MCP631
SOIC
MCP632
SOIC
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NCNC
VINA+
VINA–
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB-
VINB+
MCP635
MSOP
VINA+
VINA–
VSS
1
2
3
4
10
9
8
7
VOUTA VDD
VOUTB
VINB-
VINB+
CSA5 6 CSB
MCP632
3x3 DFN*
VINA+
VINA–
VSS
VOUTA VDD
VOUTB
VINB–
VINB+
* Includes Exposed Thermal Pad (EP); see Tabl e 3- 1.
1
2
3
4
8
7
6
5
MCP633
SOIC
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
CS
NC
MCP634
SOIC, TSSOP
VINA+
VINA-
VDD
1
2
3
4
14
13
12
11
VOUTA VOUTD
VIND-
VIND+
VSS
VINB+510 VINC+
VINB-69
VOUTB 7 8 VOUTC
VINC-
2
VDD
VINB+
VINA-VIND+
VSS
VINB-
VINC+
VOUTB
CSBC
VOUTC
VINC-
VOUTA
CSAD
VOUTD
VIND-
VINA+EP
16
1
15 14 13
3
4
12
11
10
9
5678
17
MCP639
4x4 QFN*
EP
9
MCP631
2x3 TDFN*
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NCNC
EP
9
VIN+
VOUT
VSS
VIN-
MCP631
SOT-23-5
VDD
1
2
34
5
CS
VIN+
VOUT
VSS
VIN-
MCP633
SOT-23-6
VDD
1
2
34
5
6
MCP635
3x3 DFN*
VINA+
VINA–
CSA
VOUTA VDD
VOUTB
VINB-
CSB
1
2
3
5
10
9
8
6
VSS VINB+
4
7
EP
11
2009-2014 Microchip Technology Inc. DS20002197C-page 3
MCP631/2/3/4/5/9
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD –V
SS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD +1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD +0.3V
Output Short-Circuit Current ................................Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Maximum Junction Temperature ................................ +150°C
ESD protection on all pins (HBM, MM) 1 kV, 200V
†Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
1.2 Specifications
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/3,
VOUT VDD/2, VL=V
DD/2, RL=2k to VL and CS =V
SS (refer to Figure 1-2).
Parameters Sym. Min. Typ. Max. Units Conditions
Input Offset
Input Offset Voltage VOS -8 ±1.8 +8 mV
Input Offset Voltage Drift VOS/TA—±2.0—µV/°CT
A= -40°C to +125°C
Power Supply Rejection Ratio PSRR 61 76 — dB
Input Current and Impedance
Input Bias Current IB—4—pA
Across Temperature IB— 100 — pA TA=+85°C
Across Temperature IB— 1500 5000 pA TA= +125°C
Input Offset Current IOS —±2—pA
Common-Mode Input Impedance ZCM —10
13||9 — ||pF
Differential Input Impedance ZDIFF —10
13||2 — ||pF
Common Mode
Common-Mode Input Voltage Range VCMR VSS 0.3 — VDD 1.3 V Note 1
Common-Mode Rejection Ratio CMRR 63 78 — dB VDD =2.5V, V
CM = -0.3V to 1.2V
66 81 — dB VDD =5.5V, V
CM = -0.3V to 4.2V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 88 115 — dB VDD =2.5V, V
OUT = 0.3V to 2.2V
94 124 — dB VDD =5.5V, V
OUT = 0.3V to 5.2V
Output
Maximum Output Voltage Swing VOL, VOH VSS +20 — V
DD 20 mV VDD =2.5V, G=+2,
0.5V Input Overdrive
VSS +40 — V
DD 40 mV VDD =5.5V, G=+2,
0.5V Input Overdrive
Output Short-Circuit Current ISC ±40 ±85 ±130 mA VDD =2.5V (Note 2)
ISC ±35 ±70 ±110 mA VDD =5.5V (Note 2)
Power Supply
Supply Voltage VDD 2.5 — 5.5 V
Quiescent Current per Amplifier IQ1.2 2.5 3.6 mA No Load Current
Note 1: See Figure 2-5 for temperature effects.
2: The ISC specifications are for design guidance only; they are not tested.
MCP631/2/3/4/5/9
DS20002197C-page 4 2009-2014 Microchip Technology Inc.
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2,
VOUT VDD/2, VL=V
DD/2, RL=2k to VL, CL= 50 pF and CS =V
SS (refer to Figure 1-2).
Parameters Sym. Min. Typ. Max. Units Conditions
AC Response
Gain-Bandwidth Product GBWP — 24 — MHz
Phase Margin PM — 65 — ° G = +1
Open-Loop Output Impedance ROUT —20—
AC Distortion
Total Harmonic Distortion plus Noise THD + N — 0.0015 — % G = +1, VOUT =2V
P-P
, f = 1 kHz,
VDD =5.5V, BW=80kHz
Step Response
Rise Time, 10% to 90% tr—20—nsG=+1, V
OUT = 100 mVP-P
Slew Rate SR — 10 — V/µs G = +1
Noise
Input Noise Voltage Eni —16—µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —10—nV/Hz f = 1 MHz
Input Noise Current Density ini 4—fA/Hz f = 1 kHz
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VCM =V
DD/2,
VOUT VDD/2, VL=V
DD/2, RL=2k to VL, CL= 50 pF and CS =V
SS (refer to Figures 1-1 and 1-2).
Parameters Sym. Min. Typ. Max. Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —0.1—nACS=0V
CS High Specifications
CS Logic Threshold, High VIH 0.8VDD VDD V
CS Input Current, High ICSH —0.7—µACS=V
DD
GND Current ISS -2 -1 —µA
CS Internal Pull-Down Resistor RPD —5—M
Amplifier Output Leakage IO(LEAK) —50—nACS=V
DD, TA= +125°C
CS Dynamic Specifications
CS Input Hysteresis VHYST —0.25 —V
CS High to Amplifier Off Time
(output goes High Z)
tOFF — 200 — ns G = +1 V/V, VL=V
SS,
CS=0.8V
DD to VOUT =0.1(V
DD/2)
CS Low to Amplifier On Time tON —210µs
G=+1V/V, V
L=V
SS,
CS=0.2V
DD to VOUT =0.9(V
DD/2)
2009-2014 Microchip Technology Inc. DS20002197C-page 5
MCP631/2/3/4/5/9
1.3 Timing Diagram
FIGURE 1-1: Timing Diagram.
1.4 Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-2. It independently sets VCM and VOUT
; see
Equation 1-1. The circuit’s Common-Mode voltage is
(VP+V
M)/2, not VCM. VOST includes VOS plus the
effects of temperature, CMRR, PSRR and AOL.
EQUATION 1-1:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 201.0 — °C/W
Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W
Thermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/W
Thermal Resistance, 8L-3x3 DFN θJA — 56.7 — °C/W Note 2
Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W
Thermal Resistance, 10L-3x3 DFN θJA — 54.0 — °C/W Note 2
Thermal Resistance, 10L-MSOP θJA — 202 — °C/W
Thermal Resistance, 14L-SOIC θJA — 90.8 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Thermal Resistance, 16L-4x4-QFN θJA — 52.1 — °C/W Note 2
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
2: Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.
VOUT
ISS
ICS
-1 µA
High Z
0.7 µA
On
-2.5 mA -1 µA
tON tOFF
High Z
0.1 nA 0.7 µA
CS VIL VIH
(typical) (typical) (typical)
(typical)
(typical) (typical)
Where:
GDM = Differential Mode Gain (V/V)
GN= Noise Gain (V/V)
VCM = Op Amp’s Common-Mode
Input Voltage
(V)
VOST = Op Amp’s Total Input Offset
Voltage
(mV)
GDM RF
RG
-------=
GN1G
DM
+=
VCM VP11
GN
-------–
VREF 1
GN
-------
+=
VOST VIN- VIN+
–=
VOUT VREF VPVM
–GDM VOSTGN
++=
MCP631/2/3/4/5/9
DS20002197C-page 6 2009-2014 Microchip Technology Inc.
FIGURE 1-2: AC and DC Test Circuit for
Most Specifications.
VDD
RGRF
VOUT
VM
CB2
CL
RL
VL
CB1
10 k
10 k
RGRF
VREF =V
DD/2
VP
10 k
10 k
50 pF2k
2.2 µF100 nF
VIN-
VIN+
CF
CF
6.8 pF
MCP63X
6.8 pF
2009-2014 Microchip Technology Inc. DS20002197C-page 7
MCP631/2/3/4/5/9
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
2.1 DC Signal Inputs
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input Offset Voltage vs.
Power Supply Voltage with VCM =0V.
FIGURE 2-4: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-5: Low-Input Common-Mode
Voltage Headroom vs. Ambient Temperature.
FIGURE 2-6: High-Input Common-Mode
Voltage Headroom vs. Ambient Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
-6-5-4-3-2-10123456
Input Offset Voltage (mV)
Percentage of Occurrences
396 Samples
TA = +25°C
VDD = 2.5V and 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
-8-7-6-5-4-3-2-1012345678
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
398 Samples
VDD = 2.5V and 5.5V
TA = -40°C to +125°C
-4.0
-3.8
-3.6
-3.4
-3.2
-3.0
-2.8
-2.6
-2.4
-2.2
-2.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
Input Offset Voltage (mV)
+125°C
+85°C
+25°C
-40°C
Representative Part
VCM = VSS
-3.0
-2.8
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (mV)
VDD = 2.5V
VDD = 5.5V
Representative Part
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Low Input Common
Mode Headroom (V)
1 Lot
Low (VCMR_L – VSS)
VDD = 2.5V and 5.5V
0.9
1.0
1.1
1.2
1.3
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
High Input Common
Mode Headroom (V)
VDD = 2.5V
VDD = 5.5V
1 Lot
High (VDD – VCMR_H)
MCP631/2/3/4/5/9
DS20002197C-page 8 2009-2014 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
FIGURE 2-7: Input Offset Voltage vs.
Common-Mode V oltage with VDD =2.5V.
FIGURE 2-8: Input Offset Voltage vs.
Common-Mode V oltage with VDD =5.5V.
FIGURE 2-9: CMRR and PSRR vs.
Ambient Temperature.
FIGURE 2-10: DC Open-Loop Gain vs.
Ambient Temp er atu re.
FIGURE 2-11: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-12: Input Bias and Of fset
Currents vs. Ambient Temperature with
VDD =5.5V.
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Input Common Mode Voltage (V)
Input Offset Voltage (mV)
VDD = 2.5V
Representative Part
+125°C
+85°C
+25°C
-40°C
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Common Mode Voltage (V)
Input Offset Voltage (mV)
VDD = 5.5V
Representative Part
+125°C
+85°C
+25°C
-40°C
60
65
70
75
80
85
90
95
100
105
110
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CMRR, PSRR (dB)
PSRR
CMRR, VDD = 2.5V
CMRR, VDD = 5.5V
100
105
110
115
120
125
130
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.5V
95
100
105
110
115
120
125
130
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (Ω)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.5V
100 1k 10k 100k
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
25 45 65 85 105 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
VDD = 5.5V
VCM = VCMR_H
| IOS |
IB
1p
10p
100p
1n
10n
2009-2014 Microchip Technology Inc. DS20002197C-page 9
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
FIGURE 2-13: Input Bias Current vs. Input
Voltage (below VSS).
FIGURE 2-14: Input Bias and Offset
Currents vs. Common-Mode Input Voltage with
TA= +85°C.
FIGURE 2-15: Input Bias and Offset
Currents vs. Common-Mode Input Voltage with
TA= +125°C.
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
-200
-150
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
IB
Representative Part
TA = +85°C
VDD = 5.5V
IOS
-1500
-1000
-500
0
500
1000
1500
2000
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
IB
Representative Part
TA = +125°C
VDD = 5.5V
IOS
MCP631/2/3/4/5/9
DS20002197C-page 10 2009-2014 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
2.2 Other DC Voltages and Currents
FIGURE 2-16: Output Voltage Headroom
vs. Output Current.
FIGURE 2-17: Output Voltage Headroom
vs. Ambi ent Temperature.
FIGURE 2-18: Output Short-Circuit Current
vs. Power Supply Voltage.
FIGURE 2-19: Supply Current vs. Power
Supply Voltage.
FIGURE 2-20: Supply Current vs.
Common-Mode Input Voltage.
1
10
100
1000
0.1 1 10 100
Output Current Magnitude (mA)
Output Voltage Headroom
(mV)
VDD = 2.5V
VDD = 5.5V
VDD – VOH
VOL – VSS
0
2
4
6
8
10
12
14
16
18
20
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Headroom (mV)
VDD = 5.5V
VOL – V
SS
VDD = 2.5V VDD – VOH
RL = 2 kΩ
-100
-80
-60
-40
-20
0
20
40
60
80
100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Output Short Circuit Current
(mA)
+125°C
+85°C
+25°C
-40°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Supply Current
(mA/amplifier)
+125°C
+85°C
+25°C
-40°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Supply Current
(mA/amplifier)
VDD = 2.5V
VDD = 5.5V
2009-2014 Microchip Technology Inc. DS20002197C-page 11
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
2.3 Frequency Response
FIGURE 2-21: CMRR and PSRR vs.
Frequency.
FIGURE 2-22: Open-Loop Gain vs.
Frequency.
FIGURE 2-23: Gain-Bandwidth Product
and Phase Margin vs. Ambient Temperature.
FIGURE 2-24: Gain-Bandwidth Product
and Phase Margin vs. Common-Mode Input
Voltage.
FIGURE 2-25: Gain-Bandwidth Product
and Phase Margin vs. Output Voltage.
FIGURE 2-26: Closed-Loop Output
Impedance vs. Frequency.
10
20
30
40
50
60
70
80
90
100
1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7
Frequency (Hz)
CMRR, PSRR (dB)
100 1M10k 10M100k1k
CMRR
PSRR+
PSRR-
-20
0
20
40
60
80
100
120
140
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8
Frequency (Hz)
Open-Loop Gain (dB)
-240
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
| AOL |
AOL
100 10k 1M 100M
11k 100k 10M10
20
22
24
26
28
30
32
34
36
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
40
45
50
55
60
65
70
75
80
Phase Margin (°)
PM
GBWP
VDD = 5.5V
VDD = 2.5V
20
22
24
26
28
30
32
34
36
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Gain Bandwidth Product
(MHz)
40
45
50
55
60
65
70
75
80
Phase Margin (°)
PM
GBWP
VDD = 5.5V
VDD = 2.5V
20
22
24
26
28
30
32
34
36
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Gain Bandwidth Product
(MHz)
40
45
50
55
60
65
70
75
80
Phase Margin (°)
PM
GBWP
VDD = 5.5V
VDD = 2.5V
0.1
1
10
100
1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08
Frequency (Hz)
10k 1M 10M 100M
Closed-Loop Output Impedance (Ω
)
100k
G = 101 V/V
G = 11 V/V
G = 1 V/V
MCP631/2/3/4/5/9
DS20002197C-page 12 2009-2014 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
FIGURE 2-27: Gain Peaking vs.
Normalized Capacitive Load. FIGURE 2-28: Channel-to-Channel
Separation vs . Frequ enc y.
0
1
2
3
4
5
6
7
8
9
10
1.0E-11 1.0E-10 1.0E-09
Normalized Capacitive Load; CL/GN (F)
Gain Peaking (dB)
10p
100p
1n
GN
= 1 V/V
GN
= 2 V/V
GN
4 V/V
50
60
70
80
90
100
110
120
130
140
150
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Channel-to-Channel
Separation; RTI (dB)
1k 10k 100k
VCM = VDD/2
G = +1 V/V
RS = 10 kΩ
RS = 100 kΩ
1M 10M
RS = 0Ω
RS = 100Ω
RS = 1 kΩ
2009-2014 Microchip Technology Inc. DS20002197C-page 13
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
2.4 Noise and Distortion
FIGURE 2-29: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-30: Input Noise Voltage Density
vs. Input Common-Mode Voltage with
f=100Hz.
FIGURE 2-31: Input Noise Voltage Density
vs. Input Common-Mode Voltage with f = 1 MHz.
FIGURE 2-32: Input Noise vs. Time with
0.1 Hz Filter.
FIGURE 2-33: THD+N vs. Frequency.
1.E+0
1.E+1
1.E+2
1.E+3
1.E+4
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7
Frequency (Hz)
0.1 100 10k 1M
Input Noise Voltage Density (V/Hz)
1 1k 100k 10M10
1n
100n
1µ
10µ
10n
0
20
40
60
80
100
120
140
160
180
200
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
VDD = 5.5V
VDD
= 2.5V
Input Noise Voltage Density
(nV/Hz)
f = 100 Hz
0
2
4
6
8
10
12
14
16
18
20
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
VDD
= 5.5V
VDD
= 2.5
V
Input Noise Voltage Density
(nV/Hz)
f = 1 MHz
-20
-15
-10
-5
0
5
10
15
20
0 5 10 15 20 25 30 35 40 45 50 55 60 65
Time (min)
Input Noise; e ni(t) (µV)
Representative Part
Analog NPBW = 0.1 Hz
Sample Rate = 2 SPS
VOS = -3150 µV
0.0001
0.001
0.01
0.1
1
1.E+2 1.E+3 1.E+4 1.E+5
Frequency (Hz)
THD + Noise (%)
VDD = 5.0V
VOUT = 2 VP-P
100 1k 10k 100k
BW = 22 Hz to 80 kHz
BW = 22 Hz to > 500 kHz G = 1 V/V
G = 11 V/V
MCP631/2/3/4/5/9
DS20002197C-page 14 2009-2014 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
2.5 Time Response
FIGURE 2-34: Non-Inverting Small Signal
Step Respon se .
FIGURE 2-35: Non-Inverting Large Signal
Step Respon se .
FIGURE 2-36: Inverting Small Signal Step
Response.
FIGURE 2-37: Inverting Large Signal Step
Response.
FIGURE 2-38: The MCP631/2/3/ 4/5/9
Family Shows No Input Phase Reversal With
Overdrive.
FIGURE 2-39: Slew Rate vs. Ambien t
Temperature.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Time (µs)
Output Voltage (10 mV/div)
VDD = 5.5V
G = 1
VIN VOUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.00.20.40.60.81.01.21.41.61.82.0
Time (µs)
Output Voltage (V)
VDD = 5.5V
G = 1
VIN VOUT
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Time (µs)
Output Voltage (10 mV/div)
VDD = 5.5V
G = -1
RF = 1 kΩ
VIN
VOUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
Output Voltage (V)
VDD = 5.5V
G = -1
RF = 1 kΩ
VIN
VOUT
-1
0
1
2
3
4
5
6
7
012345678910
Time (ms)
Input, Output Voltages (V)
VDD = 5.5V
G = 2
VOUT
V
IN
0
2
4
6
8
10
12
14
16
18
20
22
24
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling Edge
Rising Edge
VDD = 2.5V
VDD = 5.5V
2009-2014 Microchip Technology Inc. DS20002197C-page 15
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
FIGURE 2-40: Maximum Output Voltage
Swing vs. Frequency.
0.1
1
10
1.E+05 1.E+06 1.E+07 1.E+08
Frequency (Hz)
Maximum Output Voltage
Swing (VP-P)
VDD
= 5.5V
VDD
= 2.5V
100k 1M 10M 100M
MCP631/2/3/4/5/9
DS20002197C-page 16 2009-2014 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
2.6 Chip Select Response
FIGURE 2-41: CS Current vs. Power
Supply Voltage.
FIGURE 2-42: CS and Output Voltages vs.
Time with VDD =2.5V.
FIGURE 2-43: CS and Output Voltages vs.
Time with VDD =5.5V.
FIGURE 2-44: CS Hysteresis vs. Ambient
Temperature.
FIGURE 2-45: CS Turn-On Time vs.
Ambient Temp er atu re.
FIGURE 2-46: CS Pull-Down Resistor
(RPD) vs. Ambient Temperature.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
CS Current (µA)
CS = VDD
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 2 4 6 8 101214161820
Time (µs)
CS, VOUT (V)
VDD = 2.5V
G = 1
VL = 0V
On
CS
VOUT
OffOff
-1
0
1
2
3
4
5
6
0 2 4 6 8 101214161820
Time (µs)
CS, VOUT (V)
VDD = 5.5V
G = 1
VL = 0V
On
CS
VOUT
OffOff
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CS Hysteresis (V)
VDD = 2.5V
VDD = 5.5V
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CS Turn On Time (µs)
VDD = 2.5V
VDD = 5.5V
0
1
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CS Pull-down Resistor
(MΩ)
Representative Part
2009-2014 Microchip Technology Inc. DS20002197C-page 17
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=2kto VL, CL= 50 pF and CS =V
SS.
FIGURE 2-47: Quiescent Current in
Shutdown vs. Power Supply Voltage. FIGURE 2-48: Output Leakage Current vs.
Output Voltage.
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Negative Power Supply
Current; I SS (µA)
CS = VDD
-40°C
+25°C
+85°C
+125°C
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
Output Leakage Current (A)
+25°C
+125°C
+85°C
CS = VDD = 5.5V
1µ
100n
10n
1n
100p
10p
MCP631/2/3/4/5/9
DS20002197C-page 18 2009-2014 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP631
MCP632
MCP633
MCP634
MCP635
MCP639
Symbol
Description
SOIC SOT
-23
2x3
TDFN SOIC 3x3
DFN SOIC SOT-
23 SOIC TSSOP MSOP 3x3
DFN QFN
242 222 4 2 2 2 21 V
IN-,
VINA-
Inverting Input (op amp A)
333 333 3 3 3 3 32V
IN+,
VINA+
Non-Inverting Input (op
amp A)
757 887 6 4 4 10103 V
DD Positive Power Supply
——— 5 5 — — 5 5 7 7 4 V
INB+ Non-Inverting Input (op
amp B)
——— 6 6 — — 6 6 8 8 5 V
INB- Inverting Input (op amp B)
——— 7 7 — — 7 7 9 9 6 V
OUTB Output (op amp B)
——— ——— — — — — — 7 CSBC Chip Select Digital Input
(op amp B and C)
——— ——— — 8 8 — —8 V
OUTC Output (op amp C)
——— ——— — 9 9 — —9 V
INC- Inverting Input (op amp C)
—— — ——— — 10 10 — —10V
INC+ Non-Inverting Input (op
amp C)
424 444 21111 4 411V
SS Negative Power Supply
—— — ——— — 12 12 — —12V
IND+ Non-Inverting Input (op
amp D)
—— — ——— — 13 13 — —13 V
IND- Inverting Input (op amp D)
—— — ——— — 14 14 — —14V
OUTD Output (op amp D)
——— ——— — — — — —15 CSAD Chip Select Digital Input
(op amp A and D)
616 116 1 1 1 1 116V
OUT
,
VOUTA
Output (op amp A)
— — 9 — 9 — — — — — 11 17 EP Exposed Thermal Pad
(EP); must be connected to
VSS
——— —— 8 5 — — 5 5—CS, CSAChip Select Digital Input
(op amp A)
——— ——— — — — 6 6— CSBChip Select Digital Input
(op amp B)
1,5,
8
—1, 5,
8
— — 1, 5 — — — — — — NC No Internal Connection
2009-2014 Microchip Technology Inc. DS20002197C-page 19
MCP631/2/3/4/5/9
3.1 Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.
3.3 Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In that case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4 Chip Select Digital Input (CS)
This input (CS) is a CMOS, Schmitt-triggered input that
places the part into a low-power mode of operation.
3.5 Exposed Thermal Pad (EP)
There is an internal connection between the exposed
thermal pad (EP) and the VSS pin; they must be
connected to the same potential on the printed circuit
board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
MCP631/2/3/4/5/9
DS20002197C-page 20 2009-2014 Microchip Technology Inc.
4.0 APPLICATIONS
The MCP631/2/3/4/5/9 family is manufactured using
the Microchip state-of-the-art CMOS process. It is
designed for low-cost, low-power and high-speed
applications. Its low supply voltage, low quiescent
current and wide bandwidth make the
MCP631/2/3/4/5/9 ideal for battery-powered
applications.
4.1 Input
4.1.1 PHASE REVERSAL
The input devices are designed to exhibit no phase
inversion when the input pins exceed the supply
voltages. Figure 2-38 shows an input voltage
exceeding both supplies with no phase inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The electrostatic discharge (ESD) protection on the
inputs can be depicted as shown in Figure 4-1. This
structure was chosen to protect the input transistors
and to minimize input bias current (IB). The input ESD
diodes clamp the inputs when they try to go more than
one diode drop below VSS. They also clamp any
voltages that go too far above VDD; their breakdown
voltage is high enough to allow normal operation and
low enough to bypass quick ESD events within the
specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-2 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN-) from going too far below ground, while the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN-) from going too far above VDD and
dump any currents onto VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. If so, the currents through the
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the
Common-Mode voltage (VCM) is below ground (VSS);
see Figure 2-13. Applications that are high-impedance
may need to limit the usable voltage range.
4.1.3 NORMAL OPERATION
The input stage of the MCP631/2/3/4/5/9 op amps uses
a differential PMOS input stage. It operates at low
Common-Mode input voltages (VCM), with VCM
between VSS – 0.3V and VDD – 1.3V. To ensure proper
operation, the input offset voltage (VOS) is measured at
both VCM =V
SS – 0.3V and VCM =V
DD –1.3V. See
Figures 2-5 and 2-6 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-3.
FIGURE 4-3: Unity-Gain Volta ge
Limitations for Linear Operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad VIN-
V1
R1
VDD
D1
VOUT
V2
R2
D2
MCP63X
R1VSS minimum expecte d V1
–
2mA
------------------------------------------------------------------------
R2VSS minimum expecte d V2
–
2mA
------------------------------------------------------------------------
VIN
VDD
VOUT
MCP63X
+
-
VSS VIN
VOUT VDD 1.3V–
2009-2014 Microchip Technology Inc. DS20002197C-page 21
MCP631/2/3/4/5/9
4.2 Rail-to-Rail Output
4.2.1 MAXIMUM OUTPUT VOLTAGE
The maximum output voltage (see Figures 2-16
and 2-17) describes the output range for a given load.
For instance, the output voltage swings to within 50 mV
of the negative rail with a 1 k load tied to VDD/2.
4.2.2 OUTPUT CURRENT
Figure 4-4 shows the possible combinations of output
voltage (VOUT) and output current (IOUT), when
VDD =5.5V.
IOUT is positive when it flows out of the op amp into the
external circuit.
FIGURE 4-4: Output Current .
4.2.3 POWER DISSIPATION
Since the output short-circuit current (ISC) is specified
at ±70 mA (typical), these op amps are capable of both
delivering and dissipating significant power.
FIGURE 4-5: Diagram for Power
Calculations.
Figure 4-5 shows the power calculations used for a
single op amp:
•R
SER is 0 in most applications and can be used
to limit IOUT
.
•V
OUT is the op amp’s output voltage.
•V
L is the voltage at the load.
•V
LG is the load’s ground point.
•V
SS is usually ground (0V).
The input currents are assumed to be negligible. The
currents shown in Figure 4-5 can be approximated
using Equation 4-1:
EQUATION 4-1:
The instantaneous op amp power (POA(t)), RSER power
(PRSER(t)) and load power (PL(t)) are:
EQUATION 4-2:
The maximum op amp power, for resistive loads,
occurs when VOUT is halfway between VDD and VLG or
halfway between VSS and VLG
.
EQUATION 4-3:
The maximum ambient to junction temperature rise
(TJA) and junction temperature (TJ) can be calculated
using POAmax, the ambient temperature (TA), the
package thermal resistance (JA, found in the
Temperature Specifications table) and the number of
op amps in the package (assuming equal power
dissipations), as shown in Equation 4-4:
EQUATION 4-4:
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
IOUT (mA)
VOUT (V)
RL = 10Ω
RL = 100Ω
RL = 1 kΩ
VOH Limited
VOL Limited
-ISC Limited
+ISC Limited
(VDD = 5.5V)
VDD
VL
RL
VLG
IDD
ISS
IL
IOUT RSER
VOUT
VSS
MCP63X
+
-
Where:
IQ= Quiescent supply current
IOUT ILVOUT VLG
–
RSER RL
+
------------------------------==
IDD IQmax 0, I OUT
+
ISS I–Qmin 0, IOUT
+
POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT)
PRSER(t) = IOUT2RSER
PL(t) = IL2RL
POAmax max2VDD VLG
–VLG VSS
–
4R
SER RL
+
-------------------------------------------------------------------------
Where:
n = Number of op amps in the package (1, 2)
TJA
POA t
JA nPOAmax
JA
=
TJTATJA
+=
MCP631/2/3/4/5/9
DS20002197C-page 22 2009-2014 Microchip Technology Inc.
The power derating across temperature for an op amp
in a particular package can be easily calculated
(assuming equal power dissipations):
EQUATION 4-5:
Several techniques are available to reduce TJA for a
given POAmax:
• Lower JA
- Use another package
- PCB layout (ground plane, etc.)
- Heat sinks and air flow
• Reduce POAmax
- Increase RL
- Limit IOUT (using RSER)
- Decrease VDD
4.3 Improving Stability
4.3.1 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the phase margin (stability) of
the feedback loop decreases and the closed-loop
bandwidth is reduced. This produces gain peaking in
the frequency response, with overshoot and ringing in
the step response. A unity-gain buffer (G = +1) is the
most sensitive to capacitive loads, though all gains
show the same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-6) improves the
phase margin of the feedback loop by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-6: Output Resistor, RISO,
Stabilize s L arge Capaci tiv e L oad s.
Figure 4-7 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., -1 V/V gives GN=+2V/V).
FIGURE 4-7: Recommended RISO Values
for Capacitive Loads.
After selecting RISO, double-check the resulting
frequency response peaking and step response
overshoot. Modify the value of RISO until the response
is reasonable. Bench evaluation and simulations with
the MCP631/2/3/4/5/9 SPICE macro model are helpful.
4.3.2 GAIN PEAKING
Figure 4-8 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common-Mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
FIGURE 4-8: Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF
.
CN and RN form a low-pass filter that affects the signal
at VP
. This filter has a single real pole at 1/(2RNCN).
Where:
TJmax = Absolute maximum junction temperature
POAmax TJmax TA
–
n
JA
--------------------------
RISO
VOUT
CL
RGRF
RNMCP63X
-
+
10
100
1,000
1.E-12 1.E-11 1.E-10 1.E-09 1.E-08
Normalized Capacitance; CL/GN (F)
Recommended R ISO (Ω)
GN = +1
GN +2
10p 100p 1n 10n
VP
RF
VOUT
RN
CN
VM
RGCG
MCP63X
+
-
2009-2014 Microchip Technology Inc. DS20002197C-page 23
MCP631/2/3/4/5/9
The largest value of RF that should be used depends
on the noise gain (see GN in Section 4.3.1
“Capacitive Loads”), CG and the open-loop gain’s
phase shift. Figure 4-9 shows the maximum
recommended RF for several CG values. Some
applications may modify these values to reduce either
output loading or gain peaking (step response
overshoot).
FIGURE 4-9: Maximum Recommended
RF vs. Gain.
Figures 2-34 and 2-35 show the small signal and large
signal step responses at G = +1 V/V. The unity-gain
buffer usually has RF=0 and RG open.
Figures 2-36 and 2-37 show the small signal and large
signal step responses at G = -1 V/V. Since the noise
gain is 2 V/V and CG10 pF, the resistors were
chosen to be RF=R
G=1k and RN= 500.
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the destabilizing effect of CG
.
This makes it possible to use larger values of RF
. The
conditions for stability are summarized in Equation 4-6.
EQUATION 4-6:
4.4 MCP633, MCP635 and MCP639
Chip Select
The MCP633 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to 1 µA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 M (typical)
pull-down resistor connected to VSS, so it will go low if
the CS pin is left floating. Figures 1-1,2-42 and 2-43
show the output voltage and supply current response to
a CS pulse.
The MCP635 is a dual amplifier with two CS pins; CSA
controls op amp A and CSB controls op amp B. These
op amps are controlled independently, with an enabled
quiescent current (IQ) of 2.5 mA/amplifier (typical) and
a disabled IQ of 1 µA/amplifier (typical). The IQ seen at
the supply pins is the sum of the two op amps’ IQ; the
typical value for the IQ of the MCP635 will be 2 µA,
2.5 mA or 5 mA when there are 0, 1 or 2 amplifiers
enabled, respectively.
The MCP639 is a quad amplifier with two CS pins; CSB
controls op amp B and CSD controls op amp D.
4.5 Power Supply
With this family of operational amplifiers, the Power
Supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
1.E+02
1.E+03
1.E+04
1.E+05
1 10 100
Noise Gain; GN (V/V)
Maximum Recommended R F
(Ω)
GN > +1 V/V
100
10k
100k
1k
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG
= 1 nF
We need:
Given:
GN1 1RF
RG
-------+=
GN2 1CG
CF
-------+=
fF1
2
RFCF
---------------------=
fZfFGN1
GN2
----------
=
fF fGBWP
2GN2
--------------- ,
GN1 GN2
fF fGBWP
4GN1
--------------- ,
GN1 GN2
MCP631/2/3/4/5/9
DS20002197C-page 24 2009-2014 Microchip Technology Inc.
4.6 High-Speed PCB Layout
These op amps are fast enough that a little extra care
in the printed circuit board (PCB) layout can make a
significant difference in performance. Good PCB layout
techniques will help achieve the performance shown in
the specifications and typical performance curves; it
will also help minimize electromagnetic compatibility
(EMC) issues.
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low-speed from
high-speed, and low-power from high-power. This will
reduce interference.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim trace
and as close as possible. Connect guard traces to
ground plane at both ends and in the middle for long
traces.
Use coax cables, or low-inductance wiring, to route
signal and power to and from the PCB. Mutual and
self-inductance of power wires is often a cause of
crosstalk and unusual behavior.
4.7 Typical Applications
4.7.1 POWER DRIVER WITH HIGH GAIN
Figure 4-10 shows a power driver with high gain
(1 + R2/R1). The short-circuit current of the
MCP631/2/3/4/5/9 op amps makes it possible to drive
significant loads. The calibrated input offset voltage
supports accurate response at high gains. R3 should
be small and equal to R1||R2 in order to minimize the
bias current induced offset.
FIGURE 4-10: Power Driver.
4.7.2 OPTICAL DETECTOR AMPLIFIER
Figure 4-11 shows a transimpedance amplifier, using
the MCP63X op amp, in a photo detector circuit. The
photo detector is a capacitive current source. RF
provides enough gain to produce 10 mV at VOUT
. CF
stabilizes the gain and limits the transimpedance
bandwidth to about 1.1 MHz. The parasitic capacitance
of RF (e.g., 0.2 pF for a 0805 SMD) acts in parallel with
CF
.
FIGURE 4-11: Transimpedance Amplifier
for an Optical Detector.
4.7.3 H-BRIDGE DRIVER
Figure 4-12 shows the MCP632 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
FIGURE 4-12: H-Bridge Driv er.
This circuit automatically makes the noise gains (GN)
equal when the gains are set properly, so that the
frequency responses match well (in magnitude and in
phase). Equation 4-7 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
GDM needs to be selected first.
R1R2
VIN
VDD/2 VOUT
R3RL
MCP63X
-
+
Photo
Detector
CD
CF
RF
VDD/2
30 pF
100 k
1.5 pF
ID
100 nA
VOUT
MCP632
-
+
RF
RF
VIN
VOT
RF
RGB
VOB
VDD/2
RGT RL
½ MCP633
½ MCP633
+
-
-
+
2009-2014 Microchip Technology Inc. DS20002197C-page 25
MCP631/2/3/4/5/9
EQUATION 4-7:
Equation 4-8 gives the resulting Common-Mode and
Differential mode output voltages.
EQUATION 4-8:
GDM VOT VOB
–
VIN VDD
2
-----------–
-------------------------- 1 V/V
RGT RF
GDM
2
------------1–
---------------------=
RGB RF
GDM
2
------------
------------=
VOT V+ OB
2
--------------------------- VDD
2
-----------=
VOT V–OB GDM VIN VDD
2
-----------–
=
MCP631/2/3/4/5/9
DS20002197C-page 26 2009-2014 Microchip Technology Inc.
5.0 DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP631/2/3/4/5/9 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the
MCP631/2/3/4/5/9 op amps is available on the
Microchip web site at www.microchip.com. This model
is intended to be an initial design tool that works well in
the linear region of operation over the temperature
range of the op amp. See the model file for information
on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design
requirement. Available at no cost from the Microchip
web site at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a filter can be defined to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
5.4 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of analog
demonstration and evaluation boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at
www.microchip.com/analog tools.
Some boards that are especially useful are:
•MCP6XXX Amplifier Evaluation Board 1,
part number: MCP6XXXEV-AMP1
•MCP6XXX Amplifier Evaluation Board 2,
part number: MCP6XXXEV-AMP2
•MCP6XXX Amplifier Evaluation Board 3,
part number: MCP6XXXEV-AMP3
•MCP6XXX Amplifier Evaluation Board 4,
part number: MCP6XXXEV-AMP4
•Active Filter Demo Board Kit,
part number: MCP6XXXDM-FLTR
•8-Pin SOIC/MSOP/TSSOP/DIP Evaluation
Board, part number: SOIC8EV
5.5 Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip.com/appnotes and are
recommended as supplemental reference resources.
•ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
•AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
•AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
•AN884: “Driving Capac itive Loads With Op
Amps”, DS00884
•AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
•AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the “Signal Chain Design Guide”, DS21825.
2009-2014 Microchip Technology Inc. DS20002197C-page 27
MCP631/2/3/4/5/9
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
XXNN
XXNN
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead SOT-23 (MCP631) Example
YV25
6-Lead SOT-23 (MCP633) Example
JC25
8-Lead TDFN (2x3x0.75 mm) (MCP631) Example
ABK
425
25
8-Lead DFN (3x3x0.9 mm) (MCP632) Example
DABM
1425
256
Device Code
MCP632T-E/MF DABM
Note 1: Applies to 8-lead 3x3 DFN
MCP631/2/3/4/5/9
DS20002197C-page 28 2009-2014 Microchip Technology Inc.
NNN
8-Lead SOIC (3.90 mm) (MCP631, MCP632) Example
MCP631E
SN^^1425
256
3
e
10-Lead DFN (3x3x0.9 mm) (MCP635) Example
Device Code
MCP635T-E/MF BAFB
Note 1: Applies to 10-lead 3x3 DFN
BAFB
1425
256
10-Lead MSOP (3x3 mm) (MCP635) Example
665EUN
425256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2009-2014 Microchip Technology Inc. DS20002197C-page 29
MCP631/2/3/4/5/9
14-Lead SOIC (3.90 mm) (MCP634) Example
MCP634
E/SL^^
1425256
3
e
14-Lead TSSOP (4.4 mm) (MCP634) Example
YYWW
NNN
XXXXXXXX
634E/ST
1425
256
16-Lead QFN (4x4x0.9 mm) (MCP639) Example
PIN 1 PIN 1
639
E/ML^^
1425256
3
e
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
MCP631/2/3/4/5/9
DS20002197C-page 30 2009-2014 Microchip Technology Inc.
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
2009-2014 Microchip Technology Inc. DS20002197C-page 31
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 32 2009-2014 Microchip Technology Inc.
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 6
Pitch e 0.95 BSC
Outside Lead Pitch e1 1.90 BSC
Overall Height A 0.90 – 1.45
Molded Package Thickness A2 0.89 – 1.30
Standoff A1 0.00 – 0.15
Overall Width E 2.20 – 3.20
Molded Package Width E1 1.30 – 1.80
Overall Length D 2.70 – 3.10
Foot Length L 0.10 – 0.60
Footprint L1 0.35 – 0.80
Foot Angle I0° – 30°
Lead Thickness c 0.08 – 0.26
Lead Width b 0.20 – 0.51
b
E
4
N
E1
PIN1IDBY
LASER MARK
D
123
e
e1
A
A1
A2 c
L
L1
φ
Microchip Technology Drawing C04-028B
2009-2014 Microchip Technology Inc. DS20002197C-page 33
MCP631/2/3/4/5/9
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 34 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 35
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 36 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 37
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 38 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 39
MCP631/2/3/4/5/9
!"#$%&'*+,
MCP631/2/3/4/5/9
DS20002197C-page 40 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 41
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 42 2009-2014 Microchip Technology Inc.
./#014!55&$7'*./
2009-2014 Microchip Technology Inc. DS20002197C-page 43
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 44 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 45
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 46 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
UN
2009-2014 Microchip Technology Inc. DS20002197C-page 47
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
UN
MCP631/2/3/4/5/9
DS20002197C-page 48 2009-2014 Microchip Technology Inc.
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 49
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 50 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 51
MCP631/2/3/4/5/9
MCP631/2/3/4/5/9
DS20002197C-page 52 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 53
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP631/2/3/4/5/9
DS20002197C-page 54 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 55
MCP631/2/3/4/5/9
89;/#014!<5<5&$%'*;/
D
E
N
2
1
EXPOSED
PAD
D2
E2
2
1
e
b
K
N
NOTE 1
A3
A1
A
L
TOP VIEW BOTTOM VIEW
MCP631/2/3/4/5/9
DS20002197C-page 56 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002197C-page 57
MCP631/2/3/4/5/9
APPENDIX A: REVISION HISTORY
Revision C (July 2014)
The following is the list of modifications:
1. Updated the Features: list.
2. Added the High Gain-Bandwidth Op Amp
Portfolio table in the Features: section.
3. Updated Figures 4-6 and 4-11.
4. Updated Section 6.0 “Packaging
Information” and Section 6.1 “Package
Marking Information”.
5. Minor typographical changes.
Revision B (November 2011)
The following is the list of modifications:
1. Added the MCP634 and MCP639 amplifiers to
the product family and the related information
throughout the document.
2. Added the 2x3 TDFN (8L), SOT23 (5L) package
option for MCP631, SOT23 (6L) package option
for MCP633, 4x4 QFN (16L) package option for
MCP639, SOIC and TSSOP (14L) package
options for MCP634 and the related information
throughout the document. Updated package
types drawing with pin designation for each new
package.
3. Updated the Temperature Specifications table to
show the temperature specifications for new
packages.
4. Updated Ta b l e 3 - 1 to show all the pin functions.
5. Updated Section 6.0 “Packaging Informa-
tion” with markings for the new additions.
Added the corresponding SOT23 (5L), SOT23
(6L), TDFN (8L), SOIC, TSSOP (14L), and 4x4
QFN (16L) package options and related infor-
mation.
6. Updated table description and examples in the
Product Identification System section.
Revision A (August 2009)
• Original Release of this Document.
MCP631/2/3/4/5/9
DS20002197C-page 58 2009-2014 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -X /XX
PackageTemperature
Range
Device
Device: MCP631 Single Op Amp
MCP631T Single Op Amp (Tape and Reel)
(SOIC, SOT-23, TDFN)
MCP632 Dual Op Amp
MCP632T Dual Op Amp (Tape and Reel)
(DFN and SOIC)
MCP633 Single Op Amp with CS
MCP633T Single Op Amp with CS (Tape and Reel)
(SOIC, SOT-23)
MCP634 Quad Op Amp
MCP634T Quad Op Amp (Tape and Reel)
(TSSOP and SOIC)
MCP635 Dual Op Amp with CS
MCP635T Dual Op Amp with CS (Tape and Reel)
(DFN and MSOP)
MCP639 Quad Op Amp
MCP639T Quad Op Amp (Tape and Reel)
(QFN)
Temperature
Range:
E = -40°C to +125°C
Package: OT = Plastic Small Outline (SOT-23), 5-lead
CHY = Plastic Small Outline (SOT-23), 6-lead
MNY= Plastic Dual Flat, No Lead (2x3 TDFN), 8-lead
MF = Plastic Dual Flat, No Lead (3×3 DFN),
8-lead, 10-lead
SN = Plastic Small Outline (3.90 mm), 8-lead
UN = Plastic Micro Small Outline (MSOP), 10-lead
SL = Plastic Small Outline, Narrow, (3.90 mm SOIC),
14-lead
ST = Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),
14-lead
ML = Plastic Quad Flat, No Lead Package (4x4 QFN),
(4x4x0.9 mm), 16-lead
Examples:
a) MCP631T-E/OT: Tape and Reel
Extended temperature,
5LD SOT-23 package
b) MCP631T-E/MNY:Tape and Reel
Extended temperature,
8LD TDFN package
c) MCP631T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
d) MCP632T-E/MF: Tape and Reel
Extended temperature,
8LD DFN package
e) MCP632T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
f) MCP633T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
g) MCP633T-E/CHY: Tape and Reel
Extended temperature,
6LD SOT package
h) MCP634T-E/SL: Tape and Reel
Extended temperature,
14LD SOIC package
i) MCP634T-E/ST: Tape and Reel
Extended temperature,
14LD TSSOP package
j) MCP635T-E/MF: Tape and Reel
Extended temperature,
10LD DFN package
k) MCP635T-E/UN: Tape and Reel
Extended temperature,
10LD MSOP package
l) MCP639T-E/ML: Tape and Reel
Extended temperature,
16LD QFN package.
2009-2014 Microchip Technology Inc. DS20002197C-page 59
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-382-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hoppi ng
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20002197C-page 60 2009-2014 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
03/25/14
