KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Description The Kenet KAD2708L is the industry's lowest power, 8bit, high performance Analog-to-Digital converter. The converter runs at sampling rates up to 350MSPS, and is fabricated with Kenet's proprietary FemtoCharge(R) CMOS technology. Users can now obtain industry-leading SNR and SFDR specifications while nearly halving power consumption. Sampling rates of 275, 210, 170 and 105MSPS are also available in the same pin-compatible package and in versions with 10-bit resolution. All are available in 68-pin RoHS-compliant QFN packages with exposed paddle. Performance is specified over the full industrial temperature range (-40 to +85C). Key Specifications * * * SNR of 48.8dB at Nyquist SFDR of 64dBc at Nyquist Power consumption 320mW at fS = 350MSPS Features * * * * * * * * On-chip reference Internal track and hold 1.5VPP differential input voltage 600MHz analog input bandwidth Two's complement or binary output Over-range indicator Selectable /2 Clock Input LVDS compatible outputs Applications * * * * * * * * * High-Performance Data Acquisition Portable Oscilloscope Medical Imaging Cable Head Ends Power-Amplifier Linearization Radar and Satellite Antenna Array Processing Broadband Communications Local Multipoint Distribution System (LMDS) Communications Test Equipment Resolution, Speed LVDS Outputs LVCMOS Outputs 8 Bits 350MSPS KAD2708L-35 10 Bits 275MSPS KAD2710L-27 KAD2710C-27 8 Bits 275MSPS KAD2708L-27 KAD2708C-27 10 Bits 210MSPS KAD2710L-21 KAD2710C-21 8 Bits 210MSPS KAD2708L-21 KAD2708C-21 10 Bits 170MSPS KAD2710L-17 KAD2710C-17 8 Bits 170MSPS KAD2708L-17 KAD2708C-17 10 Bits 105MSPS KAD2710L-10 KAD2710C-10 8 Bits 105MSPS KAD2708L-10 KAD2708C-10 Table 1. Pin-Compatible Products 300 Unicorn Park Dr., Woburn, MA 01801 Sales: 1-781-497-0060 FemtoCharge is a registered trademark of Kenet, Inc. Rev 1.2 Sales@kenetinc.com Copyright (c) 2007, Kenet, Inc. Page 1 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Absolute Maximum Ratings1 Parameter Min Max Unit AVDD2 to AVSS -0.4 2.1 V AVDD3 to AVSS -0.4 3.7 V OVDD2 to OVSS -0.4 2.1 V Analog Inputs to AVSS -0.4 AVDD3 + 0.3 V Clock Inputs to AVSS -0.4 AVDD2 + 0.3 V Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4 AVDD3 + 0.3 V Logic Inputs to OVSS (RST, 2SC) -0.4 OVDD2 + 0.3 V VREF TO AVSS -0.4 AVDD3 + 0.3 V Analog Output Currents 10 mA Logic Output Currents 10 mA LVDS Output Currents 20 mA Operating Temperature -40 85 C Storage Temperature -65 150 C 150 C Junction Temperature 1. Exposing the device to levels in excess of the maximum ratings may cause permanent damage. Operation at maximum conditions for extended periods may affect device reliability. Thermal Impedance Parameter Junction to Paddle2 Symbol Typ Unit JP 30 C/W 2. Paddle soldered to ground plane. ESD Electrostatic charge accumulates on humans, tools and equipment, and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Kenet for the specific ESD sensitivity rating of this product. Rev 1.2 Page 2 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V, OVDD = 1.8V. TA = -40C to +85C, Typ values at 25C. fSAMPLE = 350MSPS, fIN = Nyquist. DC Specifications Parameter Symbol Conditions Min Typ Max Units 1.8V Analog Supply Voltage AVDD2 1.7 1.8 1.9 V 3.3V Analog Supply Voltage AVDD3 3.15 3.3 3.45 V 1.8V Output Supply Voltage OVDD 1.7 1.8 1.9 V 1.8V Analog Supply Current IAVDD2 38 mA 3.3V Analog Supply Current IAVDD3 46 mA 1.8V Output Supply Current IOVDD 53 mA PD 318 mW Power Requirements Power Dissipation Rev 1.2 Page 3 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Analog Specifications Parameter Symbol Conditions Min Typ Max Units 1.4 1.5 1.6 VPP Analog Input Full-Scale Differential Analog Input Voltage Gain Temperature Coefficient VIN AVTC Full Power Bandwidth Full Temp FPBW 90 ppm/C 600 MHz Clock Input Sampling Clock Frequency Range fSAMPLE 50 350 MHz CLKP, CLKN P-P Differential Input Voltage VCDI 0.5 1.8 VPP CLKP, CLKN Differential Input Resistance RCDI 10 M CLKP, CLKN Common-Mode Input Voltage VCCI 0.9 V Reference Internal Reference Voltage VREF Reference Voltage Temperature Coefficient VRTC Common-Mode Output Voltage VCM 1.18 1.21 Full Temp 1.24 V 38 ppm/C 0.86 V AC Specifications Parameter Conditions Min Typ SNR Full Temp 45.8 48.8 dB Signal to Noise and Distortion SINAD Full Temp 45.7 48.7 dB Effective Number of Bits ENOB Full Temp 7.3 7.8 Bits Spurious Free Dynamic Range SFDR Full Temp 58 64 dBc Two-Tone SFDR 2TSFDR f1=133MHz, f2=135MHz 63 dBc Signal to Noise Ratio Symbol Max Units Integral Nonlinearity INL -0.8 0.2 0.8 LSB Differential Nonlinearity DNL -0.3 0.2 0.4 LSB Power Supply Rejection Ratio PSRR 42 66 Word Error Rate WER Rev 1.2 dB 1x10-12 Page 4 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Digital Specifications Parameter Symbol Conditions Min Typ Max Units Inputs 0.8*AVDD3 High Input Voltage (VREFSEL) VREFSEL VIH Low Input Voltage (VREFSEL) VREFSEL VIL Input Current High (VREFSEL) VREFSEL IIH VIN = AVDD3 0 Input Current Low (VREFSEL) VREFSEL IIL VIN = AVSS 25 High Input Voltage (CLKDIV) CLKDIV VIH Low Input Voltage (CLKDIV) CLKDIV VIL Input Current High (CLKDIV) CLKDIV IIH VIN = AVDD3 25 Input Current Low (CLKDIV) CLKDIV IIL VIN = AVSS 0 0.2*AVDD3 V 1 10 A 65 75 A 0.8*AVDD3 V 0.2*AVDD3 V 65 75 A 1 10 A 0.8*OVDD2 High Input Voltage (RST,2SC) RST,2SC VIH Low Input Voltage (RST,2SC) RST,2SC VIL Input Current High (RST,2SC) RST,2SC IIH VIN = OVDD 0 Input Current Low (RST,2SC) RST,2SC IIL VIN = OVSS 25 Input Capacitance V V 0.2*OVDD2 V 1 10 A 50 75 A CDI 3 pF VT 210 mV VOS 1.15 V Output Rise Time tR 500 ps Output Fall Time tF 500 ps LVDS Outputs Differential Output Voltage Output Offset Voltage Rev 1.2 Page 5 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Timing Diagram Figure 1. LVDS Timing Diagram Timing Specifications Parameter Symbol Min Typ Max Units Aperture Delay tA 1.7 ns RMS Aperture Jitter jA 200 fs Input Clock to Data Propagation Delay tPD 1.8 ns Input Clock to Output Clock Propagation Delay tCPD 1.3 ns Output Clock to Data Propagation Delay tDC 470 ps Output Data to Output Clock Setup Time tSU 3 ns Output Clock to Output Data Hold Time tH 75 ps Latency (Pipeline Delay) L 28 cycles Over Voltage Recovery tOVR 1 cycle Rev 1.2 Page 6 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Pin Descriptions Pin # Name Function 1, 14, 18, 20 AVDD2 1.8V Analog Supply 2, 7, 10, 19, 21, 24 AVSS Analog Supply Return 3 VREF Reference Voltage Out/In 4 VREFSEL 5 VCM Reference Voltage Select (0:Int 1:Ext) Common Mode Voltage Output 6, 15, 16, 25 AVDD3 3.3V Analog Supply 8, 9 INP, INN Analog Input Positive, Negative 11-13, 29-36, 62, 63, 67 17 22, 23 26, 45, 61 27, 41, 44, 60 28 DNC CLKDIV CLKN, CLKP OVSS OVDD2 RST Do Not Connect Clock Divide by Two (Active Low) Clock Input Complement, True Output Supply Return 1.8V LVDS Supply Power On Reset (Active Low) 37, 38 D0N, D0P LVDS Bit 0 (LSB) Output Complement, True 39, 40 D1N, D1P LVDS Bit 1 Output Complement, True 42, 43 CLKOUTN, CLKOUTP LVDS Clock Output Complement, True 46, 47 D2N, D2P LVDS Bit 2 Output Complement, True 48, 49 D3N, D3P LVDS Bit 3 Output Complement, True 50, 51 D4N, D4P LVDS Bit 4 Output Complement, True 52, 53 D5N, D5P LVDS Bit 5 Output Complement, True 54, 55 D6N, D6P LVDS Bit 6 Output Complement, True 56, 57 D7N, D7P LVDS Bit 7 Output Complement, True 58, 59 ORN, ORP Over Range Complement, True 64-66 Connect to OVDD2 68 2SC Two's Complement Select (Active Low) Exposed Paddle AVSS Analog Supply Return Rev 1.2 Page 7 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter 2SC DNC OVDD2 OVDD2 OVDD2 DNC DNC OVSS OVDD2 ORP ORN D7P D7N D6P D6N D5P D5N 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 Pin Configuration AVDD2 1 51 D4P AVSS 2 50 D4N VREF 3 49 D3P VREFSEL 4 48 D3N VCM 5 47 D2P AVDD3 6 46 D2N AVSS 7 OVSS INP 8 44 OVDD2 INN 9 KAD2708L 45 43 CLKOUTP AVSS 10 42 CLKOUTN DNC 11 68 QFN 41 OVDD2 DNC 12 40 D1P DNC 13 39 D1N AVDD2 14 38 D0P AVDD3 15 37 D0N AVDD3 16 36 DNC CLKDIV 17 35 DNC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 AVDD2 AVSS AVDD2 AVSS CLKN CLKP AVSS AVDD3 OVSS OVDD2 RST DNC DNC DNC DNC DNC DNC Top View Not to Scale Figure 2. Pin Configuration Rev 1.2 Page 8 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Typical Operating Characteristics AVDD3=3.3V, AVDD2=OVDD2 =1.8V, TAMBIENT (TA)=25C, fSAMPLE=350MHz, VIN= 6.865MHz @ -0.5dBFS unless noted. 70 50 65 45 60 55 SFDR (dB) SNR (dB) 40 35 30 50 45 40 35 25 30 20 25 15 -30 -25 -20 -15 -10 -5 20 -30 0 -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) Analog Input Amplitude (dBFS) Figure 3. SNR vs. Vin Figure 4. SFDR vs. Vin 320 300 -30 260 PD (mW) HD2, HD3 dBc 280 -40 -50 HD3 -60 240 220 200 180 HD2 -70 160 -80 -30 140 -25 -20 -15 -10 -5 0 50 75 100 125 150 175 200 225 250 275 300 325 350 Input Amplitude (dBFS) f SAMPLE (MHz) Figure 5. HD2, 3 vs. Vin Figure 6. Power Dissipation vs. fSAMPLE -65 50 -70 HD3 -75 dBc SNR (dB) 49.5 49 -80 48.5 48 -90 50 75 100 125 150 175 200 225 250 275 300 325 350 f SAMPLE (MHz) Figure 7. SNR vs. fSAMPLE Rev 1.2 HD2 -85 50 75 100 125 150 175 200 225 250 275 300 325 350 f SAMPLE (MHz) Figure 8. HD2, 3 vs. fSAMPLE Page 9 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter AVDD3=3.3V, AVDD2=OVDD2 =1.8V, TAMBIENT (TA)=25C, fSAMPLE=350MHz, VIN= 6.865MHz @ -0.5dBFS unless noted. 72 0.5 0.25 70 DNL (LSBs) SFDR (dBc) 71 69 0 -0.25 68 67 -0.5 50 75 100 125 150 175 200 225 250 275 300 325 350 0 32 64 96 128 code 160 192 224 255 f SAMPLE (MHz) Figure 9. SFDR vs. fSAMPLE Figure 10. Differential Nonlinearity vs. Output Code 0.5 40,000 0.4 35,000 0.3 30,000 Code Counts INL (LSBs) 0.2 0.1 0 -0.1 25,000 20,000 15,000 -0.2 10,000 -0.3 5,000 -0.4 -0.5 0 32 64 96 128 code 160 192 224 0 125 255 126 Figure 11. Integral Nonlinearity vs. Output Code Code 128 129 130 Figure 12. Noise Histogram 0 0 -10 Vin = -0.50dBFS -10 Vin = -0.49dBFS -20 SNR = -48.4dB -20 SNR = 48.1dB -30 SFDR = 64.5dBc -30 SFDR = 67.5dBc -40 SINAD = 48.2dB -40 SINAD = 48.1dB -50 HD2 = -81dBc -50 HD2 = -78dBc -60 HD3 = -66dBc -60 HD3 = -71dBc A mplitude (dB) Amplitude (dB) 127 -70 -70 -80 -80 -90 -90 -100 0 20 40 60 80 100 Frequency (MHz) 120 140 Figure 13. Output Spectrum at 6.865MHz Rev 1.2 160 -100 0 20 40 60 80 100 Frequency (MHz) 120 140 160 Figure 14. Output Spectrum at 68.465MHz Page 10 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter AVDD3 = 3.3V, AVDD2 = OVDD2 =1.8V, TAMBIENT (TA)= 25C, fSAMPLE = 350MHz unless noted. 0 -10 Vin = -0.52dBFS -10 Vin = -0.50dBFS -20 SNR = 47.7dB -20 SNR = 48dB -30 SFDR = 68.2dBc -30 SFDR = 65.8dBc -40 SINAD = 47.6dB -40 SINAD = 47.9dB -50 HD2 = -81dBc -50 HD2 = -73dBc -60 HD3 = -69dBc -60 HD3 = -67.1dBc Amplitude (dB) Amplitude (dB) 0 -70 -70 -80 -80 -90 -90 -100 0 20 40 60 80 100 Frequency (MHz) 120 140 160 Figure 15. Output Spectrum at 174.905MHz -100 0 20 40 60 80 100 Frequency (MHz) 120 140 160 Figure 16. Output Spectrum at 175.105MHz 0 Amplitude (dB) -10 Vin = 0.50dBFS -20 SNR = 48.0dB -30 SFDR = 65.8dBc SINAD = 46.8dB -40 HD2 = -73dBc -50 HD3 = -67.1dBc -60 -70 -80 -90 -100 0 20 40 60 80 100 Frequency (MHz) 120 140 160 Figure 17. Output Spectrum at 492.965MHz Rev 1.2 Page 11 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Functional Description The KAD2708 is based upon a eight bit, 350MSPS A/D converter in a pipelined architecture. The input voltage is captured by a sample & hold circuit and converted to a unit of charge. Proprietary charge domain techniques are used to compare the input to a series of reference charges. These comparisons determine the digital code for each input value. The converter pipeline requires 24 sample clocks to produce a result. Digital error correction is also applied, resulting in a total latency of 28 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. At start-up, a self-calibration is performed to minimize gain and offset errors. The reset pin (RST) is initially held low internally at power-up and will remain in that state until the calibration is complete. The clock frequency should remain fixed during this time. system. Additionally, an externally provided reference can be changed from the nominal value to adjust the full-scale input voltage within a limited range. To select whether the full-scale reference is internally generated or externally provided, the digital input port VREFSEL should be set appropriately, low for internal or high for external. This pin also has an internal 18k pull-up resistor. To use the internally generated reference VREFSEL can be tied directly to AVSS, and to use an external reference VREFSEL can be allowed to float. Analog Input The fully differential ADC input (INP/INN) connects to the sample and hold circuit. The ideal full-scale input voltage is 1.5VPP, centered at the VCM voltage of 0.86V as shown in Figure 18. Calibration accuracy is maintained for the sample rate at which it is performed, and therefore should be repeated if the clock frequency is changed by more than 10%. Recalibration can be initiated via the RST pin, or power cycling, at any time. Reset The KAD2708L resets and calibrates automatically on power-up. To force a reset and initiate recalibration of the ADC after power-up, connect an open-drain output device to drive pin 28 (RST) and pull low for at least ten sample clock periods. Do not use a device with a pull-up on the reset pin, as it may prevent the KAD2708 from properly executing the power-on reset. Voltage Reference The VREF pin is the full-scale reference, which sets the full-scale input voltage for the chip and requires a bypass capacitor of 0.1uF or larger. An internally generated reference voltage is provided from a bandgap voltage buffer. This buffer can sink or source up to 50A externally. An external voltage may be applied to this pin to provide a more accurate reference than the internally generated bandgap voltage or to match the full-scale reference among a system of KAD2708L chips. One option in the latter configuration is to use one KAD2708L's internally generated reference as the external reference voltage for the other chips in the Rev 1.2 Figure 18. Analog Input Range Best performance is obtained when the analog inputs are driven differentially in an ac-coupled configuration. The common mode output voltage, VCM, should be used to properly bias each input as shown in Figures 19 and 20. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. The recommended biasing is shown in Figure 19. Figure 19. Transformer Input Page 12 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter The value of the termination resistor should be determined based on the desired impedance. The differential input impedance of the KAD2708 is 10M. A differential amplifier can be used in applications that require dc coupling, at the expense of reduced dynamic performance. In this configuration the amplifier will typically reduce the achievable SNR and distortion performance. A typical differential amplifier configuration is shown in Figure 20. rate, then use the KAD2708L's divide-by-2 to generate a 50%-duty-cycle clock. The divider only uses the rising edge of the clock, so 50% clock duty cycle is assured . CLKDIV Pin Divide Ratio AVSS 2 AVDD 1 Table 3. CLKDIV Pin Settings Jitter In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter and maximum SNR is shown in Equation 1 and is illustrated in Figure 22. Figure 20. Differential Amplifier Input 1 SNR = 20 log 10 2 f IN t J Where tj is the RMS uncertainty in the sampling instant. Clock Input The clock input circuit is a differential pair (see Figure 24). Driving these inputs with a high level (up to 1.8VPP on each input) sine or square wave will provide the lowest jitter performance. The recommended drive circuit is shown in Figure 21. The clock inputs can be driven single-ended, but this is not recommended as performance will suffer. Equation 1. This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as dc linearity (DNL), aperture jitter and thermal noise. 100 95 tj=0.1ps 90 14 Bits SNR - dB 85 80 tj=1ps 12 Bits 75 70 tj=10ps 65 60 10 Bits tj=100ps 55 50 Figure 21. Recommended Clock drive The CLKDIV pin is a 1.8V CMOS control pin (input) that selects whether the input clock frequency is passed directly to the ADC or divided by two. Applying a low level (or left floating) will divide by two; pulling CLKDIV up to 1.8V will not divide. Use of the clock divider is optional. The KAD2708L's ADC requires a clock with 50% duty cycle for optimum performance. If such a clock is not available, one option is to generate twice the desired sampling Rev 1.2 1 10 100 1000 Input Frequency - MHz Figure 22. SNR vs. Clock Jitter Any internal aperture jitter combines with the input clock jitter, in a root-sum-square fashion since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR. Page 13 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Equivalent Circuits Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip. Figure 23. Analog Inputs Clock Input Considerations Use matched transmission lines to the inputs for the analog input and clock signals. Locate transformers, drivers and terminations as close to the chip as possible. Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops. LVDS Outputs Output traces and connections must be designed for 50 (100 differential) characteristic impedance. Keep traces direct, and minimize bends where possible. Avoid crossing ground and power plane breaks with signal traces. Figure 24. Clock Inputs OVDD 2mA or 3mA OVDD DATA Unused Inputs DATA D[7:0]P OVDD D[7:0]N DATA DATA Three of the four standard logic inputs (RESET, CLKDIV, 2SC) which will not be operated do not require connection for best ADC performance. These inputs can be left open if they are not used. VREFSEL must be held low for internal reference, but can be left open for external reference. 2mA or 3mA Figure 25. LVDS Outputs Rev 1.2 Page 14 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Definitions Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component. The peak spurious spectral component may or may not be a harmonic. Two-Tone SFDR is the ratio of the RMS value of either input tone to the RMS value of the peak spurious component. The peak spurious component may or may not be an IMD product. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD-1.76) / 6.02. Integral Non-Linearity (INL) is the deviation of each individual code from a line drawn from negative fullscale (1/2 LSB below the first code transition) through positive full-scale (1/2 LSB above the last code transition). The deviation of any given code from this line is measured from the center of that code. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Its value in terms of input voltage is VFS/2. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the corresponding data. Power Supply Rejection Ratio (PSRR) is the ratio of a change in power supply voltage to the input voltage necessary to negate the resultant change in output code. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS value of the sum Rev 1.2 Page 15 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Outline Dimensions D D/2 D1 D1/2 PIN 1 ID 0.80 DIA E/2 E1/2 E1 TOP VIEW E C C b A1 e SECTION "C-C" SCALE: NONE TERMINAL TIP A b A1 4X P D2 D2/2 4X P 0.45 E2 16Xe REF. E2/2 0.25 MIN L e 0.25 MIN SEATING PLANE 16Xe REF. BOTTOM VIEW Rev 1.2 Page 16 of 17 KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter Package Dimensions (mm) Ref Min Nom Max A - 0.90 1.00 A1 0.00 0.01 0.05 Per JEDEC MO-220 b 0.18 0.23 0.30 Measured between 0.20 and 0.25mm from plated terminal tip D 10.00 BSC D1 9.75 BSC D2 7.55 7.70 e 0.50 BSC E 10.00 BSC E1 9.75 BSC Note 7.85 E2 7.55 7.70 7.85 L 0.50 0.60 0.65 N 68 Total terminals ND 17 Terminals in D (x) direction NE 17 Terminals in E (y) direction 0 P 0 12' 0.42 0.60 Ordering Guide This product is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Sub- RoHS stances (RoHS). Contact Kenet for a materials declaration for this product. Rev 1.2 Model Speed Package Temp. Range KAD2708L-35Q68 350MSPS 68-QFN EP -40C to +85C KAD2708L-27Q68 275MSPS 68-QFN EP -40C to +85C KAD2708L-21Q68 210MSPS 68-QFN EP -40C to +85C KAD2708L-17Q68 170MSPS 68-QFN EP -40C to +85C KAD2708L-10Q68 105MSPS 68-QFN EP -40C to +85C Page 17 of 17