GS882V37BB-300T - GSI Technology

GS882V37BB-360/333/300

256K x 36

9Mb SCD/DCD Sync Burst SRAM

360 MHz–300 MHz

1.8 V VDD

1.8 V I/O

119-Bump BGA

Commercial Temp

Industrial Temp

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V +10%/–10% core power supply

• 1.8 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-bump BGA package

Functional Description

Applications

The GS882V37BB is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

SCD and DCD Pipelined Reads

The GS882V37BB is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS882V37BB operates on a 1.8 V power supply. All inputs

are 1.8 V compatible. Separate output power (VDDQ) pins are used

to decouple output noise from the internal circuits and are 1.8 V

compatible.

Parameter Synopsis

-360 -333 -300 Unit

Pipeline

3-1-1-1

tKQ

tCycle

1.8

2.8

2.0

3.0

2.2

3.3

1.8 V Curr (x36) 475 435 395 mA

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882V37B Pad Out—119-Bump BGA—Top View (Package B)

1234567

AVDDQ A A ADSP AAV

DDQ

BNC NC A ADSC AANC

CNC A A VDD AANC

DDQCDQPCVSS ZQ VSS DQPBDQB

EDQCDQCVSS E1VSS DQBDQB

FVDDQ DQCVSS G VSS DQBVDDQ

GDQCDQCBCADV BBDQBDQB

HDQCDQCVSS GW VSS DQBDQB

JVDDQ VDD NC VDD NC VDD VDDQ

KDQDDQDVSS CK VSS DQADQA

LDQDDQDBDSCD BADQADQA

MVDDQ DQDVSS BW VSS DQAVDDQ

NDQD3 DQDVSS A1VSS DQADQA

PDQDDQPDVSS A0VSS DQPADQA

RNC A LBO VDD

VDDQ/

DNU APE

TNC NC A A A NC ZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

GS882V37BB-360/333/300

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GS882V37 BGA Pin Description

Symbol Type Description

A0, A1I Address field LSBs and Address Counter Preset Inputs

A I Address Inputs

DQA

DQB

DQC

DQD

I/O Data Input and Output pins

BA, BB, BC, BDI Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

BW I Byte Write—Writes all enabled bytes; active low

GW I Global Write Enable—Writes all bytes; active low

E1I Chip Enable; active low

E3I Chip Enable; active low

E2I Chip Enable; active high

GI Output Enable; active low

ADV I Burst address counter advance enable; active l0w

ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high

FT I Flow Through or Pipeline mode; active low

LBO I Linear Burst Order mode; active low

PE I 9th Bit Enable; active low (119-bump BGA only)

ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

TMS I Scan Test Mode Select

TDI I Scan Test Data In

TDO O Scan Test Data Out

TCK I Scan Test Clock

MCL — Must Connect Low

SCD — Single Cycle Deselect/Dual Cyle Deselect Mode Control

VDD I Core power supply

VSS I I/O and Core Ground

VDDQ I Output driver power supply

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS882V37B (PE = 0) Block Diagram

A0 A0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx1–DQx9

Note: Only x36 version shown for simplicity.

SCD

GS882V37BB-360/333/300

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GS882V37B (PE = 1) x32 Mode Block Diagram

A0 A0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx1–DQx8

Note: Only x36 version shown for simplicity.

SCD

Parity

Encode

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the

above tables.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name Pin

Name State Function

Burst Order Control LBO L Linear Burst

H Interleaved Burst

Power Down Control ZZ L or NC Active

H Standby, IDD = ISB

Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect

H or NC Single Cycle Deselect

FLXDrive Output Impedance Control ZQ L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

9th Bit Enable PE

LActivate DQPx I/Os (x18/x36

mode)

H or NC Deactivate DQPx I/Os (x16/x32

mode)

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

Byte Write Truth Table

Function GW BW BABBBCBDNotes

Read H H X X X X 1

Read HLHHHH1

Write byte a H L L H H H 2, 3

Write byte b H L H L H H 2, 3

Write byte c H L H H L H 2, 3

Write byte d H L H H H L 2, 3

Write all bytesHLLLLL2, 3

Write all bytesLXXXXX

GS882V37BB-360/333/300

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Synchronous Truth Table

Operation Address Used

State

Diagram

Key5

E1ADSP ADSC ADV W3DQ4

Deselect Cycle, Power Down None X H X L X X High-Z

Read Cycle, Begin Burst External R L L X X X Q

Read Cycle, Begin Burst External R L H L X F Q

Write Cycle, Begin Burst External W L H L X T D

Read Cycle, Continue Burst Next CR X H H L F Q

Read Cycle, Continue Burst Next CR H X H L F Q

Write Cycle, Continue Burst Next CW X H H L T D

Write Cycle, Continue Burst Next CW H X H L T D

Read Cycle, Suspend Burst Current X H H H F Q

Read Cycle, Suspend Burst Current H X H H F Q

Write Cycle, Suspend Burst Current X H H H T D

Write Cycle, Suspend Burst Current H X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low

2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding

3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram

First Write First Read

Burst Write Burst Read

Deselect

CRCW

Simple Synchronous OperationSimple Burst Synchronous Operation

CW CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram with G

First Write First Read

Burst Write Burst Read

Deselect

CRCW

CW CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

VDD Voltage on VDD Pins –0.5 to 3.6 V

VDDQ Voltage in VDDQ Pins –0.5 to 3.6 V

VCK Voltage on Clock Input Pin –0.5 to 3.6 V

VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 3.6 V max.) V

VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 3.6 V max.) V

IIN Input Current on Any Pin +/–20 mA

IOUT Output Current on Any I/O Pin +/–20 mA

PDPackage Power Dissipation 1.5 W

TSTG Storage Temperature –55 to 125 oC

TBIAS Temperature Under Bias –55 to 125 oC

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit

1.8 V Supply Voltage VDD 1.6 1.8 2.0 V

1.8 V VDDQ I/O Supply Voltage VDDQ 1.6 1.8 2.0 V

Note:

The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications

quoted are evaluated for worst case in the temperature range marked on the device.

I/O Logic Levels

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V1, 2

VDD Input Low Voltage VIL –0.3 —0.3*VDD V1, 2

VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V 1, 2, 3

VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1, 2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V, with a pulse width not to exceed 20% tKC.

3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit

Ambient Temperature (Commercial Range Versions) TA02570°C

Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C

Note:

The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications

quoted are evaluated for worst case in the temperature range marked on the device.

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

These parameters are sample tested.

Capacitance

(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance CIN VIN = 0 V 45pF

Input/Output Capacitance CI/O VOUT = 0 V 67pF

AC Test Conditions

Parameter Conditions

Input high level VDD – 0.2 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level VDD/2

Output reference level VDDQ/2

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

20% tKC

SS – 2.0 V

50%

VSS

VIH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

VDD

VIL

VDDQ/2

50Ω30pF*

Output Load 1

* Distributed Test Jig Capacitance

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. IDD and IDDQ apply to any combination of VDD3 and VDDQ operation.

2. All parameters listed are worst case scenario.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA

ZZ and PE Input Current IIN1

VDD ≥ VIN ≥ VIH

0 V ≤ VIN ≤ VIH

–1 uA

1 uA

100 uA

SCD and ZQ Input Current IIN2

VDD ≥ VIN ≥ VIL

0 V ≤ VIN ≤ VIL

–100 uA

–1 uA

1 uA

Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA

Output High Voltage VOH IOH = –4 mA, VDDQ = 1.6 V VDDQ – 0.4 V —

Output Low Voltage VOL IOL = 4 mA, VDD = 1.6 V —0.4 V

Operating Currents

Parameter Test Conditions Mode Symbol

-360 -333 -300

Unit

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

Operating

Current

1.8 V

Device Selected;

All other inputs

≥VIH or ≤ VIL

Output open

(x36) Pipeline IDD

IDDQ

415

425

380

390

345

355

50 mA

Standby

Current ZZ ≥ VDD – 0.2 V —Pipeline ISB 40 50 40 50 40 50 mA

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ VIL

—Pipeline IDD 105 115 100 105 95 100 mA

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

AC Electrical Characteristics

Parameter Symbol

-360 -333 -300

Unit

Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 2.8 —3.0 —3.3 —ns

Clock to Output Valid tKQ —1.8 —2.0 —2.2 ns

Clock to Output Invalid tKQX 1.0 —1.0 —1.0 —ns

Clock to Output in Low-Z tLZ11.0 —1.0 —1.0 —ns

Setup time tS 1.0 —1.0 —1.1 —ns

Hold time tH 0 —0—0.1 —ns

G to Output Valid tOE —1.8 —2.0 —2.2 ns

G to output in High-Z tOHZ1—1.8 —2.0 —2.2 ns

Clock HIGH Time tKH 1.2 —1.3 —1.3 —ns

Clock LOW Time tKL 1.4 —1.5 —1.5 —ns

Clock to Output in

High-Z tHZ11.0 1.8 1.0 2.0 1.0 2.2 ns

G to output in Low-Z tOLZ10—0—0—ns

ZZ setup time tZZS25—5—5—ns

ZZ hold time tZZH21—1—1—ns

ZZ recovery tZZR 20 —20 —20 —ns

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Timing (+1)

Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect

tHZ

tKQXtKQ

tLZtH

tOHZtOE

tHtS

tKCtKC

tKLtKLtKHtKH

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)

ABC

Deselected with E1

E2 and E3 only sampled with ADSC

ADSC initiated read

ADSP

ADSC

ADV

A0–An

Ba–Bd

DQa–DQd

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with

the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually

assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by VDDQ.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

tZZR

tZZHtZZS

Hold

Setup

tKLtKL

tKHtKH

tKCtKC

ADSP

ADSC

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TMS Test Mode Select In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

TDI Test Data In In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

TDO Test Data Out Out

Output that is active depending on the state of the TAP state machine. Output changes in

response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

GS882V37BB-360/333/300

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JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

ID Register Contents

Die

Revision

Code

Not Used I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x36 1XXX0000000000001000000110110011

Instruction Register

ID Code Register

Boundary Scan Register

012

····

31 30 29

012

···

······

Bypass Register

TDI TDO

TMS

TCK Test Access Port (TAP) Controller

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

0 0

110

111

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all

logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still

determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then

the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on

the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is

selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a

pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s

output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Forces all RAM output drivers to High-Z. 1

RFU 011 Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1

GSI 101 GSI private instruction. 1

RFU 110 Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

1.8 V Test Port Input High Voltage VIHJ 0.6 * VDD VDD +0.3 V1

1.8 V Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V1

TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2

TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3

TDO Output Leakage Current IOLJ –11uA4

Test Port Output High Voltage VOHJ 1.7 —V5, 6

Test Port Output Low Voltage VOLJ —0.4 V 5, 7

Test Port Output CMOS High VOHJC VDDQ – 100 mV —V5, 8

Test Port Output CMOS Low VOLJC —100 mV V 5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDDn

3. 0 V ≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOHJC = +100 uA

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter Conditions

Input high level VDD – 0.20

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level VDDQ/2

Output reference level VDDQ/2

VDDQ/2

50Ω30pF*

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Timing Diagram

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 —ns

TCK Low to TDO Valid tTKQ —20 ns

TCK High Pulse Width tTKH 20 —ns

TCK Low Pulse Width tTKL 20 —ns

TDI & TMS Set Up Time tTS 10 —ns

TDI & TMS Hold Time tTH 10 —ns

tTKQ

tTS tTH

tTKH tTKL

TCK

TMS

TDI

TDO

tTKC

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Package Dimensions—119-Bump FPBGA (Package B, Variation 2)

1 2 3 4 5 6 7 7 6 5 4 3 2 1

A1 TOP VIEW A1

BOTTOM VIEW

1.27

7.62

1.27

20.32

14±0.10

22±0.10

0.20(4x)

Ø0.10

Ø0.30

C A B

SØ0.60~0.90 (119x)

CSEATING PLANE

0.15 C

0.50~0.70

1.86.±0.13

0.70±0.05

0.15 C

0.56±0.05

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information for GSI Synchronous Burst RAMs

Org Part Number1Type Package Speed2

(MHz) TA3Status

256K x 36 GS882V37BB-360 S/DCD Pipeline 119 BGA (var. 2) 360 C

256K x 36 GS882V37BB-333 S/DCD Pipeline 119 BGA (var. 2) 333 C

256K x 36 GS882V37BB-300 S/DCD Pipeline 119 BGA (var. 2) 300 C

256K x 36 GS882V37BB-360I S/DCD Pipeline 119 BGA (var. 2) 360 I

256K x 36 GS882V37BB-333I S/DCD Pipeline 119 BGA (var. 2) 333 I

256K x 36 GS882V37BB-300I S/DCD Pipeline 119 BGA (var. 2) 300 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882V37BB-300IB.

2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

GS882V37BB-360/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

9Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content Page;Revisions;Reason

882V37B_r1 • Creation of new datasheet

882V37B_r1;

882V37B_r1_01 Format/Content

• Added 360 MHz

• Removed all speed bins below 300 MHz

• Updated format

882V37B_r1_01;

882V37B_r1_02 Content • Updated mechanical drawing and added variation number to

ordering information