14-Bit, 1300 MSPS/625 MSPS, JESD204B,
Dual Analog-to-Digital Converter
Data Sheet
AD9695
Rev. C Document Feedback
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FEATURES
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 16 Gbps
1.6 W total power at 1300 MSPS
800 mW per ADC channel
SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range)
SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range)
Noise density
−153.9 dBFS/Hz (1.59 V p-p input range)
−155.6 dBFS/Hz (2.04 V p-p input range)
0.95 V, 1.8 V, and 2.5 V supply operation
No missing codes
Internal ADC voltage reference
Flexible input range
1.36 V p-p to 2.04 V p-p (1.59 V p-p typical)
2 GHz usable analog input full power bandwidth
>95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated digital downconverters per ADC channel
48-bit NCO
Programmable decimation rates
Differential clock input
SPI control
Integer clock divide by 2 and divide by 4
Flexible JESD204B lane configurations
On-chip dithering to improve small signal linearity
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, WCDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receiver
Instrumentation
Oscilloscopes
Spectrum analyzers
Network analyzers
Integrated RF test solutions
Radars
Electronic support measures, electronic counter measures,
and electronic counter-counter measures
High speed data acquisition systems
DOCSIS 3.0 CMTS upstream receive paths
Hybrid fiber coaxial digital reverse path receivers
Wideband digital predistortion
FUNCTIONAL BLOCK DIAGRAM
ADC
CORE
FAST
DETECT SIGNAL
MONITOR
DIGITAL DOWN-
CONVERTER
CROSS BAR M UX
CROSS BAR M UX
PROGRAMMABLE
FIR FILTER
DIGITAL DOWN-
CONVERTER
14
14
BUFFER
VIN+A
VIN–A
VIN+B
CLK+
CLK–
VREF
PDWN/STBY
SYSREF±
AGND DRGND DGND
AVDD1
(0.95V) DVDD
(0.95V) DRVDD1
(0.95V) DRVDD2
(1.8V) SPIVDD
(1.8V)
AVDD2
(1.8V) AVDD3
(2.5V) AVDD1_SR
(0.95V)
SPI AND
CONTROL
REGISTERS
SDIO SCLK CSB
VIN–B
BUFFER
ADC
CORE
÷2
÷4
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
JESD204B
LINK
AND
Tx
OUTPUTS
4
JESD204B
SUBCLAS S 1
CONTROL CLOCK
DISTRIBUTION
SYNCINB±
FD_A/GPIO_A0
FD_B/GPIO_B0
GPIO MUX
AD9695
15660-001
Figure 1.
AD9695 Data Sheet
Rev. C | Page 2 of 136
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Product Highlights ........................................................................... 4
Specifications .................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications—1300 MSPS ................................................. 6
AC Specifications—625 MSPS ................................................... 8
Digital Specifications ................................................................... 9
Switching Specifications ............................................................ 10
Timing Specifications ................................................................ 11
Absolute Maximum Ratings ......................................................... 13
Thermal Characteristics ............................................................ 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions .......................... 14
Typical Performance Characteristics ........................................... 16
1300 MSPS ................................................................................... 16
625 MSPS ..................................................................................... 21
Equivalent Circuits ......................................................................... 25
Theory of Operation ...................................................................... 27
ADC Architecture ...................................................................... 27
Analog Input Considerations ................................................... 27
Voltage Reference ....................................................................... 30
DC Offset Calibration ................................................................ 30
Clock Input Considerations ...................................................... 30
Power-Down/Standby Mode .................................................... 33
Temperature Diode .................................................................... 33
ADC Overrange and Fast Detect .................................................. 34
ADC Overrange .......................................................................... 34
Fast Threshold Detection (FD_A and FD_B) ........................ 34
ADC Application Modes and JESD204B Tx Converter
Mapping ........................................................................................... 35
Programmable Finite Impulse Response (FIR) Filters .............. 37
Supported Modes ....................................................................... 37
Programming Instructions ....................................................... 39
Digital Downconverter (DDC) ..................................................... 42
DDC I/Q Input Selection .......................................................... 42
DDC I/Q Output Selection ....................................................... 42
DDC General Description ........................................................ 42
DDC Frequency Translation .................................................... 45
DDC Decimation Filters ........................................................... 53
DDC Gain Stage ......................................................................... 60
DDC Complex to Real Conversion ......................................... 61
DDC Mixed Decimation Settings ............................................ 62
DDC Example Configurations ................................................. 64
DDC Power Consumption ....................................................... 67
Signal Monitor ................................................................................ 68
SPORT Over JESD204B ............................................................ 69
Digital Outputs ............................................................................... 71
Introduction to the JESD204B Interface ................................. 71
JESD204B Overview .................................................................. 71
Functional Overview ................................................................. 72
JESD204B Link Establishment ................................................. 72
Physical Layer (Driver) Outputs .............................................. 74
Setting Up the AD9695 Digital Interface ................................ 75
Deterministic Latency .................................................................... 81
Subclass 0 Operation ................................................................. 81
Subclass 1 Operation ................................................................. 81
Multichip Synchronization ........................................................... 83
Normal Mode ............................................................................. 83
Timestamp Mode ....................................................................... 83
SYSREF± Input ........................................................................... 85
SYSREF± Setup/Hold Window Monitor ................................ 87
Latency ............................................................................................. 89
End to End Total Latency ......................................................... 89
Example Latency Calculations ................................................. 89
LMFC Referenced Latency ....................................................... 89
Test Modes ...................................................................................... 91
ADC Test Modes ........................................................................ 91
JESD204B Block Test Modes .................................................... 92
Serial Port Interface (SPI) ............................................................. 94
Configuration Using the SPI .................................................... 94
Hardware Interface .................................................................... 94
SPI Accessible Features ............................................................. 94
Memory Map .................................................................................. 95
Reading the Memory Map Register Table .............................. 95
Memory Map Registers ............................................................. 96
Applications Information ........................................................... 134
Data Sheet AD9695
Rev. C | Page 3 of 136
Power Supply Recommendations .......................................... 134
Layout GuideLines ................................................................... 135
AVDD1_SR (Pin 57) and AGND_SR (Pin 56 and Pin 60) ... 135
Outline Dimensions ..................................................................... 136
Ordering Guide ......................................................................... 136
REVISION HISTORY
6/2020—Rev. B to Rev. C
Changes to Table 48 ........................................................................ 97
12/2019—Rev. A to Rev. B
Changes to Input Common Mode Section .................................. 28
Added DDC Power Consumption Section and Table 31;
Renumbered Sequentially .............................................................. 67
Changes to Table 35 ........................................................................ 76
Changes to Table 36 ........................................................................ 77
Changes to Table 37 ........................................................................ 78
Changes to Table 48 ........................................................................ 96
10/2017—Rev. 0 to Rev. A
Changes to Table 5 .......................................................................... 10
Change to Theory of Operation Section ...................................... 27
Changes to Table 47 ...................................................................... 130
Updated Outline Dimensions ..................................................... 135
9/2017—Revision 0: Initial Version
AD9695 Data Sheet
Rev. C | Page 4 of 136
GENERAL DESCRIPTION
The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-to-
digital converter (ADC). The device has an on-chip buffer and a
sample-and-hold circuit designed for low power, small size, and
ease of use. This product is designed to support communications
applications capable of direct sampling wide bandwidth analog
signals of up to 2 GHz. The −3 dB bandwidth of the ADC input
is 2 GHz. The AD9695 is optimized for wide input bandwidth,
high sampling rate, excellent linearity, and low power in a small
package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. The analog input and clock signals
are differential inputs. The ADC data outputs are internally
connected to four digital downconverters (DDCs) through a
crossbar mux. Each DDC consists of multiple signal processing
stages: a 48-bit frequency translator (numerically controlled
oscillator (NCO)), and decimation filters. The NCO has the option
to select up to 16 preset bands over the general-purpose input/
output (GPIO) pins, or use a coherent fast frequency hopping
mechanism for band selection. Operation of the AD9695 between
the DDC modes is selectable via SPI-programmable profiles.
In addition to the DDC blocks, the AD9695 has several functions
that simplify the automatic gain control (AGC) function in a
communications receiver. The programmable threshold detector
allows monitoring of the incoming signal power using the fast
detect control bits in Register 0x0245 of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to
avoid an overrange condition at the ADC input. In addition to
the fast detect outputs, the AD9695 also offers signal
monitoring capability. The signal monitoring block provides
additional information about the signal being digitized by the
ADC.
The user can configure the Subclasss 1 JESD204B-based high
speed serialized output using either one lane, two lanes, or four
lanes, depending on the DDC configuration and the acceptable
lane rate of the receiving logic device. Multidevice synchronization
is supported through the SYSREF± and SYNCINB± input pins.
The AD9695 has flexible power-down options that allow
significant power savings when desired. All of these features
can be programmed using a 3-wire serial port interface (SPI)
and or PDWN/STBY pin.
The AD9695 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +105°C junction temperature range.
This product may be protected by one or more U.S. or
international patents.
Note that, throughout this data sheet, multifunction pins, such
as FD_A/GPIO_A0, are referred to either by the entire pin
name or by a single function of the pin, for example, FD_A,
when only that function is relevant.
PRODUCT HIGHLIGHTS
1. Low power consumption per channel.
2. JESD204B lane rate support up to 16 Gbps.
3. Wide, full power bandwidth supports intermediate
frequency (IF) sampling of signals up to 2 GHz.
4. Buffered inputs ease filter design and implementation.
5. Four integrated wideband decimation filters and NCO
blocks supporting multiband receivers.
6. Programmable fast overrange detection.
7. On-chip temperature diode for system thermal management.
Data Sheet AD9695
Rev. C | Page 5 of 136
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ)
range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C
(TA = 25°C for the AD9695-1300 speed grade).
Table 1.
Parameter
1300 MSPS 625 MSPS
Min Typ Max Min Typ Max Unit
RESOLUTION 14 14 Bits
ACCURACY
No Missing Codes Guaranteed Guaranteed
Offset Error1 5 5 Codes
Offset Matching −0.48 0 +0.48 −0.25 0 +0.25 % FSR
Gain Error −2.9 ±1 +2.9 −2.6 ±2.22 +2.6 % FSR
Gain Matching −2.64 ±0.18 +2.64 −2.5 ±0.18 +2.5 % FSR
Differential Nonlinearity (DNL) −0.7 0.8 −0.8 +0.8 LSB
Integral Nonlinearity (INL) −7 ±1 5 −5 ±2 +5 LSB
TEMPERATURE DRIFT
Offset Error ±9 ±6 ppm/°C
Gain Error 69 123 ppm/°C
INTERNAL VOLTAGE REFERENCE
Voltage 0.5 0.5 V
INPUT-REFERRED NOISE 3.8 2.7 LSB rms
ANALOG INPUTS
Differential Input Voltage Range 1.36 1.59 2.04 1.36 1.7 2.04 V p-p
Common-Mode Voltage (VCM) 1.41 1.41 V
Differential Input Resistance 200 200 Ω
Differential Input Capacitance 1.75 1.75 pF
Analog Full-Power Bandwidth 2 2 GHz
POWER SUPPLY
AVDD1 0.93 0.95 0.98 0.93 0.95 0.98 V
AVDD2 1.71 1.8 1.89 1.71 1.8 1.89 V
AVDD3 2.44 2.5 2.56 2.44 2.5 2.56 V
AVDD1_SR 0.93 0.95 0.98 0.93 0.95 0.98 V
DVDD 0.93 0.95 0.98 0.93 0.95 0.98 V
DRVDD1 0.93 0.95 0.98 0.93 0.95 0.98 V
DRVDD2 1.71 1.8 1.89 1.71 1.8 1.89 V
SPIVDD2 1.71 1.8 1.89 1.71 1.8 1.89 V
IAVDD1 304 383 182 257 mA
IAVDD2 450 500 267 292 mA
IAVDD3 55 61 29 35 mA
IAVDD1_SR 15 27 9 15 mA
IDVDD 218 400 103 293 mA
IDRVDD1 3 146 229 103 176 mA
IDRVDD2 25 29 28 35 mA
ISPIVDD 2 5 2 5 mA
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)4 1.39 1.6 2 0.86 0.98 1.35 W
Power-Down Dissipation 215 200 mW
Standby5 890 740 mW
1 DC offset calibration on (Register 0x0701, Bit 7 = 1 and Register 0x073B, Bit 7 = 0).
2 The voltage level on the SPIVDD rail and on the DRVDD2 rail must be the same.
3 All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used.
4 Default mode. No DDCs used.
5 Can be controlled by SPI.
AD9695 Data Sheet
Rev. C | Page 6 of 136
AC SPECIFICATIONS—1300 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 1300 MSPS,
DCS on, buffer current settings specified in Table 11, unless otherwise noted. Minimum and maximum specifications are guaranteed for
the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 40°C (TA = 25°C for
the AD9695-1300 speed grade).
Table 2.
Parameter1
Analog Input Full
Scale = 1.36 V p-p
Analog Input Full Scale =
1.59 V p-p
Analog Input Full Scale =
2.04 V p-p
Unit Min Typ Max Min Typ Max Min Typ Max
ANALOG INPUT FULL SCALE
1.36
1.59
2.04
V p-p
NOISE DENSITY2 −152.6 −153.9 −155.6 dBFS/Hz
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10.3 MHz 64.4 65.7 67.5 dBFS
fIN = 172.3 MHz 64.4 64.5 65.6 67.5 dBFS
fIN = 340 MHz 64.3 65.6 67.3 dBFS
fIN = 750 MHz 64.0 65.2 66.6 dBFS
fIN = 1000 MHz 63.8 64.9 66.1 dBFS
fIN = 1400 MHz 63.2 64.2 65.2 dBFS
fIN = 1700 MHz 62.7 63.6 64.5 dBFS
fIN = 1980 MHz 62.3 63.0 63.9 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
fIN = 10.3 MHz 64.3 65.4 66.1 dBFS
fIN = 172.3 MHz 64.3 64.3 65.4 66.2 dBFS
fIN = 340 MHz 64.2 65.3 65.7 dBFS
fIN = 750 MHz 63.9 65.0 65.5 dBFS
fIN = 1000 MHz 63.6 64.7 65.7 dBFS
fIN = 1400 MHz 63.1 63.8 62.9 dBFS
fIN = 1700 MHz 62.6 63.4 64.2 dBFS
fIN = 1980 MHz 62.1 62.8 61.8 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10.3 MHz 10.3 10.5 10.6 Bits
fIN = 172.3 MHz 10.3 10.3 10.5 10.7 Bits
fIN = 340 MHz 10.3 10.5 10.6 Bits
fIN = 750 MHz 10.3 10.5 10.5 Bits
fIN = 1000 MHz 10.2 10.4 10.6 dBFS
fIN = 1400 MHz 10.1 10.3 10.1 dBFS
fIN = 1700 MHz 10.1 10.2 10.3 dBFS
fIN = 1980 MHz 10.0 10.1 9.9 dBFS
SPURIOUS FREE DYNAMIC RANGE
(SFDR)
fIN = 10.3 MHz 81 79 73 dBFS
fIN = 172.3MHz 81 74 78 72 dBFS
fIN = 340 MHz 80 77 71 dBFS
fIN = 750 MHz 83 80 72 dBFS
fIN = 1000 MHz 82 81 79 dBFS
fIN = 1400 MHz 80 76 67 dBFS
fIN = 1700 MHz 80 80 78 dBFS
fIN = 1980 MHz 81 79 68 dBFS
Data Sheet AD9695
Rev. C | Page 7 of 136
Parameter1
Analog Input Full
Scale = 1.36 V p-p
Analog Input Full Scale =
1.59 V p-p
Analog Input Full Scale =
2.04 V p-p
Unit Min Typ Max Min Typ Max Min Typ Max
WORST OTHER, EXCLUDING 2ND OR
3RD HARMONIC
fIN = 10.3 MHz −96 −94 −101 dBFS
fIN = 172.3 MHz −95 −96 −85 −95 dBFS
fIN = 340 MHz −98 −99 −98 dBFS
fIN = 750 MHz −95 −95 −92 dBFS
fIN = 1000 MHz −96 −93 −91 dBFS
fIN = 1400 MHz −90 −89 −86 dBFS
fIN = 1700 MHz −91 −90 −84 dBFS
fIN = 1980 MHz −90 −90 −77 dBFS
TWO-TONE INTERMODULATION
DISTORTION (IMD), AIN1 AND AIN2 =
−7.0 dBFS
fIN1 = 170.8 MHz, fIN2 = 173.8 MHz −84 −84 −83 dBFS
fIN1 = 343.5 MHz, fIN2 = 346.5 MHz −83 −82 −81 dBFS
CROSSTALK3 >95 >95 >95 dB
Overrange Condition4 >95 >95 >95 dB
ANALOG INPUT BANDWIDTH, FULL
POWER5
2 2 2 GHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Noise density is measured at a low analog input frequency (10 MHz).
3 Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel.
4 The overrange condition is specified with 3 dB of the full-scale input range.
5 Full power bandwidth is the bandwidth of operation to achieve proper ADC performance.
AD9695 Data Sheet
Rev. C | Page 8 of 136
AC SPECIFICATIONS—625 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS,
DCS off, buffer current setting specified in Table 11, unless otherwise noted. Minimum and maximum specifications are guaranteed for the
full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the
AD9695-625 speed grade).
Table 3.
Parameter1
Analog Input Full
Scale = 1.36 V p-p
Analog Input Full Scale =
1.7 V p-p
Analog Input Full Scale =
2.04 V p-p
Unit Min Typ Max Min Typ Max Min Typ Max
ANALOG INPUT FULL SCALE
1.36
1.7
2.04
V p-p
NOISE DENSITY2 −150.5 −152.3 −153.5 dBFS/Hz
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10.3 MHz 65.5 67.3 68.6 dBFS
fIN = 172.3 MHz 65.4 65.5 67.2 68.5 dBFS
fIN = 340 MHz 65.4 67.1 68.3 dBFS
fIN = 750 MHz 65.0 66.6 67.7 dBFS
fIN = 1000 MHz 64.8 66.3 67.3 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
fIN = 10.3 MHz 65.5 66.9 67.2 dBFS
fIN = 172.3 MHz 65.4 66.3 67.0 68.0 dBFS
fIN = 340 MHz 65.2 67.0 67.9 dBFS
fIN = 750 MHz 64.9 65.4 67.0 dBFS
fIN = 1000 MHz 64.6 65.0 67.0 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10.3 MHz 10.6 10.8 10.9 Bits
fIN = 172.3 MHz 10.6 10.6 10.8 11.0 Bits
fIN = 340 MHz 10.5 10.8 11.0 Bits
fIN = 750 MHz 10.5 10.6 10.8 Bits
fIN = 1000 MHz 10.4 10.5 10.8 Bits
SPURIOUS FREE DYNAMIC RANGE
(SFDR)
fIN = 10.3 MHz 88 79 74 dBFS
fIN = 172.3MHz 88 75 89 78 dBFS
fIN = 340 MHz 79 80 77 dBFS
fIN = 750 MHz 83 84 77 dBFS
fIN = 1000 MHz 85 83 82 dBFS
WORST OTHER, EXCLUDING 2ND OR
3RD HARMONIC
fIN = 10.3 MHz −100 −101 −99 dBFS
fIN = 172.3 MHz −101 −97 −90 −99 dBFS
fIN = 340 MHz −100 −102 −98 dBFS
fIN = 750 MHz −98 −98 −100 dBFS
fIN = 1000 MHz −100 −98 −100 dBFS
TWO-TONE INTERMODULATION
DISTORTION (IMD), AIN1 AND AIN2 =
−7.0 dBFS
fIN1 = 170.8 MHz, fIN2 = 173.8 MHz −88 −88 −83 dBFS
fIN1 = 343.5 MHz, fIN2 = 346.5 MHz −89 −89 −84 dBFS
CROSSTALK3 >95 >95 >95 dB
Overrange Condition4 >95 >95 >95 dB
Data Sheet AD9695
Rev. C | Page 9 of 136
Parameter1
Analog Input Full
Scale = 1.36 V p-p
Analog Input Full Scale =
1.7 V p-p
Analog Input Full Scale =
2.04 V p-p
Unit Min Typ Max Min Typ Max Min Typ Max
ANALOG INPUT BANDWIDTH, FULL
POWER5
2 2 2 GHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Noise density is measured at a low analog input frequency (10 MHz).
3 Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel.
4 The overrange condition is specified with 3 dB of the full-scale input range.
5 Full power bandwidth is the bandwidth of operation to achieve proper ADC performance.
DIGITAL SPECIFICATIONS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and
TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
Table 4.
Parameter Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance LVDS/LVPECL
Differential Input Voltage 400 800 1600 mV p-p
Input Common-Mode Voltage 0.65 V
Input Resistance (Differential) 32 kΩ
Input Capacitance (Differential) 0.9 pF
SYSREF INPUTS (SYSREF+, SYSREF−)
Logic Compliance LVDS/LVPECL
Differential Input Voltage 400 800 1800 mV p-p
Input Common-Mode Voltage 0.65 2 V
Input Resistance (Differential) 18 kΩ
Input Capacitance (Differential) 1 pF
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0,
FD_B/GPIO_B0)
Logic Compliance CMOS
Logic 1 Voltage 0.75 × SPIVDD V
Logic 0 Voltage 0 0.35 × SPIVDD V
Input Resistance 30 kΩ
LOGIC OUTPUT (SDIO, FD_A, FD_B)
Logic Compliance CMOS
Logic 1 Voltage (IOH = 4 mA) SPIVDD − 0.45 V
Logic 0 Voltage (IOL = 4 mA) 0 0.45 V
SYNCIN INPUTS (SYNCINB−, SYNCINB+)
Logic Compliance LVDS/LVPECL/CMOS
Differential Input Voltage 400 800 1800 mV p-p
Input Common-Mode Voltage 0.65 2 V
Input Resistance (Differential) 18 kΩ
Input Capacitance (Single-Ended per Pin) 1 pF
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3)
Logic Compliance SST
Differential Output Voltage 360 520 770 mV p-p
Differential Termination Impedance 80 100 1200 Ω
AD9695 Data Sheet
Rev. C | Page 10 of 136
SWITCHING SPECIFICATIONS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ)
range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and
TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
Table 5.
Parameter
1300 MSPS
625 MSPS
Min Typ Max Min Typ Max Unit
CLOCK
Clock Rate (at CLK+/CLK− Pins) 0.24 2.8 0.24 2.8 GHz
Maximum Sample Rate1 1400 640 MSPS
Minimum Sample Rate2 240 240 MSPS
Clock Pulse Width3
High 156.25 156.25 ps
Low 156.25 156.25 ps
OUTPUT PARAMETERS
Unit Interval (UI)4 62.5 76.9 62.5 160 ps
Rise Time (tR) (20% to 80% into 100 Ω Load) 28 28 ps
Fall Time (tF) (20% to 80% into 100 Ω Load) 28 28 ps
Phase-Locked Loop (PLL) Lock Time 5 5 ms
Data Rate per Channel (NRZ)5 1.6875 13 16 1.6875 6.25 16 Gbps
LATENCY6
Pipeline Latency 56 56 Clock cycles
Fast Detect Latency 26 26 Clock cycles
Wake-Up Time7
Standby 400 400 us
Power-Down 15 15 ms
APERTURE
Aperture Delay (tA) 192 159.5 ps
Aperture Uncertainty (Jitter, tJ) 43 49.2 fs rms
Out of Range Recovery Time 1 1 Clock cycles
1 The maximum sample rate is the clock rate after the divider.
2 The minimum sample rate operates at 240 MSPS. See SPI Register 0x011A to reduce the threshold of the clock detect circuit.
3 Clock duty stabilizer (DCS) on. See SPI Register 0x011C and 0x011E to enable DCS.
4 Baud rate = 1/UI. A subset of this range can be supported.
5 Default L = 4. This number can change based on the sample rate and decimation ratio.
6 No DDCs used. L = 4, M = 2, and F = 1.
7 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Data Sheet AD9695
Rev. C | Page 11 of 136
TIMING SPECIFICATIONS
Table 6.
Parameter Test Conditions/Comments Min Typ
Ma
x Unit
CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 3
tSU_SR Device clock to SYSREF+ setup time −70 ps
tH_SR Device clock to SYSREF+ hold time 120 ps
SPI TIMING REQUIREMENTS See Figure 4
tDS Setup time between the data and the rising edge of SCLK 4 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
tCLK Period of the SCLK 40 ns
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
tHIGH Minimum period that SCLK must be in a logic high state 10 ns
tLOW Minimum period that SCLK must be in a logic low state 10 ns
tACCESS Maximum time delay between falling edge of SCLK and output
data valid for a read operation
6 10 ns
tDIS_SDIO Time required for the SDIO pin to switch from an output to an
input relative to the CSB rising edge (not shown in Figure 4)
10 ns
Timing Diagrams
A B C D E F G H I J CONVERTER0
SAMPLE N – 56 MSB
SERDOUT0–
SERDOUT0+
CLK–
CLK+
CLK–
CLK+
A B C D E F G H I J CONVERTER0
SAMP LE N – 56 L S B
SERDOUT1–
SERDOUT1+
ABCD E F G H I J CONVERTER0
SAMPLE N – 55 MSB
SERDOUT2–
SERDOUT2+
A B C D E F G H I J CONVERTER0
SAMP LE N – 55 L S B
SERDOUT3–
SERDOUT3+
APERT URE DE LAY
N – 55
N – 54 N – 53
N – 1
N + 1
SAMPLE N
N – 56
ANALOG
INPUT
SIGNAL
SAMP LE N – 56 AND N – 55
ENCODE D INT O O NE
8-BI T/10- BIT S Y M BOL
15660-002
Figure 2. Data Output Timing Diagram
CLK–
CLK+
SYSREF–
SYSREF+
t
H_SR
t
SU_SR
15660-003
Figure 3. SYSREF± Setup and Hold Timing Diagram
Data Sheet AD9695
Rev. C | Page 13 of 136
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Electrical
AVDD1 to AGND 1.05 V
AVDD1_SR to AGND 1.05 V
AVDD2 to AGND 2.00 V
AVDD3 to AGND 2.70 V
DVDD to DGND 1.05 V
DRVDD1 to DRGND 1.05 V
DRVDD2 to DRGND 2.00 V
SPIVDD to DGND 2.00 V
AGND to DRGND −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
DGND to DRGND −0.3 V to +0.3 V
VIN±x to AGND AGND − 0.3 V to AVDD3 + 0.3 V
CLK± to AGND AGND − 0.3 V to AVDD1 + 0.3 V
SCLK, SDIO, CSB to DGND DGND − 0.3 V to SPIVDD + 0.3 V
PDWN/STBY to DGND DGND − 0.3 V to SPIVDD + 0.3 V
SYSREF± to AGND 2.5 V
SYNCINB± to DRGND 2.5 V
Junction Temperature Range
(TJ)
−40°C to +125°C
Storage Temperature Range,
Ambient (TA)
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL CHARACTERISTICS
Typical θJA, θJB, and θJC are specified vs. the number of printed
circuit board (PCB) layers in different airflow velocities (in m/sec).
Airflow increases heat dissipation effectively reducing θJA and θJB.
In addition, metal in direct contact with the package leads and
exposed pad from metal traces, through holes, ground, and
power planes, reduces θJA. Thermal performance for actual
applications requires careful inspection of the conditions in
an application. The use of appropriate thermal management
techniques is recommended to ensure that the maximum
junction temperature does not exceed the limits shown in Table 7.
Table 8. Thermal Resistance
Package
Type
Airflow
Velocity
(m/sec)
θ
JA1, 2
θ
JC_BOT1, 3
θ
JC_TOP1, 3
θ
JB1, 4
θ
JT1,2
Unit
CP
-64-17 0
22.5
1.7
7.6
4.3
0.2
°C/W
1.0
17.9
°C/W
2.5
16.8
°C/W
1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
ESD CAUTION
AD9695 Data Sheet
Rev. C | Page 14 of 136
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9695
TOP VIEW
(No t t o Scal e)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FD_A/GPIO_A0
DRGND
DRVDD1
SYNCINB–
SYNCINB+
SERDOUT0–
SERDOUT0+
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SERDOUT3+
DRVDD1
DRGND
FD_B/GPIO_B0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD1
AVDD2
AVDD2
AVDD1
AGND_SR
SYSREF–
SYSREF+
AVDD1_SR
AGND_SR
AVDD1
CLK–
CLK+
AVDD1
AVDD2
AVDD2
AVDD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD1
AVDD1
AVDD2
AVDD3
VIN–A
VIN+A
AVDD3
AVDD2
AVDD2
AVDD2
DRVDD2
VREF
SPIVDD
PDWN/STBY
DVDD
DGND
AVDD1
AVDD1
AVDD2
AVDD3
VIN–B
VIN+B
AVDD3
AVDD2
AVDD2
AVDD2
SPIVDD
CSB
SCLK
SDIO
DVDD
DGND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NOTES
1. ANALOG GRO UND. CO NNE CT T HE E X P OSE D P AD TO THE
ANALOG GRO UND P LANE.
15660-005
Figure 5. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No. Mnemonic Type Description
1, 2, 47 to 49, 52,
55, 61, 64
AVDD1 Power supply Analog Power Supply (0.95 V Nominal).
3, 8 to 10, 39 to 41,
46, 50, 51, 62, 63
AVDD2 Power supply Analog Power Supply (1.8 V Nominal).
4, 7, 42, 45 AVDD3 Power supply Analog Power Supply (2.5 V Nominal).
5, 6 VIN−A, VIN+A Analog input ADC A Analog Input Complement/True.
11 DRVDD2 Power supply Digital Driver Power Supply (1.8 V Nominal).
12 VREF Input/output Reference Voltage Input (0.50 V)/Do Not Connect. This pin is configurable
through the SPI as a no connect pin or as an input. Do not connect this pin if
using the internal reference. This pin requires a 0.50 V reference voltage
input if using an external voltage reference source.
13, 38 SPIVDD Power supply Digital Power Supply for SPI (1.8 V Nominal).
14 PDWN/STBY Digital control input Power-Down Input (Active High). The operation of this pin depends on the
SPI mode and can be configured as power-down or standby.
15, 34 DVDD Power supply Digital Power Supply (0.95 V Nominal).
16, 33 DGND Ground power
supply
Digital Control Ground Supply. These pins connect to the digital ground plane.
17 FD_A/GPIO_A0 CMOS output Fast Detect Output for Channel A (FD_A). General-purpose input/output
(GPIO) Pin A0 (GPIO_A0).
32 FD_B/GPIO_B0 CMOS output Fast Detect Output for Channel B (FD_B). GPIO Pin B0 (GPIO_B0).
18, 31 DRGND Ground power
supply
Digital Driver Ground Supply. This pin connects to the digital driver ground
plane.
19, 30 DRVDD1 Power supply Digital Driver Power Supply (0.95 V Nominal).
20 SYNCINB− Digital input Active Low JESD204B LVDS/CMOS Sync Input True.
21 SYNCINB+ Digital input Active Low JESD204B LVDS Sync Input Complement.
22, 23 SERDOUT0−,
SERDOUT0+
Data output Lane 0 Output Data Complement/True.
24, 25 SERDOUT1−,
SERDOUT1+
Data output Lane 1 Output Data Complement/True.
Data Sheet AD9695
Rev. C | Page 15 of 136
Pin No. Mnemonic Type Description
26, 27 SERDOUT2−
SERDOUT2+
Data output Lane 2 Output Data Complement/True.
28, 29 SERDOUT3−,
SERDOUT3+
Data output Lane 3 Output Data Complement/True.
35 SDIO Digital control
input/output
SPI Serial Data Input/Output.
36 SCLK Digital control input SPI Serial Clock.
37 CSB Digital control input SPI Chip Select (Active Low).
43, 44 VIN+B, VIN−B Analog input ADC B Analog Input True/Complement.
53, 54 CLK+, CLK− Analog input Clock Input True/Complement.
56, 60 AGND_SR Ground power
supply
Ground Reference for SYSREF±.
57 AVDD1_SR Power supply Analog Power Supply for SYSREF± (0.95 V Nominal).
58, 59 SYSREF+,
SYSREF−
Digital input Active High JESD204B LVDS System Reference Input Complement/True.
EPAD Ground power
supply
Analog Ground. Connect the exposed pad to the analog ground plane.
AD9695 Data Sheet
Rev. C | Page 16 of 136
TYPICAL PERFORMANCE CHARACTERISTICS
1300 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), buffer current setting specified in Table 11, dc offset calibration enabled, unless otherwise noted. Minimum and maximum
specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent
performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
10
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
A
IN
= 10.3M Hz
SNR = 65. 7dBF S
SFDR = 79.0d BFS
BUFF E R CURRE NT = 300µ A
15660-305
Figure 6. Single-Tone FFT with Analog Input Frequency (fIN) = 10.3 MHz
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
AIN = 172.3MHz
SNR = 65. 6dBF S
SFDR = 78.0d BFS
BUFF E R CURRE NT = 300µ A
15660-306
Figure 7. Single-Tone FFT with Analog Input Frequency (fIN) = 172.3 MHz
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
AIN = 342.3MHz
SNR = 65. 6dBF S
SFDR = 77.0d BFS
BUFF E R CURRE NT = 300µA
15660-307
Figure 8. Single-Tone FFT with fIN = 342.3 MHz
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
AIN = 752.3MHz
SNR = 65. 2dBF S
SFDR = 80.0d BFS
BUFF E R CURRE NT = 300µA
15660-308
Figure 9. Single-Tone FFT with fIN =752.3 MHz
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
AIN = 1002.3MHz
SNR = 64. 9dBF S
SFDR = 81.0d BFS
BUFF E R CURRE NT = 300µA
15660-309
Figure 10. Single-Tone FFT with fIN = 1002.3 MHz
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
A
IN
= 1402.3M Hz
SNR = 64. 2dBF S
SFDR = 76.0d BFS
BUFF E R CURRE NT = 300µA
15660-310
Figure 11. Single-Tone FFT with fIN = 1402.3 MHz
Data Sheet AD9695
Rev. C | Page 17 of 136
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
A
IN
= 1702.3M Hz
SNR = 63. 6dBF S
SF DR = 80.0d BFS
BUFFER CURRENT = 300µA
15660-311
Figure 12. Single-Tone FFT with fIN = 1702.3 MHz
–130 0600
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
200 400
A
IN
= 1980.3M Hz
SNR = 63. 0dBF S
SF DR = 79.0d BFS
BUFFER CURRENT = 300µA
15660-312
Figure 13. Single-Tone FFT with fIN = 1980.3 MHz
85
60
500 1300
SNR/ S FDR (d BFS)
SAMPLE RATE (MHz)
65
70
75
80
700 900 1100
SNR
SFDR
15660-313
Figure 14. SNR/SFDR vs. Sample Rate, fIN =172.3 MHz
0500 1000 1500 2000
SNR (dBFS )
ANALO G I NP UT F RE QUENCY ( M Hz )
67
61
62
63
64
65
66
T
J
= +105°C
ROOM
T
J
= –40° C
15660-314
Figure 15. SNR vs. Analog Input Frequency (fIN) at Minimum, Room, and
Maximum Temperatures
0500 1000 1500 2000
SDFR (dBFS)
ANALO G I NP UT F RE QUENCY ( M Hz )
90
60
T
J
= +105°C
ROOM
T
J
= –40° C
65
70
75
80
85
15660-315
Figure 16. SFDR vs. Analog Input Frequency (fIN) at Minimum, Room, and
Maximum Temperatures
–160 0600
–110
–60
–10
200 400
AMPLITUDE (dBFS)
FREQUENCY (MHz)
15660-316
f
IN1
= 170.8M Hz
f
IN2
= 173.8M Hz
IM D = –84dBF S
BUFFER CURRENT = 300µA
Figure 17. Two-Tone FFT; fIN1 = 170.8 MHz, fIN2 = 173.8 MHz
AD9695 Data Sheet
Rev. C | Page 18 of 136
0
–140 0200 400 600
–90
–40
AMPLITUDE (dBFS)
FREQUENCY (MHz)
15660-317
f
IN1
= 343.5M Hz
f
IN2
= 346.5M Hz
IMD = –82dBF S
BUFF E R CURRE NT = 300µA
Figure 18. Two-Tone FFT; fIN1 = 343.5 MHz, fIN2 = 346.5 MHz
120
–40
–100 0
SNR/S FDR (dB)
ANALOG INPUT AMPLITUDE (dBFS)
–20
0
20
40
60
80
100
–80 –60 –40 –20
SFDR (dBFS)
SNRFS
SNR (dBc)
SFDR (dBc)
15660-318
Figure 19. SNR/SFDR vs. Analog Input Amplitude, fIN = 172.3 MHz
10
–130
–95 –15
SF DR/IM D3 (dB)
ANALO G I NP UT AMP LI TUDE ( dB)
SFDR (dBFS)
SFDR (dBc)
IMD3 (dBc)
IMD3 (dBFS)
–110
–90
–70
–50
–30
–10
–75 –55 –35
15660-319
Figure 20. SFDR/IMD3 vs. Analog Input Amplitude, fIN = 172.3 MHz
85
60
–40 110
SNR/S FDR (dBF S )
JUNCTI ON T E M P E RATURE ( °C)
65
70
75
80
10 60
SNR
SFDR
15660-320
Figure 21. SNR/SFDR vs. Junction Temperature, fIN = 172.3 MHz
2
–4 05000 10000 15000
INL (LSB)
OUT P UT CO DE
–3
–2
–1
0
1
15660-321
Figure 22. INL, fIN = 10.3 MHz
0.3
–0.4 05000 10000 15000
DNL ( LSB)
OUT P UT CO DE
–0.3
–0.2
–0.1
0
0.1
0.2
15660-322
Figure 23. DNL, fIN = 10.3 MHz
Data Sheet AD9695
Rev. C | Page 19 of 136
20000
15000
10000
5000
0
–16 14 16
NUMBER OF HIT S
CODE
–13 –10 –7 –4 –1 2 5 8 11
15660-323
Figure 24. Input Referred Noise Histogram
0
–16
–14
04000
AMPLITUDE (dBFS)
A
IN
FREQUENCY (MHz)
–12
–10
–8
–6
–4
–2
1000 2000 3000
15660-019
Figure 25. Full Power Bandwidth
2.0
1.2
–40 10 60 110
TOTAL POWER CONSUMPTION (W)
1.4
1.6
1.8
JUNCTI ON T E M P E RATURE ( °C)
15660-325
Figure 26. Total Power Dissipation vs. Junction Temperature
1.8
1.6
1.4
1.2
500 1300
POWER CONSUMPTION (W)
SAMPLE RATE (MHz)
700 900 1100
15660-326
Figure 27. Total Power Dissipation vs. Sample Rate (fS)
66
61 0500 1000 1500 2000
SNR (dBFS )
ANALO G I NP UT F RE QUENCY ( M Hz )
62
63
64
65
400mV
600mV
800mV
1000mV
1200mV
1400mV
1600mV
1800mV
2000mV
15660-327
CLO CK AMPL IT UDE
Figure 28. SNR vs. Analog Input Frequency at Different Clock Amplitudes
86
72
SFDR (dBFS)
74
76
78
80
82
84
0500 1000 1500 2000
ANALO G I NP UT F RE QUENCY ( M Hz )
BUFF E R CURRE NT = 460µA
BUFF E R CURRE NT = 400µA
BUFF E R CURRE NT = 360µA
BUFF E R CURRE NT = 300µA
15660-328
Figure 29. SFDR vs. Analog Input Frequency with Different Buffer Current Settings
AD9695 Data Sheet
Rev. C | Page 20 of 136
68
61
SNR (dBFS )
62
63
64
65
66
67
0500 1000 1500 2000
ANALO G I NP UT F RE QUENCY ( M Hz )
2.04V
1.81V
1.59V
1.36V
15660-329
Figure 30. SNR vs. Analog Input Frequency with Different Analog Input Full-
Scale Values
90
60
SFDR (dBFS)
65
70
75
80
85
0500 1000 1500 2000
ANALO G I NP UT F RE QUENCY ( M Hz )
2.04V
1.81V
1.59V
1.36V
15660-330
Figure 31. SFDR vs. Analog Input Frequency with Different Analog Input Full-
Scale Values
90
50
300 350 400 450
IAVDD3 (mA)
BUFF E R CURRE NT SE TT ING ( µ A)
60
70
80
15660-331
Figure 32. IAVDD3 vs. Buffer Control 1 Setting in Register 0x1A4C
Data Sheet AD9695
Rev. C | Page 21 of 136
625 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off
(AD9695-625 speed grade), buffer current setting specified in Table 11, and dc offset calibration enabled, unless otherwise noted. Minimum
and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications
represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
0
–120 1000200 300
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–100
–80
–60
–40
–20
AIN = –1dBFS
SNR = 67. 2dBF S
SFDR = 89dBF S
BUFF E R CURRE NT = 160µA
15660-006
Figure 33. Single-Tone FFT with Analog Input Frequency (fIN) = 172.3 MHz
0
–120 1000200 300
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–100
–80
–60
–40
–20
AIN = –1dBFS
SNR = 67. 1dBF S
SFDR = 80dBF S
BUFF E R CURRE NT = 160µA
15660-007
Figure 34. Single-Tone FFT with fIN = 340 MHz
0
–120 1000200 300
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–100
–80
–60
–40
–20
AIN = –1dBFS
SNR = 66. 6dBF S
SFDR = 84dBF S
BUFF E R CURRE NT = 300µA
15660-008
Figure 35. Single-Tone FFT with fIN =750 MHz
050 100 150 200 250 300
AIN = –1dBFS
SNR = 66. 3dBF S
SFDR = 83dBF S
BUFF E R CURRE NT = 300µA
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
–20
FREQUENCY (MHz)
15660-009
Figure 36. Single-Tone FFT with fIN = 1000 MHz
100
0450250 650 850
350 550 750
SNR/S FDR (dBF S )
SAMPLE RATE (MSPS)
20
40
60
80
SNR
SFDR
15660-010
Figure 37. SNR/SFDR vs. Sample Rate, fIN =172.3 MHz
100
40 0250 750500 1000
SNR/S FDR (dBF S )
ANALO G I NP UT F RE QUENCY ( M Hz )
50
60
70
80
90
SFDR (T
J
= –40° C)
SNR (T
J
= –40° C)
SFDR (ROOM)
SNR (RO OM)
SFDR (T
J
= +105°C)
SNR (T
J
= +105°C)
15660-011
Figure 38. SNR/SFDR vs. Analog Input Frequency (fIN) at Minimum, Room,
and Maximum Temperatures
AD9695 Data Sheet
Rev. C | Page 22 of 136
0
–120 1000200 300
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–100
–80
–60
–40
–20
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBF S
BUFF E R CURRE NT = 160µA
15660-012
Figure 39. Two-Tone FFT; fIN1 = 170.8 MHz, fIN2 = 173.8 MHz
0
–120 1000200 300
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–100
–80
–60
–40
–20
AIN1 AND AIN2 = –7dBFS
SFDR = 89dBF S
BUFF E R CURRE NT = 160µA
15660-013
Figure 40. Two-Tone FFT; fIN1 = 343.5 MHz, fIN2 = 346.5 MHz
120
100
0–60–100 0–80 –40 –20
SF DR ( dB)
ANALOG INPUT AMPLITUDE (dBFS)
20
40
60
80
SFDR (dBFS)
SFDR (dBc)
15660-014
Figure 41. SNR/SFDR vs. Analog Input Amplitude, fIN = 172.3 MHz
100
90
40 60–40 10
SNR/ S FDR (d BFS)
JUNCTI ON T E M P E RATURE ( °C)
50
60
70
80
SNR
SFDR
15660-015
Figure 42. SNR/SFDR vs. Junction Temperature, fIN = 172.3 MHz
4
–4 05000 10000 15000
INL (LSB)
OUT P UT CO DE
–3
–2
–1
0
1
2
3
15660-016
Figure 43. INL, fIN = 10.3 MHz
0.25
–0.25
DNL ( LSB)
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
05000 10000 15000
OUT P UT CO DE
15660-017
Figure 44. DNL, fIN = 10.3 MHz
Data Sheet AD9695
Rev. C | Page 23 of 136
6000
5000
4000
3000
2000
1000
0
N – 15
N + 15
NUMBER O F HI TS
CODE
N – 12
N – 9
N – 6
N – 3
0
N + 3
N + 6
N + 9
N + 12
15660-018
Figure 45. Input Referred Noise Histogram
0
–16
–14
04000
AMPLITUDE (dBFS)
A
IN
FREQUENCY (MHz)
–12
–10
–8
–6
–4
–2
1000 2000 3000
15660-019
Figure 46. Full Power Bandwidth
1.4
0
–40 110
TOTAL POWER DISSIPATION (W)
JUNCTI ON T E M P E RATURE ( °C)
0.2
0.4
0.6
0.8
1.0
1.2
10 60
15660-020
Figure 47. Total Power Dissipation vs. Junction Temperature
1.4
0
250 850
TOTAL POWER DISSIPATION (W)
SAMPLE RATE (MSPS)
0.2
0.4
0.6
0.8
1.0
1.2
350 450 550 650 750
15660-021
Figure 48. Total Power Dissipation vs. Sample Rate (fS)
68
61 01200
SNR (dBF S )
ANALO G I NP UT F RE QUENCY ( M Hz )
62
63
64
66
67
200 400 600 800 1000
400mV p- p
600mV p- p
800mV p- p
1000mV p-p
1200mV p-p
1400mV p-p
1600mV p-p
1800mV p-p
2000mV p-p
2200mV p-p
15660-022
65 CLO CK AMPL IT UDE
Figure 49. SNR vs. Analog Input Frequency at Different Clock Amplitudes
100
90
80
70
60
50
40 01200
SF DR ( dBF S )
ANALO G I NP UT F RE QUENCY ( M Hz )
200 400 600 800 1000
BUFF E R CURRE NT = 160µA
BUFF E R CURRE NT = 200µA
BUFF E R CURRE NT = 240µA
BUFF E R CURRE NT = 300µA
15660-023
Figure 50. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (AIN < 1250 MHz)
AD9695 Data Sheet
Rev. C | Page 24 of 136
80
60
1250 1450 1650 1850
SF DR ( dBF S )
ANALO G I NP UT F RE QUENCY ( M Hz )
65
70
75
BUFF E R CURRE NT = 400µA
BUFF E R CURRE NT = 300µA
BUFF E R CURRE NT = 240µA
15660-348
Figure 51. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (AIN > 1250 MHz), Register 0x1B03 = 0x02, Register 0x1B08 = 0xC1,
Register 0x1B10 = 0x1C
70
69
68
67
66
65
64
63
62
61
60 0600
SNR (dBF S )
ANALO G I NP UT F RE QUENCY ( M Hz )
200 400
INPUT F ULL - S CALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT F ULL - S CALE = 2.04V p-p
15660-024
Figure 52. SNR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN < 650 MHz)
100
95
90
85
80
75
70
65
60
55
50 0600
SF DR ( dBF S )
ANALO G I NP UT F RE QUENCY ( M Hz )
200 400
INPUT F ULL - S CALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT F ULL - S CALE = 2.04V p-p
15660-025
Figure 53. SFDR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN < 650 MHz)
69
68
67
66
65
64
63
62
61
60
650 1250
SNR (d BFS)
ANALO G I NP UT F RE QUENCY ( M Hz )
850 1050 1150750 950
INPUT F ULL - S CALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT F ULL - S CALE = 2.04V p-p
15660-026
Figure 54. SNR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN > 650 MHz)
85
80
75
70
65
60
55
50
650 1250
SFDR ( dBF S )
ANALO G I NP UT F RE QUENCY ( M Hz )
850 1050 1150750 950
INPUT F ULL - S CALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT F ULL - S CALE = 2.04V p-p
15660-027
Figure 55. SFDR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN > 650 MHz)
80
20 210 310260 360
IAV DD3 ( mA)
BUFF E R CURRE NT (µA)
160
30
40
50
60
70
15660-028
Figure 56. IAVDD3 vs. Buffer Control 1 Setting in Register 0x1A4C
Data Sheet AD9695
Rev. C | Page 25 of 136
EQUIVALENT CIRCUITS
A
IN
CONTROL
(SPI)
10pF
VIN+x
100Ω
VIN–x
AVDD3
AVDD3
V
CM
BUFFER
400Ω
100Ω
AVDD3
AVDD3
3.5pF
AVDD3
3.5pF
15660-029
Figure 57. Analog Inputs
AVDD1
25Ω
AVDD1
25Ω
16kΩ
16kΩ
V
CM
= 0.65V
CLK+
CLK–
15660-030
Figure 58. Clock Inputs
130kΩ
130kΩ
LEVEL
TRANSLATOR
SYSREF+ 10kΩ
AVDD1_SR
1.9pF
1.9pF
100Ω
SYSREF– 10kΩ
100Ω
AVDD1_SR
14808-026
Figure 59. SYSREF± Inputs
DRVDD1
DRGND
DRVDD1
DRGND
OUTPUT
DRIVER
EMPHASIS/SWING
CONTROL (SPI)
DATA+
DATA–
SERDOUTx+
x = 0, 1, 2, 3
SERDOUTx–
x = 0, 1, 2, 3
15660-032
Figure 60. Digital Outputs
130kΩ
130kΩ
LEVEL
TRANSLATOR
SYNCINB+
SYNCINB–
10kΩ
1.9pF
1.9pF
100Ω
2.5kΩ
10kΩ
100Ω
DRVDD1
DRGND
DRVDD1
DRGND
DRVDD1
DRGND
DRGND
DRGND
CMOS
PATH
SYNCI NB P IN
CONTROL (SPI)
15660-033
Figure 61. SYNCINB± Inputs
56kΩ
DGND DGND
SPIVDD
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
SCLK
15660-034
Figure 62. SCLK Input
AD9695 Data Sheet
Rev. C | Page 26 of 136
56kΩ
DGND
DGND
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
CSB
15660-035
Figure 63. CSB Input
56kΩ
SPIVDD
SDI
DGND
DGND
DGNDDGND
SDO
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
SPIVDD
SDIO
15660-036
Figure 64. SDIO Input
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
DGND
DGND
PDWN/
STBY
PDWN
CONTROL (SPI)
56kΩ
15660-037
Figure 65. PDWN/STBY Input
VREF
AGND
AVDD2
VCM OUT P UT
TEM P E RATURE DIO DE
VOLTAGE OUTPUT
EXT E RNAL REFERE NCE
VOLTAGE INPUT
VREF PIN
CONTROL (SPI)
15660-038
Figure 66. VREF Input/Output
56kΩ
FD_A/GPIO_A0,
FD_B/GPIO_B0
SPIVDD
SPIVDD
ESD
PROTECTED
ESD
PROTECTED
DGND
FD PIN CONTROL (SPI)
SPIVDD
DGND
NCO BAND SE LECT
FD
JESD204B LMF C
JESD204B SY NC~
DGND DGND
15660-039
Figure 67. FD_A/GPIO_A0 and FD_B/GPIO_B0
Data Sheet AD9695
Rev. C | Page 27 of 136
THEORY OF OPERATION
The AD9695 has two analog input channels and up to four
JESD204B output lane pairs. The ADC samples wide bandwidth
analog signals of up to 2 GHz. The actual −3 dB roll-off of the
analog inputs is 2 GHz. The AD9695 is optimized for wide input
bandwidth, high sampling rate, excellent linearity, and low
power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The AD9695 has several functions that simplify the AGC
function in a communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to
avoid an overrange condition at the ADC input.
The Subclass 1 JESD204B-based high speed, serialized output data
lanes can be configured in one-lane (L = 1), two-lane (L = 2), and
four-lane (L = 4) configurations, depending on the sample rate
and the decimation ratio. Multiple device synchronization is
supported through the SYSREF± and SYNCINB± input pins.
The SYSREF± pin in the AD9695 can also be used as a timestamp
of data as it passes through the ADC and out of the JESD204B
interface.
ADC ARCHITECTURE
The architecture of the AD9695 consists of an input buffered
pipelined ADC. The input buffer provides a termination
impedance to the analog input signal. This termination
impedance is set to 200 . The equivalent circuit diagram of the
analog input termination is shown in Figure 57. The input
buffer is optimized for high linearity, low noise, and low power
across a wide bandwidth.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample; at the same time, the remaining stages operate with the
preceding samples. Sampling occurs on the rising edge of the clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9695 is a differential buffer. The
internal common-mode voltage of the buffer is 1.41 V. The
clock signal alternately switches the input circuit between
sample mode and hold mode.
Either a differential capacitor or two single-ended capacitors
(or a combination of both) can be placed on the inputs to
provide a matching passive network. These capacitors
ultimately create a low-pass filter that limits unwanted
broadband noise. For more information, refer to the Analog
Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005). In
general, the precise front-end network component values
depend on the application.
Figure 68 shows the differential input return loss curve for the
analog inputs across a frequency range of 1 MHz to 10 GHz.
The reference impedance is 100 Ω.
15660-200
1
2
3
4
5
6
1: 1.000MHz
170.59nF
2: 100.000 MHz
45.72pF
3: 200.000MHz
12.07pF
4: 300.000MHz
6.49pF
5: 400.000MHz
4.70pF
6: 500.000MHz
4.00pF
182.88Ω
–932.98mΩ
177.37Ω
–34.81Ω
157.29Ω
–65.95Ω
128.82Ω
–81.70Ω
102.55Ω
–84.58Ω
82.01Ω
–79.60Ω
CH1 AVG = 1
> CH1: START 1.0MHz
STOP 10.0000GHz
Figure 68. AD9695 Different Input Return Loss
For best dynamic performance, the source impedances driving
VIN+x and VIN−x must be matched such that any common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. For the AD9695,
the available span is programmable through the SPI port from
1.36 V p-p to 2.04 V p-p differential, with 1.7 V p-p differential
being the default.
Differential Input Configurations
There are several ways to drive theAD9695, either actively or
passively. Optimum performance is achieved by driving the
analog input differentially.
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 69 and Table 10) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD9695.
For low to midrange frequencies, a double balun or double
transformer network (see Figure 69 and Table 10) is recom-
mended for optimum performance of the AD9695. For higher
frequencies in the second or third Nyquist zones, it is recom-
mended to remove some of the front-end passive components
to ensure wideband operation (see Table 10).
AD9695 Data Sheet
Rev. C | Page 28 of 136
ADC
200Ω
C3
C2
C1
C4
R1
NOTES:
1. SEE TABLE 9 FOR COMPONENT VALUES
R2
R2
R3
C3
C2
R1 R3
MARKI
BAL-0006
15547-050
Figure 69. Differential Transformer-Coupled Configuration for the AD9695
Table 10. Differential Transformer-Coupled Input Configuration Component Values
Speed Grade Frequency Range Transformer R1 R2 R3 C1 C2 C3 C4
AD9695-625 <2 GHz BAL-0006/BAL-0006SMG 25 Ω 25 Ω 10 Ω 0.1 μF 0.1 μF DNI1 DNI1
AD9695-1300 <2 GHz BAL-0006/BAL-0006SMG 25 Ω 25 Ω 10 Ω 0.1 μF 0.1 μF DNI1 DNI1
1 DNI means do not insert.
Input Common Mode
The analog inputs of the AD9695 are internally biased to the
common mode, as shown in Figure 71.
For dc-coupled applications, the recommended operation
procedure is to export the common-mode voltage to the VREF pin
using the SPI writes listed in this section. The common-mode
voltage must be set by the exported value to ensure proper
ADC operation. Disconnect the internal common-mode buffer
from the analog input using Register 0x1908.
When performing SPI writes for dc coupling operation, use the
following register settings, in order:
1. Set Register 0x1908, Bit 2 to 1 to disconnect the internal
common-mode buffer from the analog input.
2. Set Register 0x18A6 to 0x00 to turn off the voltage
reference.
3. Set Register 0x18E6 to 0x00 to turn off the temperature
diode export.
4. Set Register 0x18E0 to 0x02.
5. Set Register 0x18E1 to 0x14.
6. Set Register 0x18E2 to 0x14.
7. Set Register 0x18E3, Bit 6 to 0x01 to turn on the VCM export.
8. Set Register 0x18E3, Bits[5:0] to the buffer current setting
(copy the buffer current setting from Register 0x1A4C and
Register 0x1A4D to improve the accuracy of the common-
mode export).
Figure 70 shows the block diagram representation of a dc-
coupled application.
ADC
ADC
AMP A
V
OCM
V
OCM
VREF
V
CM
EXPORT SELECT
SPI REGISTERS 0x1908,
0x18A6, 0x18E3, 0x18E6)
ADC
AMP B
15660-041
Figure 70. DC-Coupled Application Using the AD9695
Analog Input Buffer Controls and SFDR Optimization
The AD9695 input buffer offers flexible controls for the analog
inputs, such as, buffer current, and input full-scale adjustment.
All the available controls are shown in Figure 71.
VIN+
100Ω
100Ω
AVDD3
A
VDD3
3.5pF
AVDD3
VIN–
AVDD3
REG
(0x0008,
0x1908)
REG (0x0008, 0x1A4C,
0x1A4D, 0x1910)
AVDD3
3.5pF
15660-042
Figure 71. Analog Input Controls
Data Sheet AD9695
Rev. C | Page 29 of 136
Using Register 0x1A4C and Register 0x1A4D, the buffer behavior
on each channel can be adjusted to optimize the SFDR over
various input frequencies and bandwidths of interest. Use Register
0x1910 to change the internal reference voltage. Changing the
internal reference voltage results in a change in the input full-scale
voltage.
When the input buffer current in Register 0x1A4C and
Register 0x1A4D is set, the amount of current required by the
AVDD3 supply changes. This relationship is shown in Figure 72.
For a complete list of buffer current settings, see Table 11.
85
80
70
60
50
75
65
55
300 350 400 450
I
AVDD3
(mA)
BUFFER CURRENT SETTING (µA)
15660-369
Figure 72. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1
Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D)
Table 11 shows the recommended values for the buffer current
for various Nyquist zones.
Absolute Maximum Input Swing
The absolute maximum input swing allowed at the inputs of the
AD9695 is 5.6 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC.
Dither
The AD9695 has internal on-chip dither circuitry that improves
the ADC linearity and SFDR, particularly at smaller signal
levels. A known but random amount of white noise is injected into
the input of theAD9695. This dither improves the small signal
linearity within the ADC transfer function and is precisely
subtracted out digitally. The dither is turned on by default and
does not reduce the ADC input dynamic range. The data sheet
specifications and limits are obtained with the dither turned on.
The dither is on by default. It is not recommended to turn it off.
Table 11. SFDR Optimization for Input Frequencies
Speed Grade Frequency
Register 0x1A4C and
Register 0x1A4D Register 0x1B03 Register 0x1B08 Register 0x1B10
AD9695-625 DC to 650 MHz 160 μA 0x00 0x01 0x00
650 MHz to 1250 MHz 300 μA 0x00 0x01 0x00
>1250 MHz 400 μA 0x02 0xC1 0x1C
AD9695-1300 All AIN frequencies 300 μA 0x02 0xC1 0x00
ADC
CORE
INPUT FULL SCALE
RANGE ADJUST
SPI REGISTER
(0x1910)
VREF PIN
CONTROL SPI
REGISTER
(0x18A6)
VFS
ADJUST
V
IN+A/VIN+B
VIN–A/VIN–B
VREF
INTERNAL
0.5V
REFERENCE
GENERATOR
15660-044
Figure 73. Internal Reference Configuration and Controls
AD9695 Data Sheet
Rev. C | Page 30 of 136
VREF PIN
AND VF S
CONTROL
VFS
ADJUST
VREFINPUT
0.1µF 0.1µF
V
OUT
V
IN
ADC
INTERNAL
0.5V
REFERENCE
GENERATOR
SETGND
NCNC
ADR130
15660-045
Figure 74. External Reference Using the ADR130
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9695. This internal 0.5 V reference sets the full-scale input
range of the ADC. The full-scale input range can be adjusted via
the ADC input full-scale control register (Register 0x1910). For
more information on adjusting the input swing, see Table 48.
Figure 73 shows the block diagram of the internal 0.5 V reference
controls.
The SPI Register 0x18A6 enables the user to either use this
internal 0.5 V reference, or to provide an external 0.5 V
reference. When using an external voltage reference, provide a
0.5 V reference. The full-scale adjustment is made using the
SPI, irrespective of the reference voltage. For more information
on adjusting the full-scale level of the AD9695, refer to the
Memory Map section.
The SPI writes required to use the external voltage reference, in
order, are as follows:
1. Set Register 0x18E3 to 0x00 to turn off the VCM export.
2. Set Register 0x18E6 to 0x00 to turn off the temperature
diode export.
3. Set Register 0x18A6 to 0x01 to turn on the external voltage
reference.
The use of an external reference may be necessary, in some
applications, to enhance the gain accuracy of the ADC or to
improve thermal drift characteristics. Figure 75 shows the
typical drift characteristics of the internal 0.5 V reference.
0.503
0.495
0.496
0.497
0.498
0.499
0.500
0.501
0.502
–40 –20 020 40 60 80 100
BANDGAP V OL TAG E ( V )
JUNCTI ON T E M P E RATURE ( °C)
15660-046
Figure 75. Typical VREF Drift
The external reference must be a stable 0.5 V reference. The
ADR130 is a sufficient option for providing the 0.5 V reference.
Figure 74 shows how the ADR130 can be used to provide the
external 0.5 V reference to the AD9695. The dashed lines show
unused blocks within the AD9695 while using the ADR130 to
provide the external reference.
DC OFFSET CALIBRATION
The AD9695 contains a digital filter to remove the dc offset
from the output of the ADC. For ac-coupled applications, this
filter can be enabled by setting Register 0x0701, Bit 7 to 0x1 and
setting Register 0x73B, Bit 7 to 0x0. The filter computes the
average dc signal and it is digitally subtracted from the ADC
output. As a result, the dc offset is improved to better than 70 dBFS
at the output. Because the filter does not distinguish between
the source of dc signals, this feature can be used when the signal
content at dc is not of interest. The filter corrects dc up to
±512 codes and saturates beyond that.
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9695 sample clock
inputs (CLK+ and CLK−) with a differential signal. This
signal is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally and
require no additional biasing.
Figure 76 shows a preferred method for clocking the AD9695.
The low jitter clock source is converted from a single-ended
signal to a differential signal using an RF transformer.
1:2Z
CLOCK I NP UT
ADC
CLK+
CLK–
100Ω
15660-047
Figure 76. Transformer Coupled Differential Clock
Data Sheet AD9695
Rev. C | Page 31 of 136
Another option is to ac couple a differential CML or LVDS
signal to the sample clock input pins, as shown in Figure 77 and
Figure 78.
ADC
CLOCK
INPUT
CLK+
CLK–
150Ω 150Ω
LVDS
DRIVER
100Ω
DIFFERENTIAL
TRACE 100Ω
15660-048
Figure 77. Differential LVPECL Sample Clock
ADC
CLOCK
INPUT
CLK+
CLK–
CML
DRIVER
DIFFERENTIAL
TRACE
100Ω
15660-049
Figure 78. Differential CML Sample Clock
ADC
ADC
CLOCK
INPUT
CLK+
CLK–
DAC
CLOCK
INPUT
CLKOUT+
CLKOUT–
100Ω
15660-050
Figure 79. Clock Output Clocking the AD9695
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. The AD9695 contains an
internal clock divider and a duty cycle stabilizer comprised of
Duty Cycle Stabilizer 1 (DCS1) and Duty Cycle Stabilizer 2
(DCS2).
For the AD9695 625 MSPS speed grade, the DCS is disabled by
default. In applications where the clock duty cycle cannot be
guaranteed to be 50%, a higher multiple frequency clock along
with the usage of the clock divider is recommended.
In the AD9695 625 MSPS speed grade, when it is not possible
to provide a higher frequency clock, it is recommended to turn
on DCSx using Register 0x011C and Register 0x011E. Figure 80
shows the different controls to the AD9695 clock inputs. The
output of the divider offers a 50% duty cycle, high slew rate
(fast edge) clock signal to the internal ADC.
In the AD9695 1300 MSPS speed grade, the DCS is enabled by
default. It is recommended to keep DCS on irrespective of clock
divide ratio in the AD9695.
See the Memory Map section for more details on using this feature.
Input Clock Divider
The AD9695 contains an input clock divider with the ability to
divide the input clock by 1, 2, or 4. Select the divider ratios
using Register 0x0108 (see Figure 80).
The maximum frequency at the CLK± inputs is 1.28 GHz,
which is the limit of the divider. In applications where the clock
input is a multiple of the sample clock, take care to program the
appropriate divider ratio into the clock divider before applying
the clock signal; this ensures that the current transients during
device startup are controlled.
REG 0x011C,
0x011E
REG 0x0108
CLK+
CLK– ÷2
÷4
15660-051
Figure 80. Clock Divider Circuit
The AD9695 clock divider can be synchronized using the
external SYSREF± input. A valid SYSREF± signal causes the
clock divider to reset to a programmable state. This synchro-
nization feature allows multiple devices to have their clock
dividers aligned to guarantee simultaneous input sampling.
See the Memory Map Register section for more information.
Input Clock Divider ½ Period Delay Adjust
The input clock divider inside the AD9695 provides phase
delay in increments of ½ the input clock cycle. Register 0x10C
can be programmed to enable this delay independently for each
channel. Changing this register does not affect the stability of
the JESD204B link.
Clock Fine Delay and Superfine Delay Adjust
Adjust the AD9695 sampling edge instant by writing to
Register 0x0110, Register 0x0111, and Register 0x0112. Bits[2:0]
of Register 0x0110 enable the selection of the fine delay, or the
fine delay with superfine delay. The fine delay allows the user to
delay the clock edges with 16 step or 192 step delay options.
The superfine delay is an unsigned control to adjust the clock
delay in superfine steps of 0.25 ps each.
Register 0x0112, Bits[7:0] offer the user the option to delay
the clock in 192 delay steps. Register 0x0111, Bits[7:0] offer the
user the option to delay the clock in 128 superfine steps. These
values can be programmed individually for each channel. To
use the superfine delay option, set the clock delay control in
Register 0x0110, Bits[2:0] to 0x2 or 0x6. Figure 81 shows the
controls available to the clock dividers within AD9695. It is
recommended to apply the same delay settings to the digital
delay circuits as are applied to the analog delay circuits to
maintain sample accuracy through the pipe.
AD9695 Data Sheet
Rev. C | Page 32 of 136
PHASE
CH. B
PHASE
CH. A
CLK_DIV
0x0108
0x0109 FINE DELAY
0x0110,
0x0111,
0x0112 CHANNEL B
CHANNEL A
CLK INPUT
15660-052
Figure 81. Clock Divider Phase and Delay Controls
The clock delay adjustment takes effect immediately when it is
enabled via SPI writes. Enabling the clock fine delay adjust in
Register 0x0110 causes a datapath reset. However, the contents
of Register 0x0111 and Register 0x0112 can be changed without
affecting the stability of the JESD204B link.
Clock Coupling Considerations
The AD9695 has many different domains within the analog
supply that control various aspects of the data conversion. The
clock domain is supplied by Pin 49 and Pin 64 on the analog
supply (AVDD1). To minimize coupling between the clock
supply domain and the other analog domains, it is recommended
to add a supply Q factor reduction circuitry (de-Q) for Pin 49
and Pin 64, as shown in Figure 82.
PIN 49
100nF
10Ω
FE RRI TE BE AD
220Ω AT
100MHz
DCR ≤ 0.5Ω
PIN 64
AVDD1
PLANE
100nF
10Ω
FE RRI TE BE AD
220Ω AT
100MHz
DCR ≤ 0.5Ω
15660-053
Figure 82. De-Q Network Recommendation for the Clock Domain Supply
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. Calculate the degradation in SNR at a given
input frequency (fIN) due only to aperture jitter (tJ) by
SNRJITTER = −20 × log10 (2 × π × fIN × tJ)
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications.
IF undersampling applications are particularly sensitive to jitter
(see Figure 83).
130
120
110
100
90
80
70
60
50
40
3010 100100010000
SNR (dB)
ANALOG INPUT FREQUENCY (MHz)
12.5
f
S
25
f
S
50
f
S
100
f
S
200
f
S
400
f
S
800
f
S
15660-054
Figure 83. Ideal SNR vs. Input Frequency and Jitter
Treat the clock input as an analog signal when aperture jitter
may affect the dynamic range of the AD9695. Separate power
supplies for clock drivers from the ADC output driver supplies
to avoid modulating the clock signal with digital noise. If the
clock is generated from another type of source (by gating,
dividing, or other methods), retime the clock by the original clock
at the last step. Refer to the AN-501 Application Note and the
AN-756 Application Note for more in depth information about
jitter performance as it relates to ADCs.
Figure 84 shows the estimated SNR of the AD9695 across input
frequency for different clock induced jitter values. Estimate the
SNR by using the following equation:
SNR (dBFS) = −10log10
+
−
−
10
10 1010
JITTER
ADC SNR
SNR
70
45
50
55
60
65
10 100 1000
SNR (dBFS )
INPUT F RE QUENCY ( M Hz )
15660-484
25
f
S
50
f
S
75
f
S
100
f
S
125
f
S
150
f
S
175
f
S
Figure 84. Estimated SNR Degradation for the AD9695 vs. Analog Input
Frequency and RMS Jitter
Data Sheet AD9695
Rev. C | Page 33 of 136
POWER-DOWN/STANDBY MODE
The AD9695 has a PDWN/STBY pin that configure the device
in power-down or standby mode. The default operation is PDWN.
The PDWN/STBY pin is a logic high pin. When in power-
down mode, the JESD204B link is disrupted. The power-down
option can also be set via Register 0x003F and Register 0x0040.
In standby mode, the JESD204B link is not disrupted and transmits
zeros for all converter samples. Change this transmission using
Register 0x0571, Bit 7 to select /K/ characters.
TEMPERATURE DIODE
The AD9695 contains diode-based temperature sensors. The
diodes output voltages commensurate to the temperature of the
silicon. There are multiple diodes on the die, but the results
established using the temperature diode at the central location
of the die can be regarded as representative of the entire die.
However, in applications where only one channel is used (the
other channel being in a power-down state), it is recommended
to read the temperature diode corresponding to the channel
that is on. Figure 85 shows the locations of the diodes in the
AD9695 with voltages that can be output to the VREF pin. In
each location, there is a pair of diodes, one of which is 20× the
size of the other. It is recommended to use both diodes in a
location to obtain an accurate estimate of the die temperature.
For more information, see the AN-1432 Application Note,
Practical Thermal Modeling and Measurements in High Power ICs.
ADC
AADC
B
ADC
DIGITAL
VREF
JESD204B DRIVER
TEMP ERATURE DIODE
LOCATIONS
CHANNEL A, CENTRAL,
CHANNEL B
15660-056
Figure 85. Temperature Diode Locations in the Die
The temperature diode voltages can be exported to the VREF pin
using the SPI. Use Register 0x18E6 to enable or disable diodes. It is
important to note that other voltages may be exported to the
VREF pin at the same time, which can result in undefined
behavior. To ensure a proper readout, switch off all other voltage
exporting circuits as described in this section. Figure 86 shows the
block diagram of the controls that are required to enable the diode
voltage readout.
TE M P ERATURE DIO DE
LOCATION SELECT
SPI RE GI S TER ( 0x18E 6)
VREF PIN
CONTROL
SPI REGISTER
(0x18A6)
CHANNEL A
CENTRAL
VREF CHANNEL B
15660-057
Figure 86. Register Controls to Output Temperature Diode Voltage on the
VREF Pin
The SPI writes required to export the central temperature diode
are as follows (see the Memory Map section for more information):
4. Set Register 0x0008 to 0x03 to select both channels.
5. Set Register 0x18E3 to 0x00 to turn off VCM export.
6. Set Register 0x18A6 to 0x00 to turn off voltage reference
export.
7. Set Register 0x18E6 to 0x01 to turn on voltage export of
the central 1× temperature diode. The typical voltage
response of the temperature diode is shown in Figure 87.
Although this voltage represents the die temperature, it is
recommended to take measurements from a pair of diodes
for improved accuracy. The following step explains how to
enable the 20× diode.
8. Set Register 0x18E6 to 0x02 to turn on the second central
temperature diode of the pair, which is 20× the size of the
first. For the method using two diodes simultaneously to
achieve a more accurate result, see the AN-1432 Application
Note, Practical Thermal Modeling and Measurements in
High Power ICs.
0.80
0.75
0.70
0.65
0.60
0.55
0.50
–40 –20 020
JUNCTION TEM P E RATURE ( °C)
TEMPERATURE DIODE VOLTAGE (V)
40 60 80 100
15660-058
Figure 87. Typical Voltage Response of the 1× Temperature Diode
The relationship between the measured delta voltage (ΔV) and
the junction temperature in degrees Celsius is shown in Figure 88.
150
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
60 65 70 75 80 85 90 95 100 105 110
DELTA VOLTAGE (mV)
T
J
(° C)
15660-059
Figure 88. Junction Temperature (TJ) vs. Delta Voltage (ΔV)
AD9695 Data Sheet
Rev. C | Page 34 of 136
ADC OVERRANGE AND FAST DETECT
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit in the JESD204B outputs provides
information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input
signals can have significant slew rates, the latency of this
function is of major concern. Highly pipelined converters can
have significant latency. The AD9695 contains fast detect
circuitry for individual channels to monitor the threshold and
assert the FD_A and FD_B pins.
ADC OVERRANGE
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be embedded within the JESD204B link as a control bit (when
CSB > 0). The latency of this overrange indicator matches the
sample latency.
The AD9695 also records any overrange condition in any of the
eight virtual converters. For more information on the virtual
converters, refer to Figure 90. The overrange status of each virtual
converter is registered as a sticky bit in Register 0x563. The
contents of Register 0x563 can be cleared using Register 0x562,
by toggling the bits corresponding to the virtual converter to set
and reset position.
FAST THRESHOLD DETECTION (FD_A AND FD_B)
The fast detect bit is immediately set whenever the absolute value
of the input signal exceeds the programmable upper threshold
level. The FD bit is only cleared when the absolute value of the
input signal drops below the lower threshold level for greater
than the programmable dwell time. This feature provides
hysteresis and prevents the FD bit from excessively toggling.
The operation of the upper threshold and lower threshold
registers, along with the dwell time registers, is shown in
Figure 89.
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located at Register 0x0247 and Register 0x0248. The selected
threshold register is compared with the signal magnitude at the
output of the ADC. The fast upper threshold detection has a
latency of 28 clock cycles (maximum). The approximate upper
threshold magnitude is defined by
Upper Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x0249 and Register 0x024A. The
fast detect lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency, but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x0247 and Register 0x0248. To set a lower threshold of
−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x24B and Register 0x024C. See
the Memory Map section (Register 0x0040, and Register 0x0245 to
Register 0x024C in Table 48) for more details.
UPPE R THRESHOL D
LOWER THRESHOLD
FD_A OR FD_B
MIDSCALE
DWELL TIME
TIMER RESET BY
RIS E ABO V E
LOWER
THRESHOLD
TIMER COMPLET ES BEFO RE
SI GNAL RISE S ABOVE
LOWER THRESHOLD
DWELL TIME
15660-060
Figure 89. Threshold Settings for FD_A and FD_B Signals
Data Sheet AD9695
Rev. C | Page 35 of 136
ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING
The AD9695 contains a configurable signal path that allows
different features to be enabled for different applications. These
features are controlled using the chip application mode register,
Register 0x0200. The chip operating mode is controlled by
Bits[3:0] in this register, and the chip Q ignore is controlled by
Bit 5.
The AD9695 contains the following modes:
• Full bandwidth mode: two 14-bit ADC cores running at
the full sample rate.
• DDC mode: up to four digital downconverter (DDC)
channels.
After the chip application mode is selected, the output
decimation ratio is set using the chip decimation ratio in
Register 0x0201, Bits[3:0]. The output sample rate = ADC
sample rate/the chip decimation ratio.
To support the different application layer modes, the AD9695
treats each sample stream (real, I, or Q) as originating from
separate virtual converters.
Table 12 shows the number of virtual converters required and
the transport layer mapping when channel swapping is
disabled. Figure 90 shows the virtual converters and their
relationship to the DDC outputs when complex outputs are
used.
Each DDC channel outputs either two sample streams (I/Q) for
the complex data components (real + imaginary), or one sample
stream for real (I) data. The AD9695 can be configured to use up
to eight virtual converters, depending on the DDC configuration.
The I/Q samples are always mapped in pairs with the I samples
mapped to the first virtual converter and the Q samples
mapped to the second virtual converter. With this transport layer
mapping, the number of virtual converters are the same
whether a single real converter is used along with a digital
downconverter block producing I/Q outputs, or whether an
analog downconversion is used with two real converters
producing I/Q outputs.
Figure 91 shows a block diagram of the two scenarios described
for I/Q transport layer mapping.
Table 12. Virtual Converter Mapping
Number of
Virtual
Converters
Supported
Chip Operating
Mode
(Reg. 0x0200,
Bits[3:0])
Chip Q Ignore
(0x0200, Bit 5)
Virtual Converter Mapping
0 1 2 3 4 5 6 7
1 to 2 Full bandwidth
mode (0x0)
Real or
complex (0x0)
ADC A
samples
ADC B
samples
Unused Unused Unused Unused Unused Unused
1 One DDC mode
(0x1)
Real (I only)
(0x1)
DDC0 I
samples
Unused Unused Unused Unused Unused Unused Unused
2 One DDC mode
(0x1)
Complex (I/Q)
(0x0)
DDC0 I
samples
DDC0 Q
samples
Unused Unused Unused Unused Unused Unused
2 Two DDC mode
(0x2)
Real (I only)
(0x1)
DDC0 I
samples
DDC1 I
samples
Unused Unused Unused Unused Unused Unused
4 Two DDC mode
(0x2)
Complex (I/Q)
(0x0)
DDC0 I
samples
DDC0 Q
samples
DDC1 I
samples
DDC1 Q
samples
Unused Unused Unused Unused
4 Four DDC mode
(0x3)
Real (I only)
(0x1)
DDC0 I
samples
DDC1 I
samples
DDC2 I
samples
DDC3 I
samples
Unused Unused Unused Unused
8
Four DDC mode
(0x3)
Complex (I/Q)
(0x0)
DDC0 I
samples
DDC0 Q
samples
DDC1 I
samples
DDC1 Q
samples
DDC2 I
samples
DDC2 Q
samples
DDC3 I
samples
DDC3 Q
samples
AD9695 Data Sheet
Rev. C | Page 36 of 136
DDC 3
OUTPUT
INTERFACE
I/Q
CROSSBAR
MUX
I
Q
I
QQ
CONVE RTER 7
REAL/I
CONVE RTER 6
REAL/Q
REAL/I
DDC 2
I
Q
I
QQ
CONVE RTER 5
REAL/I
CONVE RTER 4
REAL/Q
REAL/I
DDC 1
I
Q
I
QQ
CONVE RTER 3
REAL/I
CONVE RTER 2
REAL/Q
REAL/I
DDC 0
I
Q
I
QQ
CONVE RTER 1
REAL/I
CONVE RTER 0
REAL/Q
REAL/I
REAL/I ADC A
SAMPLING
AT f
S
REAL/Q ADC B
SAMPLING
AT f
S
15660-061
Figure 90. DDCs and Virtual Converter Mapping
JESD204B
Tx
90°
PHASE
Q
CONVE RTER 1
I
CONVE RTER 0
IADC
ADC
Q
REAL
REALREAL
L L ANE S
JESD204B
Tx
DIGITAL
DOWN-
CONVERSION Q
CONVE RTER 1
I
CONVE RTER 0
L L ANE S
I/Q ANALOG MIXING
M = 2
DIGITAL DOWNCONVERSION
M = 2
ADC
15660-062
Figure 91. I/Q Transport Layer Mapping
Data Sheet AD9695
Rev. C | Page 37 of 136
PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS
SUPPORTED MODES
The AD9695 supports the following modes of operation (the
asterisk symbol (*) denotes convolution):
• Real 48-tap filter for each I/Q channel (see Figure 92)
• DOUT_I[n] = DIN_I[n] * XY_I[n]
• DOUT_Q[n] = DIN_Q[n] * XY_Q[n]
• Real 96-tap filter for on either I or Q channel (see Figure 93)
• DOUT_I[n] = DIN_I[n] * XY_I_XY_Q[n]
• DOUT_Q[n] = DIN_Q[n]
• Real set of two cascaded 24-tap filters for each I/Q channel
(see Figure 94)
• DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n]
• DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n]
• Half complex filter using two real 48-tap filters for the I/Q
channels (see Figure 95)
• DOUT_I[n] = DIN_I[n]
• DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] *
XY_I[n]
• Full complex filter using four real 24-tap filters for the I/Q
channels (see Figure 96)
• DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] *
Y_Q[n]
• DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] *
Y_I[n]
ADC B
CORE
Q (IMAG) 48-T AP FIR
FILTER
xyQ [n ]
DINQ [n] DOUTQ [n]
ADC A
CORE
I ( REAL) 48-T AP FIR
FILTER
xyI [n ]
DINI [n] DOUTI [n] I′ (REAL)
PROGRAMMABLE FILTER (PFILT)
Q′ (IMAG)
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
15660-063
Figure 92. Real 48-Tap Filter Configuration
ADC B
CORE
Q (IMAG) DIN
Q
[n] DOUT
Q
[n]
ADC A
CORE
I ( REAL) 96-T AP FI R
FILTER
x
I
y
I
x
Q
y
Q
[n]
DIN
I
[n] DOUT
I
[n] I′ (REAL)
PROGRAMMABLE FILTER (PFILT)
Q′ (IMAG)
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
15660-064
Figure 93. Real 96-Tap Filter Configuration
AD9695 Data Sheet
Rev. C | Page 38 of 136
ADC B
CORE
Q (IMAG) DINQ [n] DOUTQ [n]
ADC A
CORE
I ( RE AL) 24-T AP FIR
FILTER
xI [n]
24-T AP FIR
FILTER
yI [n]
24-T AP FIR
FILTER
yQ [n]
24-T AP FIR
FILTER
xQ[n]
DINI [n] DOUTI [n] I′ (REAL)
PROGRAMMABLE FILTER (PFILT)
Q′ (IMAG)
SIGNAL
PROCESSING
BLOCKS JESD204B
INTERFACE
15660-065
Figure 94. Real, Two Cascaded, 24-Tap Filter Configuration
ADC B
CORE
Q (IMAG) DINQ [n] DOUTQ [n ]
+
+
ADC A
CORE
I ( RE AL) 0 T O 47
DEL AY TAPS
48-T AP FIR
FILTER
xyI [n ]
48-T AP FIR
FILTER
xyQ[n]
DINI [n] DOUTI [n] I′ (REAL)
PROGRAMMABLE FILTER (PFILT)
Q′ (IMAG)
SIGNAL
PROCESSING
BLOCKS JESD204B
INTERFACE
15660-066
Figure 95. 48-Tap Half Complex Filter Configuration
ADC B
CORE
Q (IMAG)
DINQ [n]
DOUTQ [n]
+
+
+
+
ADC A
CORE
I ( RE AL) 24-T AP FIR
FILTER
xI [n]
24-T AP FIR
FILTER
yI [n]
24-T AP FIR
FILTER
yQ [n]
24-T AP FIR
FILTER
xQ[n]
DINI [n] DOUTI [n] I′ (REAL)
PROGRAMMABLE FILTER (PFILT)
Q′ (IMAG)
SIGNAL
PROCESSING
BLOCKS JESD204B
INTERFACE
15660-067
Figure 96. 24-Tap Full Complex Filter Configuration.
Data Sheet AD9695
Rev. C | Page 39 of 136
PROGRAMMING INSTRUCTIONS
Use the following procedure to set up the programmable FIR filter:
1. Enable the sample clock to the device.
2. Configure the mode registers as follows:
a. Set the device index to Channel A (I path)
(Register 0x0008 = 0x01).
b. Set the I path mode (I mode) and gain in
Register 0x0DF8 and Register 0x0DF9 (see Table 13
and Table 14).
c. Set the device index to Channel B (Q path)
(Register 0x0008 = 0x02).
d. Set the Q path mode (Q mode) and gain in
Register 0x0DF8 and Register 0x0DF9.
3. Wait at least 5 µs to allow the programmable filter to power
up.
4. Program the I path coefficients to the internal shadow
registers as follows:
a. Set the device index to Channel A (I path)
(Register 0x0008 = 0x01).
b. Program the XI coefficients in Register 0x0E00 to
Register 0x0E2F (see Table 15 and Table 16).
c. Program the YI coefficients in Register 0x0F00 to
Register 0x0F2F (see Table 15 and Table 16).
d. Program the tapped delay in Register 0x0F30 (note
that this step is optional).
5. Program the Q path coefficients to the internal shadow
registers as follows:
a. Set the device index to Channel B (Q path)
(Register 0x0008 = 0x02).
b. Set the Q path mode and gain in Register 0x0DF8 and
Register 0x0DF9 (see Table 13 and Table 14).
c. Program the XQ coefficients in Register 0x0E00 to
Register 0x0E2F (see Table 15 and Table 16).
d. Program the YQ coefficients in Register 0x0F00 to
Register 0x0F2F (see Table 15 and Table 16)
e. Program the tapped delay in Register 0x0F30 (note
that this step is optional).
6. Set the chip transfer bit using either of the following
methods (note that setting the chip transfer bit applies the
programmed shadow coefficients to the filter):
a. Via the register map by setting the chip transfer bit
(Register 0x000F = 0x01).
b. Via a GPIO pin, as follows:
i. Configure one of the GPIO pins as the chip
transfer bit in Register 0x0040 to Register 0x0042.
ii. Toggle the GPIO pin to initiate the chip transfer
(the rising edge is triggered).
7. When the I or Q path mode register changes in
Register 0x0DF8, all coefficients must be reprogrammed.
Table 13. Register 0x0DF8 Definition
Bits Description
[7:3] Reserved
[2:0] Filter mode (I mode or Q mode)
000: filters bypassed
001: real 24-tap filter (X only)
010: real 48-tap filter (X and Y together)
100: real set of two cascaded 24-tap filters (X then Y
cascaded)
101: full complex filter using four real 24-tap filters for
the A/B channels (opposite channel must also be set to
101)
110: half complex filter using two real 48-tap filters +
48-tap delay line (X and Y together) (opposite
channel must also be set to 010)
111: real 96-tap filter (XI, YI, XQ, and YQ together)
(opposite channel must be set to 000)
Table 14. Register 0x0DF9 Definition
Bits Description
7 Reserved
[6:4] Y filter gain
110: −12 dB loss
111: −6 dB loss
000: 0 dB gain
001: 6 dB gain
010: 12 dB gain
3 Reserved
[2:0] X filter gain
110: −12 dB loss
111: −6 dB loss
000: 0 dB gain
001: 6 dB gain
010: 12 dB gain
Table 15 and Table 16 show the coefficient tables in
Register 0x0E00 to Register 0x0F30. All coefficients are
Q1.15 format (sign bit + 15 fractional bits).
AD9695 Data Sheet
Rev. C | Page 40 of 136
Table 15. I Coefficient Table (Device Selection = 0x1)1
Addr.
Single 24-Tap
Filter (I Mode
[2:0] = 0x1)
Single 48-Tap
Filter (I Mode
[2:0] = 0x2)
Two Cascaded
24-Tap Filters (I
Mode [2:0] = 0x4)
Full Complex
24-Tap Filters (I
Mode [2:0] = 0x5
and Q Mode
[2:0] = 0x5)
Half Complex
48-Tap Filters (I
Mode [2:0] = 0x6
and Q Mode
[2:0] = 0x2)2
I Path 96-Tap Filter
(I Mode[2:0] = 0x7
and Q Mode
[2:0] = 0x0)3
Q Path 96-Tap
Filter (I Mode
[2:0] = 0x0 and Q
Mode [2:0] = 0x7)3
0x0E00 XI C0 [7:0] XI C0 [7:0] XI C0 [7:0] XI C0 [7:0] XI C0 [7:0] XI C0 [7:0] XQ C48 [7:0]
0x0E01 XI C0 [15:8] XI C0 [15:8] XI C0 [15:8] XI C0 [15:8] XI C0 [15:8] XI C0 [15:8] XQ C48 [15:8]
0x0E02 XI C1 [7:0] XI C1 [7:0] XI C1 [7:0] XI C1 [7:0] XI C1 [7:0] XI C1 [7:0] XQ C49 [7:0]
0x0E03 XI C1 [15:8] XI C1 [15:8] XI C1 [15:8] XI C1 [15:8] XI C1 [15:8] XI C1 [15:8] XQ C49 [15:8]
… … … … … … … …
0x0E2E XI C23 [7:0] XI C23 [7:0] XI C23 [7:0] XI C23 [7:0] XI C23 [7:0] XI C23 [7:0] XQ C71 [7:0]
0x0E2F XI C23 [15:0] XI C23 [15:0] XI C23 [15:0] XI C23 [15:0] XI C23 [15:0] XI C23 [15:0] XQ C71 [15:0]
0x0F00 Unused YI C24 [7:0] YI C0 [7:0] YI C0 [7:0] YI C24 [7:0] YI C24 [7:0] YQ C72 [7:0]
0x0F01 Unused YI C24 [15:8] YI C0 [15:8] YI C0 [15:8] YI C24 [15:8] YI C24 [15:8] YQ C72 [15:8]
0x0F02 Unused YI C25 [7:0] YI C1 [7:0] YI C1 [7:0] YI C25 [7:0] YI C25 [7:0] YQ C73 [7:0]
0x0F03 Unused YI C25 [15:8] YI C1 [15:8] YI C1 [15:8] YI C25 [15:8] YI C25 [15:8] YQ C73 [15:8]
… … … … … … … …
0x0F2E Unused YI C47 [7:0] YI C23 [7:0] YI C23 [7:0] YI C47 [7:0] YI C47 [7:0] YQ C95 [7:0]
0x0F2F Unused YI C47 [15:0] YI C23 [15:0] YI C23 [15:0] YI C47 [15:0] YI C47 [15:0] YQ C95 [15:0]
0x0F30 Unused Unused Unused Unused I path tapped delay Unused Unused
0: 0 tapped delay
(matches C0 in the
filter)
1: 1 tapped delays
…
47: 47 tapped delays
1 XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n.
2 When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.
3 When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
Data Sheet AD9695
Rev. C | Page 41 of 136
Table 16. Q Coefficient Table (Device Selection = 0x2)1
Addr.
Single 24-Tap
Filter (Q Mode
[2:0] = 0x1)
Single 48-Tap
Filter (Q Mode
[2:0] = 0x2)
Two Cascaded
24-Tap Filters (Q
Mode [2:0] = 0x4)
Full Complex
24-Tap Filters (Q
Mode [2:0] = 0x5
and I Mode
[2:0] = 0x5)
Half Complex
48-Tap Filters (Q
Mode [2:0] = 0x6
and I Mode
[2:0] = 0x2)2
I Path 96-Tap
Filter (Q Mode
[2:0] = 0x0 and I
Mode [2:0] = 0x7)3
Q Path 96-Tap
Filter (Q Mode
[2:0] = 0x7 and I
Mode [2:0] = 0x0)3
0x0E00 XQ C0 [7:0] XQ C0 [7:0] XQ C0 [7:0] XQ C0 [7:0] XQ C0 [7:0] XI C48 [7:0] XQ C0 [7:0]
0x0E01 XQ C0 [15:8] XQ C0 [15:8] XQ C0 [15:8] XQ C0 [15:8] XQ C0 [15:8] XI C48 [15:8] XQ C0 [15:8]
0x0E02 XQ C1 [7:0] XQ C1 [7:0] XQ C1 [7:0] XQ C1 [7:0] XQ C1 [7:0] XI C49 [7:0] XQ C1 [7:0]
0x0E03 XQ C1 [15:8] XQ C1 [15:8] XQ C1 [15:8] XQ C1 [15:8] XQ C1 [15:8] XI C49 [15:8] XQ C1 [15:8]
… … … … … … … …
0x0E2E XQ C23 [7:0] XQ C23 [7:0] XQ C23 [7:0] XQ C23 [7:0] XQ C23 [7:0] XI C71 [7:0] XQ C23 [7:0]
0x0E2F XQ C23 [15:0] XQ C23 [15:0] XQ C23 [15:0] XQ C23 [15:0] XQ C23 [15:0] XI C71 [15:0] XQ C23 [15:0]
0x0F00 Unused YQ C24 [7:0] YQ C0 [7:0] YQ C0 [7:0] YQ C24 [7:0] YI C72 [7:0] YQ C24 [7:0]
0x0F01 Unused YQ C24 [15:8] YQ C0 [15:8] YQ C0 [15:8] YQ C24 [15:8] YI C72 [15:8] YQ C24 [15:8]
0x0F02 Unused YQ C25 [7:0] YQ C1 [7:0] YQ C1 [7:0] YQ C25 [7:0] YI C73 [7:0] YQ C25 [7:0]
0x0F03 Unused YQ C25 [15:8] YQ C1 [15:8] YQ C1 [15:8] YQ C25 [15:8] YI C73 [15:8] YQ C25 [15:8]
… … … … … … … …
0x0F2E Unused YQ C47 [7:0] YQ C23 [7:0] YQ C23 [7:0] YQ C47 [7:0] YI C95 [7:0] YQ C47 [7:0]
0x0F2F Unused YQ C47 [15:0] YQ C23 [15:0] YQ C23 [15:0] YQ C47 [15:0] YI C95 [15:0] YQ C47 [15:0]
0x0F30 Unused Unused Unused Unused Q path tapped
delay
Unused Unused
0: 0 tapped delay
(matches C0 in the
filter)
1: 1 tapped delays
…
47: 47 tapped
delays
1 XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n.
2 When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.
3 When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
AD9695 Data Sheet
Rev. C | Page 42 of 136
DIGITAL DOWNCONVERTER (DDC)
The AD9695 includes four digital downconverters (DDC 0 to
DDC 3) that provide filtering and reduce the output data rate.
This digital processing section includes an NCO, multiple
decimating FIR filters, a gain stage, and a complex to real
conversion stage. Each of these processing blocks has control lines
that allow it to be independently enabled and disabled to provide
the desired processing function. The digital downconverter can be
configured to output either real data or complex output data.
The DDCs output a 16-bit stream. To enable this operation, the
converter number of bits, N, is set to a default value of 16, even
though the analog core only outputs 14 bits. In full bandwidth
operation, the ADC outputs are the 14-bit word followed by two
zeros, unless the tail bits are enabled.
DDC I/Q INPUT SELECTION
The AD9695 has two ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real and complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (that is, DDC Input Port I = ADC Channel A
and DDC Input Port Q = ADC Channel A). For complex
signals, each DDC input port must select different ADC
channels (that is, DDC Input Port I = ADC Channel A and
DDC Input Port Q = ADC Channel B).
The inputs to each DDC are controlled by the DDC input selec-
tion registers (Register 0x0311, Register 0x0331, Register 0x0351
and Register 0x0371). See Table 48 for information on how to
configure the DDCs.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real and complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit, Bit 3, in the DDC control
registers (Register 0x0310, Register 0x0330, Register 0x0350
and Register 0x370).
The chip Q ignore bit in the chip mode register (Register 0x0200,
Bit 5) controls the chip output muxing of all the DDC channels.
When all DDC channels use real outputs, set this bit high to
ignore all DDC Q output ports. When any of the DDC
channels are set to use complex I/Q outputs, the user must clear
this bit to use both DDC Output Port I and DDC Output Port
Q. For more information, see Figure 130.
DDC GENERAL DESCRIPTION
The four DDC blocks extract a portion of the full digital
spectrum captured by the ADC(s). They are intended for IF
sampling or oversampled baseband radios requiring wide
bandwidth input signals.
Each DDC block contains the following signal processing stages:
• Frequency translation stage (optional)
• Filtering stage
• Gain stage (optional)
• Complex to real conversion stage (optional)
Frequency Translation Stage (Optional)
This stage consists of a phase coherent NCO and quadrature
mixers that can be used for frequency translation of both real or
complex input signals. The phase coherent NCO allows an
infinite number of frequency hops that are all referenced back
to a single synchronization event. It also includes 16 shadow
registers for fast switching applications. This stage shifts a
portion of the available digital spectrum down to baseband.
Filtering Stage
After shifting down to baseband, this stage decimates the
frequency spectrum using multiple low pass finite impulse
response (FIR) filters for rate conversion. The decimation
process lowers the output data rate, which in turn reduces the
output interface rate.
Gain Stage (Optional)
Due to losses associated with mixing a real input signal down to
baseband, this stage compensates by adding an additional 0 dB
or 6 dB of gain.
Complex to Real Conversion Stage (Optional)
When real outputs are necessary, this stage converts the complex
outputs back to real by performing an fS/4 mixing operation
plus a filter to remove the complex component of the signal.
Figure 97 shows the detailed block diagram of the DDCs
implemented in the AD9695.
Figure 98 shows an example usage of one of the four DDC
channels with a real input signal and four half-band filters
(HB4 + HB3 + HB2 + HB1) used. It shows both complex
(decimate by 16) and real (decimate by 8) output options.
Data Sheet AD9695
Rev. C | Page 43 of 136
NCO
+
MIXER
(OPTIONAL)
DECIMATION
FILTERS
REAL/I
DDC 0
I
REAL/I Q
REAL/I
CONVE RTER 0
Q CO NV E RTER 1
GAI N = 0 OR +6dB
COMPLEX TO REAL
CONVERSION (OPTIONAL)
NCO
+
MIXER
(OPTIONAL)
DECIMATION
FILTERS
REAL/I
JESD204B T RANS M IT INT E RFACE
DDC 1
I
REAL/I Q
REAL/I
CONVE RTER 2
Q CO NV E RTER 3 L
JESD204B
LANES
AT UP TO
16Gbps
GAI N = 0 OR +6dB
COMPLEX TO REAL
CONVERSION (OPTIONAL)
NCO
+
MIXER
(OPTIONAL)
DECIMATION
FILTERS
REAL/I
DDC 2
I
REAL/I Q
REAL/I
CONVE RTER 4
Q CO NV E RTER 5
GAI N = 0 OR +6dB
COMPLEX TO REAL
CONVERSION (OPTIONAL)
NCO
+
MIXER
(OPTIONAL)
SYNCHRONIZATION
CONTROL CI RCUIT S
SYSREF
PIN SYSREF± SYSREF
REGISTER MAP
CONTROLS
GPIO PINS NCO CHANNEL
SELECTION
CIRCUITS
NCO CHANNEL SE LECTI ON
DCM = DECIMATI ON
DECIMATION
FILTERS
REAL/I
DDC 3
I
REAL/I Q
REAL/I
CONVE RTER 6
Q CO NV E RTER 7
GAI N = 0 OR +6dB
COMPLEX TO REAL
CONVERSION (OPTIONAL)
ADC B
SAMPLING
AT
fS
REAL/Q
ADC A
SAMPLING
AT
fS
REAL/I
I/ Q CRO S S BAR M UX
15660-068
Figure 97. DDC Detailed Block Diagram
AD9695 Data Sheet
Rev. C | Page 44 of 136
cos(ωt)
0°
90°
I
Q
REAL
BANDWI DTH O F
INTEREST
BANDWI DTH O F
INTEREST IMAGE
DIGITAL FILTER
RESPONSE
DC
DC
ADC
SAMPLING
AT fS
REAL REAL
HALF-
BAND
FILTER
HB4 FI R
2
HALF-
BAND
FILTER
HB3 FI R
2
HALF-
BAND
FILTER
HB2 FI R
2
HALF-
BAND
FILTER
HB1 FI R
I I
HALF-
BAND
FILTER
HB4 FI R
2
HALF-
BAND
FILTER
HB3 FI R
2
HALF-
BAND
FILTER
HB2 FI R
2
HALF-
BAND
FILTER
HB1 FI R
Q Q
ADC
REAL INPUT—S AM P LED AT fS
FILTERING STAGE
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
FREQ UENCY TRANSLATION STAGE (O PTIONAL)
NCO T UNE S CE NTER OF
BANDWI DTH O F I NTERES T
TO BAS E BAND
BANDWI DTH O F
INTEREST IMAGE
(–6dB LO S S DUE TO
NCO + M IXE R)
BANDWI DTH O F I NTERES T
(–6dB LO S S DUE TO
NCO + M IXE R)
–fS/2 –fS/3 –fS/4 –fS/8 fS/16 fS/8 fS/4 fS/3 fS/2–fS/16
–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 fS/16 fS/8 fS/4 fS/3 fS/2–fS/16
–fS/32 fS/32
–sin(ωt)
48-BIT
NCO
DC
DIGITAL FILTER
RESPONSE
DC
DC
I
Q
I
Q
2
2
I
Q
REAL/I
COMPLEX
TO
REAL
I
Q
GAIN STAGE (OPTIONAL)
0dB O R 6dB G AIN
GAIN STAGE (OPTIONAL)
0dB O R 6dB G AIN
COMPLEX (I/Q) OUTPUTS
DECIM ATE BY 16
REAL (I) OUTPUTS
DECIM ATE BY 8
COMPLEX TO REAL
CONVERSION S T AGE (O PTIONAL)
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
–fS/8 fS/16 fS/8–fS/16
–fS/32 fS/32
–fS/8 fS/16 fS/8–fS/16
–fS/32 fS/32
fS/16–fS/16
–fS/32 fS/32
6dB G AIN T O
COMPENSATE FOR
NCO + MIXER LOSS
6dB G AIN T O
COMPENSATE FOR
NCO + MIXER LOSS
DOWNSAMPLE BY 2
+6dB
+6dB
+6dB
+6dB
DIGITAL MIXER + NCO
FOR fS/3 T UNING , T HE FREQ UE NCY TUNI NG WORD = ROUND
((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
15660-069
Figure 98. DDC Theory of Operation Example (Real Input)
Data Sheet AD9695
Rev. C | Page 45 of 136
DDC FREQUENCY TRANSLATION
DDC Frequency Translation General Description
Frequency translation is accomplished by using a 48-bit
complex NCO with a digital quadrature mixer. This stage
translates either a real or complex input signal from an IF to a
baseband complex digital output (carrier frequency = 0 Hz).
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x0310, Register 0x0330,
Register 0x0350, and Register 0x0370). These IF modes are as
follows:
• Variable IF mode
• 0 Hz IF or zero IF (ZIF) mode
• fS/4 Hz IF mode
• Test mode
Variable IF Mode
NCO and mixers are enabled. NCO output frequency can be
used to digitally tune the IF frequency.
0 Hz IF (ZIF) Mode
The mixers are bypassed, and the NCO is disabled.
fS/4 Hz IF Mode
The mixers and the NCO are enabled in special downmixing by
fS/4 mode to save power.
Test Mode
Input samples are forced to 0.999 to positive full scale. The
NCO is enabled. This test mode allows the NCOs to directly
drive the decimation filters.
Figure 99 and Figure 100 show examples of the frequency
translation stage for both real and complex inputs.
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
NCO FRE QUENCY TUNING WORD (FTW) SELE CTION
48-BI T NCO FT W = M IXING FREQUENCY/ADC SAM P LE RATE × 4096
ADC + DIGI T AL MIXER + NCO
REAL INPUT—S AM P LED AT
f
S
DC
DC
–
f
S/32
f
S/32
DC
–
f
S/32
f
S/32
cos(ωt)
0°
90°
I
Q
ADC
SAMPLING
AT
f
S
REAL REAL
–sin(ωt)
48-BIT
NCO
POSITIVE FTW VALUES
NEGATIVE FTW VALUES
COMPLEX
–6dB LOS S DUE TO
NCO + MIXER
–
f
S/2 –
f
S/3 –
f
S/4 –
f
S/8
f
S/16
f
S/8
f
S/4
f
S/3
f
S/2–
f
S/16
–
f
S/32
f
S/32
48-BI T NCO FT W =
ROUND ( (
f
S/3)/
f
S × 248) = +9. 382513
(0x5555_5555_5555)
48-BI T NCO FT W =
ROUND ( (
f
S/3)/
f
S × 248) = –9.382513
(0xAAAA_AAAA_AAAA)
15660-070
Figure 99. DDC NCO Frequency Tuning Word Selection—Real Inputs
AD9695 Data Sheet
Rev. C | Page 46 of 136
NCO FRE QUENCY TUNING WORD (FTW) SELECT ION
48-BI T NCO FT W = M IXING FREQ UE NCY /ADC SAM P LE RATE × 2
48
QUADRATURE ANALOG MI XER +
2 ADCs + QUADRATURE DIGITAL
MIXER + NCO
COMPLEX INPUT—SAMPLED AT f
S
–
f
S/32
f
S/32
DC
BANDWI DTH O F
INTEREST
POSITIVE FTW VALUES
IMAGE DUE TO
ANALOG I/Q
MISMATCH
REAL
I
Q
QUADRAT URE M IXE R
I
Q
I
–
+
Q
Q
I
Q+
+
Q
I
I
COMPLEX
I
Q
–sin(ωt)
ADC
SAMPLING
AT fS
ADC
SAMPLING
AT fS
90°
PHASE 48-BIT
NCO 90°
0°
48-BI T NCO FT W =
ROUND ( (fS/3)/fS × 248) = + 9.382513
(0x5555_5555_5555)
–fS/2 –fS/3 –fS/4 –fS/8 fS/16 fS/8 fS/4 fS/3 fS/2–fS/16
–fS/32 fS/32
DC
15660-071
Figure 100. DDC NCO Frequency Tuning Word Selection—Complex Inputs
Data Sheet AD9695
Rev. C | Page 47 of 136
DDC NCO Description
Each DDC contains one NCO. Each NCO enables the
frequency translation process by creating a complex
exponential frequency (e−jωct), which can be mixed with the
input spectrum to translate the desired frequency band of
interest to dc, where it can be filtered by the subsequent low-
pass filter blocks to prevent aliasing.
When placed in variable IF mode, the NCO supports two
different additional modes.
DDC NCO Programmable Modulus Mode
This mode supports >48-bit frequency tuning accuracy for
applications that require exact rational (M/N) frequency
synthesis at a single carrier frequency. In this mode, the NCO is
set up by providing the following:
• 48-bit frequency tuning word (FTW)
• 48-bit Modulus A word (MAW)
• 48-bit Modulus B word (MBW)
• 48-bit phase offset word (POW)
DDC NCO Coherent Mode
This mode allows an infinite number of frequency hops where the
phase is referenced to a single synchronization event at time 0.
This mode is useful when phase coherency must be maintained
when switching between different frequency bands. In this mode,
the user can switch to any tuning frequency without the need to
reset the NCO. Although only one FTW is required, the NCO
contains 16 shadow registers for fast-switching applications.
Selection of the shadow registers is controlled by the CMOS
GPIO pins or through the register map of the SPI. In this mode,
the NCO can be set up by providing the following:
• Up to sixteen 48-bit FTWs.
• Up to sixteen 48-bit POWs.
• The 48-bit MAW must be set to zero in coherent mode.
Figure 101 shows a block diagram of one NCO and its
connection to the rest of the design. The coherent phase
accumulator block contains the logic that allows an infinite
number of frequency hops.
NCO
COS/SIN
GENERATOR
Q
cos(x)
–sin(x)
Q
I
NCO CHANNEL
SELECTION
SYSREF
DIGITAL
QUADRATURE
MIXER
FT W = FREQUENCY TUNI NG WORD
POW = PHASE OFFSET W O RD
MAW = MODULUS A WO RD ( NUM E RATO R)
MBW = MODULUS B WO RD ( DE NOMINAT O R)
I
COHERENT
PHASE
ACCUMULATOR
BLOCK
48-BIT
MAW/MBW
MODULUS
ERROR
NCO
CHANNEL
SELECTION
CIRCUITS
I/O
CROSSBAR
MUX
SYNCHRONIZATION
CONT ROL CIRCUI TS
DECIMATION
FILTERS
MAW/MBW
FTW/POW
FTW/POW
WRI TE INDEX
0
1
15
0
1
15
48-BIT
FTW/POW
48-BIT
FTW/POW
48-BIT
FTW/POW
REGISTER
MAP
15660-072
Figure 101. NCO + Mixer Block Diagram
AD9695 Data Sheet
Rev. C | Page 48 of 136
NCO FTW/POW/MAW/MAB Description
The NCO frequency value is determined by the following settings:
• 48-bit twos complement number entered in the FTW
• 48-bit unsigned number entered in the MAW
• 48-bit unsigned number entered in the MBW
Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are
represented using the following values:
• FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000
represents a frequency of –fS/2.
• FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000
represents dc (frequency is 0 Hz).
• FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000
represents a frequency of +fS/2.
NCO FTW/POW/MAW/MAB Programmable
Modulus Mode
For programmable modulus mode, the MAW must be set to a
nonzero value (not equal to 0x0000_0000_0000). This mode is
only needed when frequency accuracy of >48 bits is required.
One example of a rational frequency synthesis requirement that
requires >48 bits of accuracy is a carrier frequency of 1/3 the
sample rate. When frequency accuracy of ≤48 bits is required,
coherent mode must be used (see the NCO FTW/POW/MAW/
MAB Coherent Mode section).
In programmable modulus mode, the FTW, MAW, and MBW
must satisfy the following four equations (for a detailed
description of the programmable modulus feature, see the DDS
architecture described in the AN-953 Application Note):
48
2
),mod( MBW
MAW
FTW
N
M
f
ff
s
sc
+
==
(1)
)
),mod(
2floor(
48
s
sc
f
ff
FTW =
(2)
MAW = mod(248 × M, N) (3)
MBW = N (4)
where:
fC is the desired carrier frequency.
fS is the ADC sampling frequency.
M is the integer representing the rational numerator of the
frequency ratio.
N is the integer representing the rational denominator of the
frequency ratio.
FTW is the 48-bit twos complement number representing the
NCO FTW.
MAW is the 48-bit unsigned number representing the NCO
MAW (must be <247).
MBW is the 48-bit unsigned number representing the NCO MBW.
mod(x) is a remainder function. For example mod(110,100) =
10 and for negative numbers, mod(−32,10) = −2.
floor(x) is defined as the largest integer less than or equal to x.
For example, floor(3.6) = 3.
Equation 1 to Equation 4 apply to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals).
M and N are integers reduced to their lowest terms. MAW and
MBW are integers reduced to their lowest terms. When MAW
is set to zero, the programmable modulus logic is automatically
disabled.
For example, if the ADC sampling frequency (fS) is 625 MSPS
and the carrier frequency (fC) is 208.6 MHz, then,
( )
1300
1300,8.417mod
6250
2089
== N
M
( )
=1300
1300,8.2417mod
2
48
floorFTW
= 0x5590_C0AD_03D9
MAW = mod(248 × 2089, 6250) = 0x0000_0000_1117
MBW = 0x0000_0000_186A
The actual carrier frequency can be calculated based on the
following equation:
48
_
2
S
ACTUALC
f
MBW
MAW
FTW
f
×+
=
For the previous example, the actual carrier frequency (fC_ACTUAL) is
MHz8.417
MHz1300
2
0_186A
0x0000_000
0_11170x0000_000
D_03D90x5590_C0A
48
_
=
×
+
=
ACTUALC
f
A 48-bit POW is available for each NCO to create a known
phase relationship between multiple chips or individual DDC
channels inside the chip.
While in programmable modulus mode, the FTW and POW
registers can be updated at any time while still maintaining
deterministic phase results in the NCO. However, the following
procedure must be followed to update the MAW and/or MBW
registers to ensure proper operation of the NCO:
1. Write to the MAW and MBW registers for all the DDCs.
2. Synchronize the NCOs either through the DDC soft reset
bit accessible through the SPI or through the assertion of
the SYSREF± pin (see the Memory Map section).
Data Sheet AD9695
Rev. C | Page 49 of 136
NCO FTW/POW/MAW/MAB Coherent Mode
For coherent mode, the NCO MAW must be set to zero
(0x0000_0000_0000). In this mode, the NCO FTW can be
calculated by the following equation:
)
)
,
mod(
2
round( 48
s
sc
f
ff
FTW =
(5)
where:
FTW is the 48-bit twos complement number representing the
NCO FTW.
fS is the ADC sampling frequency.
fC is the desired carrier frequency.
mod() is a remainder function. For example mod(110,100) = 10
and for negative numbers, mod(–32,10) = –2.
round() is a rounding function. For example round(3.6) = 4
and for negative numbers, round(–3.4) = –3.
Note that Equation 5 applies to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals). The MAW must be set to zero to use coherent
mode. When MAW is zero, the programmable modulus logic is
automatically disabled.
For example, if the ADC sampling frequency (fS) is 1300 MSPS
and the carrier frequency (fC) is 417.3333 MHz, then,
NCO_FTW = round
1300
33331300.417mod(
2
48
=
0x5578_49CE_E73F
The actual carrier frequency can be calculated based on the
following equation:
48
_
2
S
ACTUALC
fFTW
f×
=
For the previous example, the actual carrier frequency (fC_ACTUAL) is
fC_ACTUAL =
48
2
1300E_E73F0x5578_49C ×
= 417.33 MHz
A 48-bit POW is available for each NCO to create a known
phase relationship between multiple chips or individual DDC
channels inside the chip.
While in coherent mode, the FTW and POW registers can be
updated at any time while still maintaining deterministic phase
results in the NCO.
NCO Channel Selection
When configured in coherent mode, only one FTW is required
in the NCO. In this mode, the user can switch to any tuning
frequency without the need to reset the NCO by writing to the
FTW directly. However, for fast switching applications, where
either all FTWs are known beforehand or it is possible to queue
up the next set of FTWs, the NCO contains 16 additional
shadow registers (see Figure 106). These shadow registers are
hereafter referred to as the NCO channels.
Figure 102 shows a simplified block diagram of the NCO
channel selection block.
Only one NCO channel is active at a time, and NCO channel
selection is controlled either by the CMOS GPIO pins or
through the register map.
Each NCO channel selector supports three different modes, as
described in the following sections.
NCO CHANNEL
SELECTION
NCO CHANNEL SE LECTI ON
COUNTER
GPIO
CMOS
PINS GPIO
SELECTION
MUX INC
[0] NCO
REGISTER M AP NCO
CHANNEL S E LECTI ON
0x0314, 0x0334, 0x0354, 0x0374
NCO CHANNEL MODE
[3:0]
IN
IN
IN
IN
REGISTER
MAP
15660-073
Figure 102. NCO Channel Selection Block
AD9695 Data Sheet
Rev. C | Page 50 of 136
GPIO Level Control Mode
The GPIO pins determine the exact NCO channel selected.
The following procedure must be followed to use GPIO level
control for NCO channel selection:
1. Configure one or more GPIO pins as NCO channel
selection inputs. GPIO pins not configured as NCO
channel selection are internally tied low.
a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to
0x6 and Bits[3:0] in Register 0x0041 to 0x0.
b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to
0x6 and Bits [7:4] in Register 0x0041 to 0x0.
2. Configure the NCO channel selector in GPIO level control
mode by setting Bits[7:4] in the NCO control registers
(Register 0x0314, Register 0x0334, Register 0x0354, and
Register 0x0374) to 0x1 through 0x6, depending on the
desired GPIO pin ordering.
3. Select the desired NCO channel through the GPIO pins.
GPIO Edge Control Mode
Low to high transition on a single GPIO pin determines the
exact NCO channel selected. The internal channel selection
counter is reset by either SYSREF± or the DDC soft reset.
The following procedure must be followed to use GPIO edge
control for NCO channel selection:
1. Configure one or more GPIO pins as NCO channel
selection inputs.
a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to
0x6 and Bits[3:0] in Register 0x0041 to 0x0.
b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to
0x6 and Bits[7:4] in Register 0x0041 to 0x0.
2. Configure the NCO channel selector in GPIO edge control
mode by setting Bits[7:4] in the NCO control registers
(Register 0x0314, Register 0x0334, Register 0x0354, and
Register 0x0374) to 0x8 through 0xB, depending on the
desired GPIO Pin.
3. Configure the wrap point for the NCO channel selection
by setting Bits[3:0] in the NCO control registers
(Register 0x0314, Register 0x0334, Register 0x0354, and
Register 0x0374). A value of 4 causes the channel selection
to wrap at Channel 4 (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, and so on).
4. Transition the selected GPIO pin from low to high to
increment the NCO channel selection.
Register Map Mode
NCO channel selection is controlled directly through the
register map.
Data Sheet AD9695
Rev. C | Page 51 of 136
fS
/2
DC
B1
NCO CHANNE L 0
CARRIE R FREQ UE NCY 0
(ACTIVE)
NCO CHANNE L 1
CARRIE R FREQ UE NCY 1
(STANDBY)
NCO CHANNE L 2
CARRIE R FREQ UE NCY 2
(STANDBY)
B2
B0
f0f1f2
ACTIVE
DDC
15660-074
Figure 103. NCO Coherent Mode with Three NCO Channels (B0 Selected)
Figure 103 shows an example use case for coherent mode
utilizing three NCO channels. In this example, NCO Channel 0 is
actively downconverting bandwidth 0 (B0) while NCO
Channel 1 and Channel 2 are in standby and tuned to
Bandwidth 1 and Bandwidth 2 (B1 and B2), respectively.
The phase coherent NCO switching feature allows an infinite
number of frequency hops that are all phase coherent. The initial
phase of the NCO is established at time t0 from SYSREF±
synchronization. Switching the NCO FTW does not affect the
phase. With this feature, only one FTW is required; however, the
user may want to use all 16 channels to queue up the next hop.
After SYSREF± synchronization at start-up, all NCOs across
multiple chips are inherently synchronized.
Setting Up the Multichannel NCO Feature
The first step to configure the multichannel NCO is to program
the FTWs. The AD9695 memory map has a FTW index register
for each DDC. This index determines which NCO channel
receives the FTW from the register map. The following
sequence describes the method for programming the FTWs.
1. Write the FTW index register with the desired DDC channel.
2. Write the FTW with the desired value. This value is
applied to the NCO channel index mentioned in Step 1.
3. Repeat Step 1 and Step 2 for other NCO channels.
After setting the FTWs, the user must then select an active
NCO channel. This selection can be done either through the
SPI registers or through the external GPIO pins. The following
sequence describes the method for selecting the active NCO
channel using SPI.
1. Set the NCO channel selection mode (Bits[7:4]) in
Register 0x0314, Register 0x0334, Register 0x0354, and
Register 0x0374 to 0x0 to enable SPI selection.
2. Choose the active NCO channel (Bits[3:0]) in
Register 0x0314, Register 0x0334, Register 0x0354, and
Register 0x0374.
The following sequence describes the method for selecting the
active NCO channel using GPIO CMOS pins.
1. Set NCO channel selection mode (Bits[7:4]) in
Register 0x0314, Register 0x0334, Register 0x0354, and
Register 0x0374 to a nonzero value to enable GPIO pin
selection.
2. Configure the GPIO pins as NCO channel selection inputs
by writing to Register 0x0040, Register 0x0041, and
Register 0x0042.
3. NCO switching is done by externally controlling the GPIO
CMOS pins.
NCO Synchronization
Each NCO contains a separate phase accumulator word
(PAW). The initial reset value of each PAW is set to zero and
increments every clock cycle. The instantaneous phase of the
NCO is calculated using the PAW, FTW, MAW, MBW, and
POW. Due to this architecture, the FTW and POW registers
can be updated at any time while still maintaining deterministic
phase results in the PAW of the NCO.
Two methods can be used to synchronize multiple PAWs
within the chip:
• Using the SPI. Use the DDC soft reset bit in the DDC
synchronization control register (Register 0x0300, Bit 4) to
reset all the PAWs in the chip. This reset is accomplished
by setting the DDC soft reset bit high, and then setting this
bit low. Note that this method can only be used to
synchronize DDC channels within the same chip.
• Using the SYSREF± pin. When the SYSREF± pin is
enabled in the SYSREF control registers (Register 0x0120
and Register 0x0121), and the DDC synchronization is
enabled in the DDC synchronization control register
(Register 0x0300, Bits[1:0]), any subsequent SYSREF±
event resets all the PAWs in the chip. Note that this method
can be used to synchronize DDC channels within the same
chip or DDC channels within separate chips.
AD9695 Data Sheet
Rev. C | Page 52 of 136
NCO Multichip Synchronization
In some applications, it is necessary to synchronize all the NCOs
and local multiframe clocks (LMFCs) within multiple devices
in a system. For applications requiring multiple NCO tuning
frequencies in the system, a designer likely needs to generate a
single SYSREF± pulse at all devices simultaneously. For many
systems, generating or receiving a single-shot SYSREF± pulse at
all devices is challenging because of the following factors:
• Enabling or disabling the SYSREF± pulse is often an
asynchronous event.
• Not all clock generation chips support this feature.
For these reasons, the AD9695 contains a synchronization
triggering mechanism that allows the following:
• Multichip synchronization of all NCOs and LMFCs at
system startup.
• Multichip synchronization of all NCOs after applying new
tuning frequencies during normal operation.
The synchronization triggering mechanism uses a master/slave
arrangement, as shown in Figure 104.
CLOCK
GENERATION
SYSREF±
DEVICE_CLOCK±
MNTO
SNTI
SNTI
SNTI
1 LI NK,
L L ANE S
1 LI NK,
L L ANE S
1 LI NK,
L L ANE S
1 LI NK,
L L ANE S
ADC DEVI CE 0
(MASTER)
ADC DEVI CE 1
(SLAVE)
ADC DEVI CE 2
(SLAVE)
ADC DEVI CE 3
(SLAVE)
MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS)
SNTI = SLAVE NEXT TRIGG ER INPUT (CMOS)
15660-075
Figure 104. System Using Master/Slave Synchronization Triggering
Each device has an internal next synchronization trigger enable
(NSTE) signal that controls whether the next SYSREF± signal
causes a synchronization event. Slave ADC devices must source
their NSTE from an external slave next trigger input (SNTI) pin.
Master devices can either use an external master next trigger
output (MNTO) pin (default setting), or use an external SNTI pin.
See Table 48 (Register 0x0041 and Register 0x0042) to
configure the FD/GPIO pins for this operation.
NCO Multichip Synchronization at Startup
Figure 105 shows a timing diagram along with the required
sequence of events for NCO multichip synchronization using
triggering and SYSREF± at startup. Using this startup sequence
synchronizes all the NCOs and LMFCs in the system at once.
NCO Multichip Synchronization During Normal Operation
See the NCO Multichip Synchronization section.
Data Sheet AD9695
Rev. C | Page 53 of 136
MNTO
SNTI
SYSREF
DEVICE
CLOCK
LMFCs DON’T CARE
DON’T CARE
NCOs
NCO
SYNCHRONIZED
LMFC
SYNCHRONIZED
BOARD P ROPAG ATI ON
DELAY
NSTE
INP UT DEL AY
CONFIGURE M AS TER
AND SL AV E DEV ICES ENABLE TRIGGER IN
MASTER DEVICES
MNTO SET HIGH SNTI SET HIGH SYSTEM
SYNCHRONIZATION
ACHIEVED
SYSREF
IGNORED
MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS)
SNTI = SLAVE NEXT TRIG G ER INPUT (CMOS)
NST E = NE X T SY NCHRONI ZAT IO N TRI GG E R E NABLE
LMFC = LOCAL MULTIFRAME CLOCK
NCO = NUMERICALLY CONTROLLED OSCILLATOR
15660-076
Figure 105. NCO Multichip Synchronization at Startup (Using Triggering and SYSREF)
DDC Mixer Description
When not bypassed (Register 0x0200 ≠ 0x00), the digital
quadrature mixer performs a similar operation to an analog
quadrature mixer. It performs the downconversion of input
signals (real or complex) by using the NCO frequency as a local
oscillator. For real input signals, a real mixer operation (with
two multipliers) is performed. For complex input signals, a
complex mixer operation (with four multipliers and two
adders) is performed. The selection of real or complex inputs
can be controlled individually for each DDC block using Bit 7
of the DDC control registers (Register 0x0310, Register 0x0330,
Register 0x0350, and Register 0x0370).
DDC NCO + Mixer Loss and SFDR
When mixing a real input signal down to baseband, −6 dB of
loss is introduced in the signal due to filtering of the negative
image. An additional −0.05 dB of loss is introduced by the
NCO. The total loss of a real input signal mixed down to
baseband is −6.05 dB. For this reason, it is recommended that
the user compensate for this loss by enabling the 6 dB of gain in
the gain stage of the DDC to recenter the dynamic range of the
signal within the full scale of the output bits (see the DDC Gain
Stage section for more information).
When mixing a complex input signal (where I and Q DDC
inputs come from the different ADCs) down to baseband, the
maximum value each I/Q sample can reach is 1.414 × full-scale
after it passes through the complex mixer. To avoid overrange
of the I/Q samples and to keep the data bit widths aligned with
real mixing, −3.06 dB of loss is introduced in the mixer for
complex signals. An additional −0.05 dB of loss is introduced
by the NCO. The total loss of a complex input signal mixed
down to baseband is −3.11 dB.
The worst case spurious signal from the NCO is greater than
102 dBc SFDR for all output frequencies.
DDC DECIMATION FILTERS
After the frequency translation stage, there are multiple
decimation filter stages used to reduce the output data rate.
After the carrier of interest is tuned down to dc (carrier
frequency = 0 Hz), these filters efficiently lower the sample rate,
while providing sufficient alias rejection from unwanted
adjacent carriers around the bandwidth of interest.
Figure 106 shows a simplified block diagram of the decimation
filter stage, and Table 17 describes the filter characteristics of
the different FIR filter blocks.
Table 18, Table 19, and Table 20 show the different filter
configurations selectable by including different filters. In all
cases, the DDC filtering stage provides 80% of the available
output bandwidth, <±0.005 dB of pass-band ripple, and >100 dB
of stop band alias rejection.
AD9695 Data Sheet
Rev. C | Page 54 of 136
DECIMATION FILTERS DCM = 3
FIR = FINITE IMPULSE RESPONSE FILTER
DCM = DECIMATI ON
HB1
FIR
TB1
FIR
DCM = 2
HB4
FIR
TB2
FIR
DCM = 3
DCM = 3
DCM = 2
HB4
FIR
DCM = 2
FB2
FIR
DCM = 5
FB2
FIR
DCM = 5
DCM = 2
TB1
FIR
HB1
FIR
DCM = 3
I
TB2
FIR
Q
I
Q
HB3
FIR
DCM = 2
HB2
FIR
DCM = 2
HB3
FIR
DCM = 2
HB2
FIR
DCM = 2
Q
I
Q
I
Q
I
I
Q
I
Q
I
Q
I
I
Q
Q
NCO
AND
MIXERS
(OPTIONAL)
NOTES
1. TB1 IS ONL Y S UP P ORT E D IN DDC0 AND DDC1
GAI N = 0dB O R + 6dB
COMPLEX TO REAL CONVERSION
(OPTIONAL)
15660-077
Figure 106. DDC Decimation Filter Block Diagram
Table 17. DDC Decimation Filter Characteristics
Filter Name Filter Type
Decimation
Ratio
Pass Band
(rad/sec)
Stop Band
(rad/sec)
Pass-Band
Ripple (dB)
Stop-Band
Attenuation (dB)
HB4 FIR low-pass 2 0.1 x π/2 1.9 x π/2 <±0.001 >100
HB3 FIR low-pass 2 0.2 x π/2 1.8 x π/2 <±0.001 >100
HB2 FIR low-pass 2 0.4 x π/2 1.6 x π/2 <±0.001 >100
HB1 FIR low-pass 2 0.8 x π/2 1.2 x π/2 <±0.001 >100
TB2 FIR low-pass 3 0.4 x π/3 1.6 x π/3 <±0.002 >100
TB11 FIR low-pass 3 0.8 x π/3 1.2 x π/3 <±0.005 >100
FB2 FIR low-pass 5 0.4 x π/5 1.6 x π/5 <±0.001 >100
1 TB1 is only supported in DDC0 and DDC1.
Data Sheet AD9695
Rev. C | Page 55 of 136
Table 18. DDC Filter Configurations1
ADC
Sample
Rate DDC Filter Configuration
Real (I) Output Complex (I/Q) Outputs Alias
Protected
Bandwidth
Ideal SNR
Improvement
(dB)2
Decimation
Ratio
Sample
Rate
Decimation
Ratio Sample Rate
fS HB1 1 fS 2 fS/2 (I) + fS/2 (Q) fS/2 × 80% 1
fS TB13 N/A N/A 3 f fS/3 (I) + fS/3 (Q) fS/3 × 80% 2.7
fS HB2 + HB1 2 fS/2 4 fS/4 (I) + fS/4 (Q) fS/4 × 80% 4
fS TB2 + HB1 3 fS/3 6 fS/6 (I) + fS/6 (Q) fS/6 × 80% 5.7
fS HB3 + HB2 + HB1 4 fS/4 8 fS/8 (I) + fS/8 (Q) fS/8 × 80% 7
fS FB2 + HB1 5 fS/5 10 fS/10 (I) + fS/10 (Q) fS/10 × 80% 8
fS TB2 + HB2 + HB1 6 fS/6 12 fS/12 (I) + fS/12 (Q) fS/12 × 80% 8.8
fS FB2 + TB13 N/A N/A 15 fS/15 (I) + fS/15 (Q) fS/15 × 80% 9.7
fS HB4 + HB3 + HB2 + HB1 8 fS/8 16 fS/16 (I) + fS/16 (Q) fS/16 × 80% 10
fS FB2 + HB2 + HB1 10 fS/10 20 fS/20 (I) + fS/20 (Q) fS/20 × 80% 11
fS TB2 + HB3 + HB2 + HB1 12 fS/12 24 fS/24 (I) + fS/24 (Q) fS/24 × 80% 11.8
fS HB2 + FB2 + TB13 N/A N/A 30 fS/30 (I) + fS/30 (Q) fS/30 × 80% 12.7
fS FB2 + HB3 + HB2 + HB1 20 fS/20 40 fS/40 (I) + fS/40 (Q) fS/40 × 80% 14
fS TB2 + HB4 + HB3 + HB2 + HB1 24 fS/24 48 fS/48 (I) + fS/48 (Q) fS/48 × 80% 14.8
1 N/A means not applicable.
2 Ideal SNR improvement due to oversampling + filtering > 10log(bandwidth/fS/2).
3 TB1 is only supported in DDC0 and DDC1.
Table 19. DDC Filter Configurations (fS = 1300 MSPS)1
ADC Sample
Rate (MSPS) DDC Filter Configuration
Real (I) Output Complex (I/Q) Outputs Alias-Protected
Bandwidth
(MHz)
Decimation
Ratio
Sample Rate
(MSPS)
Decimation
Ratio
Sample Rate
(MSPS)
1300 HB1 1 1300 2 650 (I) + 650 (Q) 520
1300 TB12 N/A N/A 3
433.33 (I) + 433.33
(Q)
346.67
1300 HB2 + HB1 2 650 4 325 (I) + 325 (Q) 260
1300 TB2 + HB1 3 433.33 6 216.67 (I) + 216.67
(Q)
173.33
1300 HB3 + HB2 + HB1 4 325 8 162.5 (I) + 162.5 (Q) 130
1300 FB2 + HB1 5 260 10 130 (I) + 130 (Q) 104
1300 TB2 + HB2 + HB1 6 216.67 12 108.33 (I) + 108.33
(Q)
86.67
1300 FB2 + TB12 N/A N/A 15 86.67 (I) + 86.67 (Q) 69.33
1300 HB4 + HB3 + HB2 + HB1 8 162.5 16 81.25 (I) + 81.25 (Q) 65
1300 FB2 + HB2 + HB1 10 130 20 65 (I) + 65 (Q) 52
1300 TB2 + HB3 + HB2 + HB1 12 108.33 24 54.16 (I) + 54.16 (Q) 43.33
1300 HB2 + FB2 + TB12 N/A N/A 30 43.44 (I) + 43.44 (Q) 34.67
1300 FB2 + HB3 + HB2 + HB1 20 65 40 32.5 (I) + 32.5 (Q) 26
1300 TB2 + HB4 + HB3 + HB2 + HB1 24 54.16 48 27.08 (I) + 27.08 (Q) 21.67
1 N/A means not applicable.
2 TB1 is only supported in DDC0 and DDC1.
AD9695 Data Sheet
Rev. C | Page 56 of 136
Table 20. DDC Filter Configurations (fS = 625 MSPS)1
ADC Sample
Rate (MSPS) DDC Filter Configuration
Real (I) Output Complex (I/Q) Outputs Alias-Protected
Bandwidth
(MHz)
Decimation
Ratio
Sample Rate
(MSPS)
Decimation
Ratio
Sample Rate
(MSPS)
625 HB1 1 625 2 312.5 (I) + 312.5 (Q) 250
625 TB12 N/A N/A 3 208.33 (I) + 208.33
(Q)
166.67
625 HB2 + HB1 2 312.5 4 156.25 (I) + 156.25
(Q)
125
625 TB2 + HB1 3 208.33 6 104.17 (I) + 104.17
(Q)
83.33
625 HB3 + HB2 + HB1 4 156.25 8 78.125 (I) + 78.125
(Q)
62.5
625 FB2 + HB1 5 125 10 62.5 (I) + 62.5 (Q) 50
625 TB2 + HB2 + HB1 6 104.17 12 52.08 (I) + 52.08 (Q) 41.67
625 FB2 + TB12 N/A N/A 15 41.67 (I) + 41.67 (Q) 33.33
625 HB4 + HB3 + HB2 + HB1 8 78.125 16 39.06 (I) + 39.06 (Q) 31.25
625 FB2 + HB2 + HB1 10 62.5 20 31.25 (I) + 31.25 (Q) 25
625 TB2 + HB3 + HB2 + HB1 12 52.08 24 26.04 (I) + 26.04 (Q) 20.83
625 HB2 + FB2 + TB12 N/A N/A 30 20.83 (I) + 20.83 (Q) 16.67
625 FB2 + HB3 + HB2 + HB1 20 31.25 40 15.625 (I) + 15.625
(Q)
12.5
625 TB2 + HB4 + HB3 + HB2 + HB1 24 26.04 48 13.02 (I) + 13.02 (Q) 10.42
1 N/A means not applicable.
2 TB1 is only supported in DDC0 and DDC1.
HB4 Filter Description
The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses
an 11-tap, symmetrical, fixed coefficient filter implementation
that is optimized for low power consumption. The HB4 filter is
only used when complex outputs (decimate by 16) or real outputs
(decimate by 8) are enabled; otherwise, it is bypassed. Table 21 and
Figure 107 show the coefficients and response of the HB4 filter.
Table 21. HB4 Filter Coefficients
HB4 Coefficient
Number
Normalized
Coefficient
Decimal
Coefficient (15-Bit)
C1, C11 +0.006042 +99
C2, C10 0 0
C3, C9 −0.049377 −809
C4, C8 0 0
C5, C7 +0.293335 +4806
C6 +0.5 +8192
–160
–140
–120
–100
–80
–60
–40
–20
0
20
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAG NITUDE ( dB)
NORMALI ZED FREQUENC Y (× Π RAD/s)
15660-078
Figure 107. HB4 Filter Response
Data Sheet AD9695
Rev. C | Page 57 of 136
HB3 Filter Description
The second decimate by 2, half-band, low-pass, FIR filter (HB3)
uses an 11-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption. The HB3
filter is only used when complex outputs (decimate by 8 or 16)
or real outputs (decimate by 4 or 8) are enabled; otherwise, it is
bypassed. Table 22 and Figure 108 show the coefficients and
response of the HB3 filter.
Table 22. HB3 Filter Coefficients
HB3 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(17-Bit)
C1, C11 +0.006638 +435
C2, C10 0 0
C3, C9 −0.051056 −3346
C4, C8 0 0
C5, C7 +0.294418 +19,295
C6 +0.500000 +32,768
–160
–140
–120
–100
–80
–60
–40
–20
0
20
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAG NITUDE ( dB)
NORMALI ZED FREQUENC Y (× Π RAD/s)
15660-079
Figure 108. HB3 Filter Response
HB2 Filter Description
The third decimate by 2, half-band, low-pass, FIR filter (HB2)
uses a 19-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption.
The HB2 filter is only used when complex or real outputs
(decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed.
Table 23 and Figure 109 show the coefficients and response of
the HB2 filter.
Table 23. HB2 Filter Coefficients
HB2 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(18-Bit)
C1, C19 +0.000671 +88
C2, C18 0 0
C3, C17 −0.005325 −698
C4, C16 0 0
C5, C15 +0.022743 +2981
C6, C14 0 0
C7, C13 −0.074181 −9723
C8, C12 0 0
C9, C11 +0.306091 +40120
C10 +0.5 +65536
–160
–140
–120
–100
–80
–60
–40
–20
0
20
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAG NITUDE ( dB)
NORMALIZED FREQUENCY (× Π RAD/s)
15660-080
Figure 109. HB2 Filter Response
AD9695 Data Sheet
Rev. C | Page 58 of 136
HB1 Filter Description
The fourth and final decimate by 2, half-band, low-pass, FIR
filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter
implementation that is optimized for low power consumption.
The HB1 filter is always enabled and cannot be bypassed.
Table 24 and Figure 110 show the coefficients and response of
the HB1 filter.
Table 24. HB1 Filter Coefficients
HB1 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(20-Bit)
C1, C63 −0.000019 −10
C2, C62 0 0
C3, C61 +0.000072 +38
C4, C60 0 0
C5, C59 −0.000195 −102
C6, C58 0 0
C7, C57 +0.000443 +232
C8, C56 0 0
C9, C55 −0.000891 −467
C10, C54 0 0
C11, C53 +0.001644 +862
C12, C52 0 0
C13, C51 −0.002840 −1489
C14, C50 0 0
C15, C49 +0.004654 +2440
C16, C48 0 0
C17, C47 −0.007311 −3833
C18, C46 0 0
C19, C45 +0.011122 +5831
C20, C44 0 0
C21, C43 −0.016554 −8679
C22, C42 0 0
C23, C41 0.024420 12803
C24, C40 0 0
C25, C39 −0.036404 −19086
C26, C38 0 0
C27, C37 +0.056866 +29814
C28, C36 0 0
C29, C35 −0.101892 −53421
C30, C34 0 0
C31, C33 +0.316883 +166138
C32 +0.5 +262144
–160
–140
–120
–100
–80
–60
–40
–20
0
20
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAG NITUDE ( dB)
NORMALI ZED FREQUENC Y (× Π RAD/s)
15660-081
Figure 110. HB1 Filter Response
TB2 Filter Description
The TB2 uses a 26-tap, symmetrical, fixed coefficient filter
implementation that is optimized for low power consumption.
The TB2 filter is only used when decimation ratios of 6, 12, or
24 are required. Table 25 and Figure 111 show the coefficients
and response of the TB2 filter.
Table 25. TB2 Filter Coefficients
TB2 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(19-Bit)
C1, C26 −0.000191 −50
C2, C25 −0.000793 +208
C3, C24 −0.001137 −298
C4, C23 +0.000916 +240
C5, C22 +0.006290 +1649
C6, C21 +0.009823 +2575
C7, C20 +0.000916 +240
C8, C19 −0.023483 −6156
C9, C18 −0.043152 −11312
C10, C17 −0.019318 −5064
C11, C16 +0.071327 +18698
C12, C15 +0.201172 +52736
C13, C14 +0.297756 +78055
–160
–140
–120
–100
–80
–60
–40
–20
0
20
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAG NITUDE ( dB)
NORMALI ZED FREQUENC Y (× Π RAD/s)
15660-082
Figure 111. TB2 Filter Response
Data Sheet AD9695
Rev. C | Page 59 of 136
TB1 Filter Description
The TB1 decimate by 3, low-pass, FIR filter uses a 76-tap,
symmetrical, fixed coefficient filter implementation. Table 26
shows the TB1 filter coefficients, and Figure 112 shows the TB1
filter response. TB1 is only supported in DDC0 and DDC1.
Table 26. TB1 Filter Coefficients
TB1 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(22-Bit)
1, 76 −0.000023 −96
2, 75 −0.000053 −224
3, 74 −0.000037 −156
4, 73 +0.000090 +379
5, 72 +0.000291 +1220
6, 71 +0.000366 +1534
7, 70 +0.000095 +398
8, 69 −0.000463 −1940
9, 68 −0.000822 −3448
10, 67 −0.000412 −1729
11, 66 +0.000739 +3100
12, 65 +0.001665 +6984
13, 64 +0.001132 +4748
14, 63 −0.000981 −4114
15, 62 −0.002961 −12418
16, 61 −0.002438 −10226
17, 60 +0.001087 +4560
18, 59 +0.004833 +20272
19, 58 +0.004614 +19352
20, 57 −0.000871 −3652
21, 56 −0.007410 −31080
22, 55 −0.008039 −33718
23, 54 +0.000053 +222
24, 53 +0.010874 +45608
25, 52 +0.013313 +55840
26, 51 +0.001817 +7620
27, 50 −0.015579 −65344
28, 49 −0.021590 −90556
29, 48 −0.005603 −23502
30, 47
+0.022451
+94167
31, 46 +0.035774 +150046
32, 45 +0.013541 +56796
33, 44 −0.034655 −145352
34, 43 −0.066549 −279128
35, 42 −0.035213 −147694
36, 41 +0.071220 +298720
37, 40 +0.210777 +884064
38, 39 +0.309200 +1296880
MAG NITUDE ( dB)
NORMALI ZED FREQUENC Y (× Π RAD/s)
–160
–140
–120
–100
–80
–60
–40
–20
0
20
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
15660-083
Figure 112. TB1 Filter Response
AD9695 Data Sheet
Rev. C | Page 60 of 136
FB2 Filter Description
The FB2 decimate by 5, low-pass, FIR filter uses a 48-tap,
symmetrical, fixed coefficient filter implementation. Table 27
shows the FB2 filter coefficients, and Figure 113 shows the FB2
filter response.
Table 27. FB2 Filter Coefficients
FB2 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(21-Bit)
1, 48 +0.000007 7
2, 47 −0.000004 −4
3, 46 −0.000069 −72
4, 45 −0.000244 −256
5, 44 −0.000544 −570
6, 43 −0.000870 −912
7, 42 −0.000962 −1009
8, 41 −0.000448 −470
9, 40 +0.000977 +1024
10, 39 +0.003237 +3394
11, 38 +0.005614 +5887
12, 37 +0.006714 +7040
13, 36 +0.004871 +5108
14, 35 −0.001011 −1060
15, 34 −0.010456 −10964
16, 33 −0.020729 −21736
17, 32 −0.026978 −28288
18, 31 −0.023453 −24592
19, 30 −0.005608 −5880
20, 29 +0.027681 +29026
21, 28 +0.072720 +76252
22, 27 +0.121223 +127112
23, 26 +0.162346 +170232
24, 25 +0.185959 +194992
–160
–140
–120
–100
–80
–60
–40
–20
0
20
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAG NITUDE ( dB)
NORMALIZED FREQUENCY (× Π RAD/s)
15660-084
Figure 113. FB2 Filter Response
DDC GAIN STAGE
Each DDC contains an independently controlled gain stage.
The gain is selectable as either 0 dB or 6 dB. When mixing a
real input signal down to baseband, it is recommended that the
user enable the 6 dB of gain to recenter the dynamic range of
the signal within the full scale of the output bits.
When mixing a complex input signal down to baseband, the
mixer has already recentered the dynamic range of the signal
within the full scale of the output bits, and no additional gain is
necessary. However, the optional 6 dB gain compensates for
low signal strengths. The downsample by 2 portion of the HB1
FIR filter is bypassed when using the complex to real
conversion stage. The TB1 filter does not have the 6 dB gain
stage.
Data Sheet AD9695
Rev. C | Page 61 of 136
DDC COMPLEX TO REAL CONVERSION
Each DDC contains an independently controlled complex to
real conversion block. The complex to real conversion block
reuses the last filter (HB1 FIR) in the filtering stage along with
an fS/4 complex mixer to upconvert the signal. After upconverting
the signal, the Q portion of the complex mixer is no longer
needed and is dropped. The TB1 filter does not support
complex to real conversion.
Figure 114 shows a simplified block diagram of the complex to
real conversion.
LOW-PASS
FILTER
2
I
Q
REAL
HB1 FIR
LOW-PASS
FILTER 2
HB1 FIR
0
1
COMPLEX TO
REAL ENABLE
Q
90°0°
+
–
COMPLEX TO REAL CONVERSION
I
Q
I
Q
GAIN STAGE
cos(wt)
sin(wt)
I/REAL
0dB
OR
6dB
0dB
OR
6dB
0dB
OR
6dB
0dB
OR
6dB
f
S
/4
15660-085
Figure 114. Complex to Real Conversion Block
AD9695 Data Sheet
Rev. C | Page 62 of 136
DDC MIXED DECIMATION SETTINGS
The AD9695 also supports DDCs with different decimation
rates. In this scenario, the chip decimation ratio must be set to
the lowest decimation ratio of all the DDC channels. Samples of
higher decimation ratio DDCs are repeated to match the chip
decimation ratio sample rate. Only mixed decimation ratios
that are integer multiples of 2 are supported. For example,
decimate by 1, 2, 4, 8, or 16 can be mixed together, decimate by
3, 6, 12, 24, or 48 can be mixed together, or decimate by 5, 10,
20, or 40 can be mixed together.
Table 28 shows the DDC sample mapping when the chip
decimation ratio is different than the DDC decimation ratio.
For example, if the chip decimation ratio is set to decimate by 4,
DDC0 is set to use the HB2 + HB1 filters (complex outputs,
decimate by 4) and DDC1 is set to use the HB4 + HB3 + HB2 +
HB1 filters (real outputs, decimate by 8), then DDC1 repeats its
output data 2 times for every one DDC0 output. The resulting
output samples are shown in Table 29.
Table 28. Sample Mapping when Chip Decimation Ratio (DCM) Does Not Match DDC DCM
Sample Index DDC DCM = Chip DCM DDC DCM = 2 × Chip DCM DDC DCM = 4 × Chip DCM DDC DCM = 8 × Chip DCM
0 N N N N
1 N + 1 N N N
2 N + 2 N + 1 N N
3 N + 3 N + 1 N N
4 N + 4 N + 2 N + 1 N
5 N + 5 N + 2 N + 1 N
6 N + 6 N + 3 N + 1 N
7 N + 7 N + 3 N + 1 N
8 N + 8 N + 4 N + 2 N + 1
9
N + 9
N + 4
N + 2
N + 1
10 N + 10 N + 5 N + 2 N + 1
11 N + 11 N + 5 N + 2 N + 1
12 N + 12 N + 6 N + 3 N + 1
13 N + 13 N + 6 N + 3 N + 1
14 N + 14 N + 7 N + 3 N + 1
15 N + 15 N + 7 N + 3 N + 1
16 N + 16 N + 8 N + 4 N + 2
17 N + 17 N + 8 N + 4 N + 2
18 N + 18 N + 9 N + 4 N + 2
19 N + 19 N + 9 N + 4 N + 2
20 N + 20 N + 10 N + 5 N + 2
21 N + 21 N + 10 N + 5 N + 2
22 N + 22 N + 11 N + 5 N + 2
23 N + 23 N + 11 N + 5 N + 2
24 N + 24 N + 12 N + 6 N + 3
25 N + 25 N + 12 N + 6 N + 3
26 N + 26 N + 13 N + 6 N + 3
27 N + 27 N + 13 N + 6 N + 3
28 N + 28 N + 14 N + 7 N + 3
29 N + 29 N + 14 N + 7 N + 3
30 N + 30 N + 15 N + 7 N + 3
31 N + 31 N + 15 N + 7 N + 3
Data Sheet AD9695
Rev. C | Page 63 of 136
Table 29. Chip DCM = 4, DDC0 DCM = 4 (Complex), and DDC1 DCM = 8 (Real)1
DDC Input Samples
DDC0 DDC1
Output Port I Output Port Q Output Port I Output Port Q
N I0[N] Q0[N] I1[N] Not applicable
N + 1 I0[N] Q0[N] I1[N] Not applicable
N + 2 I0[N] Q0[N] I1[N] Not applicable
N + 3 I0[N] Q0[N] I1[N] Not applicable
N + 4 I0[N + 1] Q0[N + 1] I1[N] Not applicable
N + 5 I0[N + 1] Q0[N + 1] I1[N] Not applicable
N + 6 I0[N + 1] Q0[N + 1] I1[N] Not applicable
N + 7 I0[N + 1] Q0[N + 1] I1[N] Not applicable
N + 8 I0[N + 2] Q0[N + 2] I1[N + 1] Not applicable
N + 9 I0[N + 2] Q0[N + 2] I1[N + 1] Not applicable
N + 10 I0[N + 2] Q0[N + 2] I1[N + 1] Not applicable
N + 11 I0[N + 2] Q0[N + 2] I1[N + 1] Not applicable
N + 12 I0[N + 3] Q0[N + 3] I1[N + 1] Not applicable
N + 13 I0[N + 3] Q0[N + 3] I1[N + 1] Not applicable
N + 14 I0[N + 3] Q0[N + 3] I1[N + 1] Not applicable
N + 15 I0[N + 3] Q0[N + 3] I1[N + 1] Not applicable
1 DCM means decimation.
AD9695 Data Sheet
Rev. C | Page 64 of 136
DDC EXAMPLE CONFIGURATIONS
Table 30 describes the register settings for multiple DDC example configurations. Bandwidths listed are with <−0.005 dB of pass-band
ripple and >100 dB of stop band alias rejection.
Table 30. DDC Example Configurations (per ADC Channel Pair)
Chip
Application
Layer
Chip
Decimation
Ratio
DDC
Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of Virtual
Converters
Required Register Settings
One DDC 2 Complex Complex 40% × fS 2 0x0200 = 0x01 (one DDC; I/Q selected)
0x0201 = 0x01 (chip decimate by 2)
0x0310 = 0x83 (complex mixer; 0 dB gain; variable IF;
complex outputs; HB1 filter)
0x0311 = 0x04 (DDC I Input = ADC Channel A; DDC Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
Two DDCs 4 Complex Complex 20% × fS 4 0x0200 = 0x02 (two DDCs; I/Q selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain;
variable IF; complex outputs; HB2+HB1 filters)
0x0311, 0x0331 = 0x04 (DDC I input = ADC Channel A;
DDC Q input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
Two DDCs 4 Complex Real 10% × fS 2 0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain;
variable IF; real output; HB3 + HB2 + HB1 filters)
0x0311, 0x0331 = 0x04 (DDC I Input = ADC Channel A;
DDC Q input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
Two DDCs 4 Real Real 10% × fS 2 0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable
IF; real output; HB3 + HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
Data Sheet AD9695
Rev. C | Page 65 of 136
Chip
Application
Layer
Chip
Decimation
Ratio
DDC
Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of Virtual
Converters
Required Register Settings
Two DDCs 4 Real Complex 20% × fS 4 0x0200 = 0x02 (two DDCs; I/Q selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable
IF; complex output; HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
Two DDCs 8 Real Real 5% × fS 2 0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x03 (chip decimate by 8)
0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable
IF; real output; HB4 + HB3 + HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
Four DDCs 8 Real Complex 10% × fS 8 0x0200 = 0x03 (four DDCs; I/Q selected)
0x0201 = 0x03 (chip decimate by 8)
0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer; 6 dB
gain; variable IF; complex output; HB3 + HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q
input = ADC Channel A)
0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q
input = ADC Channel B)
0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,
0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 =
FTW and POW set as required by application for DDC2
0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,
0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 =
FTW and POW set as required by application for DDC3
AD9695 Data Sheet
Rev. C | Page 66 of 136
Chip
Application
Layer
Chip
Decimation
Ratio
DDC
Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of Virtual
Converters
Required Register Settings
Four DDCs 8 Real Real 5% × fS 4 0x0200 = 0x23 (four DDCs; I only selected)
0x0201 = 0x03 (chip decimate by 8)
0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer; 6 dB
gain; variable IF; real output; HB4 + HB3 + HB2 + HB1
filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q
input = ADC Channel A)
0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q
input = ADC Channel B)
0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,
0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 =
FTW and POW set as required by application for DDC2
0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,
0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 =
FTW and POW set as required by application for DDC3
Four DDCs 16 Real Complex 5% × fS 8 0x0200 = 0x03 (four DDCs; I/Q selected)
0x0201 = 0x04 (chip decimate by 16)
0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer;
6 dB gain; variable IF; complex output; HB4 + HB3 +
HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q
input = ADC Channel A)
0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q
input = ADC Channel B)
0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,
0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 =
FTW and POW set as required by application for DDC2
0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,
0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 =
FTW and POW set as required by application for DDC3
1 fS is the ADC sample rate.
Data Sheet AD9695
Rev. C | Page 67 of 136
DDC POWER CONSUMPTION
Table 31 describes the typical and maximum DVDD and DRVDD1 power for certain DDC modes. fS = 1.3 GHz in all cases.
Table 31. DDC Power Consumption for Example Configurations
Number
of DDCs
DDC Decimation
Ratio
Number of
Lanes (L)
Number of Virtual
Converters (M)
Number of Octets
per Frame (F)
DVDD Power (mW) DRVDD1 Power (mW)
Typ Max Typ Max
2 2 4 4 2 209 380 179 263
2 3 4 4 2 206 379 138 217
2 4 2 4 4 205 379 109 188
2 8 1 4 8 200 375 72 150
4 4 4 8 4 236 407 180 264
4 6 4 8 4 230 404 138 220
4 8 2 8 8 227 400 110 190
AD9695 Data Sheet
Rev. C | Page 68 of 136
SIGNAL MONITOR
The signal monitor block provides additional information
about the signal being digitized by the ADC. The signal
monitor computes the peak magnitude of the digitized signal.
This information can be used to drive an AGC loop to optimize
the range of the ADC in the presence of real-world signals.
The results of the signal monitor block can be obtained either
by reading back the internal values from the SPI port or by
embedding the signal monitoring information into the JESD204B
interface as special control bits. A global, 24-bit programmable
period controls the duration of the measurement. Figure 115
shows the simplified block diagram of the signal monitor block.
FROM
MEMORY
MAP DOWN
COUNTER IS
COUNT = 1?
MAGNITUDE
STORAGE
REGISTER
FROM
INPUT SIGNAL
MONITOR
HOLDING
REGISTER
LOAD
CLEAR
COMPARE
A > B
LOAD
LOAD TO SPORT OVER
JESD204B AND
MEMORY MAP
SIGNAL MONITOR
PERIOD REGISTER
(SMPR)
0x0271, 00x272, 0x0273
15660-086
Figure 115. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 of Register 0x0270 in the signal
monitor control register. The 24-bit SMPR must be
programmed before activating this mode.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
decimated clock rate. The magnitude of the input signal is
compared with the value in the internal magnitude storage
register (not accessible to the user), and the greater of the two
is updated as the current peak level. The initial value of the
magnitude storage register is set to the current ADC input signal
magnitude. This comparison continues until the monitor period
timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained previously,
continues.
Data Sheet AD9695
Rev. C | Page 69 of 136
SPORT OVER JESD204B
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bits[1:0]
of Register 0x0279 and Bit 1 of Register 0x027A. Figure 116 shows
two different example configurations for the signal monitor
control bit locations inside the JESD204B samples. A maximum
of three control bits can be inserted into the JESD204B samples;
however, only one control bit is required for the signal monitor.
Control bits are inserted from MSB to LSB. If only one control bit
is to be inserted (CS = 1), only the most significant control bit is
used (see Example Configuration 1 and Example Configuration 2
in Figure 116). To select the SPORT over JESD204B option,
program Register 0x0559, Register 0x055A, and Register 0x058F.
See Table 48 for more information on setting these bits.
Figure 117 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 118 shows the SPORT over JESD204B signal monitor
data with a monitor period timer set to 80 samples.
15
14-BI T CONV E RTER RE S OL UTI ON (N = 14)
TAIL
X
1
CONTROL
BIT
(CS = 1)
1-BIT
CONTROL
BIT
(CS = 1)
14 13 12 11 10 98 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 TAI L
BIT
SERIALIZED SIGNAL MONITOR
FRAM E DATA
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
SERIALIZED SIGNAL MONITOR
FRAM E DATA
16-BI T JESD204B S AM P LE S IZ E ( N' = 16)
S[13]
XS[12]
XS[11]
XS[10]
XS[9]
XS[8]
XS[7]
XS[6]
XS[5]
XS[4]
XS[3]
XS[2]
XS[1]
XS[0]
X
CTRL
[BIT 2 ]
X
CTRL
[BIT 2 ]
X
S[14]
XS[13]
XS[12]
XS[11]
XS[10]
XS[9]
XS[8]
XS[7]
XS[6]
XS[5]
XS[4]
XS[3]
XS[2]
XS[1]
XS[0]
X
15-BI T CONV E RTER RE S OL UTI ON (N = 15)
16-BI T JESD204B S AM P LE S IZ E ( N' = 16)
15660-087
Figure 116. Signal Monitor Control Bit Locations
25-BIT
FRAME
5-BIT IDLE
SUBFRAME
(OPTIONAL)
5-BIT IDENTIFIER
SUBFRAME
5-BIT DAT A
MSB
SUBFRAME
5-BIT DAT A
SUBFRAME
5-BIT DAT A
SUBFRAME
5-BIT DAT A
LSB
SUBFRAME
5-BIT SUBFRAME S
P[x] = P E AK M AGNI TUDE V ALUE
IDLE
1IDLE
1IDLE
1IDLE
1IDLE
1
START
0P[0] 000
START
0P[4] P[3] P[2] P1]
START
0P[8] P[7] P[6] P5]
START
0P[12] P[11] P[10] P[9]
START
0ID[3]
0ID[2]
0ID[1]
0ID[0]
1
15660-088
Figure 117. SPORT over JESD204B Signal Monitor Frame Data
AD9695 Data Sheet
Rev. C | Page 70 of 136
PAYLOAD
25-BI T FRAM E ( N)
PAYLOAD
25-BI T FRAM E ( N + 1)
PAYLOAD
25-BI T FRAM E ( N + 2)
IDLE IDLE IDLE IDLE IDLE IDLEIDLE IDLE IDLE IDLE IDLEIDENT. DATA
MSB DATA DATA DATA
LSB
IDLE IDLE IDLE IDLE IDLE IDLEIDLE IDLE IDLE IDLE IDLEIDENT. DATA
MSB DATA DATA DATA
LSB
IDLE IDLE IDLE IDLE IDLE IDLEIDLE IDLE IDLE IDLE IDLEIDENT. DATA
MSB DATA DATA DATA
LSB
SMP R = 80 S AM P LES ( 0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00)
80 SAMPLE PERIOD
80 SAMPLE PERIOD
80 SAMPLE PERIOD
15660-089
Figure 118. SPORT over JESD204B Signal Monitor Example
Data Sheet AD9695
Rev. C | Page 71 of 136
DIGITAL OUTPUTS
INTRODUCTION TO THE JESD204B INTERFACE
The AD9695 digital outputs are designed to the JEDEC standard
JESD204B, serial interface for data converters. JESD204B is a
protocol to link the AD9695 to a digital processing device over
a serial interface with lane rates of up to 16 Gbps. The benefits
of the JESD204B interface over LVDS include a reduction in
required board area for data interface routing, and an ability to
enable smaller packages for converter and logic devices.
JESD204B OVERVIEW
The JESD204B data transmit block assembles the parallel data
from the ADC into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of special control
characters during the initial establishment of the link. Additional
control characters are embedded in the data stream to maintain
synchronization thereafter. A JESD204B receiver is required to
complete the serial link. For additional details on the JESD204B
interface, refer to the JESD204B standard.
The AD9695 JESD204B data transmit block maps up to two
physical ADCs or up to eight virtual converters (when DDCs
are enabled) over a link. A link can be configured to use one,
two, or four JESD204B lanes. The JESD204B specification refers
to a number of parameters to define the link, and these parameters
must match between the JESD204B transmitter (the AD9695
output) and the JESD204B receiver (the logic device input).
The JESD204B link is described according to the following
parameters:
• L is the number of lanes/converter device (lanes/link)
(AD9695 value = 1, 2, or 4)
• M is the number of converters/converter device (virtual
converters/link) (AD9695 value = 1, 2, 4, or 8)
• F is the octets/frame (AD9695 value = 1, 2, 4, 8, or 16)
• N΄ is the number of bits per sample (JESD204B word size)
(AD9695 value = 8 or 16)
• N is the converter resolution (AD9695 value = 7 to 16)
• CS is the number of control bits/sample
(AD9695 value = 0, 1, 2, or 3)
• K is the number of frames per multiframe
(AD9695 value = 4, 8, 12, 16, 20, 24, 28, or 32 )
• S is the samples transmitted/single converter/frame cycle
(AD9695 value = set automatically based on L, M, F, and N΄)
• HD is the high density mode (AD9695 = set automatically
based on L, M, F, and N΄)
• CF is the number of control words/frame clock
cycle/converter device (AD9695 value = 0)
Figure 119 shows a simplified block diagram of the AD9695
JESD204B link. By default, the AD9695 is configured to use
two converters and four lanes. Converter A data is output to
SERDOUT0± and/or SERDOUT1±, and Converter B is output
to SERDOUT2± and/or SERDOUT3±. The AD9695 allows
other configurations, such as combining the outputs of both
converters onto a single lane, or changing the mapping of the
A and B digital output paths. These modes are customizable,
and can be set up via the SPI. Refer to the Memory Map section
for more details.
By default in the AD9695, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or a pseudorandom number
sequence. The tail bits can also be replaced with control bits
indicating overrange, SYSREF±, or fast detect output.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is recommended to avoid spectral peaks
when transmitting similar digital data patterns. The scrambler
uses a self-synchronizing, polynomial-based algorithm defined
by the equation 1 + x14 + x15. The descrambler in the receiver is
a self synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8-bit/10-bit encoder.
The 8-bit/10-bit encoder works by taking eight bits of data (an
octet) and encoding them into a 10-bit symbol. Figure 119
shows how the 14-bit data is taken from the ADC, how the tail
bits are added, how the two octets are scrambled, and how the
octets are encoded into two 10-bit symbols. Figure 120 shows the
default data format.
MUX/
FORMAT
(SPI
REGISTERS
0x0561,
0x0564)
JESD204B LI NK
CONTROL
(L, M, F)
(SPI REGIST ER
0x058B,
0x058E, 0x058C)
LANE M UX
AND
MAPPING
(SPI
REGISTERS
0x05B0,
0x05B2,
0x05B3,
0x05B5,
0x05B6)
CONV E RTER A
INPUT ADC A
CONV E RTER B
CONV E RTER 0
CONV E RTER 1
INPUT
SYSREF±
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYNCINB±
ADC B
15660-090
Figure 119. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00)
AD9695 Data Sheet
Rev. C | Page 72 of 136
ADC TES T PATT E RNS
(0x0550,
0x0551 TO 0x0558)
JESD204B L ONG
TRANSP ORT TES T
PATTERN
0x0571[5]
JESD204B
INT E RFACE TES T
PATTERN
(0x0573,
0x0551 TO 0x0558)
JESD204B DAT A
LI NK LAYE R TES T
PATTERNS
0x0574[2:0]
JESD204B SAM P LE
CONSTRUCTION
TAIL BITS
0x0571[6]
A13MSB
LSB
A12
A11
A10
A9
A8
A7 A13
A12
A11
A10
A9
A8
A7
A5
A4
A3
A2
A1
A0
C2
A6
MSB
LSB T
A6
A5
A4
A3
A2
A1
A0
C2
C1CONTROL BITS C0
ADC
SERDOUT0±
SERDOUT3±
SERDOUT2±
SERDOUT1±
FRAME
CONSTRUCTION
SERIALIZER
SYMBOL0 SYMBOL1
SCRAMBLER
1 + x
14
+ x
15
(OPTIONAL)
OCTET0
OCTET1
S7
S6
S5
S4
S3
S2
S1
S0
S7
ab i j a bi j
a b c de f ghij
a b c d ef g h i j
S6
S5
S4
S3
S2
S1
S0
MSB
LSB
8-BIT/
10-BIT
ENCODER
OCTET0
OCTET1
15660-091
Figure 120. ADC Output Datapath Showing Data Framing
SYSREF±
SYNCINB±
PROCESSED
SAMPLES
FRO M ADC SAMPLE
CONSTRUCTION FRAME
CONSTRUCTION 8-BIT/10-BIT
ENCODER CROSSBAR
MUX
SCRAMBLER SERIALIZER Tx
ALIGNMENT
CHARACTER
GENERATION OUTPUT
TRANSPORT
LAYER DATA L INK
LAYER PHYSICAL
LAYER
15660-092
Figure 121. Data Flow
FUNCTIONAL OVERVIEW
The block diagram in Figure 121 shows the flow of data
through the JESD204B hardware from the sample input to the
physical output. The processing can be divided into layers that
are derived from the open source initiative (OSI) model, widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer,
and physical layer (serializer and output driver).
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. The packing of samples into frames
are determined by the JESD204B configuration parameters for
number of lanes (L), number of converters (M), the number of
octets per lane per frame (F), the number of samples per
converter per frame (S), and the number of bits in a nibble
group (sometimes called the JESD204 word size − N’).
Samples are mapped in order starting from Converter 0, then
Converter 1, and so on until Converter M − 1. If S > 1, each
sample from the converter is mapped before mapping the
samples from the next converter. Each sample is mapped into
words formed by appending converter control bits, if enabled,
to the LSBs of each sample. The words are then padded with tail
bits, if necessary, to form nibble groups (NGs) of the appropriate
size as determined by the N’ parameter. The following equation
can be used to determine the number of tail bits within a nibble
group (JESD204B word):
T = N΄ − N − CS
Data Link Layer
The data link layer is responsible for the low level functions
of passing data across the link. These include optionally
scrambling the data, inserting control characters during the
initial lane alignment sequence (ILAS) and for frame and
multiframe synchronization monitoring, and encoding 8-bit
octets into 10-bit symbols. The data link layer is also responsible
for sending the ILAS, which contains the link configuration
data used by the receiver to verify the settings in the transport
layer.
Physical Layer
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data.
JESD204B LINK ESTABLISHMENT
The AD9695 JESD204B transmitter (Tx) interface operates in
Subclass 0 or Subclass 1 as defined in the JEDEC Standard
JESD204B (July 2011 specification). The link establishment
process is divided into the following steps: code group synchro-
nization, initial lane alignment sequence, and user data and error
correction.
Code Group Synchronization (CGS)
CGS is the process by which the JESD204B receiver finds the
boundaries between the 10-bit symbols in the stream of data.
During the CGS phase, the JESD204B transmit block transmits
/K/ characters (/K28.5/ symbols). The receiver must locate the
/K/ characters in its input data stream using clock and data
recovery (CDR) techniques.
Data Sheet AD9695
Rev. C | Page 73 of 136
The receiver issues a synchronization request by asserting the
SYNCINB± pin of the AD9695 low. The JESD204B Tx then begins
sending /K/ characters. Once the receiver has synchronized, it
waits for the correct reception of at least four consecutive /K/
symbols. It then deasserts SYNCINB±. The AD9695 then
transmits an ILAS on the following local multiframe clock
(LMFC) boundary.
For more information on the code group synchronization
phase, refer to the JEDEC Standard JESD204B, July 2011,
Section 5.3.3.1.
The SYNCINB± pin operation can also be controlled by the
SPI. The SYNCINB± signal is a differential dc-coupled LVDS
mode signal by default, but it can also be driven single-ended.
For more information on configuring the SYNCINB± pin
operation, refer to Register 0x572.
The SYNCINB± pins can also be configured to run in CMOS
(single-ended) mode by setting Bit 4 in Register 0x572. When
running SYNCINB± in CMOS mode, connect the CMOS
SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20
(SYNCINB−) disconnected.
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary after SYNCINB± deassertion. The ILAS
consists of four mulitframes, with an /R/ character marking the
beginning and an /A/ character marking the end. The ILAS
begins by sending an /R/ character followed by 0 to 255 ramp
data for one multiframe. On the second multiframe, the link
configuration data is sent, starting with the third character. The
second character is a /Q/ character to confirm that the link
configuration data follows. All undefined data slots are filled
with ramp data. The ILAS sequence is never scrambled.
The ILAS sequence construction is shown in Figure 122. The
four multiframes include the following:
• Multiframe 1 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
• Multiframe 2 begins with an /R/ character followed by a
/Q/ character (/K28.4/), followed by link configuration
parameters over 14 configuration octets (see Table 32) and
ends with an /A/ character. Many of the parameter values
are of the value – 1 notation.
• Multiframe 3 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
• Multiframe 4 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
User Data and Error Detection
After the initial lane alignment sequence is complete, the user
data (ADC samples) is sent. During transmission of the user data,
a mechanism called character replacement monitors the frame
clock and multiframe clock alignment. This mechanism replaces
the last octet of a frame or multiframe with an /F/ or /A/
alignment characters when the data meets certain conditions.
These conditions are different for unscrambled and scrambled
data. The scrambling operation is enabled by default, but it can
be disabled using the SPI.
For scrambled data, any 0xFC character at the end of a frame
is replaced by an /F/, and any 0x7C character at the end of a
multiframe is replaced with an /A/. The JESD204B receiver
(Rx) checks for /F/ and /A/ characters in the received data
stream and verifies that they only occur in the expected
locations. If an unexpected /F/ or /A/ character is found, the
receiver handles the situation by using dynamic realignment or
asserting the SYNCINB± signal for more than four frames to
initiate a resynchronization. For unscrambled data, if the final
octet of two subsequent frames are equal, the second octet is
replaced with an /F/ symbol if it is at the end of a frame, and an
/A/ symbol if it is at the end of a multiframe.
Insertion of alignment characters can be modified using SPI.
The frame alignment character insertion (FACI) is enabled by
default. More information on the link controls is available in
the Memory Map section, Register 0x571.
8-Bit/10-Bit Encoder
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols
and inserts control characters into the stream when needed. The
control characters used in JESD204B are shown in Table 32.
The 8-bit/10-bit encoding ensures that the signal is dc balanced by
using the same number of ones and zeros across multiple symbols.
The 8-bit/10-bit interface has options that can be controlled via
the SPI. These operations include bypass and invert. These options
are troubleshooting tools for the verification of the digital front
end (DFE). Refer to the Memory Map section, Register 0x572,
Bits[2:1] for information on configuring the 8-bit/10-bit
encoder.
K K R D
START OF
ILAS
●●●DA R Q D A RD DARD D
END OF
MULTIFRAME
A DC C D
START OF LINK
CONF IG URATI ON DATA START OF
USER DAT A
●●● ●●● ●●●●●●
●●● ●●● ●●● ●●●●●●
15660-093
Figure 122. Initial Lane Alignment Sequence
AD9695 Data Sheet
Rev. C | Page 74 of 136
Table 32. AD9695 Control Characters Used in JESD204B
Abbreviation Control Symbol 8-Bit Value
10-Bit Value,
RD1 = −1
10-Bit Value,
RD1 = +1 Description
/R/ /K28.0/ 000 11100 001111 0100 110000 1011 Start of multiframe
/A/ /K28.3/ 011 11100 001111 0011 110000 1100 Lane alignment
/Q/ /K28.4/ 100 11100 001111 0100 110000 1101 Start of link configuration data
/K/ /K28.5/ 101 11100 001111 1010 110000 0101 Group synchronization
/F/ /K28.7/ 111 11100 001111 1000 110000 0111 Frame alignment
1 RD means running disparity.
SERDOUTx+
DRVDD1
SERDOUTx–
O
UTPUT SWING = 0.85 × DRVDD1 V p-p DIFFERENTIAL
ADJUSTABLE TO
1 × DRVDD1, 0.75 × DRVDD1
100Ω
0.1µF
0.1µF RECEIVER
100Ω
DIFFERENTIAL
TRACE PAIR
15660-094
Figure 123. AC-Coupled Digital Output Termination Example
PHYSICAL LAYER (DRIVER) OUTPUTS
Digital Outputs, Timing, and Controls
The AD9695 physical layer consists of drivers that are defined in
the JEDEC Standard JESD204B, July 2011. The differential digital
outputs are powered up by default. The drivers use a dynamic
100 internal termination to reduce unwanted reflections.
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 0.85 × DRVDD1 V p-p swing at the
receiver (see Figure 123). The swing is adjustable through the
SPI registers. AC coupling is recommended to connect to the
receiver. See the Memory Map section (Register 0x05C0 to
Register 0x05C3 in Table 48) for more details.
The AD9695 digital outputs can interface with custom ASICs
and field programmable gate array (FPGA) receivers, providing
superior switching performance in noisy environments. Single
point-to-point network topologies are recommended with a
single differential 100 termination resistor placed as close to
the receiver inputs as possible.
If there is no far end receiver termination, or if there is poor
differential trace routing, timing errors can result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 124 to Figure 126 show an example of the digital output
data eye, jitter histogram, and bathtub curve for one AD9695
lane running at 16 Gbps. The format of the output data is twos
complement by default. To change the output data format, see
the Memory Map section (Register 0x0561).
15660-095
Figure 124. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps
15660-096
Figure 125. Digital Outputs Jitter Histogram, External 100 Ω Terminations at
16 Gbps
15660-097
Figure 126. Digital Outputs Bathtub Curve, External 100 Ω Terminations at
16 Gbps
Data Sheet AD9695
Rev. C | Page 75 of 136
De-Emphasis
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. Use the de-emphasis feature
only when the receiver is unable to recover the clock due to
excessive insertion loss. Under normal conditions, it is disabled
to conserve power. Additionally, enabling and setting too high
a de-emphasis value on a short link can cause the receiver eye
diagram to fail. Use the de-emphasis setting with caution
because it can increase electromagnetic interference (EMI). See
the Memory Map section (Register 0x05C4 to Register 0x05CA
in Table 48) for more details.
Phase-Locked Loop (PLL)
The PLL generates the serializer clock, which operates at the
JESD204B lane rate. The status of the PLL lock can be checked
in the PLL locked status bit (Register 0x056F, Bit 7). This read
only bit notifies the user if the PLL achieved a lock for the
specific setup. Register 0x056F also has a loss of lock (LOL)
sticky bit (Bit 3) that notifies the user that a loss of lock is
detected. The sticky bit can be reset by issuing a JESD204B link
restart (Register 0x0571, Bit 0 = 0x1, followed by Register 0x0571,
Bit 0 = 0x0). Refer to Table 34 for the reinitialization of the link
following a link power cycle.
The JESD204B lane rate control, Bits[7:4] of Register 0x056E,
must be set to correspond with the lane rate. Table 33 shows
the lane rates supported by the AD9695 using Register 0x056E.
Table 33. AD9695 Register 0x056E Supported Lane Rates
Value Lane Rate
0x00 Lane rate = 6.75 Gbps to 13.5
0x10 Lane rate = 3.375 Gbps to 6.75 Gbps (default)
0x30 Lane rate = 13.5 Gbps to 16 Gbps
0x50 Lane rate = 1.6875 Gbps to 3.375 Gbps
SETTING UP THE AD9695 DIGITAL INTERFACE
To ensure proper operation of the AD9695 at startup, some SPI
writes are required to initialize the link. Additionally, these
registers must be written every time the ADC is reset. Any one
of the following resets warrants the initialization routine for the
digital interface:
• Hard reset, as with power-up.
• Power-up using the PDWN pin.
• Power-up using the SPI via Register 0x0002, Bits[1:0].
• SPI soft reset by setting Register 0x0000 = 0x81.
• Datapath soft reset by setting Register 0x0001 = 0x02.
• JESD204B link power cycle by setting Register 0x0571,
Bit 0 = 0x1, then 0x0.
The initialization SPI writes are as shown in Table 34.
Table 34. AD9695 JESD204B Initialization
Registe
r
Valu
e Comment
0x1228 0x4F Reset JESD204B start-up circuit
0x1228 0x0F JESD204B start-up circuit in normal operation
0x1222 0x00 JESD204B PLL force normal operation
0x1222 0x04 Reset JESD204B PLL calibration
0x1222 0x00 JESD204B PLL normal operation
0x1262 0x08 Clear loss of lock bit
0x1262 0x00 Loss of lock bit normal operation
The AD9695 has one JESD204B link. The serial outputs
(SERDOUT0± to SERDOUT3±) are considered to be part of
one JESD204B link. The basic parameters that determine the
link setup are
• Number of lanes per link (L)
• Number of converters per link (M)
• Number of octets per frame (F)
If the internal DDCs are used for on-chip digital processing, M
represents the number of virtual converters. The virtual converter
mapping setup is shown in Table 11.
By default in the AD9695, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or a pseudorandom number
sequence. The tail bits can also be replaced with control bits
indicating overrange, SYSREF±, or fast detect output. Control
bits are filled and inserted MSB first such that enabling CS = 1
activates Control Bit 2, enabling CS = 2 activates Control Bit 2
and Control Bit 1, and enabling CS = 3 activates Control Bit 2,
Control Bit 1, and Control Bit 0.
The maximum lane rate allowed by the AD9695 is 16 Gbps.
The lane rate is related to the JESD204B parameters using the
following equation:
Lane Rate =
L
f
NM
OUT
×
×× 8
10
'
where fOUT =
RatioDecimation
f
CLOCKADC _
The decimation ratio (DCM) is the parameter programmed in
Register 0x0201.
Use the following procedure to configure the output:
1. Power down the link.
2. Select the JESD204B link configuration options.
3. Configure the detailed options.
4. Set output lane mapping (optional).
5. Set additional driver configuration options (optional).
6. Power up the link.
7. Initialize the JESD204B link by issuing the commands
described in Table 34.
AD9695 Data Sheet
Rev. C | Page 76 of 136
Register 0x056E must be programmed according to the lane
rate calculated. Refer to the Phase-Locked Loop (PLL) section
for more details.
Table 35 and Table 36 show the JESD204B output configurations
supported for both N΄ = 16, N’=12, and N΄ = 8 for a given
number of virtual converters. Take care to ensure that the serial
lane rate for a given configuration is within the supported
range of 1.6875 Gbps to 16 Gbps.
Table 35. JESD204B Output Configurations for N΄ = 161
Number
of Virtual
Converters
Supported
(Same as M)
JESD204B
Serial
Lane
Rate2
Supported Decimation Rates
JESD204B Transport Layer Settings3
Lane Rate =
1.6875 Gbps to
3.375 Gbps
Lane Rate =
3.375 Gbps to
6.75 Gbps
Lane Rate =
6.75 Gbps to
13.5 Gbps
Lane Rate =
13.5 Gbps to
16 Gbps L M F S HD N N' CS K
1 20 × fOUT 2, 4, 5, 6, 8, 10,
12
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 1 2 1 0 8 to 16 16 0 to 3 See
Note 4
20 × fOUT 2, 4, 5, 6, 8, 10,
12
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 1 4 2 0 8 to 16 16 0 to 3 See
Note 4
10 × fOUT 1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4 1, 2 1 2 1 1 1 1 8 to 16 16 0 to 3 See
Note 4
10 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 2 1 2 2 0 8 to 16 16 0 to 3 See
Note 4
5 × fOUT 1, 2, 3, 4 1, 2 1 4 1 1 2 1 8 to 16 16 0 to 3 See
Note 4
5 × fOUT 1, 2, 3, 4 1, 2 1 4 1 2 4 0 8 to 16 16 0 to 3 See
Note 4
2 40 × fOUT 4, 8, 10, 12, 15,
16, 20, 24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1 2 4 1 0 8 to 16 16 0 to 3 See
Note 4
40 × fOUT 4, 8, 10, 12, 15,
16, 20, 24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1 2 8 2 0 8 to 16 16 0 to 3 See
Note 4
20 × fOUT 2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 2 2 2 1 0 8 to 16 16 0 to 3 See
Note 4
20 × fOUT 2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 2 2 4 2 0 8 to 16 16 0 to 3 See
Note 4
10 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 2 1 1 1 8 to 16 16 0 to 3 See
Note 4
10 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 2 2 2 0 8 to 16 16 0 to 3 See
Note 4
4 80 × fOUT 8, 16, 20, 24, 30,
40, 48
4, 8, 10, 12, 16,
20, 24, 30
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8 1 4 8 1 0 8 to 16 16 0 to 3 See
Note 4
40 × fOUT 4, 8, 10, 12, 15,
16, 20, 24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 2 4 4 1 0 8 to 16 16 0 to 3 See
Note 4
40 × fOUT 4, 8, 10, 12, 15,
16, 20, 24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 2 4 8 2 0 8 to 16 16 0 to 3 See
Note 4
20 × fOUT 2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 4 4 2 1 0 8 to 16 16 0 to 3 See
Note 4
20 × fOUT 2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 4 4 4 2 0 8 to 16 16 0 to 3 See
Note 4
8 160 × fOUT 16, 40, 48 8, 16, 20, 24, 40,
48
4, 8, 12, 16, 20,
24
4, 8, 12, 16 1 8 16 1 0 8 to 16 16 0 to 3 See
Note 4
80 × fOUT 8, 16, 20, 24, 40,
48
4, 8, 10, 12, 16,
20, 24
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8 2 8 8 1 0 8 to 16 16 0 to 3 See
Note 4
40 × fOUT 4, 8, 10, 12, 16,
20, 24
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8 2, 4 4 8 4 1 0 8 to 16 16 0 to 3 See
Note 4
40 × fOUT 4, 8, 10, 12, 16,
20, 24
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8 2, 4 4 8 8 2 0 8 to 16 16 0 to 3 See
Note 4
1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
3 fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations
must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple(20 × DCM × fOUT/SLR, DCM) ≤
64. When the SLR is ≤16,000 Mbps and >13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13,500 Mbps and ≥6750 Mbps, Register 0x056E must be
set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and ≥1687.5 Mbps, Register 0x056E
must be set to 0x50.
4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,
K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
Data Sheet AD9695
Rev. C | Page 77 of 136
Table 36. JESD204B Output Configurations (N' = 12)1
Supported Decimation Rates
No. of Virtual
Converters
Supported
(Same Value as M)
Serial
Lane
Rate2
Lane Rate =
1.6875 Gbps
to 3.375 Gbps
Lane Rate =
3.375 Gbps to
6.75 Gbps
Lane Rate =
6.75 Gbps to
13.5 Gbps
Lane Rate =
13.5 Gbps to
16 Gbps
JESD204B Transport Layer Settings3
L
M
F
S
HD
N
N'
CS
K
1 15 × fOUT 3, 6, 12 3, 6 3 1 1 3 2 0 8 to 12 12 0 to 3 See
Note 4
7.5 × fOUT 3, 6 3 2 1 3 4 1 8 to 12 12 0 to 3 See
Note 4
7.5 × fOUT 3, 6 3 2 1 6 8 0 8 to 12 12 0 to 3 See
Note 4
5 × fOUT 1, 2, 3, 4 1, 2 1 3 1 1 2 1 8 to 12 12 0 to 3 See
Note 4
2 30 × fOUT 3, 6, 12, 24 3, 6, 12 3, 6 1 2 3 1 0 8 to 12 12 0 to 3 See
Note 4
15 × fOUT 3, 6, 12 3, 6 3 2 2 3 2 0 8 to 12 12 0 to 3 See
Note 4
10 × fOUT 1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4 1, 2 1 3 2 1 1 1 8 to 12 12 0 to 3 See
Note 4
7.5 × fOUT 3, 6 3 4 2 3 4 0 8 to 12 12 0 to 3 See
Note 4
4 60 × fOUT 6, 12, 24, 48 3, 6, 12, 24 3, 6, 12 1 4 6 1 0 8 to 12 12 0 to 3 See
Note 4
30 × fOUT 3, 6, 12, 24 3, 6, 12 3, 6 2 4 3 1 0 8 to 12 12 0 to 3 See
Note 4
20 × fOUT 2, 4, 5, 6, 8, 10,
12, 16
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4 1, 2 3 4 2 1 1 8 to 12 12 0 to 3 See
Note 4
15 × fOUT 3, 6, 12 3, 6 3 4 4 3 2 0 8 to 12 12 0 to 3 See
Note 4
8 60 × fOUT 6, 12, 24, 48 6, 12, 24 6, 12 2 8 6 1 0 8 to 12 12 0 to 3 See
Note 4
30 × fOUT 6, 12, 24 6, 12 6 4 8 3 1 0 8 to 12 12 0 to 3 See
Note 4
1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2 fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following
equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple(20 × DCM ×
fOUT/SLR, DCM) ≤ 64. When the SLR is ≤16,000 Mbps and >13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13,500 Mbps and ≥6750 Mbps,
Register 0x056E must be set to 0x00. When the SLR is <6750 Mbps and ≥3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and
≥1687.5 Mbps, Register 0x056E must be set to 0x50.
3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,
K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
AD9695 Data Sheet
Rev. C | Page 78 of 136
Table 37. JESD204B Output Configurations for N΄ = 81
Supported Decimation Rates
No. of Virtual
Converters
Supported
(Same Value as M)
Serial
Lane
Rate2
Lane Rate =
1.6875 Gbps to
3.375 Gbps
Lane Rate =
3.375 Gbps to
6.75 Gbps
Lane Rate =
6.75 Gbps to
13.5 Gbps
Lane Rate =
13.5 Gbps to
16 Gbps
JESD204B Transport Layer Settings3
L
M
F
S
HD
N
N'
CS
K
1 10 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 1 1 1 1 0 7 to 8 8 0 to 1 See
Note 4
1 10 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 1 1 2 2 0 7 to 8 8 0 to 1 See
Note 4
1 5 × fOUT 1, 2, 3, 4 1, 2 1 2 1 1 2 0 7 to 8 8 0 to 1 See
Note 4
1 5 × fOUT 1, 2, 3, 4 1, 2 1 2 1 2 4 0 7 to 8 8 0 to 1 See
Note 4
1 5 × fOUT 1, 2, 3, 4 1, 2 1 2 1 4 8 0 7 to 8 8 0 to 1 See
Note 4
1 2.5 × fOUT 1, 2 1 4 1 1 4 0 7 to 8 8 0 to 1 See
Note 4
1 2.5 × fOUT 1, 2 1 4 1 2 8 0 7 to 8 8 0 to 1 See
Note 4
2 20 × fOUT 2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5,
6, 8
1, 2, 3, 4 1, 2 1 2 2 1 0 7 to 8 8 0 to 1 See
Note 4
2 10 × fOUT 1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4 1, 2 1 2 2 1 1 0 7 to 8 8 0 to 1 See
Note 4
2 10 × fOUT 1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4 1, 2 1 2 2 2 2 0 7 to 8 8 0 to 1 See
Note 4
2 5 × fOUT 1, 2, 3, 4 1, 2 1 4 2 1 2 0 7 to 8 8 0 to 1 See
Note 4
2 5 × fOUT 1, 2, 3, 4 1, 2 1 4 2 2 4 0 7 to 8 8 0 to 1 See
Note 4
2 5 × fOUT 1, 2, 3, 4 1, 2 1 4 2 4 8 0 7 to 8 8 0 to 1 See
Note 4
1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2 fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following
equations must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple(20 × DCM ×
fOUT/SLR, DCM) ≤ 64. When the SLR is ≤16,000 Mbps and >13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps,
Register 0x056E must be set to 0x00. When the SLR is <6750 Mbps and ≥3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and
≥1687.5 Mbps, Register 0x056E must be set to 0x50.
3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,
K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
Data Sheet AD9695
Rev. C | Page 79 of 136
Example Setup 1—Full Bandwidth Mode
JESD204B
LINK
(L = 4,
M = 2,
F = 1,
S = 2,
N' = 16,
N = 16,
CS = 0,
HD = 1)
L0M0S0[15:8]
M0S0[7:0]
M0S1[15:8]
M0S1[7:0]
L1
L2
L3
VIN_A
REAL
I = RE AL CO M P ONENT
Q = QUADRAT URE COMP ONENT
DCM = DECIMATI ON
C2R = COM P LEX TO RE AL
MX = VI RTUAL CONVE RTER X
LY = LANE Y
SZ = SAMP LE Z I NS IDE A JE S D204B FRAME
C = CONTRO L BI T (OVE RRANGE, AMO NG O THERS )
T = TAIL BIT
VIN_B
REAL
M0
SYNC~
1300MSPS 13GBit/sec
F = 1
M1
14-BIT
ADC
CORE
14-BIT
ADC
CORE
15660-098
Figure 127. Full Bandwidth Mode
The AD9695 is set up as shown in Figure 127, with the
following configurations:
• Two 14-bit converters at 1300 MSPS.
• Full bandwidth application layer mode.
• Decimation filters bypassed.
The JESD204B output configuration is as follows:
• Two virtual converters required (see Table 35).
• Output sample rate (fOUT) = 1300/1 = 1300 MSPS.
The JESD204B supported output configurations are as follows
(see Table 35):
• N΄ = 16 bits.
• N = 14 bits.
• L = 4, M = 2, and F = 1.
• CS = 0.
• K = 32.
• Output serial lane rate:
• 13 Gbps per lane (L = 4).
• PLL control register:
• Register 0x056E is set to 0x00 (L = 4).
AD9695 Data Sheet
Rev. C | Page 80 of 136
Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs)
VIN_A
REAL
VIN_B
REAL
14-BI T ADC CORE
DDC0
(REAL INPUT,
DCM = 4
C2R = BYPAS S )
14-BI T ADC CORE
DDC1
(REAL INPUT,
DCM = 4
C2R = BYPAS S )
JESD204B
LINK
(L = 2
M = 4
F = 4,
S = 1,
N' = 16,
N = 16,
CS = 0,
HD =0)
SYNC
AB~
M
0
(I)S
0
[15:8]
F = 4
LEGEND
I = RE AL CO M P ONENT
Q = QUADRAT URE COMP ONENT
DCM = DECIMATI ON
C2R = COM P LEX TO RE AL
M
X
= VI RTUAL CONVE RTER X
L
Y
= LINK L ANE Y
SZ = S AM P LE Z I NS IDE A JE S D204B FRAME
C = CONTROL BIT (OVER-RANGE, ETC.)
T = TAIL BIT
M
0
(I)S
0
[7:0]
M
1
(Q)S
0
[15:8]
M
1
(Q)S
0
[7:0]
M
0
(I)
M
1
(Q)
M
2
(I)
M
3
(Q)
L
AB0
L
AB1
M
2
(I)S
0
[15:8]
M
2
(I)S
0
[7:0]
M
3
(Q)S
0
[15:8]
M
3
(Q)S
0
[7:0]
Fs (MHz) 40 x F
OUT
MbPS
F
OUT
= Fs / 4 (M Hz )
HB2_HB1 USED
15660-099
Figure 128. Two ADCs Plus Two DDCs Mode (L = 4, M = 4, F = 2, S = 1)
This example shows the flexibility in the digital and lane
configurations for the AD9695. The sample rate is 1300 MSPS,
whereas the outputs are all combined in a combination of either
two, four, or eight lanes, depending on the input/output speed
capability of the receiving device.
The AD9695 is set up as shown in Figure 128, with the
following configuration:
• Two 14-bit converters at 1300 MSPS.
• Two DDC application layer mode with complex outputs
(I/Q).
• Chip decimation ratio = 4.
• DDC decimation ratio = 4 (see the Memory Map section).
The JESD204B output configuration is as follows:
• Four virtual converters required (see Table 35).
• Output sample rate (fOUT) = 1300 MSPS/4 = 325 MSPS.
The JESD204B supported output configurations are as follows
(see Table 35):
• N΄ = 16 bits.
• N = 14 bits.
• L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 4.
• CS = 0.
• K = 32.
• Output serial lane rate = 6.5 Gbps per lane (L = 4), 13 Gbps
per lane (L = 2)
For L = 2, set the PLL control register, Register 0x056E, to 0x00.
For L = 4, set the PLL control register, Register 0x056E, to 0x10.
Data Sheet AD9695
Rev. C | Page 81 of 136
DETERMINISTIC LATENCY
Both ends of the JESD204B link contain various clock domains
distributed throughout each system. Data traversing from one
clock domain to a different clock domain can lead to
ambiguous delays in the JESD204B link. These ambiguities lead
to non-repeatable latencies across the link from one power
cycle or link reset to the next. Section 6 of the JESD204B
specification addresses the issue of deterministic latency with
mechanisms defined as Subclass 1 and Subclass 2.
The AD9695 supports JESD204B Subclass 0 and Subclass 1
operation. Register 0x0590, Bit 5 sets the subclass mode for the
AD9695; the default mode is the Subclass 1 operating mode
(Register 0x0590, Bit 5 = 1). If deterministic latency is not a
system requirement, Subclass 0 operation is recommended and
the SYSREF± signal may not be required. Even in Subclass 0
mode, the SYSREF± signal may be required in an application
where multiple AD9695 devices must be synchronized with each
other. This topic is addressed in the Timestamp Mode section.
SUBCLASS 0 OPERATION
If there is no requirement for multichip synchronization while
operating in Subclass 0 mode (Register 0x0590, Bit 5 = 0), the
SYSREF± input can be left disconnected. In this mode, the
relationship of the JESD204B clocks between the JESD204B trans-
mitter and receiver are arbitrary but does not affect the ability of
the receiver to capture and align the lanes within the link.
SUBCLASS 1 OPERATION
The JESD204B protocol organizes data samples into octets, frames,
and multiframes as described in the Transport Layer section. The
LMFC is synchronous with the beginnings of these
multiframes. In Subclass 1 operation, the SYSREF± signal
synchronizes the LMFCs for each device in a link or across
multiple links (within the AD9695, SYSREF± also synchronizes
the internal sample dividers). This synchronization is shown in
Figure 129. The JESD204B receiver uses the multiframe
boundaries and buffering to achieve consistent latency across
lanes (or even multiple devices), and to achieve a fixed latency
between power cycles and link reset conditions.
Deterministic Latency Requirements
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system:
• SYSREF± signal distribution skew within the system must
be less than the desired uncertainty for the system.
• SYSREF± setup and hold time requirements must be met
for each device in the system.
• The total latency variation across all lanes, links, and
devices must be ≤1 LMFC period (see Figure 129). This
includes both variable delays and the variation in fixed
delays from lane to lane, link to link, and device to device
in the system.
Setting Deterministic Latency Registers
The JESD204B receive buffer in the logic device buffers data
starting on the LMFC boundary. If the total link latency in the
system is near an integer multiple of the LMFC period, it is
possible that from one power cycle to the next, the data arrival
time at the receive buffer may straddle an LMFC boundary. To
ensure deterministic latency in this case, a phase adjustment of
the LMFC at either the transmitter or receiver must be
performed. Typically, adjustments to accommodate the receive
buffer are made to the LMFC of the receiver. In the AD9695, this
adjustment can be made using the LMFC offset bits
(Register 0x578, Bits[4:0]). These bits delay the LMFC in frame
clock increments, depending on the F parameter, which is the
number of octets per lane per frame). For F = 1, every fourth
setting (0, 4, 8, …, and so on) results in a one frame clock shift.
For F = 2, every other setting (0, 2, 4, …, and so on) results in a
1-frame clock shift. For all other values of F, each setting results
in a 1-frame clock shift.
SYSREF-ALIGNED
GLOBAL LMFC
ALL LMFCs
DATA
DEVICE CL OCK
SYSREF
ILAS DATA
SYSREF TO L MF C DELAY
PO WER CYCLE V ARIAT IO N
(MUST BE <
tLMFC
)
15660-100
Figure 129. SYSREF± and LMFC
AD9695 Data Sheet
Rev. C | Page 82 of 136
Figure 130 shows that, in the case where the link latency is near
an LMFC boundary, the local LMFC of the AD9695 can be
delayed to, in turn, delay the data arrival time at the receiver.
Figure 131 shows how the LMFC of the receiver is delayed to
accommodate the receive buffer timing. Refer to the applicable
JESD204B receiver user guide for details on making this adjust-
ment. If the total latency in the system is not near an integer
multiple of the LMFC period, or if the appropriate adjustments
are made to the LMFC phase at the clock source, it is still possible
to have variable latency from one power cycle to the next. In this
case, check for the possibility that the setup and hold time
requirements for the SYSREF± signal are not being met. Perform
this check by reading the SYSREF± setup and hold monitor
register (Register 0x0128). This function is described in the
SYSREF± Setup/Hold Window Monitor section.
If reading Register 0x0128 indicates a timing problem, there are
adjustments that can made in the AD9695. Changing the
SYSREF± level used for alignment is possible using the SYSREF±
transition select bit (Register 0x0120, Bit 4). Also, changing
which edge of the clock is used to capture SYSREF± can be
performed using the clock edge select bit (Register 0x0120,
Bit 3). Both of these options are described in the SYREF±
Control Features section. If neither of these measures help
achieve an acceptable setup and hold time, adjusting the phase
of SYSREF± and/or the device clock (CLK±) may be required.
SYSREF-ALIGNED
GLOBAL LMFC
DATA
(AT Tx I NP UT)
DATA
(AT Rx INPUT)
Tx LOCAL LMFC
Tx L M FC MOVE D ( DE LAYING THE ARRIVAL O F DATA RE LAT IVE
TO THE GLOBAL LMFC) SO THE RECIEVE BUFFER RELEASE TIME
IS ALWAYS REFERENCED TO THE SAME LMFC EDGE
LMFCTX DELAY TIME PO WER CY CLE V ARIAT ION
ILAS DATA
ILAS DATA
15660-101
Figure 130. Adjusting the JESD204B Tx LMFC in the AD9695
DATA
POWER CY CLE V ARIAT IO N
LMFC
RX
DELAY TIME
ILAS ILAS
ILAS
SYSREF-ALIGNED
GLOBAL LMFC
DATA
(AT Tx INP UT)
DATA
(AT Rx I NP UT)
Rx LOCAL LMFC
Rx LMFC MOVED SO THE RECEIVE BUFFER RELEASE TIME
IS ALWAYS REFERENCED TO THE SAME LMFC EDGE
DATA
15660-102
Figure 131. Adjusting the JESD204B Rx LMFC in the Logic Device
Data Sheet AD9695
Rev. C | Page 83 of 136
MULTICHIP SYNCHRONIZATION
The flowchart shown in Figure 133 describes the internal
mechanism for multichip synchronization in the AD9695.
There are two methods by which multichip synchronization
can take place, as determined by the chip synchronization
mode bit (Register 0x1FF, Bit 0). Each method involves
different applications of the SYSREF± signal.
NORMAL MODE
The default sate of the chip synchronization mode bit is 0,
which configures the AD9695 for normal chip synchronization.
The JESD204B standard specifies the use of SYSREF± to provide
deterministic latency within a single link. This same concept, when
applied to a system with multiple converters and logic devices, can
also provide multichip synchronization. In Figure 133, this is
referred to as normal mode. Following the process outlined in the
flowchart ensures that the AD9695 is configured appropriately.
Consult the logic devices user intellectual property (IP) guide to
ensure that the JESD204B receivers are configured appropriately.
TIMESTAMP MODE
For all AD9695 full bandwidth operating modes, the SYSREF±
input can also be used to timestamp samples. This is another
method by which multiple channels and multiple devices can
achieve synchronization. This is especially effective when
synchronizing multiple devices to one or more logic devices.
The logic devices buffer the data streams, identify the time
stamped samples, and align them. When the chip synchro-
nization mode bit (Register 0x1FF, Bit 0) is set to 1, the
timestamp method is used for synchronization of multiple
channels and/or devices. In timestamp mode, the clocks are not
reset but instead, the coinciding sample is time stamped using
the JESD204B control bits of that sample. To operate in timestamp
mode, the following additional settings are necessary:
• Continuous or N-shot SYSREF enabled (Register 0x0120,
Bits[2:1] = 1 or 2).
• At least one control bit must be enabled (CS > 0,
Register 0x058F, Bits[7:6] = 1, 2, or 3).
• Set the function for one of the control bits to SYSREF:
• Register 0x0559, Bits[2:0] = 5 if using Control Bit 0.
• Register 0x0559, Bits[6:4] = 5 if using Control Bit 1.
• Register 0x055A, Bits[2:0] = 5 if using Control Bit 2.
Enable control bits MSB first. In other words, if only using one
control bit (CS = 1), then Control Bit 2 must be enabled. If two
control bits are used, then Control Bits[2:1] must be enabled.
Figure 132 shows how the input sample coincident with
SYSREF± is time stamped and ultimately output of the ADC. In
this example, there are two control bits and Control Bit 1 is the
bit indicating which sample was coincident with the SYSREF
rising edge. Note that the pipeline latencies for each channel are
identical. If so desired, the SYSREF timestamp delay register
(Register 0x0123) can be used to adjust the timing of which
sample is time stamped.
Note that time stamping is not supported by any AD9695
operating modes that use decimation.
AINA
AINB
ENCODE CLK
SYSREF
CHANNEL B
CHANNEL A
N – 1 N
N + 1 N + 2 N + 3
N – 1 N
N + 1 N + 2 N + 3
N – 1 NN + 1
2 CONTROL BITS
CONT ROL BIT 0 US E D TO
TIME STAMP SAMPLE N
14-BIT SAMPLES OUT
N + 2 N + 300 00 00 0001
N – 1 NN + 1 N + 2 N + 300 00 00 0001
15660-103
Figure 132. AD9695 Timestamping—CS = 2 (Register 0x058F, Bits[7:6] = 2), Control Bit 1 is SYSREF± (Register 0x0559, Bits[6:4] = 5)
AD9695 Data Sheet
Rev. C | Page 84 of 136
YES
UPDAT E SE TUP/HO LD
DET E CTOR S TAT US
(0x0128)
INCREMENT
SYSREF IGNORE
COUNTER
YES
NO
SYSREF
IGNORE
COUNTER
EXPIRED?
(0x0121)
SYSREF
ENABLED?
(0x0120)
NO
CLOCK
DIVIDER
>1?
(
0x
010B)
YES
INPUT
CLO CK DIVIDER
ALIGNMENT
REQUIRED?
CLOCK
DIVIDER
AUTO ADJUS T
ENABLED?
YES
NO NO NO
YES
ALIGN CLOCK
DIV I DE R P HAS E
TO SYSREF
SYNCHRO-
NIZATION
MODE?
(0x01FF)
TIMESTAMP
MODE
NORMAL
MODE
YES SYSREF INSERTED
IN JE SD204B
CONTROL BITS
BACK TO ST ART
BACK TO ST ART
NO
JESD204B
LMFC
ALIGNMENT
REQUIRED?
DDC NCO
ALIGNMENT
ENABLED?
(0x0300)
YES
NO
ALI GN PHASE OF AL L
INT ERNAL CL OCKS
(INCLUDING LMFC)
TO SYSREF
SYNC~
ASSERTED
SEND I NVALID 8 -BI T /
10- BIT CHARACTERS
(ALL 0s)
NO
YES SEND K28. 5
CHARACTERS NORMAL
JESD204B
INITIALIZATION
SYSREF
ENABLED
IN CONTROL BITS?
(0x0559, 0x055A,
0x058F)
RESET
SYSREF IGNORE
COUNTER
START
SYSREF
ASSERTED? YES
NO
ALIGN DDC NCO
PHASE
ACCUMULATOR
YES
SIGNAL
MONITOR
ALIGNMENT
ENABLED?
(0x026F)
ALIGN SIGNAL
MONITOR
COUNTERS
YES
NO NO
SYSREF RESETS
RAMP TEST MODE
GENERATOR
RAMP
TEST MO DE
ENABLED?
(0x0550)
YES
NO
INCREMENT
SYSREF COUNTER
(0x012A)
SYSREF
TIMESTAMP
DELAY
(0x0123)
SYSREF
MODE
(0x0120)
N-SHOT
MODE
CONTINUOUS
MODE CLEAR S Y S RE F I GNO RE COUNT E R
AND DIS ABLE SY S RE F
(CL E AR BIT 2 IN 0x0120)
15660-104
Figure 133. SYSREF± Capture Scenarios and Multichip Synchronization
Data Sheet AD9695
Rev. C | Page 85 of 136
SYSREF± INPUT
The SYSREF± input signal is used as a high accuracy system
reference for deterministic latency and multichip synchronization.
The AD9695 accepts a single-shot or periodic input signal. The
SYSREF± mode select bits (Register 0x0120, Bits[2:1]) select the
input signal type and arm the SYSREF± state machine when
set. If in single- (or N) shot mode (Register 0x0120, Bits[2:1] =
2), the SYSREF± mode select bit self clears after the appropriate
SYSREF± transition is detected. The pulse width must have a
minimum width of two CLK± periods. If the clock divider
(Register 0x010B, Bits[2:0]) is set to a value other than divide by
1, then multiply this minimum pulse width requirement by the
divide ratio (for example, if set to divide by 8, the minimum
pulse width is 16 CLK± cycles). When using a continuous
SYSREF± signal (Register 0x0120, Bits[2:1] = 1), the period of
the SYSREF± signal must be an integer multiple of the LMFC.
Derive the LMFC using the following formula:
LMFC = ADC Clock/S × K
where:
S is the JESD204B parameter for number of samples per
converter.
K is JESD204B parameter for number of frames per multiframe.
The input clock divider, DDCs, signal monitor block, and
JESD204B link are all synchronized using the SYSREF± input
when in normal synchronization mode (Register 0x01FF,
Bits[1:0] = 0). The SYSREF± input can also be used to time
stamp an ADC sample to provide a mechanism for synchronizing
multiple AD9695 devices in a system. For the highest level of
timing accuracy, SYSREF± must meet the setup and hold
requirements relative to the CLK± input. There are several
features in the AD9695 to ensure these requirements are met
(see the SYREF± Control Features section).
SYREF± Control Features
SYSREF± is used, along with the input clock (CLK±), as part of
a source synchronous timing interface and requires setup and
hold timing requirements of 117 ps and −96 ps, relative to the
input clock (see Figure 134). The AD9695 has several features
to meet these requirements. First, the SYSREF± sample event
can be defined as either a synchronous low to high transition
or synchronous high to low transition. Second, the AD9695
allows the SYSREF± signal to be sampled using either the rising
edge or falling edge of the input clock. Figure 134, Figure 135,
Figure 136, and Figure 137 show all four possible combinations.
The third SYSREF± related feature available is the ability to
ignore a programmable number (up to 16) of SYSREF± events.
The SYSREF± ignore feature is enabled by setting the SYSREF±
mode register (Register 0x0120, Bits[2:1]) to 2’b10, which is
labeled as N-shot mode. The AD9695 is able to ignore N
SYSREF± events, which is useful to handle periodic SYSREF±
signals that require time to settle after startup. Ignoring SYSREF±
until the clocks in the system have settled avoids an inaccurate
SYSREF± trigger. Figure 138 shows an example of the
SYSREF± ignore feature when ignoring three SYSREF± events.
CLK
SYSREF
KEEP OUT WINDOW
SYSREF
SAMPLE POINT
HOLD
REQUIREMENT
120ps
SETUP
REQUIREMENT
–70ps
15660-105
Figure 134. SYSREF± Setup and Hold Time Requirements; SYSREF± Low to
High Transition Using the Rising Edge Clock (Default)
CLK
SYSREF
SYSREF
SAMPLE POINT
HOLD
REQUIREMENT
120ps
SETUP
REQUIREMENT
–70ps
15660-106
Figure 135. SYSREF± Low to High Transition Using Falling Edge Clock
Capture (Register 0x0120, Bit 4 = 1’b0 and Register 0x0120, Bit 3 = 1’b1)
CLK
SYSREF
SYSREF
SAMPLE POINT
HOLD
REQUIREMENT
120ps
SETUP
REQUIREMENT
–70ps
15660-107
Figure 136. SYSREF± High to Low Transition Using Rising Edge Clock Capture
(Register 0x0120, Bit 4 = 1’b1 and Register 0x0120, Bit 3 = 1’b0)
SYSREF
SAMPLE POINT
CLK
SYSREF
HOLD
REQUIREMENT
120ps
SETUP
REQUIREMENT
–70ps
15660-108
Figure 137. SYSREF± High to Low Transition Using Falling Edge Clock
Capture (Register 0x0120, Bit 4= 1’b1 and Register 0x0120, Bit 3 = 1’b1)
AD9695 Data Sheet
Rev. C | Page 86 of 136
CLK
SYSREF
SYSREF SAMPLE PART 1 SYSREF SAMPLE PART 2 SYSREF SAMPLE PART 3 SYSREF SAMPLE PART 4 SYSREF SAMPLE PART 5
IGNORE FIRST T HREE SYSREFs SAMPLE THE FO URTH SYSREF
15660-109
Figure 138. SYSREF± Ignore Example; SYSREF± Ignore Count Bits (Register 0x0121, Bits[3:0]) = 3
SAMPLE CLOCK
SYSREF
SYSREF SKEW WINDOW = ±1
SYSREF SKEW WINDOW = ±2
SYSREF SKEW WINDOW = ±3
SYSREF SKEW WINDOW = 0
15660-110
Figure 139. SYSREF± Skew Window
When in continuous SYSREF± mode (Register 0x0120, Bits[2:1] =
1), the AD9695 monitors the placement of the SYSREF±
leading edge compared to the internal LMFC. If the SYSREF±
edge is captured with a clock edge other than the one that is
aligned with LMFC, the AD9695 initiates a resynchronization
of the link. Because the input clock rates for the AD9695 can be
up to 4 GHz, the AD9695 provides another SYSREF± related
feature that makes it possible to accommodate periodic
SYSREF± signals where cycle accurate capture is not feasible or
not required. For these scenarios, the AD9695 has a
programmable SYSREF± skew window that allows the internal
dividers to remain undisturbed, unless SYSREF± occurs outside
the skew window. The resolution of the SYSREF± skew window
is set in sample clock cycles. If the SYSREF± negative skew
window is 1 and the positive skew window is 1, then the total
skew window is ±1 sample clock cycles, meaning that, as long
as SYSREF± is captured within ±1 sample clock cycle of the
clock that is aligned with LMFC, the link continues to operate
normally. If the SYSREF± has jitter, which can cause a
misalignment between SYSREF± and the LMFC, the system
continues to run without a resynchro-nization, while still
allowing the device to monitor for larger errors not caused by
jitter. For the AD9695, the positive and negative skew window is
controlled by the SYSREF± window negative bits
(Register 0x0122, Bits[3:2]) and the SYSREF± window positive
bits (Register 0x0122, Bits[1:0]). Figure 139 shows information
on the location of the skew window settings relative to Phase 0 of
the internal dividers. Negative skew is defined as occurring before
the internal dividers reach Phase 0 and positive skew is defined
after the internal dividers reach Phase 0.
Data Sheet AD9695
Rev. C | Page 87 of 136
SYSREF± SETUP/HOLD WINDOW MONITOR
To ensure a valid SYSREF± signal capture, the AD9695 has a
SYSREF± setup/hold window monitor. This feature allows the
system designer to determine the location of the SYSREF±
signals relative to the CLK± signals by reading back the amount
of setup/hold margin on the interface through the memory
map. Figure 140 and Figure 141 show the setup and hold status
values for different phases of SYSREF±. The setup detector
returns the status of the SYSREF± signal before the CLK± edge,
and the hold detector returns the status of the SYSREF signal
after the CLK± edge. Register 0x0128 stores the status of
SYSREF± and lets the user know if the SYSREF± signal is
captured by the ADC.
Table 38 describes the contents of Register 0x0128 and how to
interpret them.
VALID
REG 0x0128[ 3: 0]
CLK±
INPUT
SYSREF±
INPUT
FLIP-FLOP
HOLD (MIN)
FLIP-FLOP
HOLD (MIN)
FLIP-FLOP
SETUP (MIN)
0xF
0xE
0xD
0xC
0xB
0xA
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
15660-111
Figure 140. SYSREF± Setup Detector
AD9695 Data Sheet
Rev. C | Page 88 of 136
CLK±
INPUT
SYSREF±
INPUT VALID
REG 0x0128[7:4]
FLIP-FLOP
HOLD (MIN) FLIP-FLOP
HOLD (MIN)
FLIP-FLOP
SETUP (MIN)
0xF
0xE
0xD
0xC
0xB
0xA
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
15660-112
Figure 141. SYSREF± Hold Detector
Table 38. SYSREF± Setup/Hold Monitor, Register 0x0128
Register 0x0128, Bits[7:4]
Hold Status
Register 0x0128, Bits[3:0]
Setup Status Description
0x0 0x0 to 0x7 Possible setup error. The smaller this number, the smaller the setup margin.
0x0 to 0x8 0x8 No setup or hold error (best hold margin).
0x8 0x9 to 0xF No setup or hold error (best setup and hold margin).
0x8 0x0 No setup or hold error (best setup margin).
0x9 to 0xF 0x0 Possible hold error. The larger this number, the smaller the hold margin.
0x0 0x0 Possible setup or hold error.
Data Sheet AD9695
Rev. C | Page 89 of 136
LATENCY
END TO END TOTAL LATENCY
Total latency in the AD9695 is dependent on the chip
application mode and the JESD204B configuration. For any
given combination of these parameters, the latency is
deterministic, however, the value of this deterministic latency
must be calculated as described in the Example Latency
Calculations section.
Table 39 shows the combined latency through the ADC and
DSP for the different chip application modes supported by the
AD9695. Table 40 shows the latency through the JESD204B
block for each application mode based on the M/L ratio. For
both tables, latency is typical and is in units of the encode clock.
The latency through the JESD204B block does not depend on
the output data type (real or complex). Therefore, data type is
not included in Table 40.
To determine the total latency, select the appropriate ADC +
DSP latency from Table 39 and add it to the appropriate
JESD204B latency from Table 40. Example calculations are
provided in the following section.
EXAMPLE LATENCY CALCULATIONS
Example Configuration 1 is as follows:
• ADC application mode = full bandwidth
• Real outputs
• L = 4, M = 2, F = 1, S = 1 (JESD204B mode)
• M/L = 0.5
• Latency = 31 + 25 = 56 encode clocks
Example Configuration 2 is as follows:
• ADC application mode = DCM4
• Complex outputs
• L = 2, M = 2, F = 2, S = 1 (JESD204B mode)
• M/L = 1
• Latency = 162 + 50 = 212 encode clocks
LMFC REFERENCED LATENCY
Some FPGA vendors may require the end user to know LMFC
referenced latency to make appropriate deterministic latency
adjustments. If they are required, the latency values in Table 39
and Table 40 can be used for the analog input to LMFC and
LMFC to data output latency values, respectively.
AD9695 Data Sheet
Rev. C | Page 90 of 136
Table 39. Latency Through the ADC + DSP Blocks (Number of Sample Clocks)1
Chip Application Mode Enabled Filters ADC + DSP Latency
Full Bandwidth Not applicable 31
DCM1 (Real) HB1 90
DCM2 (Complex) HB1 90
DCM3 (Complex) TB1 102
DCM2 (Real) HB2 + HB1 162
DCM4 (Complex) HB2 + HB1 162
DCM3 (Real) TB2 + HB1 212
DCM6 (Complex) TB2 + HB1 212
DCM4 (Real) HB3 +HB2 + HB1 292
DCM8 (Complex) HB3 +HB2 + HB1 292
DCM5 (Real) FB2 + HB1 380
DCM10 (Complex) FB2 + HB1 380
DCM6 (Real) TB2 + HB2 + HB1 424
DCM12 (Complex) TB2 + HB2 + HB1 424
DCM15 (Real) FB2 + TB1 500
DCM8 (Real) HB4 + HB3 + HB2 + HB1 552
DCM16 (Complex) HB4 + HB3 + HB2 + HB1 552
DCM10 (Real) FB2 + HB2 + HB1 694
DCM20 (Complex) FB2 + HB2 + HB1 694
DCM12 (Real) TB2 + HB3 + HB2 + HB1 814
DCM24 (Complex) TB2 + HB3 + HB2 + HB1 814
DCM30 (Complex) HB2 + FB2 + TB1 836
DCM20 (Real) FB2 + HB3 + HB2 + HB1 1420
DCM40 (Complex) FB2 + HB3 + HB2 + HB1 1420
DCM24 (Real) TB2 + HB4 + HB3 + HB2 + HB1 1594
DCM48 (Complex) TB2 + HB4 + HB3 + HB2 + HB1 1594
1 DCMx indicates the decimation ratio.
Table 40. Latency Through JESD204B Block (Number of Sample Clocks)1
Chip Application Mode
M/L Ratio2
0.125 0.25 0.5 1 2 4 8
Full Bandwidth 82 44 25 14 7 9 3
DCM1 82 44 25 14 7 N/A N/A
DCM2 160 84 46 27 14 7 N/A
DCM3 237 124 67 39 21 11 N/A
DCM4 315 164 88 50 27 14 9
DCM5 N/A 2033 1093 623 433 N/A N/A
DCM6 N/A 243 130 73 39 21 14
DCM8 N/A 323 172 96 50 27 18
DCM10 N/A N/A 213 119 62 33 22
DCM12 N/A N/A 255 142 73 39 27
DCM15 N/A N/A 3184 1764 904 474 334
DCM16 N/A N/A 3394 1884 964 504 354
DCM20 N/A N/A N/A 233 119 62 43
DCM24 N/A N/A N/A 279 142 73 51
DCM30 N/A N/A N/A 3484 1764 904 624
DCM40 N/A N/A N/A N/A 2334 1194 824
DCM48
N/A
N/A
N/A
N/A
279
4
142
4
97
4
1 N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed.
2 M/L ratio is the number of converters divided by the number of lanes for the configuration.
3 The application mode at the M/L ratio listed is only supported in real output mode.
4 The application mode at the M/L ratio listed is only supported in complex output mode.
Data Sheet AD9695
Rev. C | Page 91 of 136
TEST MODES
ADC TEST MODES
The AD9695 has various test options that aid in the system
level implementation. The AD9695 has ADC test modes that
are available in Register 0x0550. These test modes are described
in Table 41. When an output test mode is enabled, the analog
section of the ADC is disconnected from the digital back end
blocks, and the test pattern is run through the output formatting
block. Some of the test patterns are subject to output formatting
and some are not. The pseudorandom number (PN) generators
from the PN sequence tests can be reset by setting Bit 4 or Bit 5
of Register 0x0550. These tests can be performed with or
without an analog signal (if present, the analog signal is
ignored); however, they do require an encode clock.
If the application mode is set to select a DDC mode of
operation, the test modes must be enabled for each DDC
enabled. The test patterns can be enabled via Bit 2 and Bit 0 of
Register 0x0327, Register 0x0347, and Register 0x0367,
depending on which DDC(s) are selected. The (I) data uses the
test patterns selected for Channel A, and the (Q) data uses the
test patterns selected for Channel B. For DDC3 only, the (I)
data uses the test patterns from Channel A, and the (Q) data
does not output test patterns. Bit 0 of Register 0x0387 selects
the Channel A test patterns to be used for the (I) data. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
8-BIT/10-BIT
ENCODER
SERDOUT0±
SERDOUT1±
TAIL BITS
0x571[6]
SERIALIZER
ADC
SYMBOL0 SYMBOL1
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C2
C1
C0
MSB
LSB
CONT ROL BITS
ADC TEST PATTERNS
(RE0x550,
REG 0x551 TO
REG 0x558)JESD204B SAMPLE
CONSTRUCTION
JESD204B
INTERFACE
TEST PATTERN
(REG 0x573,
REG 0x551 TO
REG 0x558)
FRAME
CONSTRUCTION
JESD20 4 B DATA
LI NK LAYE R TES T
PATTERNS
REG 0x574[2:0]
SCRAMBLER
1 + x14 + x15
(OPTIONAL)
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C2
T
MSB
LSB
OCTET 0
OCTET 1
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
MSB
LSB
OCTET 0
OCTET 1
a b cd e fg h i j
ab c de f g h ij
ab i ja b i j
15660-214
JESD204B
LO NG TRANSPORT
TEST PATTERN
REG 0x571[5]
Figure 142. ADC Output Datapath Showing Data Framing
Table 41. ADC Test Modes1
Output Test Mode
Bit Sequence Pattern Name Expression
Default/
Seed Value Sample (N, N + 1, N + 2, …)
0000 Off (default) N/A N/A N/A
0001 Midscale short 0000 0000 0000 N/A N/A
0010 Positive full-scale short 01 1111 1111 1111 N/A N/A
0011 Negative full-scale short 10 0000 0000 0000 N/A N/A
0100
Checkerboard
10 1010 1010 1010
N/A
0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555
0101 PN sequence long x23 + x18 + 1 0x3AFF 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6
0110 PN sequence short x9 + x5 + 1 0x0092 0x125B, 0x3C9A, 0x2660, 0x0C65, 0x0697
0111 One-/zero-word toggle 11 1111 1111 1111 N/A 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000
1000 User input Register 0x0551 to
Register 0x0558
N/A User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
User Pattern 1[15:2] … for repeat mode.
User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
0x0000 … for single mode.
1111 Ramp output (x) % 214 N/A (x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214
1 N/A means not applicable.
AD9695 Data Sheet
Rev. C | Page 92 of 136
JESD204B BLOCK TEST MODES
In addition to the ADC pipeline test modes, the AD9695 also has
flexible test modes in the JESD204B block. These test modes are
listed in Register 0x0573 and Register 0x0574. These test patterns
can be injected at various points along the output datapath. These
test injection points are shown in Figure 142. Table 42 describes
the various test modes available in the JESD204B block. For the
AD9695, a transition from test modes (Register 0x0573 ≠ 0x00)
to normal mode (Register 0x0573 = 0x00) requires an SPI soft
reset. This is done by writing 0x81 to Register 0x0000 (self cleared).
Transport Layer Sample Test Mode
The transport layer samples are implemented in the AD9695 as
defined by Section 5.1.6.3 in the JEDEC JESD204B specification.
These tests are shown in Register 0x0571, Bit 5. The test pattern
is equivalent to the raw samples from the ADC.
Interface Test Modes
The interface test modes are described in Register 0x0573,
Bits[3:0]. These test modes are also explained in Table 43. The
interface tests can be injected at various points along the data.
See Figure 142 for more information on the test injection points.
Register 0x0573, Bits[5:4] show where these tests are injected.
Table 44 and Table 45 show examples of some of the test modes
when injected at the JESD sample input, PHY 10-bit input, and
scrambler 8-bit input. UPx in the tables represent the user
pattern control bits from the customer register map.
Table 42. JESD204B Interface Test Modes
Output Test Mode
Bit Sequence Pattern Name Expression Default
0000 Off (default) Not applicable Not applicable
0001 Alternating checker board 0x5555, 0xAAAA, 0x5555, … Not applicable
0010 1/0 word toggle 0x0000, 0xFFFF, 0x0000, … Not applicable
0011 31-bit PN sequence x31 + x28 + 1 0x0003AFFF
0100 23-bit PN sequence x23 + x18 + 1 0x003AFF
0101 15-bit PN sequence x15 + x14 + 1 0x03AF
0110 9-bit PN sequence x9 + x5 + 1 0x092
0111 7-bit PN sequence x7 + x6 + 1 0x07
1000 Ramp output (x) % 216 Ramp size depends on test injection point
1110 Continuous/repeat user test Register 0x0551 to Register 0x0558 User Pattern 1 to User Pattern 4, then repeat
1111 Single user test Register 0x0551 to Register 0x0558 User Pattern 1 to User Pattern 4, then zeros
Table 43. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00)
Frame
Number
Converter
Number
Sample
Number
Alternating
Checkerboard
1/0 Word
Toggle Ramp PN9 PN23 User Repeat User Single
0 0 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
0 0 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
0 1 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
0 1 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
1 0 0 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
1 0 1 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
1 1 0 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
1 1 1 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
2 0 0 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
2 0 1 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
2 1 0 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
2 1 1 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
3 0 0 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
3 0 1 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
3 1 0 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
3 1 1 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
4 0 0 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
4 0 1 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
4 1 0 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
4 1 1 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
Data Sheet AD9695
Rev. C | Page 93 of 136
Table 44. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01)
10-Bit Symbol
Number
Alternating
Checkerboard
1/0 Word
Toggle Ramp PN9 PN23 User Repeat User Single
0 0x155 0x000 (x) % 210 0x125 0x3FD UP1[15:6] UP1[15:6]
1 0x2AA 0x3FF (x + 1) % 210 0x2FC 0x1C0 UP2[15:6] UP2[15:6]
2 0x155 0x000 (x + 2) % 210 0x26A 0x00A UP3[15:6] UP3[15:6]
3 0x2AA 0x3FF (x + 3) % 210 0x198 0x1B8 UP4[15:6] UP4[15:6]
4 0x155 0x000 (x + 4) % 210 0x031 0x028 UP1[15:6] 0x000
5 0x2AA 0x3FF (x + 5) % 210 0x251 0x3D7 UP2[15:6] 0x000
6 0x155 0x000 (x + 6) % 210 0x297 0x0A6 UP3[15:6] 0x000
7 0x2AA 0x3FF (x + 7) % 210 0x3D1 0x326 UP4[15:6] 0x000
8 0x155 0x000 (x + 8) % 210 0x18E 0x10F UP1[15:6] 0x000
9 0x2AA 0x3FF (x + 9) % 210 0x2CB 0x3FD UP2[15:6] 0x000
10 0x155 0x000 (x + 10) % 210 0x0F1 0x31E UP3[15:6] 0x000
11 0x2AA 0x3FF (x + 11) % 210 0x3DD 0x008 UP4[15:6] 0x000
Table 45. Scrambler 8-Bit Input (Register 0x0573, Bits[5:4] = 'b10)
8-Bit Octet
Number
Alternating
Checkerboard
1/0 Word
Toggle Ramp PN9 PN23 User Repeat User Single
0 0x55 0x00 (x) % 28 0x49 0xFF UP1[15:9] UP1[15:9]
1 0xAA 0xFF (x + 1) % 28 0x6F 0x5C UP2[15:9] UP2[15:9]
2 0x55 0x00 (x + 2) % 28 0xC9 0x00 UP3[15:9] UP3[15:9]
3 0xAA 0xFF (x + 3) % 28 0xA9 0x29 UP4[15:9] UP4[15:9]
4 0x55 0x00 (x + 4) % 28 0x98 0xB8 UP1[15:9] 0x00
5 0xAA 0xFF (x + 5) % 28 0x0C 0x0A UP2[15:9] 0x00
6 0x55 0x00 (x + 6) % 28 0x65 0x3D UP3[15:9] 0x00
7 0xAA 0xFF (x + 7) % 28 0x1A 0x72 UP4[15:9] 0x00
8 0x55 0x00 (x + 8) % 28 0x5F 0x9B UP1[15:9] 0x00
9 0xAA 0xFF (x + 9) % 28 0xD1 0x26 UP2[15:9] 0x00
10 0x55 0x00 (x + 10) % 28 0x63 0x43 UP3[15:9] 0x00
11 0xAA 0xFF (x + 11) % 28 0xAC 0xFF UP4[15:9] 0x00
Data Link Layer Test Modes
The data link layer test modes are implemented in the AD9695
as defined by Section 5.3.3.8.2 in the JEDEC JESD204B
specification. These tests are shown in Register 0x0574,
Bits[2:0]. Test patterns inserted at this point are useful for
verifying the functionality of the data link layer. When the data
link layer test modes are enabled, disable SYNCINB± by
writing 0xC0 to Register 0x0572.
AD9695 Data Sheet
Rev. C | Page 94 of 136
SERIAL PORT INTERFACE (SPI)
The AD9695 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the Serial Control Interface Standard (Rev. 1.0).
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD9695 ADC: the SCLK pin,
the SDIO pin, and the CSB pin (see Table 46). The SCLK (serial
clock) pin is used to synchronize the read and write data
presented to and from the ADC. The SDIO (serial data input/
output) pin is a dual-purpose pin that allows data to be sent and
read from the internal ADC memory map registers. The CSB
(chip select bar) pin is an active low control that enables or
disables the read and write cycles.
Table 46. Serial Port Interface Pins
Pin Function
SCLK Serial clock. The serial shift clock input that is used to
synchronize serial interface, reads, and writes.
SDIO
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
CSB Chip select bar. An active low control that gates the read
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 4 and
Table 6.
Other modes involving the CSB pin are available. The CSB pin
can be held low indefinitely, which permanently enables the
device; this is called streaming. The CSB can stall high between
bytes to allow additional external timing. When CSB is tied
high, SPI functions are placed in a high impedance mode. This
mode turns on any SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
command is issued, which allows the SDIO pin to change
direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the SDIO
pin to change direction from an input to an output at the
appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB first
is the default on power-up and can be changed via the SPI port
configuration register. For more information about this and
other features, see the Serial Control Interface Standard (Rev.
1.0).
HARDWARE INTERFACE
The pins described in Table 46 comprise the physical interface
between the user programming device and the serial port of the
AD9695. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is
used for other devices, it may be necessary to provide buffers
between this bus and the AD9695 to prevent these signals from
transitioning at the converter inputs during critical sampling
periods.
SPI ACCESSIBLE FEATURES
Table 47 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the Serial Control Interface Standard (Rev. 1.0). The AD9695
device specific features are described in the Memory Map section.
Table 47. Features Accessible Using the SPI
Feature Name Description
Mode Allows the user to set either power-down mode or standby mode.
Clock Allows the user to access the clock divider via the SPI.
DDC Allows the user to set up decimation filters for different applications.
Test Input/Output Allows the user to set test modes to have known data on output bits.
Output Mode Allows the user to set up outputs.
SERDES Output Setup Allows the user to vary SERDES settings such as swing and emphasis.
Data Sheet AD9695
Rev. C | Page 95 of 136
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit
locations. The memory map is divided into the following
sections:
• Analog Devices SPI registers (Register 0x0000 to
Register 0x000F)
• Clock/SYSREF/chip power-down pin control registers
(Register 0x003F to Register 0x0201)
• Fast detect and signal monitor control registers
(Register 0x0245 to Register 0x027A)
• DDC function registers (Register 0x0300 to
Register 0x03CD)
• Digital outputs and test modes registers (Register 0x0550 to
Register 0x05CB)
• Programmable filter control and coefficients registers
(Register 0x0DF8 to Register 0x0F7F)
• VREF/analog input control registers (Register 0x18A6 to
Register 0x1A4D)
Table 48 (see the Memory Map Registers section) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x0561, the
output sample mode register, has a hexadecimal default value
of 0x01, which means that Bit 0 = 1, and the remaining bits are
0s. This setting is the default output format value, which is twos
complement. For more information on this function and
others, see Table 48.
Open and Reserved Locations
All address and bit locations that are not included in Table 48
are not currently supported for this device. Write unused bits
of a valid address location with 0s unless the default value is
set otherwise. Writing to these locations is required only when
part of an address location is unassigned (for example,
Address 0x0561). If the entire address location is open (for
example, Address 0x0013), do not write to this address location.
Default Values
After the AD9695 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 48.
Logic Levels
An explanation of logic level terminology follows:
• “Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
• X denotes a don’t care bit.
Channel Specific Registers
Some channel setup functions, such as the input buffer control
register (Register 0x1A4C), can be programmed to a different
value for each channel. In these cases, channel address locations
are internally duplicated for each channel. These registers and
bits are designated in Table 48 as local. These local registers and
bits can be accessed by setting the appropriate Channel A or
Channel B bits in Register 0x0008. If both bits are set, the
subsequent write affects the registers of both channels. In a read
cycle, set only Channel A or Channel B to read one of the two
registers. If both bits are set during an SPI read cycle, the device
returns the value for Channel A. Registers and bits designated as
global in Table 48 affect the entire device and the channel
features for which independent settings are not allowed
between channels. The settings in Register 0x0005 do not affect
the global registers and bits.
SPI Soft Reset
After issuing a soft reset by programming 0x81 to Register 0x0000,
the AD9695 requires 5 ms to recover. When programming the
AD9695 for application setup, ensure that an adequate delay is
programmed into the firmware after asserting the soft reset and
before starting the device setup.
AD9695 Data Sheet
Rev. C | Page 96 of 136
MEMORY MAP REGISTERS
All address locations that are not included in Table 48 are not currently supported for this device and must not be written.
Table 48. Memory Map Registers
Address Name Bits Bit Name Settings Description Reset Access
Analog Devices SPI Registers
0x0000 SPI
Configuration A
7 Soft reset mirror (self
clearing)
Whenever a soft reset is issued, the
user must wait 5 ms before writing to
any other register; this provides
sufficient time for the boot loader to
complete.
0x0 R/WC
0 Do nothing.
1 Reset the SPI and registers (self
clearing).
6 LSB first mirror 1 Least significant bit shifted first for all
SPI operations.
0x0 R/W
0 Most significant bit shifted first for all
SPI operations.
5 Address ascension
mirror
0 Multibyte SPI operations cause
addresses to auto decrement.
0x0 R/W
1 Multibyte SPI operations cause
addresses to auto increment.
[4:3] Reserved Reserved. 0x0 R
2 Address ascension 0 Multibyte SPI operations cause
addresses to auto decrement.
0x0 R/W
1 Multibyte SPI operations cause
addresses to auto increment.
1 LSB first 1 Least significant bit shifted first for all
SPI operations.
0x0 R/W
0 Most significant bit shifted first for all
SPI operations.
0 Soft reset (self clearing) Whenever a soft reset is issued, the
user must wait 5 ms before writing to
any other register; this provides
sufficient time for the boot loader to
complete.
0x0 R/WC
0 Do nothing.
1 Reset the SPI and registers (self
clearing).
0x0001 SPI
Configuration B
[7:2] Reserved Reserved. 0x0 R
1 Datapath soft reset
(self clearing)
0 Normal operation. 0x0 R/WC
1 Datapath soft reset (self clearing).
0 Reserved Reserved. 0x0 R
0x0002 Chip
configuration
(local)
[7:2] Reserved Reserved. 0x0 R
[1:0] Channel power mode Channel power modes. 0x0 R/W
00 Normal mode (power-up).
10 Standby mode. Digital datapath
clocks disabled; JESD204B interface
enabled.
11 Power-down mode. Digital datapath
clocks disabled; digital datapath held
in reset; JESD204B interface disabled.
0x0003 Chip type [7:0] Chip type Chip type. 0x3 R
0x3 High speed ADC.
0x0004 Chip ID LSB [7:0] Chip ID LSB [7:0] Chip ID. R
0xDE AD9695.
0x0005 Chip ID MSB [7:0] Chip ID MSB [15:8] Chip ID. 0x0 R
Data Sheet AD9695
Rev. C | Page 97 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0006 Chip grade [7:4] Chip speed grade Chip speed grade. 0x0 R
0x00 1300 MSPS.
0x01 625 MSPS.
[3:0] Reserved Reserved. DNC R
0x0008 Device index [7:2] Reserved Reserved. 0x0 R
1 Channel B 0 ADC Core B does not receive the next
SPI command.
0x1 R/W
1
ADC Core B receives the next SPI
command.
0 Channel A 0 ADC Core A does not receive the next
SPI command.
0x1 R/W
1 ADC Core A receives the next SPI
command.
0x000A Scratch pad [7:0] Scratch pad Chip scratch pad register. This
register provides a consistent
memory location for software debug.
0x0 R/W
0x000B SPI revision [7:0] SPI revision SPI revision register. 0x1 R
0x01 Revision 1.0.
00000001 Revision 1.0.
0x000C Vendor ID LSB [7:0] Vendor ID [7:0]. 0x56 R
0x000D Vendor ID MSB [7:0] Vendor ID [15:8]. 0x04 R
0x000F Transfer [7:1] Reserved Reserved. 0x0 R
0 Chip transfer Self clearing chip transfer bit. This bit
is used to update the DDC phase
increment and phase offset registers
when the DDC phase update mode bit
(Register 0x0300, Bit 7) = 1. This setting
makes it possible to synchronously
update the DDC mixer frequencies. It
is also used to update the coefficients
for the programmable filter (PFILT).
0x0 R/W
0 Do nothing. This bit it is only cleared
after the transfer completes.
1 Self clearing bit used to synchronize
the transfer of data from master to
slave registers.
Clock/SYSREF/Chip Power-Down Pin Control Registers
0x003F Chip power-
down pin (local)
7 Local chip power-
down pin disable
Function is determined by
Register 0x0040, Bits[7:6].
0x0 R/W
0 Power-down pin (PDWN/STBY)
enabled (default).
1 Power-down pin (PDWN/STBY)
disabled/ignored.
[6:0] Reserved Reserved. 0x0 R
AD9695 Data Sheet
Rev. C | Page 98 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0040 Chip Pin Control 1 [7:6] Global chip power-
down pin functionality
External power-down pin functionality.
Assertion of the external power-down
pin (PDWN/STBY) has higher priority
than the channel power mode control
bits (Register 0x0002, Bits[1:0]). The
PDWN/STBY pin is only used when
Register 0x0040, Bits[7:6] = 00 or 01.
0x0 R/W
00 Power-down pin (default). Assertion
of the external power-down pin
(PDWN/STBY) causes the chip to
enter full power-down mode.
01 Standby pin. Assertion of the external
power-down pin (PDWN/STBY) causes
the chip to enter standby mode.
10 Pin disabled. Power-down pin
(PDWN/STBY) is ignored.
[5:3] Chip FD_B/GPIO_B0
pin functionality
Fast Detect B/GPIO B0 pin functionality. 0x7 R/W
000
Fast Detect B output.
001 JESD204B LMFC output.
110 Pin functionality determined by
Register 0x0041, Bits[7:4].
111 Disabled. Configured as input with
weak pull-down (default).
[2:0] Chip FD_A/GPIO_A0
pin functionality
Fast Detect A/GPIO A0 pin functionality. 0x7 R/W
000 Fast Detect A output.
001 JESD204B LMFC output.
110 Pin functionality determined by
Register 0x0041, Bits[3:0].
111 Disabled. Configured as input with
weak pull-down. (default)
0x0041 Chip Pin Control 2 [7:4] Chip FD_B/GPIO_B0
pin secondary
functionality
Fast Detect B/GPIO B0 pin secondary
functionality. Only used when
Register 0x0040, Bits[5:3] = 110.
0x0 R/W
0000 Chip GPIO B0 input (NCO channel
selection).
0001 Chip transfer input.
1000 Master next trigger output (MNTO).
1001 Slave next trigger input (SNTI).
[3:0] Chip FD_A/GPIO_A0
pin secondary
functionality
Fast Detect A/GPIO B0 pin secondary
functionality. Only used when
Register 0x0040, Bits[2:0] = 110.
0x0 R/W
0000 Chip GPIO A0 input (NCO channel
selection).
0001 Chip transfer input.
1000 Master next trigger output (MNTO).
1001 Slave next trigger input (SNTI).
Data Sheet AD9695
Rev. C | Page 99 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0042 Chip Pin Control 3 [7:4] Chip GPIO_B1 pin
functionality
GPIO_B1 pin functionality. 0x0 R/W
0000 Chip GPIO B1 input (NCO channel
selection).
1000 Master next trigger output (MNTO).
1001 Slave next trigger input (SNTI).
1111 Disabled (configured as an input with
a weak pull down).
[3:0] Chip GPIO_A1 pin
functionality
GPIO_A1 pin functionality. 0x0 R/W
0000 Chip GPIO A1 input (NCO channel
selection).
1000 Master next trigger output (MNTO).
1001 Slave next trigger input (SNTI).
1111 Disabled (configured as an input with
a weak pull down).
0x0108 Clock divider
control
[7:3] Reserved Reserved. 0x0 R
[2:0] Input clock divider
(CLK± pins)
00 Divide by 1. 0x0 R/W
01 Divide by 2.
11 Divide by 4.
0x0109 Clock divider
phase (local)
[7:4] Reserved Reserved. 0x0 R
[3:0] Clock divider phase
offset
0000 0 input clock cycles delayed. 0x0 R/W
0001 1/2 input clock cycles delayed (invert
clock).
0010 1 input clock cycles delayed.
…
1110 7 input clock cycles delayed.
1111 7 1/2 input clock cycles delayed.
0x010A Clock divider and
SYSREF control
7 Clock divider
autophase adjust
enable
Clock divider autophase adjust enable.
When enabled, Register 0x0129,
Bits[3:0] contain the phase of the
divider when SYSREF occurred. The
actual divider phase offset =
Register 0x0129, Bits[3:0] +
Register 0x0109, Bits[3:0].
0x0 R/W
0 Clock divider phase is not changed by
SYSREF± (disabled).
1
Clock divider phase is automatically
adjusted by SYSREF± (enabled).
[6:4] Reserved Reserved. 0x0 R
[3:2] Clock divider negative
skew window
Clock divider negative skew window
(measured in 1/2 input device clocks).
Number of 1/2 clock cycles before the
input device clock by which captured
SYSREF± transitions are ignored. Only
used when Register 0x010A, Bit 7 = 1.
Register 0x010A, Bits[3:2] +
Register 0x010A, Bits[1:0] <
Register 0x0108, Bits[2:0]; this allows
some uncertainty in the sampling of
SYSREF± without disturbing the input
clock divider. Also, SYSREF± must be
disabled (Register 0x0120, Bits[2:1] =
0x0) when changing this control field.
0x0 R/W
0 No negative skew. SYSREF± must be
captured accurately.
1 1/2 device clock of negative skew.
10 1 device clocks of negative skew.
11 1 1/2 device clocks of negative skew.
AD9695 Data Sheet
Rev. C | Page 100 of 136
Address Name Bits Bit Name Settings Description Reset Access
[1:0] Clock divider positive
skew window
Clock divider positive skew window
(measured in 1/2 input device clocks).
Number of clock cycles after the input
device clock by which captured
SYSREF± transitions are ignored. Only
used when Register 0x010A,
Bit 7 = 1. Register 0x010A, Bits[3:2] +
Register 0x010A, Bits[1:0] <
Register 0x0108, Bits[2:0]; this allows
some uncertainty in the sampling of
SYSREF± without disturbing the input
clock divider. Also, SYSREF± must be
disabled (Register 0x0120, Bits[2:1] =
0x0) when changing this control field.
0x0 R/W
0 No positive skew. SYSREF± must be
captured accurately.
1 1/2 device clock of positive skew.
10 1 device clocks of positive skew.
11 1 1/2 device clocks of positive skew.
0x010B Clock divider
SYSREF status
[7:4] Reserved Reserved 0x0 R
[3:0] Clock divider SYSREF±
offset
Clock divider phase status (measured in
1/2 clock cycles). Internal clock divider
phase of the captured SYSREF± signal
applied to the phase offset. Only used
when Register 0x010A, Bit 7 = 1.
When Register 0x010A, Bit 7 = 1,
Register 0x010A, Bits[3:2] = 0, and
Register 0x010A, Bits[1:0] = 0, clock
divider SYSREF± offset =
Register 0x0129, Bits[3:0].
0x0 R
0x0110 Clock delay
control
[7:3] Reserved Reserved. 0x0 R
[2:0] Clock delay mode
select
Clock delay mode select. Used in
conjunction with Register 0x0111 and
Register 0x0112.
0x0 R/W
000 No clock delay.
010 Fine delay. Only Delay Step 0 to Delay
Step 16 are valid.
011 Fine delay (lowest jitter). Only Delay
Step 0 to Delay Step 16 are valid.
100 Fine delay. All 192 delay steps valid.
110 Fine delay enabled (all 192 delay
steps valid). Super fine delay enabled
(all 128 delay steps valid).
0x0111 Clock super fine
delay (local)
[7:0] Clock super fine delay
adjust
Clock super fine delay adjust. This is
an unsigned control to adjust the
super fine sample clock delay in
0.25 ps steps. These bits are only used
when Register 0x0110, Bits[2:0] = 010
or 110.
0x0 R/W
0x00 = 0 delay steps.
…
0x08 = 8 delay steps.
…
0x80 = 128 delay steps.
Data Sheet AD9695
Rev. C | Page 101 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0112 Clock fine delay
(local)
[7:0] Set clock fine delay Clock fine delay adjust. This is an
unsigned control to adjust the fine
sample clock skew in 1.725 ps steps.
These bits are only used when
Register 0x0110, Bits[2:0] = 0x2, 0x3,
0x4, or 0x6.
0xC0 R/W
0x00 = 0 delay steps.
…
0x08 = 8 delay steps.
…
0xC0 = 192 delay steps.
Minimum = 0.
Maximum = 192.
Increment = 1.
Unit = delay steps.
0x0113 Digital clock
super fine delay
[7:0] Digital clock super fine
delay adjust
Digital clock super fine delay adjust.
This is an unsigned control to adjust
the super fine sample clock delay in
0.25ps steps. These bits are only used
when Register 0x0110, Bits[2:0] = 010
or 110.
0x0 R/W
0x00 = 0 delay steps.
…
0x08 = 8 delay steps.
…
0x80 = 128 delay steps.
0x0114 Digital clock fine
delay
[7:0] Set digital clock fine
delay
Digital clock fine delay adjust. This is
an unsigned control to adjust the fine
sample clock skew in 1.725 ps steps.
These bits are only used when
Register 0x0110, Bits[2:0] = 0x2, 0x3,
0x4 or 0x6.
0xC0 R/W
0x00 = 0 delay steps.
…
0x08 = 8 delay steps.
…
0xC0 = 192 delay steps.
Minimum = 0.
Maximum = 192.
Increment = 1.
Unit = delay steps.
0x011A Clock detection
control
[7:5] Reserved Reserved. 0x0 R/W
[4:3] Clock detection
threshold
Clock detection threshold. 0x1 R/W
01 Threshold 1 for sample rate ≥
300 MSPS.
11 Threshold 2 for sample rate <300 MSPS.
[2:0] Reserved Reserved 0x6 R/W
0x011B Clock status [7:1] Reserved Reserved. 0x0 R
0 Input clock detect Clock detection status. 0x0 R
0 Input clock not detected.
1 Input clock detected/locked.
AD9695 Data Sheet
Rev. C | Page 102 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x011C Clock Duty Cycle
Stabilizer 1
(DCS1) control
(local)
[7:2] Reserved Reserved 0x0 R/W
1 DCS1 enable Clock DCS1 enable. 0x1 R/W
0 DCS1 bypassed.
1 DCS1 enabled.
0 DCS1 power-up Clock DCS1 power-up. 0x1 R/W
0 DCS1 powered down.
1 DCS1 powered up.
0x011E
Clock Duty Cycle
Stabilizer 2
(DCS2) control
[7:2] Reserved Reserved. 0x0 R/W
1 DCS2 enable Clock DCS2 enable. 0x1 R/W
0 DCS2 bypassed.
1 DCS2 enabled.
0 DCS2 power-up Clock DCS2 power-up. 0x1 R/W
0 DCS2 powered down.
1 DCS2 powered up.
0x0120 SYSREF±
Control 1
7 Reserved Reserved. 0x0 R
6 SYSREF± flag reset 0 Normal flag operation. 0x0 R/W
1 SYSREF flags held in reset (setup/hold
error flags cleared).
5 Reserved Reserved. 0x0 R
4 SYSREF± transition
select
0 SYSREF is valid on low to high transi-
tions using the selected CLK± edge.
When changing this setting, SYSREF±
mode select must be set to disabled.
0x0 R/W
1 SYSREF is valid on high to low
transitions using the selected CLK±
edge. When changing this setting,
SYSREF± mode select must be set to
disabled.
3 CLK± edge select 0 Captured on rising edge of CLK± input. 0x0 R/W
1 Captured on falling edge of CLK± input.
[2:1] SYSREF± mode select 0 Disabled. 0x0 R/W
1 Continuous.
10 N-shot.
0 Reserved Reserved. 0x0 R
0x0121 SYSREF±
Control 2
[7:4] Reserved Reserved. 0x0 R
[3:0] SYSREF± N-shot
ignore counter select
0000 Next SYSREF only (do not ignore). 0x0 R/W
0001 Ignore the first SYSREF± transition.
0010 Ignore the first two SYSREF± transitions.
0011 Ignore the first three SYSREF±
transitions.
…
1110 Ignore the first 14 SYSREF± transitions.
1111 Ignore the first 15 SYSREF± transitions.
Data Sheet AD9695
Rev. C | Page 103 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0122 SYSREF±
Control 3
[7:4] Reserved Reserved 0x0 R
[3:2] SYSREF± window
negative
Negative skew window (measured in
sample clocks). Number of clock cycles
before the sample clock by which
captured SYSREF± transitions are
ignored.
0x0 R/W
00 No negative skew. SYSREF± must be
captured accurately.
01 One sample clock of negative skew.
10 Two sample clocks of negative skew.
11 Three sample clocks of negative
skew.
[1:0] SYSREF± window
negative
Positive skew window (measured in
sample clocks). Number of clock
cycles before the sample clock by
which captured SYSREF± transitions
are ignored.
0x0 R/W
00 No positive skew. SYSREF± must be
captured accurately.
01 One sample clock of positive skew.
10
Two sample clocks of positive skew.
11 Three sample clocks of positive skew.
0x0123 SYSREF Control 4 7 Reserved Reserved. 0x0 R
[6:0] SYSREF± timestamp
delay
SYSREF± timestamp delay (in
converter sample clock cycles).
0x40 R/W
0: 0 sample clock cycle delay.
1: 1 sample clock cycle delay.
…
127: 127 sample clock cycle delay.
0x0128 SYSREF Status 1 [7:4] SYSREF± hold status SYSREF± hold status. 0x0 R
[3:0] SYSREF± setup status SYSREF± setup status. 0x0 R
0x0129 SYSREF Status 2 [7:4] Reserved Reserved. 0x0 R
[3:0] Clock divider phase
when SYSREF± is
captured
SYSREF divider phase. These bits
represent the phase of the divider
when SYSREF± is captured.
0x0 R
0000 = in phase.
0001 = SYSREF± is ½ cycle delayed
from clock.
0010 = SYSREF± is 1 cycle delayed
from clock.
0011 = 1½ input clock cycles delayed.
0100 = 2 input clock cycles delayed.
0101 = 2½ input clock cycles delayed.
…
1111 = 7½ input clock cycles delayed.
0x012A SYSREF Status 3 [7:0] SYSREF± counter,
Bits[7:0] increments
when a SYSREF± is
captured
SYSREF± count. Running counter that
increments whenever a SYSREF event
is captured. Reset by Register 0x0120,
Bit 6. Wraps around at 255. Only read
these bits while Register 0x0120,
Bits[2:1] are set to disabled.
0x0 R
AD9695 Data Sheet
Rev. C | Page 104 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x01FF Chip sync mode [7:1] Reserved Reserved. 0x0 R
0 Synchronization mode 0x0 JESD204B synchronization mode. The
SYSREF± signal resets all internal
clock dividers. Use this mode when
synchronizing multiple chips as
specified in the JESD204B standard. If
the phase of any of the dividers must
change, the JESD204B link goes down.
0x0 R/W
0x1 Timestamp mode. The SYSREF±
signal does not reset the internal
clock dividers. In this mode, the
JESD204B link and the signal monitor
are not affected by the SYSREF±
signal. The SYSREF± signal simply
time stamps a sample as it passes
through the ADC and is used as a
control bit in the JESD204B output
word.
Chip Operating Mode Control Registers
0x0200 Chip mode [7:6] Reserved Reserved. 0x0 R/W
5 Chip Q ignore Chip real (I) only selection. 0x0 R/W
0 Both real (I) and complex (Q) selected.
1 Only real (I) selected. Complex (Q) is
ignored.
4 Reserved Reserved. 0x0 R
[3:0] Chip application mode 0000 Full bandwidth mode (default). 0x0 R/W
0001 One DDC mode (DDC 0 only).
0010 Two DDC mode (DDC 0 and DDC 1
only).
0011 Four DDC mode (DDC 0, DDC 1, DDC 2,
and DDC 3).
0x0201 Chip decimation
ratio
[7:4] Reserved Reserved. 0x0 R
[3:0] Chip decimation ratio Chip decimation ratio. 0x0 R/W
0000 Full sample rate (decimate by 1, DDCs
are bypassed).
0001 Decimate by 2.
1000 Decimate by 3.
0010 Decimate by 4.
0101 Decimate by 5.
1001 Decimate by 6.
0011 Decimate by 8.
0110 Decimate by 10.
1010 Decimate by 12.
0111 Decimate by 15.
0100 Decimate by 16.
1101 Decimate by 20.
1011 Decimate by 24.
1110 Decimate by 30.
1111 Decimate by 40.
1100 Decimate by 48.
Data Sheet AD9695
Rev. C | Page 105 of 136
Address Name Bits Bit Name Settings Description Reset Access
Fast Detect and Signal Monitor Control Registers
0x0245 Fast detect
control (local)
[7:4] Reserved Reserved. 0x0 R
3 Force FD A/FD B pins 0 Normal operation of fast detect pin. 0x0 R/W
1 Force a value on fast detect pin (see
Bit 2 in this register).
2 Force value of
FD_A/FD_B pins
The fast detect output pin for this
channel is set to this value when the
output is forced.
0x0 R/W
1 Reserved Reserved. 0x0 R
0 Enable fast detect
output
0 Fast detect disabled. 0x0 R/W
1 Fast detect enabled.
0x0247 Fast detect
upper LSB (local)
[7:0] Fast detect upper
threshold
LSBs of fast detect upper threshold.
Eight LSBs of the programmable
13-bit upper threshold compared to
the fine ADC magnitude
0x0 R/W
0x0248 Fast detect upper
MSB (local)
[7:5] Reserved Reserved. 0x0 R
[4:0] Fast detect upper
threshold
LSBs of fast detect upper threshold.
Eight LSBs of the programmable 13-bit
upper threshold compared to the fine
ADC magnitude.
0x0 R/W
0x0249 Fast detect low
LSB (local)
[7:0] Fast detect lower
threshold
LSBs of the fast detect lower threshold.
Eight LSBs of the programmable 13-bit
lower threshold compared to the fine
ADC magnitude.
0x0 R/W
0x024A Fast detect low
MSB (local)
[7:5] Reserved Reserved. 0x0 R
[4:0] Fast detect lower
threshold
LSBs of fast detect lower threshold.
Eight LSBs of the programmable 13-bit
lower threshold compared to the fine
ADC magnitude.
0x0 R/W
0x024B Fast detect dwell
LSB (local)
[7:0] Fast detect dwell time LSBs of fast detect dwell time counter
target. This is a load value for a 16-bit
counter that determines how long
the ADC data must remain below the
lower threshold before the FD_x pins
are reset to 0.
0x0 R/W
0x024C
Fast detect dwell
MSB (local)
[7:0] Fast detect dwell time
LSBs of fast detect dwell time counter
target. This is a load value for a 16-bit
counter that determines how long
the ADC data must remain below the
lower threshold before the FD_x pins
are reset to 0.
0x0 R/W
0x026F Signal monitor
sync control
[7:2] Reserved Reserved. 0x0 R
1 Signal monitor next
synchronization mode
Signal monitor next synchronization
mode.
0x0 R/W
0 Continuous mode.
1 Next synchronization mode. Only the
next valid edge of SYSREF± pin
synchronizes the signal monitor
block. Subsequent edges of the
SYSREF± pin are ignored. After the
next SYSREF is found, Register 0x026F,
Bit 0 is cleared. The SYSREF± pin must
be an integer multiple of the signal
monitor period for this function to
operate correctly in continuous mode.
AD9695 Data Sheet
Rev. C | Page 106 of 136
Address Name Bits Bit Name Settings Description Reset Access
0 Signal monitor
synchronization mode
Signal monitor synchronization enable. 0x0 R/W
0 Synchronization disabled.
1 If Register 0x026F, Bit 1 = 1, only the
next valid edge of the SYSREF± pin is
used to synchronize the signal
monitor block. Subsequent edges of
the SYSREF± pin are ignored. After
the next SYSREF± is received, this bit
is cleared. The SYSREF± input pin
must be enabled to synchronize the
signal monitor blocks.
0x0270 Signal monitor
control (local)
[7:2] Reserved Reserved. 0x0 R
1 Peak detector 0 Peak detector disabled. 0x0 R/W
1 Peak detector enabled.
0 Reserved Reserved. 0x0 R
0x0271 Signal Monitor
Period 0 (local)
[7:0] Signal monitor period
[7:0]
This 24-bit value sets the number of
output clock cycles over which the
signal monitor performs its operation.
Only even values are supported.
0x80 R/W
0x0272 Signal Monitor
Period 1 (local)
[7:0] Signal monitor period
[15:8]
0x0 R/W
0x0273 Signal Monitor
Period 2 (local)
[7:0] Signal monitor period
[23:16]
0x0 R/W
0x0274 Signal monitor
status control
(local)
[7:5] Reserved Reserved. 0x0 R
4 Result update 1 Update signal monitor status,
Register 0x0275 to Register 0x0278.
Self clearing.
0x0 R/WC
3 Reserved Reserved. 0x0 R
[2:0] Result selection 001 Peak detector placed on status
readback signals.
0x1 R/W
0x0275 Signal Monitor
Status 0 (local)
[7:0] Signal monitor result
[7:0]
Signal monitor status result. This 20-bit
value contains the status result
calculated by the signal monitor block.
0x0 R
0x0276 Signal Monitor
Status 1 (local)
[7:0] Signal monitor result
[15:8]
Signal monitor status result. 0x0 R
0x0277
Signal Monitor
Status 2 (local)
[7:4] Reserved Reserved. 0x0 R
[3:0] Signal monitor result
[19:16]
Signal monitor status result. 0x0 R
0x0278 Signal monitor
status frame
counter (local)
[7:0] Period count result Signal monitor frame counter status
bits. The frame counter increments
whenever the period counter expires.
0x0 R
0x0279 Signal monitor
serial framer
control (local)
[7:2] Reserved Reserved. 0x0 R
[1:0] Signal monitor SPORT
over JESD204B enable
00 Disabled. 0x0 R/W
11 Enabled.
0x027A SPORT over
JESD204B input
selection (local)
[7:6] Reserved Reserved. 0x0 R
1 SPORT over JESD204B
input selection
Signal monitor serial framer input
selection. When each individual bit is
a 1, the corresponding signal statistics
information is sent within the frame.
0x1 R/W
0 Disabled.
1 Peak detector data inserted in serial
frame.
0 Reserved Reserved 0x0 R
Data Sheet AD9695
Rev. C | Page 107 of 136
Address Name Bits Bit Name Settings Description Reset Access
DDC Function Registers (See the Digital Downconverter (DDC) Section)
0x0300 DDC sync control 7 DDC FTW/POW/MAW/
MBW update mode
Select DDC FTW/POW/MAW/MBW
update mode.
0x0 R/W
0 Instantaneous/continuous update.
The FTW/POW/MAW/MBW values are
updated immediately.
1 The FTW/POW/MAW/MBW values are
updated synchronously when the
chip transfer bit (Register 0x000F,
Bit 0) is set.
[6:5] Reserved Reserved. 0x0 R
4 DDC NCO soft reset This bit can be used to synchronize all
the NCOs inside the DDC blocks.
0x0 R/W
0 Normal operation.
1 DDC held in reset.
[3:2] Reserved Reserved. 0x0 R
1 DDC next sync 0 Continuous mode. The SYSREF±
frequency must be an integer
multiple of the NCO frequency for
this function to operate correctly in
continuous mode.
0x0 R/W
1 Only the next valid edge of the
SYSREF± pin is used to synchronize the
NCO in the DDC block. Subsequent
edges of the SYSREF± pin are ignored.
After the next SYSREF is found, the
DDC synchronization enable bit
(Register 0x0300, Bit 0) is cleared.
0 DDC synchronization
mode
The SYSREF± input pin must be
enabled to synchronize the DDCs.
0x0 R/W
0 Synchronization disabled.
1 If the DDC next sync bit
(Register 0x0300, Bit 1) = 1, only the
next valid edge of the SYSREF± pin is
used to synchronize the NCO in the
DDC block. Subsequent edges of the
SYSREF± pin are ignored. After the next
SYSREF± is received, this bit is cleared.
0x0310 DDC 0 control 7 DDC 0 mixer select 0 Real mixer (I and Q inputs must be
from the same real channel).
0x0 R/W
1 Complex mixer (I and Q must be from
separate, real and imaginary
quadrature ADC receive channels;
analog demodulator).
6 DDC 0 gain select Gain can be used to compensate for the
6 dB loss associated with mixing an
input signal down to baseband and
filtering out its negative component.
0x0 R/W
0 0 dB gain.
1 6 dB gain (multiply by 2).
AD9695 Data Sheet
Rev. C | Page 108 of 136
Address Name Bits Bit Name Settings Description Reset Access
[5:4] DDC 0 intermediate
frequency (IF) mode
00 Variable IF mode. 0x0 R/W
01 0 Hz IF mode.
10 fS/4 Hz IF mode.
11 Test mode.
3 DDC 0 complex to real
enable
0 Complex (I and Q) outputs contain
valid data.
0x0 R/W
1 Real (I) output only. Complex to real
enabled. Uses extra fS/4 mixing to
convert to real.
[2:0] DDC 0 decimation rate
select
Decimation filter selection. 0x0 R/W
000
HB1 + HB2 filter selection: decimate
by 2 (complex to real enabled), or
decimate by 4 (complex to real
disabled).
001 HB1 + HB2 + HB3 filter selection:
decimate by 4 (complex to real
enabled), or decimate by 8 (complex
to real disabled).
010 HB1 + HB2 + HB3 + HB4 filter
selection: decimate by 8 (complex to
real enabled), or decimate by 16
(complex to real disabled).
011 HB1 filter selection: decimate by 1
(complex to real enabled), or
decimate by 2 (complex to real
disabled).
100 HB1 + TB2 filter selection: decimate
by 3 (complex to real enabled), or
decimate by 6 (complex to real
disabled).
101 HB1 + HB2 + TB2 filter selection:
decimate by 6 (complex to real
enabled), or decimate by 12 (complex
to real disabled).
110 HB1 + HB2 + HB3 + TB2 filter
selection: decimate by 12 (complex to
real enabled), or decimate by 24
(complex to real disabled).
111 Decimation determined by
Register 0x0311, Bits[7:4].
0x0311 DDC 0 input
select
[7:4] DDC 0 decimation rate
select
Only valid when Register 0x0310,
Bits[2:0] = 3'b111.
0x0 R/W
0 TB2 + HB4 + HB3 + HB2 + HB1 filter
selection: decimate by 48 (complex to
real disabled), or decimate by 24
(complex to real enabled).
10 FB2 + HB1 filter selection: decimate by
10 (complex to real disabled) or
decimate by 5 (complex to real
enabled).
11 FB2 + HB2 + HB1 filter selection:
decimate by 20 (complex to real
disabled), or decimate by 10
(complex to real enabled).
100 FB2 + HB3 + HB2 + HB1 filter
selection: decimate by 40 (complex to
real disabled), or decimate by 20
(complex to real enabled).
Data Sheet AD9695
Rev. C | Page 109 of 136
Address Name Bits Bit Name Settings Description Reset Access
111
TB1 filter selection: decimate by 3
(decimate by 1.5 not supported).
1000
FB2 + TB1 filter selection: decimate
by 15 (decimate by 7.5 not
supported).
1001
HB2 + FB2 + TB1 filter selection:
decimate by 30 (decimate by 15 not
supported).
3 Reserved Reserved. 0x0 R
2 DDC 0 Q input select 0 Channel A. 0x0 R/W
1 Channel B.
1 Reserved Reserved. 0x0 R
0 DDC 0 I input select 0 Channel A. 0x0 R/W
1 Channel B.
0x0314 DDC 0 NCO
control
[7:4] DDC 0 NCO channel
select mode
For edge control, the internal counter
wraps after the Register 0x0314,
Bits[3:0] value is reached.
0x0 R/W
0 Use Register 0x0314, Bits[3:0].
1 2'b0, GPIO B0, GPIO A0.
1000
Increment internal counter on rising
edge of the GPIO A0 pin.
1010
Increment internal counter on rising
edge of the GPIO B0 pin.
[3:0]
DDC 0 NCO register
map channel select
NCO channel select register map
control.
0x0 R/W
0 Select NCO Channel 0.
1 Select NCO Channel 1.
10 Select NCO Channel 2.
11 Select NCO Channel 3.
100 Select NCO Channel 4.
101 Select NCO Channel 5.
110 Select NCO Channel 6.
111 Select NCO Channel 7.
1000 Select NCO Channel 8.
1001 Select NCO Channel 9.
1010 Select NCO Channel 10.
1011 Select NCO Channel 11.
1100 Select NCO Channel 12.
1101 Select NCO Channel 13.
1110 Select NCO Channel 14.
1111 Select NCO Channel 15.
0x0315 DDC 0 phase
control
[7:4] Reserved Reserved. 0x0 R
[3:0]
DDC 0 phase update
index
Indexes the NCO channel whose
phase and offset are updated. The
update method is based on the DDC
phase update mode, which may be
continuous or require chip transfer.
0x0 R/W
0000 Update NCO Channel 0.
0001 Update NCO Channel 1.
0010 Update NCO Channel 2.
0011 Update NCO Channel 3.
0100 Update NCO Channel 4.
0101 Update NCO Channel 5.
0110 Update NCO Channel 6.
0111 Update NCO Channel 7.
AD9695 Data Sheet
Rev. C | Page 110 of 136
Address Name Bits Bit Name Settings Description Reset Access
1000 Update NCO Channel 8.
1001 Update NCO Channel 9.
1010 Update NCO Channel 10.
1011 Update NCO Channel 11.
1100 Update NCO Channel 12.
1101 Update NCO Channel 13.
1110 Update NCO Channel 14.
1111 Update NCO Channel 15.
0x0316 DDC 0 Phase
Increment 0
[7:0] DDC 0 phase
increment [7:0]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0317 DDC 0 Phase
Increment 1
[7:0] DDC 0 phase
increment [15:8]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0318 DDC 0 Phase
Increment 2
[7:0] DDC 0 phase
increment [23:16]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0319 DDC 0 Phase
Increment 3
[7:0] DDC 0 phase
increment [31:24]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x031A DDC 0 Phase
Increment 4
[7:0] DDC 0 phase
increment [39:32]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x031B DDC 0 Phase
Increment 5
[7:0] DDC 0 phase
increment [47:40]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x031D DDC 0 Phase
Offset 0
[7:0] DDC 0 phase offset
[7:0]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x031E DDC 0 Phase
Offset 1
[7:0] DDC 0 phase offset
[15:8]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x031F DDC 0 Phase
Offset 2
[7:0] DDC 0 phase offset
[23:16]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0320 DDC 0 Phase
Offset 3
[7:0] DDC 0 phase offset
[31:24]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0321 DDC 0 Phase
Offset 4
[7:0] DDC 0 phase offset
[39:32]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0322 DDC 0 Phase
Offset 5
[7:0] DDC 0 phase offset
[47:40]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0327 DDC 0 test enable [7:3] Reserved Reserved. 0x0 R
2
DDC 0 Q output test
mode enable
Q samples always use the Test Mode B
block. The test mode is selected using
the channel dependent bits
(Register 0x0550, Bits[3:0]).
0x0 R/W
0 Test mode disabled.
1 Test mode enabled.
1 Reserved Reserved. 0x0 R
0
DDC 0 I output test
mode enable
I samples always use the Test Mode A
block. The test mode is selected using
the channel dependent bits
(Register 0x0550, Bits[3:0]).
0x0 R/W
0 Test mode disabled.
1 Test mode enabled.
Data Sheet AD9695
Rev. C | Page 111 of 136
Address Name Bits Bit Name Settings Description Reset Access
1 Test mode enabled.
0x0330 DDC 1 control 7 DDC 1 mixer select 0 Real mixer (I and Q inputs must be
from the same real channel).
0x0 R/W
1 Complex mixer (I and Q must be from
separate, real and imaginary
quadrature ADC receive channels;
analog demodulator).
6 DDC 1 gain select Gain can be used to compensate for the
6 dB loss associated with mixing an
input signal down to baseband and
filtering out its negative component.
0x0 R/W
0 0 dB gain.
1 6 dB gain (multiply by 2).
[5:4] DDC 1 intermediate
frequency (IF) mode
00 Variable IF mode. 0x0 R/W
01 0 Hz IF mode.
10 fS/4 Hz IF mode.
11 Test mode.
3 DDC 1 Complex to real
enable
0 Complex (I and Q) outputs contain
valid data.
0x0 R/W
1 Real (I) output only. Complex to real
enabled. Uses extra fS/4 mixing to
convert to real.
[2:0] DDC 1 decimation rate
select
Decimation filter selection. 0x0 R/W
000 HB1 + HB2 filter selection: decimate
by 2 (complex to real enabled), or
decimate by 4 (complex to real
disabled).
001 HB1 + HB2 + HB3 filter selection:
decimate by 4 (complex to real
enabled), or decimate by 8 (complex
to real disabled).
010 HB1 + HB2 + HB3 + HB4 filter
selection: decimate by 8 (complex to
real enabled), or decimate by 16
(complex to real disabled).
011 HB1 filter selection: decimate by 1
(complex to real enabled), or
decimate by 2 (complex to real
disabled).
100 HB1 + TB2 filter selection: decimate
by 3 (complex to real enabled), or
decimate by 6 (complex to real
disabled).
101 HB1 + HB2 + TB2 filter selection:
decimate by 6 (complex to real
enabled), or decimate by 12 (complex
to real disabled).
110 HB1 + HB2 + HB3 + TB2 filter
selection: decimate by 12 (complex to
real enabled), or decimate by 24
(complex to real disabled).
111 Decimation determined by
Register 0x0331, Bits[7:4].
AD9695 Data Sheet
Rev. C | Page 112 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0331 DDC 1 input
select
[7:4] DDC 1 decimation rate
select
Only valid when Register 0x0310,
Bits[2:0] = 3'b111.
0x0 R/W
0 TB2 + HB4 + HB3 + HB2 + HB1 filter
selection: decimate by 48 (complex to
real disabled), or decimate by 24
(complex to real enabled).
10 FB2 + HB1 filter selection: decimate by
10 (complex to real disabled), or deci-
mate by 5 (complex to real enabled).
11 FB2 + HB2 + HB1 filter selection:
decimate by 20 (complex to real
disabled), or decimate by 10
(complex to real enabled).
100 FB2 + HB3 + HB2 + HB1 filter
selection: decimate by 40 (complex to
real disabled), or decimate by 20
(complex to real enabled).
111 TB1 filter selection: decimate by 3
(decimate by 1.5 not supported).
1000 FB2 + TB1 filter selection: decimate
by 15 (decimate by 7.5 not
supported).
1001 HB2 + FB2 + TB1 filter select: decimate
by 30 (decimate by 15 not supported).
3 Reserved Reserved. 0x0 R
2 DDC 1 Q input select 0 Channel A. 0x1 R/W
1 Channel B.
1 Reserved Reserved. 0x0 R
0 DDC 1 I input select 0 Channel A. 0x1 R/W
1 Channel B.
0x0334 DDC 1 NCO
control
[7:4] DDC 1 NCO channel
select mode
For edge control, the internal counter
wraps after the Register 0x0334,
Bits[3:0] value is reached.
0x0 R/W
0 Use Register 0x0314, Bits[3:0].
1 2'b0, GPIO B0, GPIO A0.
1000
Increment internal counter when
rising edge of the GPIO A0 pin.
1010 Increment internal counter when
rising edge of the GPIO B0 pin.
[3:0] DDC 1 NCO register
map channel select
NCO channel select register map
control.
0x0 R/W
0 Select NCO Channel 0.
1 Select NCO Channel 1.
10 Select NCO Channel 2.
11 Select NCO Channel 3.
100 Select NCO Channel 4.
101 Select NCO Channel 5.
110 Select NCO Channel 6.
111 Select NCO Channel 7.
1000 Select NCO Channel 8.
1001 Select NCO Channel 9.
1010 Select NCO Channel 10.
1011 Select NCO Channel 11.
1100 Select NCO Channel 12.
1101 Select NCO Channel 13.
1110 Select NCO Channel 14.
Data Sheet AD9695
Rev. C | Page 113 of 136
Address Name Bits Bit Name Settings Description Reset Access
1111 Select NCO Channel 15.
0x0335 DDC 1 phase
control
[7:4] Reserved Reserved. 0x0 R
[3:0] DDC 1 phase update
index
Indexes the NCO channel whose
phase and offset are updated. The
update method is based on the DDC
phase update mode, which may be
continuous or require chip transfer.
0x0 R/W
0000 Update NCO Channel 0.
0001 Update NCO Channel 1.
0010 Update NCO Channel 2.
0011 Update NCO Channel 3.
0100 Update NCO Channel 4.
0101 Update NCO Channel 5.
0110 Update NCO Channel 6.
0111 Update NCO Channel 7.
1000 Update NCO Channel 8.
1001 Update NCO Channel 9.
1010 Update NCO Channel 10.
1011 Update NCO Channel 11.
1100 Update NCO Channel 12.
1101 Update NCO Channel 13.
1110 Update NCO Channel 14.
1111 Update NCO Channel 15.
0x0336 DDC 1 Phase
Increment 0
[7:0] DDC 1 phase
increment [7:0]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0337 DDC 1 Phase
Increment 1
[7:0] DDC 1 phase
increment [15:8]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0338 DDC 1 Phase
Increment 2
[7:0] DDC 1 phase
increment [23:16]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0339 DDC 1 Phase
Increment 3
[7:0] DDC 1 phase
increment [31:24]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x033A DDC 1 Phase
Increment 4
[7:0] DDC 1 phase
increment [39:32]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x033B DDC 1 Phase
Increment 5
[7:0] DDC 1 phase
increment [47:40]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x033D DDC 1 Phase
Offset 0
[7:0] DDC 1 phase offset
[7:0]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x033E DDC 1 Phase
Offset 1
[7:0] DDC 1 phase offset
[15:8]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x033F DDC 1 Phase
Offset 2
[7:0] DDC 1 phase offset
[23:16]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0340 DDC 1 Phase
Offset 3
[7:0] DDC 1 phase offset
[31:24]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0341 DDC 1 Phase
Offset 4
[7:0] DDC 1 phase offset
[39:32]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
AD9695 Data Sheet
Rev. C | Page 114 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0342 DDC 1 Phase
Offset 5
[7:0] DDC 1 phase offset
[47:40]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0347 DDC 1 test enable [7:3] Reserved Reserved. 0x0 R
2 DDC 1 Q output test
mode enable
Q Samples always use the Test Mode B
block. The test mode is selected using
the channel dependent bits,
Register 0x0550, Bits[3:0].
0x0 R/W
0 Test mode disabled.
1 Test mode enabled.
1 Reserved Reserved. 0x0 R
0 DDC 1 I output test
mode enable
I samples always use the Test Mode A
block. The test mode is selected using
the channel dependent bits,
Register 0x0550, Bits[3:0] bits.
0x0 R/W
0 Test mode disabled.
1 Test mode enabled.
0x0350 DDC 2 control 7 DDC 2 mixer select 0 Real mixer (I and Q inputs must be
from the same real channel).
0x0 R/W
1
Complex mixer (I and Q must be from
separate, real and imaginary
quadrature ADC receive channels;
analog demodulator).
6 DDC 2 gain select Gain can be used to compensate for the
6 dB loss associated with mixing an
input signal down to baseband and
filtering out its negative component.
0x0 R/W
0 0 dB gain.
1 6 dB gain (multiply by 2).
[5:4] DDC 2 intermediate
frequency (IF) mode
00 Variable IF mode. 0x0 R/W
01 0 Hz IF mode.
10 fS/4 Hz IF mode.
11 Test mode.
3 DDC 2 complex to real
enable
0 Complex (I and Q) outputs contain
valid data.
0x0 R/W
1 Real (I) output only. Complex to real
enabled. Uses extra fS/4 mixing to
convert to real.
[2:0] DDC 2 decimation rate
select
Decimation filter selection. 0x0 R/W
000 HB1 + HB2 filter selection: decimate
by 2 (complex to real enabled), or
decimate by 4 (complex to real
disabled).
001 HB1 + HB2 + HB3 filter selection:
decimate by 4 (complex to real
enabled), or decimate by 8 (complex
to real disabled).
010 HB1 + HB2 + HB3 + HB4 filter
selection: decimate by 8 (complex to
real enabled), or decimate by 16
(complex to real disabled).
011 HB1 filter selection: decimate by 1
(complex to real enabled), or
decimate by 2 (complex to real
disabled).
100 HB1 + TB2 filter selection: decimate
by 3 (complex to real enabled), or
decimate by 6 (complex to real
disabled).
Data Sheet AD9695
Rev. C | Page 115 of 136
Address Name Bits Bit Name Settings Description Reset Access
101 HB1 + HB2 + TB2 filter selection:
decimate by 6 (complex to real
enabled), or decimate by 12 (complex
to real disabled).
110
HB1 + HB2 + HB3 + TB2 filter
selection: decimate by 12 (complex to
real enabled), or decimate by 24
(complex to real disabled).
111 Decimation determined by
Register 0x0351, Bits[7:4].
0x0351 DDC 2 input
select
[7:4] DDC 2 decimation rate
select
Only valid when Register 0x0310,
Bits[2:0] = 3'b111.
0x0 R/W
0 TB2 + HB4 + HB3 + HB2 + HB1 filter
selection: decimate by 48 (complex to
real disabled), or decimate by 24
(complex to real enabled).
10 FB2 + HB1 filter selection: decimate
by 10 (complex to real disabled), or
decimate by 5 (complex to real
enabled).
11 FB2 + HB2 + HB1 filter selection:
decimate by 20 (complex to real
disabled), or decimate by 10
(complex to real enabled).
100 FB2 + HB3 + HB2 + HB1 filter
selection: decimate by 40 (complex to
real disabled), or decimate by 20
(complex to real enabled).
3 Reserved Reserved. 0x0 R
2 DDC 2 Q input select 0 Channel A. 0x0 R/W
1 Channel B.
1
Reserved
Reserved.
0x0
R
0 DDC 2 I input select 0 Channel A. 0x0 R/W
1 Channel B.
0x0354 DDC 2 NCO
control
[7:4] DDC 2 NCO channel
select mode
For edge control, the internal counter
wraps after the Register 0x0354,
Bits[3:0] value is reached.
0x0 R/W
0 Use Register 0x0314, Bits[3:0].
1 2'b0, GPIO B0, GPIO A0.
1000 Increment internal counter when
rising edge of the GPIO A0 pin.
1010 Increment internal counter when
rising edge of the GPIO B0 pin.
[3:0] DDC 2 NCO register
map channel select
NCO channel select register map
control.
0x0 R/W
0
Select NCO Channel 0.
1 Select NCO Channel 1.
10 Select NCO Channel 2.
11 Select NCO Channel 3.
100 Select NCO Channel 4.
101 Select NCO Channel 5.
110 Select NCO Channel 6.
111 Select NCO Channel 7.
1000 Select NCO Channel 8.
1001 Select NCO Channel 9.
1010 Select NCO Channel 10.
1011 Select NCO Channel 11.
AD9695 Data Sheet
Rev. C | Page 116 of 136
Address Name Bits Bit Name Settings Description Reset Access
1100 Select NCO Channel 12.
1101 Select NCO Channel 13.
1110 Select NCO Channel 14.
1111 Select NCO Channel 15.
0x0355 DDC 2 phase
control
[7:4] Reserved Reserved. 0x0 R
[3:0] DDC 2 phase update
index
Indexes the NCO channel whose
phase and offset are updated. The
update method is based on the DDC
phase update mode, which may be
continuous or require chip transfer.
0x0 R/W
0000 Update NCO Channel 0.
0001 Update NCO Channel 1.
0010 Update NCO Channel 2.
0011 Update NCO Channel 3.
0100 Update NCO Channel 4.
0101 Update NCO Channel 5.
0110 Update NCO Channel 6.
0111 Update NCO Channel 7.
1000 Update NCO Channel 8.
1001 Update NCO Channel 9.
1010 Update NCO Channel 10.
1011 Update NCO Channel 11.
1100 Update NCO Channel 12.
1101 Update NCO Channel 13.
1110 Update NCO Channel 14.
1111 Update NCO Channel 15.
0x0356 DDC 2 Phase
Increment 0
[7:0] DDC 2 phase
increment [7:0]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0357 DDC 2 Phase
Increment 1
[7:0] DDC 2 phase
increment [15:8]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0358 DDC 2 Phase
Increment 2
[7:0] DDC 2 phase
increment [23:16]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0359 DDC 2 Phase
Increment 3
[7:0] DDC 2 phase
increment [31:24]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x035A DDC 2 Phase
Increment 4
[7:0] DDC 2 phase
increment [39:32]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x035B DDC 2 Phase
Increment 5
[7:0] DDC 2 phase
increment [47:40]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x035D DDC 2 Phase
Offset 0
[7:0] DDC 2 phase offset
[7:0]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x035E DDC 2 Phase
Offset 1
[7:0] DDC 2 phase offset
[15:8]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x035F DDC 2 Phase
Offset 2
[7:0] DDC 2 phase offset
[23:16]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
Data Sheet AD9695
Rev. C | Page 117 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0360 DDC 2 Phase
Offset 3
[7:0] DDC 2 phase offset
[31:24]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0361 DDC 2 Phase
Offset 4
[7:0] DDC 2 phase offset
[39:32]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0362 DDC 2 Phase
Offset 5
[7:0] DDC 2 phase offset
[47:40]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0367 DDC 2 test enable [7:3] Reserved Reserved. 0x0 R
2 DDC 2 Q output test
mode enable
Q samples always use the Test Mode B
block. The test mode is selected using
the channel dependent bits,
Register 0x0550, Bits[3:0].
0x0 R/W
0 Test mode disabled.
1 Test mode enabled.
1 Reserved Reserved. 0x0 R
0 DDC 2 I output test
mode enable
I samples always use the Test Mode A
block. The test mode is selected using
the channel dependent bits,
Register 0x0550, Bits[3:0].
0x0 R/W
0 Test mode disabled.
1 Test mode enabled.
0x0370 DDC 3 control 7 DDC 3 mixer select 0 Real mixer (I and Q inputs must be
from the same real channel).
0x0 R/W
1 Complex mixer (I and Q must be from
separate, real and imaginary
quadrature ADC receive channels;
analog demodulator).
6 DDC 3 gain select Gain can be used to compensate for
the 6 dB loss associated with mixing
an input signal down to baseband
and filtering out its negative
component.
0x0 R/W
0 0 dB gain.
1 6 dB gain (multiply by 2).
[5:4] DDC 3 intermediate
frequency (IF) mode
00 Variable IF mode. 0x0 R/W
01 0 Hz IF mode.
10 fS/4 Hz IF mode.
11 Test mode.
3 DDC 3 complex to real
enable
0 Complex (I and Q) outputs contain
valid data.
0x0 R/W
1 Real (I) output only. Complex to real
enabled. Uses extra fS/4 mixing to
convert to real.
[2:0] DDC 3 decimation rate
select
Decimation filter selection. 0x0 R/W
000 HB1 + HB2 filter selection: decimate
by 2 (complex to real enabled), or
decimate by 4 (complex to real
disabled).
001 HB1 + HB2 + HB3 filter selection:
decimate by 4 (complex to real
enabled), or decimate by 8 (complex
to real disabled).
010 HB1 + HB2 + HB3 + HB4 filter
selection: decimate by 8 (complex to
real enabled), or decimate by 16
(complex to real disabled).
AD9695 Data Sheet
Rev. C | Page 118 of 136
Address Name Bits Bit Name Settings Description Reset Access
011 HB1 filter selection: decimate by 1
(complex to real enabled), or
decimate by 2 (complex to real
disabled).
100
HB1 + TB2 filter selection: decimate
by 3 (complex to real enabled), or
decimate by 6 (complex to real
disabled).
101 HB1 + HB2 + TB2 filter selection:
decimate by 6 (complex to real
enabled), or decimate by 12 (complex
to real disabled).
110 HB1 + HB2 + HB3 + TB2 filter
selection: decimate by 12 (complex to
real enabled), or decimate by 24
(complex to real disabled).
111 Decimation determined by
Register 0x0371, Bits[7:4].
0x0371
DDC 3 input
select
[7:4]
DDC 3 decimation rate
select
Only valid when Register 0x0310,
Bits[2:0] = 3'b111.
0x0 R/W
0 TB2 + HB4 + HB3 + HB2 + HB1 filter
selection: decimate by 48 (complex to
real disabled), or decimate by 24
(complex to real enabled).
10 FB2 + HB1 filter selection: decimate
by 10 (complex to real disabled), or
decimate by 5 (complex to real
enabled)
11 FB2 + HB2 + HB1 filter selection:
decimate by 20 (complex to real
disabled), or decimate by 10
(complex to real enabled)
100 FB2 + HB3 + HB2 + HB1 filter
selection: decimate by 40 (complex to
real disabled), or decimate by 20
(complex to real enabled)
3 Reserved Reserved. 0x0 R
2 DDC 3 Q input select 0 Channel A. 0x1 R/W
1 Channel B.
1 Reserved Reserved. 0x0 R
0 DDC 3 I input select 0 Channel A. 0x1 R/W
1 Channel B.
0x0374 DDC 3 NCO
control
[7:4] DDC 3 NCO channel
select mode
For edge control, the internal counter
wraps after the Register 0x0374,
Bits[3:0] value is reached.
0x0 R/W
0 Use Register 0x0314, Bits[3:0].
1 2'b0, GPIO B0, GPIO A0.
1000 Increment internal counter when
rising edge of the GPIO A0 pin.
1010
Increment internal counter when
rising edge of the GPIO B0 pin.
[3:0] DDC 3 NCO register
map channel select
NCO channel select register map
control.
0x0 R/W
0 Select NCO Channel 0.
1 Select NCO Channel 1.
10 Select NCO Channel 2.
11 Select NCO Channel 3.
100 Select NCO Channel 4.
Data Sheet AD9695
Rev. C | Page 119 of 136
Address Name Bits Bit Name Settings Description Reset Access
101 Select NCO Channel 5.
110 Select NCO Channel 6.
111 Select NCO Channel 7.
1000 Select NCO Channel 8.
1001 Select NCO Channel 9.
1010 Select NCO Channel 10.
1011 Select NCO Channel 11.
1100 Select NCO Channel 12.
1101 Select NCO Channel 13.
1110 Select NCO Channel 14.
1111 Select NCO Channel 15.
0x0375 DDC 3 phase
control
[7:4] Reserved Reserved. 0x0 R
[3:0] DDC 3 phase update
index
Indexes the NCO channel whose
phase and offset are updated. The
update method is based on the DDC
phase update mode, which may be
continuous or require chip transfer.
0x0 R/W
0000 Update NCO Channel 0.
0001 Update NCO Channel 1.
0010 Update NCO Channel 2.
0011 Update NCO Channel 3.
0100 Update NCO Channel 4.
0101 Update NCO Channel 5.
0110 Update NCO Channel 6.
0111 Update NCO Channel 7.
1000 Update NCO Channel 8.
1001 Update NCO Channel 9.
1010 Update NCO Channel 10.
1011 Update NCO Channel 11.
1100 Update NCO Channel 12.
1101 Update NCO Channel 13.
1110 Update NCO Channel 14.
1111 Update NCO Channel 15.
0x0376 DDC 3 Phase
Increment 0
[7:0] DDC 3 phase
increment [7:0]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0377 DDC 3 Phase
Increment 1
[7:0] DDC 3 phase
increment [15:8]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0378 DDC 3 Phase
Increment 2
[7:0] DDC 3 phase
increment [23:16]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x0379 DDC 3 Phase
Increment 3
[7:0] DDC 3 phase
increment [31:24]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x037A DDC 3 Phase
Increment 4
[7:0] DDC 3 phase
increment [39:32]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
0x037B DDC 3 Phase
Increment 5
[7:0] DDC 3 phase
increment [47:40]
FTW. Twos complement phase
increment value for the NCO.
Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
0x0 R/W
AD9695 Data Sheet
Rev. C | Page 120 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x037D DDC 3 Phase
Offset 0
[7:0] DDC 3 phase offset [7:0] Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x037E DDC 3 Phase
Offset 1
[7:0] DDC 3 phase offset
[15:8]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x037F DDC 3 Phase
Offset 2
[7:0] DDC 3 phase offset
[23:16]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0380 DDC 3 Phase
Offset 3
[7:0] DDC 3 phase offset
[31:24]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0381 DDC 3 Phase
Offset 4
[7:0] DDC 3 phase offset
[39:32]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0382 DDC 3 Phase
Offset 5
[7:0] DDC 3 phase offset
[47:40]
Twos complement phase offset value
for the NCO (POW).
0x0 R/W
0x0387 DDC 3 test enable [7:3] Reserved Reserved. 0x0 R
2 DDC 3 Q output test
mode enable
Q samples always use the Test Mode B
block. The test mode is selected using
the channel dependent bit,
Register 0x0550, Bits[3:0].
0x0 R/W
0
Test mode disabled.
1 Test mode enabled.
1 Reserved Reserved. 0x0 R
0 DDC 3 I output test
mode enable
I samples always use the Test Mode A
block. The test mode is selected using
the channel dependent bits,
Register 0x0550, Bits[3:0].
0x0 R/W
0 Test mode disabled.
1 Test mode enabled.
0x0390 DDC 0 Phase
Increment
Fractional A0
[7:0] DDC 0 Phase
Increment Fractional A
[7:0]
Numerator correction term for the
modulus phase accumulator (MAW).
0x0 R/W
0x0391 DDC 0 Phase
Increment
Fractional A1
[7:0] DDC 0 Phase
Increment Fractional A
[15:8]
Numerator correction term for the
MAW.
0x0 R/W
0x0392
DDC 0 Phase
Increment
Fractional A2
[7:0]
DDC 0 Phase
Increment Fractional A
[23:16]
Numerator correction term for the
MAW.
0x0 R/W
0x0393 DDC 0 Phase
Increment
Fractional A3
[7:0] DDC 0 Phase
Increment Fractional A
[31:24]
Numerator correction term for the
MAW.
0x0 R/W
0x0394 DDC 0 Phase
Increment
Fractional A4
[7:0] DDC 0 Phase
Increment Fractional A
[39:32]
Numerator correction term for the
MAW.
0x0 R/W
0x0395 DDC 0 Phase
Increment
Fractional A5
[7:0] DDC 0 Phase
Increment Fractional A
[47:40]
Numerator correction term for the
MAW.
0x0 R/W
0x0398 DDC 0 Phase
Increment
Fractional B0
[7:0] DDC 0 Phase
Increment Fractional B
[7:0]
Denominator correction term for the
modulus phase accumulator (MBW).
0x0 R/W
0x0399 DDC 0 Phase
Increment
Fractional B1
[7:0] DDC 0 Phase
Increment Fractional B
[15:8]
Denominator correction term for the
MBW.
0x0 R/W
0x039A DDC 0 Phase
Increment
Fractional B2
[7:0] DDC 0 Phase
Increment Fractional B
[23:16]
Denominator correction term for the
MBW.
0x0 R/W
0x039B DDC 0 Phase
Increment
Fractional B3
[7:0] DDC 0 Phase
Increment Fractional B
[31:24]
Denominator correction term for the
MBW.
0x0 R/W
Data Sheet AD9695
Rev. C | Page 121 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x039C DDC 0 Phase
Increment
Fractional B4
[7:0] DDC 0 Phase
Increment Fractional B
[39:32]
Denominator correction term for the
MBW.
0x0 R/W
0x039D DDC 0 Phase
Increment
Fractional B5
[7:0] DDC 0 Phase
Increment Fractional B
[47:40]
Denominator correction term for the
MBW.
0x0 R/W
0x03A0 DDC 1 Phase
Increment
Fractional A0
[7:0] DDC 1 Phase
Increment Fractional A
[7:0]
Numerator correction term for the
modulus phase accumulator (MAW).
0x0 R/W
0x5C00x03A1 DDC 1 Phase
Increment
Fractional A1
[7:0] DDC 1 Phase
Increment Fractional A
[15:8]
Numerator correction term for the
MAW.
0x0 R/W
0x03A2 DDC 1 Phase
Increment
Fractional A2
[7:0] DDC 1 Phase
Increment Fractional A
[23:16]
Numerator correction term for the
MAW.
0x0 R/W
0x03A3 DDC 1 Phase
Increment
Fractional A3
[7:0] DDC 1 Phase
Increment Fractional A
[31:24]
Numerator correction term for the
MAW.
0x0 R/W
0x03A4 DDC 1 Phase
Increment
Fractional A4
[7:0] DDC 1 Phase
Increment Fractional A
[39:32]
Numerator correction term for the
MAW.
0x0 R/W
0x03A5 DDC 1 Phase
Increment
Fractional A5
[7:0] DDC 1 Phase
Increment Fractional A
[47:40]
Numerator correction term for the
MAW.
0x0 R/W
0x03A8 DDC 1 Phase
Increment
Fractional B0
[7:0] DDC 1 Phase Increment
Fractional B [7:0]
Denominator correction term for the
MBW.
0x0 R/W
0x03A9 DDC 1 Phase
Increment
Fractional B1
[7:0] DDC 1 Phase Increment
Fractional B [15:8]
Denominator correction term for the
MBW.
0x0 R/W
0x03AA DDC 1 Phase
Increment
Fractional B2
[7:0] DDC 1 Phase Increment
Fractional B [23:16]
Denominator correction term for the
MBW.
0x0 R/W
0x03AB DDC 1 Phase
Increment
Fractional B3
[7:0] DDC 1 Phase Increment
Fractional B [31:24]
Denominator correction term for the
MBW.
0x0 R/W
0x03AC DDC 1 Phase
Increment
Fractional B4
[7:0] DDC 1 Phase Increment
Fractional B [39:32]
Denominator correction term for the
MBW.
0x0 R/W
0x03AD DDC 1 Phase
Increment
Fractional B5
[7:0] DDC 1 Phase Increment
Fractional B [47:40]
Denominator correction term for the
MBW.
0x0 R/W
0x03B0 DDC 2 Phase
Increment
Fractional A0
[7:0] DDC 2 Phase Increment
Fractional A [7:0]
Numerator correction term for the
MAW.
0x0 R/W
0x03B1 DDC 2 Phase
Increment
Fractional A1
[7:0] DDC 2 Phase Increment
Fractional A [15:8]
Numerator correction term for the
MAW.
0x0 R/W
0x03B2 DDC 2 Phase
Increment
Fractional A2
[7:0] DDC 2 Phase Increment
Fractional A [23:16]
Numerator correction term for the
MAW.
0x0 R/W
0x03B3 DDC 2 Phase
Increment
Fractional A3
[7:0] DDC 2 Phase Increment
Fractional A [31:24]
Numerator correction term for the
MAW.
0x0 R/W
0x03B4 DDC 2 Phase
Increment
Fractional A4
[7:0] DDC 2 Phase Increment
Fractional A [39:32]
Numerator correction term for the
MAW.
0x0 R/W
AD9695 Data Sheet
Rev. C | Page 122 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x03B5 DDC 2 Phase
Increment
Fractional A5
[7:0] DDC 2 Phase Increment
Fractional A [47:40]
Numerator correction term for the
MAW.
0x0 R/W
0x03B8 DDC 2 Phase
Increment
Fractional B0
[7:0] DDC 2 Phase Increment
Fractional B [7:0]
Denominator correction term for the
MBW.
0x0 R/W
0x03B9 DDC 2 Phase
Increment
Fractional B1
[7:0] DDC 2 Phase Increment
Fractional B [15:8]
Denominator correction term for the
MBW.
0x0 R/W
0x03BA DDC 2 Phase
Increment
Fractional B2
[7:0] DDC 2 Phase Increment
Fractional B [23:16]
Denominator correction term for the
MBW.
0x0 R/W
0x03BB DDC 2 Phase
Increment
Fractional B3
[7:0] DDC 2 Phase Increment
Fractional B [31:24]
Denominator correction term for the
MBW.
0x0 R/W
0x03BC DDC 2 Phase
Increment
Fractional B4
[7:0] DDC 2 Phase Increment
Fractional B [39:32]
Denominator correction term for the
MBW.
0x0 R/W
0x03BD DDC 2 Phase
Increment
Fractional B5
[7:0] DDC 2 Phase Increment
Fractional B [47:40]
Denominator correction term for the
MBW.
0x0 R/W
0x03C0 DDC 3 Phase
Increment
Fractional A0
[7:0] DDC 3 Phase Increment
Fractional A [7:0]
Numerator correction term for the
MAW.
0x0 R/W
0x03C1 DDC 3 Phase
Increment
Fractional A1
[7:0] DDC 3 Phase Increment
Fractional A [15:8]
Numerator correction term for the
MAW.
0x0 R/W
0x03C2 DDC 3 Phase
Increment
Fractional A2
[7:0] DDC 3 Phase Increment
Fractional A [23:16]
Numerator correction term for the
MAW.
0x0 R/W
0x03C3 DDC 3 Phase
Increment
Fractional A3
[7:0] DDC 3 Phase Increment
Fractional A [31:24]
Numerator correction term for the
MAW.
0x0 R/W
0x03C4 DDC 3 Phase
Increment
Fractional A4
[7:0] DDC 3 Phase Increment
Fractional A [39:32]
Numerator correction term for the
MAW.
0x0 R/W
0x03C5 DDC 3 Phase
Increment
Fractional A5
[7:0] DDC 3 Phase Increment
Fractional A [47:40]
Numerator correction term for the
MAW.
0x0 R/W
0x03C8 DDC 3 Phase
Increment
Fractional B0
[7:0] DDC 3 Phase Increment
Fractional B [7:0]
Denominator correction term for the
MBW.
0x0 R/W
0x03C9 DDC 3 Phase
Increment
Fractional B1
[7:0] DDC 3 Phase Increment
Fractional B [15:8]
Denominator correction term for the
MBW.
0x0 R/W
0x03CA DDC 3 Phase
Increment
Fractional B2
[7:0] DDC 3 Phase Increment
Fractional B [23:16]
Denominator correction term for the
MBW.
0x0 R/W
0x03CB DDC 3 Phase
Increment
Fractional B3
[7:0] DDC 3 Phase Increment
Fractional B [31:24]
Denominator correction term for the
MBW.
0x0 R/W
0x03CC DDC 3 Phase
Increment
Fractional B4
[7:0] DDC 3 Phase Increment
Fractional B [39:32]
Denominator correction term for the
MBW.
0x0 R/W
0x03CD DDC 3 Phase
Increment
Fractional B5
[7:0] DDC 3 Phase Increment
Fractional B [47:40]
Denominator correction term for the
MBW.
0x0 R/W
Data Sheet AD9695
Rev. C | Page 123 of 136
Address Name Bits Bit Name Settings Description Reset Access
Digital Outputs and Test Mode Registers
0x0550 ADC test mode
control (local)
7 User pattern selection Test mode user pattern selection.
These bits are only used when
TMODE_GEN_SEL is in user input
mode (TMODE_GEN_SEL = 1000).
Otherwise, they are ignored. User
Pattern 1 is found in the USR_PAT_
1_MSB and USR_PAT_1_LSB registers.
User Pattern 2 is found in the USR_
PAT_2_MSB and USR_PAT_2_LSB
registers, and so on.
0x0 R/W
0 Continuous/repeat pattern. Place
each user pattern (User Pattern 1
through User Pattern 4) on the
output for 1 clock cycle and then
repeat. (Output User Pattern 1, User
Pattern 2, User Pattern 3, User Pattern
4, User Pattern 1, User Pattern 2, User
Pattern 3, User Pattern 4, User Pattern 1,
User Pattern 2, User Pattern 3, User
Pattern 4, and so on).
1 Single Pattern. Place each User
Pattern (User Pattern 1 through User
Pattern 4) on the output for 1 clock
cycle and then output all zeros.
(Output User Pattern 1 through User
Pattern 4, then output all zeros).
6 Reserved Reserved. 0x0 R
5 Reset pseudorandom
long generator
Test mode long pseudorandom
number test generator reset.
0x0 R/W
0 Long pseudorandom enabled.
1 Long pseudorandom held in reset.
4
Reset pseudorandom
short generator
Test mode short pseudorandom
number Test generator reset.
0x0 R/W
0 Short pseudorandom enabled.
1 Short pseudorandom held in reset.
[3:0] Test mode selection Test mode generation selection. 0x0 R/W
0000 Off; normal operation.
0001 Midscale short.
0010 Positive full scale.
0011 Negative full scale.
0100 Alternating checker board.
0101 Pseudorandom sequence, long.
0110 Pseudorandom sequence, short.
0111 1/0 word toggle.
1000 User pattern test mode (used with
TMODE_USR_PAT_SEL and the User
Pattern 1 through User Pattern 4
registers).
1111: ramp output.
0x0551 User Pattern 1 LSB [7:0] User Pattern 1 [7:0] User Test Pattern 1 LSB. 0x0 R/W
0x0552 User Pattern 1
MSB
[7:0] User Pattern 1 [15:8] User Test Pattern 1 LSB. 0x0 R/W
0x0553 User Pattern 2 LSB [7:0] User Pattern 2 [7:0] User Test Pattern 2 LSB. 0x0 R/W
0x0554 User Pattern 2
MSB
[7:0] User Pattern 2 [15:8] User Test Pattern 2 LSB. 0x0 R/W
0x0555 User Pattern 3 LSB [7:0] User Pattern 3 [7:0] User Test Pattern 3 LSB. 0x0 R/W
AD9695 Data Sheet
Rev. C | Page 124 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x0556 User Pattern 3
MSB
[7:0] User Pattern 3 [15:8] User Test Pattern 3 LSB. 0x0 R/W
0x0557 User Pattern 4 LSB [7:0] User Pattern 4 [7:0] User Test Pattern 4 LSB. 0x0 R/W
0x0558 User Pattern 4
MSB
[7:0] User Pattern 4 [15:8] User Test Pattern 4 LSB. 0x0 R/W
0x0559 Output Mode
Control 1
[7:4] Converter control Bit 1
selection
0000 Tie low (1'b0). 0x0 R/W
0001 Overrange bit.
0010 Signal monitor bit.
0011 Fast detect (FD) bit.
0101 SYSREF±.
[3:0]
Converter control Bit 0
selection
0000 Tie low (1'b0). 0x0 R/W
0001 Overrange bit.
0010 Signal monitor bit.
0011 Fast detect (FD) bit.
0101 SYSREF±.
0x055A Output Mode
Control 2
[7:4] Reserved Reserved. 0x0 R
[3:0] Converter control Bit 2
selection
0000 Tie low (1'b0). 0x1 R/W
0001 Overrange bit.
0010 Signal monitor bit.
0011 Fast detect (FD) bit.
0101 SYSREF±.
0x0561 Output sample
mode
[7:3] Reserved Reserved. 0x0 R/W
2 Sample invert 0 ADC sample data is not inverted. 0x0 R/W
1 ADC sample data is inverted.
[1:0] Data format select 00 Offset binary. 0x1 R/W
01 Twos complement (default).
0x0562 Output
overrange clear
[7:0] Data format overrange
clear
Overrange clear bits (one bit for each
virtual converter).
0x0 R/W
0 Overrange bit enabled.
1 Overrange bit cleared. Writing a 1 to
the overrange clear bit clears the
corresponding overrange sticky bit.
0x0563 Output
overrange status
[7:0] Data format overrange Overrange sticky bit status (one bit
for each virtual converter).
0x0 R
0 No overrange occurred
1
Overrange occurred. Writing a 1 to
the overrange clear bit clears the
corresponding overrange sticky bit.
0x0564 Output channel
select
[7:1] Reserved Reserved. 0x0 R
0 Converter channel
swap control
0 Normal channel ordering. 0x0 R/W
1 Channel swap enabled. Depending
on the application mode selected in
Register 0x0200, enabling the channel
swap bit (Register 0x0564, Bit 0) swaps
the A/B or I/Q converters.
0x056E PLL control [7:4] JESD204B lane rate
control
0011 Lane rate = 13.5 Gbps to 16 Gbps. 0x3 R/W
0000 Lane rate = 6.75 Gbps to 13.5 Gbps.
0001 Lane rate = 3.375 Gbps to 6.75 Gbps.
0101 Lane rate = 1.6875 Gbps to 3.375 Gbps.
[3:0] Reserved Reserved. 0x0 R
Data Sheet AD9695
Rev. C | Page 125 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x056F PLL status 7 PLL lock status 0 Not locked. 0x0 R
1 Locked.
[6:4] Reserved Reserved. 0x0 R
3 PLL loss of lock Loss of lock sticky bit.
1 Indicates a loss of lock occurred at
some time; cleared by setting
Register 0x0571, Bit 0.
[2:0] Reserved Reserved
0x0571 JESD204B Link
Control 1
7 Standby mode 0 Standby mode forces zeros for all
converter samples.
0x0 R/W
1 Standby mode forces code group
synchronization (K28.5 characters).
6 Tail bit (t) PN 0 Disable. 0x0 R/W
1 Enable.
5 Long transport layer
test
0 JESD204B test samples disabled. 0x0 R/W
1 JESD204B test samples enabled; long
transport layer test sample sequence
(as specified in JESD204B Section
5.1.6.3) sent on all link lanes.
4 Lane synchronization 0 Disable FACI uses /K28.7/. 0x1 R/W
1 Enable FACI uses /K28.3/ and /K28.7/.
[3:2] ILAS sequence mode 00
Initial lane alignment sequence
disabled (JESD204B, Section 5.3.3.5).
0x1 R/W
01 Initial lane alignment sequence
enabled (JESD204B, Section 5.3.3.5).
11 Initial lane alignment sequence always
on test mode (JESD204B data link layer
test mode) where repeated lane
alignment sequence (as specified in
JESD204B, Section 5.3.3.8.2) sent on all
lanes.
1 FACI 0 Frame alignment character insertion
enabled (JESD204B, Section 5.3.3.4).
0x0 R/W
1 Frame alignment character insertion
disabled; for debug only (JESD204B,
Section 5.3.3.4).
0 Link control 0 JESD204B serial transmit link enabled.
Transmission of the /K28.5/
characters for code group
synchronization is controlled by the
SYNCINB± pin.
0x0 R/W
1 JESD204B serial transmit link powered
down (held in reset and clock gated).
0x0572 JESD204B Link
Control 2
[7:6] SYNCINB± pin control 00 Normal mode. 0x0 R/W
10 Ignore SYNCINB± (force CGS).
11 Ignore SYNCINB± (force ILAS/user data).
5 SYNCINB± pin invert 0 SYNCINB± pin not inverted. 0x0 R/W
1 SYNCINB± pin inverted.
4 SYNCINB± pin type 0 LVDS differential pair SYNC input. 0x0 R/W
1 CMOS single-ended SYNC input.
3 Reserved Reserved. 0x0 R
2 8-bit/10-bit bypass 0 8-bit/10-bit enabled. 0x0 R/W
1 8-bit/10-bit bypassed (the most
significant 2 bits are 0).
1 8-bit/10-bit bit invert 0 Normal. 0x0 R/W
1 Invert a, b, c, d, e, f, g, h, I, and j symbols.
AD9695 Data Sheet
Rev. C | Page 126 of 136
Address Name Bits Bit Name Settings Description Reset Access
0 Reserved Reserved. 0x0 R/W
0x0573 JESD204B Link
Control 3
[7:6] Checksum mode 00 Checksum is the sum of all 8-bit
registers in the link configuration table.
0x0 R/W
01 Checksum is the sum of all individual
link configuration fields (LSB aligned).
10 Checksum is disabled (set to zero).
For test purposes only.
11 Unused.
[5:4] Test injection point 0 N' sample input. 0x0 R/W
1 10 bit data at 8-bit/10-bit output (for
PHY testing)
10 8-bit data at scrambler input.
[3:0] JESD204B test mode
patterns
0 Normal operation (test mode disabled). 0x0 R/W
1 Alternating checkerboard.
10 1/0 word toggle.
11 31-bit PN sequence (x31 + x28 + 1).
100 23-bit PN sequence (x23 + x18 + 1).
101 15-bit PN sequence (x15 + x14 + 1).
110 9-bit PN sequence (x9 + x5 + 1).
111 7-bit PN sequence (x7 + x6 + 1).
1000 Ramp output.
1110 Continuous/repeat user test.
1111 Single user test.
0x0574 JESD204B Link
Control 4
[7:4] ILAS delay 0 Transmit ILAS on first LMFC after
SYNCINB± deasserted.
0x0 R/W
1 Transmit ILAS on second LMFC after
SYNCINB± deasserted.
10 Transmit ILAS on third LMFC after
SYNCINB± deasserted.
11 Transmit ILAS on fourth LMFC after
SYNCINB± deasserted.
100 Transmit ILAS on fifth LMFC after
SYNCINB± deasserted.
101 Transmit ILAS on sixth LMFC after
SYNCINB± deasserted.
110 Transmit ILAS on seventh LMFC after
SYNCINB± deasserted.
111 Transmit ILAS on eighth LMFC after
SYNCINB± deasserted.
1000 Transmit ILAS on ninth LMFC after
SYNCINB± deasserted.
1001 Transmit ILAS on tenth LMFC after
SYNCINB± deasserted.
1010 Transmit ILAS on eleventh LMFC after
SYNCINB± deasserted.
1011 Transmit ILAS on twelfth LMFC after
SYNCINB± deasserted.
1100 Transmit ILAS on thirteenth LMFC
after SYNCINB± deasserted.
1101 Transmit ILAS on fourteenth LMFC
after SYNCINB± deasserted.
1110 Transmit ILAS on fifteenth LMFC after
SYNCINB± deasserted.
1111 Transmit ILAS on sixteenth LMFC
after SYNCINB± deasserted.
3 Reserved Reserved. 0x0 R
Data Sheet AD9695
Rev. C | Page 127 of 136
Address Name Bits Bit Name Settings Description Reset Access
[2:0] Link layer test mode 000 Normal operation (link layer test
mode disabled).
0x0 R/W
001 Continuous sequence of /D21.5/
characters.
010 Reserved.
011 Reserved.
100 Modified RPAT test sequence.
101 JSPAT test sequence.
110 JTSPAT test sequence.
111 Reserved.
0x0578 JESD204B LMFC
offset
[7:5] Reserved Reserved. 0x0 R
[4:0] LMFC phase offset
value
Local multiframe clock (LMFC) phase
offset value. Reset value for the LMFC
phase counter when SYSREF± is
asserted. Used for deterministic delay
applications.
0x0 R/W
0x0580 JESD204B device
identification
(DID) config-
uration
[7:0] JESD204B Tx DID value JESD204B serial DID number. 0x0 R/W
0x0581 JESD204B bank
identification
(BID) config-
uration
[7:4] Reserved Reserved. 0x0 R
[3:0] JESD204B Tx BID value JESD204B serial BID number
(extension to DID).
0x0 R/W
0x0583 JESD204B Lane
Identification 0
(LID0) config-
uration
[7:5] Reserved Reserved. 0x0 R
[4:0] Lane 0 LID value JESD204B serial LID number for Lane 0. 0x0 R/W
0x0584 JESD204B LID1
configuration
[7:5] Reserved Reserved. 0x0 R
[4:0] Lane 1 LID value JESD204B serial LID number for Lane 1. 0x1 R/W
0x0585 JESD204B LID2
configuration
[7:5] Reserved Reserved. 0x0 R
[4:0] Lane 2 LID value JESD204B serial LID number for Lane 2. 0x2 R/W
0x0586
JESD204B LID3
configuration
[7:5] Reserved Reserved. 0x0 R
[4:0] Lane 3 LID value JESD204B serial LID number for Lane 3. 0x3 R/W
0x058B JESD204B
scrambling and
number of lanes
(L) configuration
7 JESD204B scrambling
(SCR)
0 JESD204B scrambler disabled (SCR = 0). 0x1 R/W
1 JESD204B scrambler enabled (SCR = 1).
[6:5] Reserved Reserved. 0x0 R
[4:0] JESD204B lanes (L) 0x0 One lane per link (L = 1). 0x3 R/W
0x1 Two lanes per link (L = 2).
0x3 Four lanes per link (L = 4).
0x058C JESD204B link
number of octets
per frames (F)
[7:0] JESD204B F
configuration
JESD204B number of octets per frame
(F = JESD204B_F_CONFIG + 1).
0x0 R/W
0 F = 1.
1 F = 2.
10 F = 3.
11 F = 4.
101 F = 6.
111 F = 8.
1111 F = 16.
0x058D
JESD204B link
number of
frames per
multiframe (K)
[7:5] Reserved Reserved. 0x0 R
[4:0] JESD204B K
configuration
JESD204B number of frames per multi-
frame (K = JESD204B_K_CONFIG + 1).
Only values where F × K, which are
divisible by 4, can be used.
0x1F R/W
AD9695 Data Sheet
Rev. C | Page 128 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x058E JESD204B link
number of
converters (M)
[7:0] JESD204B M
configuration
JESD204B number of converters per
link/device (M = JESD204B_M_CFG).
0x1 R/W
0 Link connected to one virtual
converter (M = 1).
1 Link connected to two virtual
converters (M = 2).
11 Link connected to four virtual
converters (M = 4).
111 Link connected to eight virtual
converters (M = 8).
0x058F JESD204B
number Of
control bits (CS)
and ADC
resolution (N)
[7:6] Number of control bits
(CS) per sample
0 No control bits (CS = 0) 0x0 R/W
1 1 control bit (CS = 1), Control Bit 2 only.
10 2 control bits (CS = 2), Control Bit 2
and Control Bit 1only.
11 3 control bits (CS = 3), all control bits
(2, 1, and 0).
5 Reserved Reserved. 0x0 R
[4:0] ADC converter
resolution (N)
00110 N = 7-bit resolution. 0xF R/W
00111 N = 8-bit resolution.
01000 N = 9-bit resolution.
01001 N = 10-bit resolution.
01010 N = 11-bit resolution.
01011 N = 12-bit resolution.
01100 N = 13-bit resolution.
01101 N = 14-bit resolution.
01110 N = 15-bit resolution.
01111 N = 16-bit resolution.
0x0590 JESD204B SCV
NP configuration
[7:5] Subclass support 000 Subclass 0. 0x1 R/W
001 Subclass 1.
[4:0] ADC number of bits
per sample (N')
00111 N' = 8. 0xF R/W
01111 N' = 16.
0x0591
JESD204B JV S
configuration
[7:5]
Reserved
Reserved.
0x1
R
[4:0] Samples per converter
frame cycle (S)
Samples per converter frame cycle (S =
Register 0x0591, Bits[4:0]+1)
0x0 R
0x0592 JESD204B HD CF
configuration
7 HD value 0 High density format disabled. 0x0 R
1 High density format enabled.
[6:5] Reserved Reserved. 0x0 R
[4:0] Control words per
frame clock cycle per
link (CF)
Number of control words per frame
clock cycle per link (CF =
Register 0x0592, Bits[4:0]).
0x0 R
0x05A0 JESD204B
Checksum 0
configuration
[7:0] Checksum 0 value for
SERDOUT0±
Serial Checksum Value for Lane 0.
Automatically calculated for each
lane. Sum(all link configuration
parameters for Lane 0) mod 256.
0xC3 R
0x05A1 JESD204B
Checksum 1
configuration
[7:0] Checksum 1 value for
SERDOUT1±
Serial Checksum Value for Lane 1.
Automatically calculated for each
lane. Sum(all link configuration
parameters for Lane 1) mod 256.
0xC4 R
0x05A2 JESD204B
Checksum 2
configuration
[7:0] Checksum 2 value for
SERDOUT2±
Serial Checksum Value for Lane 2.
Automatically calculated for each
lane. Sum(all link configuration
parameters for each lane) mod 256.
0xC5 R
0x05A3 JESD204B
Checksum 3
configuration
[7:0] Checksum 3 value for
SERDOUT3±
Serial Checksum Value for Lane 3.
Automatically calculated for each
lane. Sum(all link configuration
parameters for Lane 3) mod 256.
0xC6 R
Data Sheet AD9695
Rev. C | Page 129 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x05B0 JESD204B lane
power-down
7 Reserved Reserved. 0x0 R
6 JESD204B Lane 3
power-down
Physical Lane 3 force power-down. 0x0 R/W
5 Reserved Reserved. 0x0 R
4 JESD204B Lane 2
power-down
Physical Lane 2 force power-down. 0x0 R/W
3 Reserved Reserved. 0x0 R
2
JESD204B Lane 1
power-down
Physical Lane 1 force power-down. 0x0 R/W
1 Reserved Reserved. 0x0 R
0 JESD204B Lane 0
power-down
Physical Lane 0 force power-down. 0x0 R/W
0x05B2 JESD204B Lane
Assignment 1
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT0± lane
assignment
Physical Lane 0 assignment. 0x0 R/W
0 Logical Lane 0.
1 Logical Lane 1.
10 Logical Lane 2.
11 Logical Lane 3.
0x05B3 JESD204B Lane
Assignment 2
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT1± lane
assignment
Physical Lane 1 assignment. 0x1 R/W
0 Logical Lane 0.
1 Logical Lane 1
10 Logical Lane 2
11 Logical Lane 3.
0x05B5 JESD204B Lane
Assignment 3
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT2± lane
assignment
Physical Lane 2 assignment. 0x2 R/W
0 Logical Lane 0.
1 Logical Lane 1.
10 Logical Lane 2.
11 Logical Lane 3.
0x05B6 JESD204B Lane
Assignment 4
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT3± lane
assignment
Physical Lane 3 assignment. 0x3 R/W
0 Logical Lane 0.
1 Logical Lane 1.
10 Logical Lane 2.
11 Logical Lane 3.
0x05BF SERDOUTx± data
invert
7 Reserved Reserved. 0x0 R/W
6 Invert SERDOUT3± data Invert SERDOUT3± data. 0x0 R/W
0 Normal.
1 Invert.
5 Reserved Reserved. 0x0 R/W
4 Invert SERDOUT2± data Invert SERDOUT2± data. 0x0 R/W
0 Normal.
1 Invert.
3 Reserved Reserved. 0x0 R/W
2 Invert SERDOUT1± data Invert SERDOUT1± data 0x0 R/W
0 Normal.
1 Invert.
1 Reserved Reserved. 0x0 R/W
0 Invert SERDOUT0± data Invert SERDOUT0± data. 0x0 R/W
0 Normal.
1 Invert.
AD9695 Data Sheet
Rev. C | Page 130 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x05C0 JESD204B Swing
Adjust 1
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT0± voltage
swing adjust
Output swing level for SERDOUT0±. 0x1 R/W
0 1.0 × DRVDD1.
1 0.850 × DRVDD1.
2 0.750 × DRVDD1.
0x05C1 JESD204B Swing
Adjust 2
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT1± voltage
swing adjust
Output swing level for SERDOUT1±. 0x1 R/W
0 1.0 × DRVDD1.
1 0.850 × DRVDD1.
2 0.750 × DRVDD1.
0x05C2 JESD204B Swing
Adjust 3
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT2± voltage
swing adjust
Output swing level for SERDOUT2±. 0x1 R/W
0 1.0 × DRVDD1.
1 0.850 × DRVDD1.
2 0.750 × DRVDD1.
0x05C3 JESD204B Swing
Adjust 4
[7:3] Reserved Reserved. 0x0 R
[2:0] SERDOUT3± voltage
swing adjust
Output swing level for SERDOUT3±. 0x1 R/W
0
1.0 × DRVDD1.
1 0.850 × DRVDD1.
2 0.750 × DRVDD1.
0x05C4 SERDOUT0± pre-
emphasis select
7 Post tap enable Post tab enable. 0x0 R/W
0 Disable.
1 Enable.
[6:4] Set post tap level for
SERDOUT0±
Set post tap level. 0x0 R/W
000 0 dB.
001 3 dB.
010 6 dB.
011 9 dB.
[3:0] Reserved Reserved. 0x0 R/W
0x05C6 SERDOUT1± pre-
emphasis select
7 Post tap enable Post tab enable. 0x0 R/W
0 Disable.
1 Enable.
[6:4] Set post tap level for
SERDOUT1
Set post tap level. 0x0 R/W
000 0 dB.
001 3 dB.
010 6 dB.
011 9 dB.
[3:0] Reserved Reserved. 0x0 R/W
0x05C8 SERDOUT2± pre-
emphasis select
7 Post tap enable Post tab enable. 0x0 R/W
0 Disable.
1 Enable.
[6:4] Set post tap level for
SERDOUT2
Set post tap level. 0x0 R/W
000 0 dB.
001 3 dB.
010 6 dB.
011
9 dB.
[3:0] Reserved Reserved. 0x0 R/W
0x05CA SERDOUT3± pre-
emphasis select
7 Post tap enable Post tab enable. 0x0 R/W
0 Disabled
1 Enabled.
Data Sheet AD9695
Rev. C | Page 131 of 136
Address Name Bits Bit Name Settings Description Reset Access
[6:4] Set post tap level for
SERDOUT3±
Set post tap level. 0x0 R/W
000 0 dB.
001 3 dB.
010 6 dB.
011 9 dB.
[3:0] Reserved Reserved. 0x0 R/W
0x1222 JESD204B PLL
calibration
[7:0] See Table 34. 0x00 R/W
0x00 JESD204B PLL normal operation.
0x04 Reset JESD204B PLL calibration.
0x1228 JESD204B PLL
start-up control
[7:0] See Table 34. 0x0F R/W
0x00 JESD204B start-up circuit in normal
operation.
0x4F Reset JESD204B start-up circuit.
0x1262 JESD204B PLL
LOL bit control
[7:0] See Table 34. 0x00 R/W
0x00 Loss of lock bit normal operation.
0x80 Clear loss of lock bit.
Programmable Filter Control and Coefficients Registers
0x0DF8 Programmable
filter control
[7:3] Reserved Reserved. 0x0 R
[2:0] Programmable filter
mode
Programmable filter (PFILT) mode. 0x0 R/W
000 Disabled (filters bypassed).
001 Single filter (Filter X only).
DOUT_I[n] = DIN_I[n] × X_I[n].
DOUT_Q[n] = DIN_Q[n] × X_Q[n].
010 Single filter (Filter X and Filter Y
together).
DOUT_I[n] = DIN_I[n] × XY_I[n].
DOUT_Q[n] = DIN_Q[n] × XY_Q[n].
100 Cascaded filters (Filter X to Filter Y).
DOUT_I[n] = DIN_I[n] × X_I[n] × Y_I[n].
DOUT_Q[n] = DIN_Q[n] × X_Q[n] ×
Y_Q[n].
101 Complex filters.
DOUT_I[n] = DIN_I[n] × X_I[n] +
DIN_Q[n] × Y_Q[n].
DOUT_Q[n] = DIN_Q[n] × X_Q[n] +
DIN_I[n] × Y_I[n].
0x0DF9 PFILT gain 7 Reserved Reserved. 0x0 R
[6:4] PFILT Y gain Programmable filter (PFILT) Y gain 0x0 R/W
100 Reserved.
101 Reserved.
110 −12 dB loss.
111 −6 dB loss.
000 0 dB gain.
001 +6 dB gain.
010 +12 dB gain.
011 Reserved.
3 Reserved Reserved. 0x0 R
[2:0] PFILT X gain Programmable filter (PFILT) X gain. 0x0 R/W
100 Reserved.
101 Reserved.
110 −12 dB loss.
AD9695 Data Sheet
Rev. C | Page 132 of 136
Address Name Bits Bit Name Settings Description Reset Access
111 −6 dB loss.
000 0 dB gain.
001 +6 dB gain.
010 +12 dB gain.
011 Reserved.
0x0E00 to
0x0E7F
Programmable
Filter X
Coefficient x
[7:0] Programmable Filter X
Coefficient 0 to
Programmable Filter X
Coefficient 127
Refer to the I coefficient table (Table 15)
and the Q coefficient table (Table 16) in
the Programmable Finite Impulse
Response (FIR) Filters section for
details. Coefficients are only applied
after the chip transfer bit
(Register 0x000F, Bit 0) is set.
0x0 R/W
0x0F00 to
0x0F7F
Programmable
Filter Y
Coefficient x
[7:0] Programmable Filter Y
Coefficient 0 to
Programmable Filter Y
Coefficient 127
Refer to the I coefficient table (Table 15)
and the Q coefficient table (Table 16) in
the Programmable Finite Impulse
Response (FIR) Filters section for
details. Coefficients are only applied
after the chip transfer bit
(Register 0x000F, Bit 0) is set.
0x0 R/W
VREF/Analog Input Control Registers
0x0701 DC Offset
Calibration
Control 1 (local)
[7] DC Offset Calibration
Enable 1
0 Disabled (must set to 0 when
Register 0x073B, Bit 7 = 1).
0x0 R/W
1 Enabled (must set to 1 when
Register 0x073B, Bit 7 = 0).
[6:0] Reserved 110 Reserved. 0x6 R
0x073B DC Offset
Calibration
Control 2 (local)
[7] DC Offset Calibration
Enable 2
0 Enabled (must set to 0 when
Register 0x0701, Bit 7 = 1).
0x1 R/W
1 Disabled (must set to 1 when
Register 0x0701, Bit 7 = 0).
[6:0] Reserved 111111 Reserved. 0x3F R
0x18A6 VREF control [7:1] Reserved Reserved. 0x0 R
0 VREF control 0 Internal reference. 0x0 R/W
1 External reference.
0x18E0 External VCM
Buffer Control 1
[7:0] External VCM Buffer
Control 1
See the Input Common Mode section
for details.
0x0 R/W
0x18E1
External V
CM
Buffer Control 2
[7:0]
External V
CM
Buffer
Control 2
See the Input Common Mode section
for details.
0x0 R/W
0x18E2 External VCM
Buffer Control 3
[7:0] External VCM Buffer
Control 3
See the Input Common Mode section
for details.
0x0 R/W
0x18E3 External VCM
buffer control
7 Reserved Reserved. 0x0 R
6 External VCM buffer 0 Disable. 0x0 R/W
1 Enable.
[5:0] External VCM buffer
[5:0]
See the Input Common Mode section. 0x0 R/W
0x18E6 Temperature
diode export
[7:0] Temperature diode
location select
See the Temperature Diode section. 0x0 R/W
0x00 Central diode. VREF pin = high-Z.
0x01 Central diode. VREF pin = 1× diode
voltage output.
0x02 Central diode. VREF pin = 20× diode
voltage output.
0x03 Central diode. VREF pin = GND.
0x40 Channel A diode. VREF pin = high-Z.
0x41 Channel A diode. VREF pin = 1× diode
voltage output.
0x42 Channel A diode. VREF pin = 20× diode
voltage output.
0x43 Channel A diode. VREF pin = GND.
Data Sheet AD9695
Rev. C | Page 133 of 136
Address Name Bits Bit Name Settings Description Reset Access
0x50 Channel B diode. VREF pin = high-Z.
0x51 Channel B diode. VREF pin = 1× diode
voltage output.
0x52 Channel B diode. VREF pin = 20× diode
voltage output.
0x53 Channel B diode. VREF pin = GND.
0x1908
Analog input
control (local)
[7:3]
Reserved
Reserved.
0x0
R
2 Enable dc coupling 0 Analog input optimized for ac coupling. 0x0 R/W
1 Analog input optimized for dc coupling.
[1:0] Reserved Reserved. 0x0 R
0x1910
Input full-scale
control (local)
[7:4] Reserved Reserved. 0x0 R
[3:0] TRM VREF 1.8 V Full-scale voltage setting. 0xD R/W
0 2.04 V p-p differential.
1010 1.36 V p-p differential.
1011 1.47 V p-p differential.
1100 1.59 V p-p differential.
1101 1.70 V p-p differential.
1110 1.81 V p-p differential.
1111 1.93 V p-p differential.
0x1A4C Buffer Control 1
(local)
[7:6] Reserved Reserved. 0x0 R
[5:0] Buffer Control P Input buffer main current (P). 0x1E R/W
00110 Buffer current set to 120 µA.
01000 Buffer current set to 160 µA.
01010 Buffer current set to 200 µA.
01100 Buffer current set to 240 µA.
01110 Buffer current set to 280 µA.
10000 Buffer current set to 320 µA.
10010 Buffer current set to 360 µA.
10100 Buffer current set to 400 µA.
0x1A4D Buffer Control 2
(local)
[7:6] Reserved Reserved. 0x0 R
[5:0] Buffer Control N Input buffer main current (N). 0x1E R/W
00110 Buffer current set to 120 µA.
01000 Buffer current set to 160 µA.
01010 Buffer current set to 200 µA.
01100 Buffer current set to 240 µA.
01110 Buffer current set to 280 µA.
10000 Buffer current set to 320 µA.
10010 Buffer current set to 360 µA.
10100 Buffer current set to 400 µA.
0x1B03 Buffer Control 3
(local)
[7:0] Buffer Control 3 Buffer Control 3. 0x00 R/W
0x00 Setting 1
0x02 Setting 2
0x1B08 Buffer Control 4
(local)
[7:0] Buffer Control 4 Buffer Control 4. 0x01 R/W
0x01 Setting 1
0xC1 Setting 2
0x1B10 Buffer Control 5
(local)
[7:0] Buffer Control 5 Buffer Control 5. 0x00 R/W
0x00 Setting 1
0x1C Setting 2
AD9695 Data Sheet
Rev. C | Page 134 of 136
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
The power supplies required to power the AD9695 are shown
in Table 49.
Table 49. Typical Power Supplies for AD9695
Domain Voltage (V) Tolerance (%)
AVDD1 0.95 ±2.5
AVDD1_SR 0.95 ±2.5
DVDD 0.95 ±2.5
DRVDD1 0.95 ±2.5
AVDD2 1.8 ±5
DRVDD2 1.8 ±5
SPIVDD 1.8 ±5
AVDD3 2.5 ±2.5
For applications requiring an optimal high power efficiency
and low noise performance, it is recommended that the
ADP5054 quad switching regulator be used to convert the 6.0 V
or 12 V input rails to intermediate rails (1.3 V, 2.4 V, and 3.0
V). These intermediate rails are then postregulated by very low
noise, low dropout (LDO) regulators (ADP1763, ADP7159, and
ADP151). Figure 143 shows the recommended power supply
scheme for the AD9695.
AVDD1
0.95V
1.3V
ANALOG
AVDD1_SR
0.95V
DVDD
0.95V
DRVDD1
0.95V
AVDD2
1.8V
DRVDD2
1.8V
ADP5054
6.0V
TO
15.0V
AVDD3
2.5V
3.0V
LDO
SWITCHER
OPTIONAL PATH
1.3V
DIGITAL
OPTIONAL
2.4V
SPIVDD
1.8V
REFE RE NCE D TO AGND
OPTIONAL
ADP1763
ADP1763
ADP7159
ADP151
ADP7159
15660-113
Figure 143. High Efficiency, Low Noise Power Solution for the AD9695
It is not necessary to split all of these power domains in all cases.
The recommended solution shown in Figure 143 provides the
lowest noise, highest efficiency power delivery system for the
AD9695. If only one 0.975 V supply is available, route to AVDD1
first and then tap it off and isolate it with a ferrite bead or a filter
choke, preceded by decoupling capacitors for AVDD1_SR,
DVDD, and DRVDD1, in that order. Figure 144 shows the
simplified schematic. Alternatively, the LDOs can be bypassed
altogether and the AD9695 can be driven directly from the dc-
to-dc converter. Note that this approach has risks in that there
may be more power supply noise injected into the power supply
domains of the ADC. To minimize noise, follow the layout
guidelines of the dc-to-dc converter.
AVDD1
0.95V
1.3V
ANALOG AVDD1_SR
0.95V
DVDD
0.95V
DRVDD1
0.95V
AVDD2
1.8V
DRVDD2
1.8V
ADP5054
12V FROM FMC OR
6.0V FRO M WAL L
SUPPLY
AVDD3
2.5V
3.0V
LDO
SWITCHER
OPTIONAL PATH
FERRIT E BE AD
1.3V
DIGITAL
2.4V
SW3
SW4
SW1
SW2
ADP1763
ADP7159
ADP7159
SPIVDD
1.8V
NOTES
1. AL L VOLTAG E S RE FERE NCE D TO AGND.
15660-114
Figure 144. Simplified Power Solution for the AD9695
The user can employ several different decoupling capacitors to
cover both high and low frequencies. These capacitors must be
located close to the point of entry at the PCB level and close to
the devices, with minimal trace lengths.
Data Sheet AD9695
Rev. C | Page 135 of 136
LAYOUT GUIDELINES
The ADC evaluation board can be used as a guide to follow
good layout practices. The evaluation board layout is set up in
such a way as to
• Minimize coupling between the analog inputs (Channel A
to Channel B and Channel B to Channel A).
• Minimize clock coupling to the analog inputs.
• Provide enough power and ground planes for the various
supply domains while reducing cross coupling.
• Provide adequate thermal relief to the ADC.
Figure 145 shows the overall layout scheme used for the
AD9695 evaluation board.
AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND
PIN 60)
AVDD1_SR (Pin 57) and AGND_SR (Pin 56 and Pin 60) can
be used to provide a separate power supply node to the
SYSREF± circuits of AD9695. If running in Subclass 1, the
AD9695 can support periodic one-shot or gapped signals. To
minimize the coupling of this supply into the AVDD1 supply
node, adequate supply bypassing is needed.
ADC
CH.A
CH.B
CLK JE S D204B LANES
POWER
SYSREF
15660-115
Figure 145. Recommended PCB Layout for the AD9695
AD9695 Data Sheet
Rev. C | Page 136 of 136
OUTLINE DIMENSIONS
0.30
0.25
0.18
0.80
0.75
0.70
0.50
BSC
BOTTOM VIEW
TOP VIEW
6.30
6.20 SQ
6.10
0.05 M AX
0.02 NO M
0.203 REF
COPLANARITY
0.08
10-26-2018-A
9.10
9.00 SQ
8.90
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
0.20 M IN
7.50 REF
COM P LIANT T O JEDE C S TANDARDS M O-220- WMM D
1
64
16
17
49
48
32
33
0.45
0.40
0.35
PKG-004559
EXPOSED
PAD
END VIEW
DETAIL A
(JEDEC 95)
PIN 1
IN D ICATO R AR EA OP TIO NS
(SEE DETAIL A)
PIN 1
INDICATOR
AREA
SEATING
PLANE
Figure 146. 64-Lead Lead Frame Chip Scale Package [LFCSP]
9 mm × 9 mm Body and 0.75 mm Package Height
(CP-64-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9695BCPZ-625 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17
AD9695BCPZRL7-625 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17
AD9695-625EBZ Evaluation Board
AD9695BCPZ-1300 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17
AD9695BCPZRL7-1300 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17
AD9695-1300EBZ Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15660-6/20(C)
